1; RUN: llc -march=amdgcn -verify-machineinstrs -enable-misched -asm-verbose < %s | FileCheck -check-prefix=SI %s 2 3declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 4 5; SI-LABEL: {{^}}test_if: 6; Make sure the i1 values created by the cfg structurizer pass are 7; moved using VALU instructions 8 9 10; waitcnt should be inserted after exec modification 11; SI: v_cmp_lt_i32_e32 vcc, 0, 12; SI: v_mov_b32_e32 {{v[0-9]+}}, 0 13; SI-NEXT: s_and_saveexec_b64 [[SAVE1:s\[[0-9]+:[0-9]+\]]], vcc 14; SI-NEXT: s_xor_b64 [[SAVE2:s\[[0-9]+:[0-9]+\]]], exec, [[SAVE1]] 15; SI-NEXT: ; mask branch [[FLOW_BB:BB[0-9]+_[0-9]+]] 16; SI-NEXT: s_cbranch_execz [[FLOW_BB]] 17 18; SI-NEXT: BB{{[0-9]+}}_1: ; %LeafBlock3 19; SI-NOT: s_mov_b64 s[{{[0-9]:[0-9]}}], -1 20; SI: v_mov_b32_e32 v{{[0-9]}}, -1 21; SI: s_and_saveexec_b64 22; SI-NEXT: ; mask branch 23 24; v_mov should be after exec modification 25; SI: [[FLOW_BB]]: 26; SI-NEXT: s_or_saveexec_b64 [[SAVE3:s\[[0-9]+:[0-9]+\]]], [[SAVE2]] 27; SI-NEXT: v_mov_b32_e32 v{{[0-9]+}} 28; SI-NEXT: s_xor_b64 exec, exec, [[SAVE3]] 29; SI-NEXT: ; mask branch 30; 31define amdgpu_kernel void @test_if(i32 %b, i32 addrspace(1)* %src, i32 addrspace(1)* %dst) #1 { 32entry: 33 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 34 switch i32 %tid, label %default [ 35 i32 0, label %case0 36 i32 1, label %case1 37 ] 38 39case0: 40 %arrayidx1 = getelementptr i32, i32 addrspace(1)* %dst, i32 %b 41 store i32 13, i32 addrspace(1)* %arrayidx1, align 4 42 br label %end 43 44case1: 45 %arrayidx5 = getelementptr i32, i32 addrspace(1)* %dst, i32 %b 46 store i32 17, i32 addrspace(1)* %arrayidx5, align 4 47 br label %end 48 49default: 50 %cmp8 = icmp eq i32 %tid, 2 51 %arrayidx10 = getelementptr i32, i32 addrspace(1)* %dst, i32 %b 52 br i1 %cmp8, label %if, label %else 53 54if: 55 store i32 19, i32 addrspace(1)* %arrayidx10, align 4 56 br label %end 57 58else: 59 store i32 21, i32 addrspace(1)* %arrayidx10, align 4 60 br label %end 61 62end: 63 ret void 64} 65 66; SI-LABEL: {{^}}simple_test_v_if: 67; SI: v_cmp_ne_u32_e32 vcc, 0, v{{[0-9]+}} 68; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc 69; SI-NEXT: ; mask branch [[EXIT:BB[0-9]+_[0-9]+]] 70 71; SI-NEXT: BB{{[0-9]+_[0-9]+}}: 72; SI: buffer_store_dword 73 74; SI-NEXT: {{^}}[[EXIT]]: 75; SI: s_endpgm 76define amdgpu_kernel void @simple_test_v_if(i32 addrspace(1)* %dst, i32 addrspace(1)* %src) #1 { 77 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 78 %is.0 = icmp ne i32 %tid, 0 79 br i1 %is.0, label %then, label %exit 80 81then: 82 %gep = getelementptr i32, i32 addrspace(1)* %dst, i32 %tid 83 store i32 999, i32 addrspace(1)* %gep 84 br label %exit 85 86exit: 87 ret void 88} 89 90; FIXME: It would be better to endpgm in the then block. 91 92; SI-LABEL: {{^}}simple_test_v_if_ret_else_ret: 93; SI: v_cmp_ne_u32_e32 vcc, 0, v{{[0-9]+}} 94; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc 95; SI-NEXT: ; mask branch [[EXIT:BB[0-9]+_[0-9]+]] 96 97; SI-NEXT: BB{{[0-9]+_[0-9]+}}: 98; SI: buffer_store_dword 99 100; SI-NEXT: {{^}}[[EXIT]]: 101; SI: s_endpgm 102define amdgpu_kernel void @simple_test_v_if_ret_else_ret(i32 addrspace(1)* %dst, i32 addrspace(1)* %src) #1 { 103 %tid = call i32 @llvm.amdgcn.workitem.id.x() 104 %is.0 = icmp ne i32 %tid, 0 105 br i1 %is.0, label %then, label %exit 106 107then: 108 %gep = getelementptr i32, i32 addrspace(1)* %dst, i32 %tid 109 store i32 999, i32 addrspace(1)* %gep 110 ret void 111 112exit: 113 ret void 114} 115 116; Final block has more than a ret to execute. This was miscompiled 117; before function exit blocks were unified since the endpgm would 118; terminate the then wavefront before reaching the store. 119 120; SI-LABEL: {{^}}simple_test_v_if_ret_else_code_ret: 121; SI: v_cmp_eq_u32_e32 vcc, 0, v{{[0-9]+}} 122; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc 123; SI: s_xor_b64 [[BR_SREG]], exec, [[BR_SREG]] 124; SI: ; mask branch [[FLOW:BB[0-9]+_[0-9]+]] 125 126; SI-NEXT: {{^BB[0-9]+_[0-9]+}}: ; %exit 127; SI: ds_write_b32 128 129; SI-NEXT: {{^}}[[FLOW]]: 130; SI-NEXT: s_or_saveexec_b64 131; SI-NEXT: s_xor_b64 exec, exec 132; SI-NEXT: ; mask branch [[UNIFIED_RETURN:BB[0-9]+_[0-9]+]] 133 134; SI-NEXT: {{^BB[0-9]+_[0-9]+}}: ; %then 135; SI: s_waitcnt 136; SI-NEXT: buffer_store_dword 137 138; SI-NEXT: {{^}}[[UNIFIED_RETURN]]: ; %UnifiedReturnBlock 139; SI: s_endpgm 140define amdgpu_kernel void @simple_test_v_if_ret_else_code_ret(i32 addrspace(1)* %dst, i32 addrspace(1)* %src) #1 { 141 %tid = call i32 @llvm.amdgcn.workitem.id.x() 142 %is.0 = icmp ne i32 %tid, 0 143 br i1 %is.0, label %then, label %exit 144 145then: 146 %gep = getelementptr i32, i32 addrspace(1)* %dst, i32 %tid 147 store i32 999, i32 addrspace(1)* %gep 148 ret void 149 150exit: 151 store volatile i32 7, i32 addrspace(3)* undef 152 ret void 153} 154 155; SI-LABEL: {{^}}simple_test_v_loop: 156; SI: v_cmp_ne_u32_e32 vcc, 0, v{{[0-9]+}} 157; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc 158; SI-NEXT: ; mask branch 159; SI-NEXT: s_cbranch_execz [[LABEL_EXIT:BB[0-9]+_[0-9]+]] 160 161; SI: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, 0{{$}} 162 163; SI: [[LABEL_LOOP:BB[0-9]+_[0-9]+]]: 164; SI: buffer_load_dword 165; SI-DAG: buffer_store_dword 166; SI-DAG: v_cmp_eq_u32_e32 vcc, 0x100 167; SI: s_cbranch_vccz [[LABEL_LOOP]] 168; SI: [[LABEL_EXIT]]: 169; SI: s_endpgm 170 171define amdgpu_kernel void @simple_test_v_loop(i32 addrspace(1)* %dst, i32 addrspace(1)* %src) #1 { 172entry: 173 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 174 %is.0 = icmp ne i32 %tid, 0 175 %limit = add i32 %tid, 64 176 br i1 %is.0, label %loop, label %exit 177 178loop: 179 %i = phi i32 [%tid, %entry], [%i.inc, %loop] 180 %gep.src = getelementptr i32, i32 addrspace(1)* %src, i32 %i 181 %gep.dst = getelementptr i32, i32 addrspace(1)* %dst, i32 %i 182 %load = load i32, i32 addrspace(1)* %src 183 store i32 %load, i32 addrspace(1)* %gep.dst 184 %i.inc = add nsw i32 %i, 1 185 %cmp = icmp eq i32 %limit, %i.inc 186 br i1 %cmp, label %exit, label %loop 187 188exit: 189 ret void 190} 191 192; SI-LABEL: {{^}}multi_vcond_loop: 193 194; Load loop limit from buffer 195; Branch to exit if uniformly not taken 196; SI: ; %bb.0: 197; SI: buffer_load_dword [[VBOUND:v[0-9]+]] 198; SI: v_cmp_lt_i32_e32 vcc 199; SI: s_and_saveexec_b64 [[OUTER_CMP_SREG:s\[[0-9]+:[0-9]+\]]], vcc 200; SI-NEXT: ; mask branch 201; SI-NEXT: s_cbranch_execz [[LABEL_EXIT:BB[0-9]+_[0-9]+]] 202 203; Initialize inner condition to false 204; SI: BB{{[0-9]+_[0-9]+}}: ; %bb10.preheader 205; SI: s_mov_b64 [[COND_STATE:s\[[0-9]+:[0-9]+\]]], 0{{$}} 206 207; Clear exec bits for workitems that load -1s 208; SI: [[LABEL_LOOP:BB[0-9]+_[0-9]+]]: 209; SI: buffer_load_dword [[B:v[0-9]+]] 210; SI: buffer_load_dword [[A:v[0-9]+]] 211; SI-DAG: v_cmp_ne_u32_e64 [[NEG1_CHECK_0:s\[[0-9]+:[0-9]+\]]], -1, [[A]] 212; SI-DAG: v_cmp_ne_u32_e32 [[NEG1_CHECK_1:vcc]], -1, [[B]] 213; SI: s_and_b64 [[ORNEG1:s\[[0-9]+:[0-9]+\]]], [[NEG1_CHECK_1]], [[NEG1_CHECK_0]] 214; SI: s_and_saveexec_b64 [[ORNEG2:s\[[0-9]+:[0-9]+\]]], [[ORNEG1]] 215; SI: s_xor_b64 [[ORNEG3:s\[[0-9]+:[0-9]+\]]], exec, [[ORNEG2]] 216; SI: s_cbranch_execz [[LABEL_FLOW:BB[0-9]+_[0-9]+]] 217 218; SI: BB{{[0-9]+_[0-9]+}}: ; %bb20 219; SI: buffer_store_dword 220; SI: v_cmp_ge_i64_e{{32|64}} [[CMP:s\[[0-9]+:[0-9]+\]|vcc]] 221; SI: s_or_b64 [[TMP:s\[[0-9]+:[0-9]+\]]], [[CMP]], [[COND_STATE]] 222 223; SI: [[LABEL_FLOW]]: 224; SI-NEXT: ; in Loop: Header=[[LABEL_LOOP]] 225; SI-NEXT: s_or_b64 exec, exec, [[ORNEG3]] 226; SI-NEXT: s_mov_b64 [[MOVED_TMP:s\[[0-9]+:[0-9]+\]]], [[TMP]] 227; SI-NEXT: s_and_b64 [[MASKED_ORNEG3:s\[[0-9]+:[0-9]+\]]], exec, [[ORNEG3]] 228; SI-NEXT: s_or_b64 [[COND_STATE]], [[MASKED_ORNEG3]], [[MOVED_TMP]] 229; SI-NEXT: s_andn2_b64 exec, exec, [[COND_STATE]] 230; SI-NEXT: s_cbranch_execnz [[LABEL_LOOP]] 231 232; SI: [[LABEL_EXIT]]: 233; SI-NOT: [[COND_STATE]] 234; SI: s_endpgm 235 236define amdgpu_kernel void @multi_vcond_loop(i32 addrspace(1)* noalias nocapture %arg, i32 addrspace(1)* noalias nocapture readonly %arg1, i32 addrspace(1)* noalias nocapture readonly %arg2, i32 addrspace(1)* noalias nocapture readonly %arg3) #1 { 237bb: 238 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0 239 %tmp4 = sext i32 %tmp to i64 240 %tmp5 = getelementptr inbounds i32, i32 addrspace(1)* %arg3, i64 %tmp4 241 %tmp6 = load i32, i32 addrspace(1)* %tmp5, align 4 242 %tmp7 = icmp sgt i32 %tmp6, 0 243 %tmp8 = sext i32 %tmp6 to i64 244 br i1 %tmp7, label %bb10, label %bb26 245 246bb10: ; preds = %bb, %bb20 247 %tmp11 = phi i64 [ %tmp23, %bb20 ], [ 0, %bb ] 248 %tmp12 = add nsw i64 %tmp11, %tmp4 249 %tmp13 = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i64 %tmp12 250 %tmp14 = load i32, i32 addrspace(1)* %tmp13, align 4 251 %tmp15 = getelementptr inbounds i32, i32 addrspace(1)* %arg2, i64 %tmp12 252 %tmp16 = load i32, i32 addrspace(1)* %tmp15, align 4 253 %tmp17 = icmp ne i32 %tmp14, -1 254 %tmp18 = icmp ne i32 %tmp16, -1 255 %tmp19 = and i1 %tmp17, %tmp18 256 br i1 %tmp19, label %bb20, label %bb26 257 258bb20: ; preds = %bb10 259 %tmp21 = add nsw i32 %tmp16, %tmp14 260 %tmp22 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp12 261 store i32 %tmp21, i32 addrspace(1)* %tmp22, align 4 262 %tmp23 = add nuw nsw i64 %tmp11, 1 263 %tmp24 = icmp slt i64 %tmp23, %tmp8 264 br i1 %tmp24, label %bb10, label %bb26 265 266bb26: ; preds = %bb10, %bb20, %bb 267 ret void 268} 269 270attributes #0 = { nounwind readnone } 271attributes #1 = { nounwind } 272