1; RUN: llc -march=amdgcn -verify-machineinstrs -enable-misched -asm-verbose < %s | FileCheck -check-prefix=SI %s
2
3declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
4
5; SI-LABEL: @test_if
6; Make sure the i1 values created by the cfg structurizer pass are
7; moved using VALU instructions
8; SI-NOT: s_mov_b64 s[{{[0-9]:[0-9]}}], -1
9; SI: v_mov_b32_e32 v{{[0-9]}}, -1
10define void @test_if(i32 %b, i32 addrspace(1)* %src, i32 addrspace(1)* %dst) #1 {
11entry:
12  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
13  switch i32 %tid, label %default [
14    i32 0, label %case0
15    i32 1, label %case1
16  ]
17
18case0:
19  %arrayidx1 = getelementptr i32, i32 addrspace(1)* %dst, i32 %b
20  store i32 0, i32 addrspace(1)* %arrayidx1, align 4
21  br label %end
22
23case1:
24  %arrayidx5 = getelementptr i32, i32 addrspace(1)* %dst, i32 %b
25  store i32 1, i32 addrspace(1)* %arrayidx5, align 4
26  br label %end
27
28default:
29  %cmp8 = icmp eq i32 %tid, 2
30  %arrayidx10 = getelementptr i32, i32 addrspace(1)* %dst, i32 %b
31  br i1 %cmp8, label %if, label %else
32
33if:
34  store i32 2, i32 addrspace(1)* %arrayidx10, align 4
35  br label %end
36
37else:
38  store i32 3, i32 addrspace(1)* %arrayidx10, align 4
39  br label %end
40
41end:
42  ret void
43}
44
45; SI-LABEL: @simple_test_v_if
46; SI: v_cmp_ne_i32_e32 vcc, 0, v{{[0-9]+}}
47; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
48; SI: s_xor_b64 [[BR_SREG]], exec, [[BR_SREG]]
49
50; SI: ; BB#1
51; SI: buffer_store_dword
52; SI: s_endpgm
53
54; SI: BB1_2:
55; SI: s_or_b64 exec, exec, [[BR_SREG]]
56; SI: s_endpgm
57define void @simple_test_v_if(i32 addrspace(1)* %dst, i32 addrspace(1)* %src) #1 {
58  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
59  %is.0 = icmp ne i32 %tid, 0
60  br i1 %is.0, label %store, label %exit
61
62store:
63  %gep = getelementptr i32, i32 addrspace(1)* %dst, i32 %tid
64  store i32 999, i32 addrspace(1)* %gep
65  ret void
66
67exit:
68  ret void
69}
70
71; SI-LABEL: @simple_test_v_loop
72; SI: v_cmp_ne_i32_e32 vcc, 0, v{{[0-9]+}}
73; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
74; SI: s_xor_b64 [[BR_SREG]], exec, [[BR_SREG]]
75; SI: s_cbranch_execz BB2_2
76
77; SI: ; BB#1:
78; SI: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, 0{{$}}
79
80; SI: BB2_3:
81; SI: buffer_load_dword
82; SI-DAG: buffer_store_dword
83; SI-DAG: v_cmp_eq_i32_e32 vcc,
84; SI-DAG: s_and_b64 vcc, exec, vcc
85; SI: s_cbranch_vccnz BB2_2
86; SI: s_branch BB2_3
87; SI: BB2_2:
88; SI: s_endpgm
89
90define void @simple_test_v_loop(i32 addrspace(1)* %dst, i32 addrspace(1)* %src) #1 {
91entry:
92  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
93  %is.0 = icmp ne i32 %tid, 0
94  %limit = add i32 %tid, 64
95  br i1 %is.0, label %loop, label %exit
96
97loop:
98  %i = phi i32 [%tid, %entry], [%i.inc, %loop]
99  %gep.src = getelementptr i32, i32 addrspace(1)* %src, i32 %i
100  %gep.dst = getelementptr i32, i32 addrspace(1)* %dst, i32 %i
101  %load = load i32, i32 addrspace(1)* %src
102  store i32 %load, i32 addrspace(1)* %gep.dst
103  %i.inc = add nsw i32 %i, 1
104  %cmp = icmp eq i32 %limit, %i.inc
105  br i1 %cmp, label %exit, label %loop
106
107exit:
108  ret void
109}
110
111; SI-LABEL: @multi_vcond_loop
112
113; Load loop limit from buffer
114; Branch to exit if uniformly not taken
115; SI: ; BB#0:
116; SI: buffer_load_dword [[VBOUND:v[0-9]+]]
117; SI: v_cmp_lt_i32_e32 vcc
118; SI: s_and_saveexec_b64 [[OUTER_CMP_SREG:s\[[0-9]+:[0-9]+\]]], vcc
119; SI: s_xor_b64 [[OUTER_CMP_SREG]], exec, [[OUTER_CMP_SREG]]
120; SI: s_cbranch_execz BB3_2
121
122; Initialize inner condition to false
123; SI: ; BB#1:
124; SI: s_mov_b64 [[ZERO:s\[[0-9]+:[0-9]+\]]], 0{{$}}
125; SI: s_mov_b64 [[COND_STATE:s\[[0-9]+:[0-9]+\]]], [[ZERO]]
126
127; Clear exec bits for workitems that load -1s
128; SI: BB3_3:
129; SI: buffer_load_dword [[B:v[0-9]+]]
130; SI: buffer_load_dword [[A:v[0-9]+]]
131; SI-DAG: v_cmp_ne_i32_e64 [[NEG1_CHECK_0:s\[[0-9]+:[0-9]+\]]], -1, [[A]]
132; SI-DAG: v_cmp_ne_i32_e32 [[NEG1_CHECK_1:vcc]], -1, [[B]]
133; SI: s_and_b64 [[ORNEG1:s\[[0-9]+:[0-9]+\]]], [[NEG1_CHECK_1]], [[NEG1_CHECK_0]]
134; SI: s_and_saveexec_b64 [[ORNEG2:s\[[0-9]+:[0-9]+\]]], [[ORNEG1]]
135; SI: s_xor_b64 [[ORNEG2]], exec, [[ORNEG2]]
136; SI: s_cbranch_execz BB3_5
137
138; SI: BB#4:
139; SI: buffer_store_dword
140; SI: v_cmp_ge_i64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]]
141; SI: s_or_b64 [[COND_STATE]], [[CMP]], [[COND_STATE]]
142
143; SI: BB3_5:
144; SI: s_or_b64 exec, exec, [[ORNEG2]]
145; SI: s_or_b64 [[COND_STATE]], [[ORNEG2]], [[COND_STATE]]
146; SI: s_andn2_b64 exec, exec, [[COND_STATE]]
147; SI: s_cbranch_execnz BB3_3
148
149; SI: BB#6
150; SI: s_or_b64 exec, exec, [[COND_STATE]]
151
152; SI: BB3_2:
153; SI-NOT: [[COND_STATE]]
154; SI: s_endpgm
155
156define void @multi_vcond_loop(i32 addrspace(1)* noalias nocapture %arg, i32 addrspace(1)* noalias nocapture readonly %arg1, i32 addrspace(1)* noalias nocapture readonly %arg2, i32 addrspace(1)* noalias nocapture readonly %arg3) #1 {
157bb:
158  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0
159  %tmp4 = sext i32 %tmp to i64
160  %tmp5 = getelementptr inbounds i32, i32 addrspace(1)* %arg3, i64 %tmp4
161  %tmp6 = load i32, i32 addrspace(1)* %tmp5, align 4
162  %tmp7 = icmp sgt i32 %tmp6, 0
163  %tmp8 = sext i32 %tmp6 to i64
164  br i1 %tmp7, label %bb10, label %bb26
165
166bb10:                                             ; preds = %bb, %bb20
167  %tmp11 = phi i64 [ %tmp23, %bb20 ], [ 0, %bb ]
168  %tmp12 = add nsw i64 %tmp11, %tmp4
169  %tmp13 = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i64 %tmp12
170  %tmp14 = load i32, i32 addrspace(1)* %tmp13, align 4
171  %tmp15 = getelementptr inbounds i32, i32 addrspace(1)* %arg2, i64 %tmp12
172  %tmp16 = load i32, i32 addrspace(1)* %tmp15, align 4
173  %tmp17 = icmp ne i32 %tmp14, -1
174  %tmp18 = icmp ne i32 %tmp16, -1
175  %tmp19 = and i1 %tmp17, %tmp18
176  br i1 %tmp19, label %bb20, label %bb26
177
178bb20:                                             ; preds = %bb10
179  %tmp21 = add nsw i32 %tmp16, %tmp14
180  %tmp22 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp12
181  store i32 %tmp21, i32 addrspace(1)* %tmp22, align 4
182  %tmp23 = add nuw nsw i64 %tmp11, 1
183  %tmp24 = icmp slt i64 %tmp23, %tmp8
184  br i1 %tmp24, label %bb10, label %bb26
185
186bb26:                                             ; preds = %bb10, %bb20, %bb
187  ret void
188}
189
190attributes #0 = { nounwind readnone }
191attributes #1 = { nounwind }
192