1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck --check-prefix=GFX6 %s
3; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck --check-prefix=GFX8 %s
4; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s
5
6define i8 @v_usubsat_i8(i8 %lhs, i8 %rhs) {
7; GFX6-LABEL: v_usubsat_i8:
8; GFX6:       ; %bb.0:
9; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
10; GFX6-NEXT:    s_movk_i32 s4, 0xff
11; GFX6-NEXT:    v_and_b32_e32 v1, s4, v1
12; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
13; GFX6-NEXT:    v_max_u32_e32 v0, v0, v1
14; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
15; GFX6-NEXT:    s_setpc_b64 s[30:31]
16;
17; GFX8-LABEL: v_usubsat_i8:
18; GFX8:       ; %bb.0:
19; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
20; GFX8-NEXT:    v_sub_u16_sdwa v0, v0, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
21; GFX8-NEXT:    s_setpc_b64 s[30:31]
22;
23; GFX9-LABEL: v_usubsat_i8:
24; GFX9:       ; %bb.0:
25; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
26; GFX9-NEXT:    v_sub_u16_sdwa v0, v0, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
27; GFX9-NEXT:    s_setpc_b64 s[30:31]
28  %result = call i8 @llvm.usub.sat.i8(i8 %lhs, i8 %rhs)
29  ret i8 %result
30}
31
32define i16 @v_usubsat_i16(i16 %lhs, i16 %rhs) {
33; GFX6-LABEL: v_usubsat_i16:
34; GFX6:       ; %bb.0:
35; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
36; GFX6-NEXT:    s_mov_b32 s4, 0xffff
37; GFX6-NEXT:    v_and_b32_e32 v1, s4, v1
38; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
39; GFX6-NEXT:    v_max_u32_e32 v0, v0, v1
40; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
41; GFX6-NEXT:    s_setpc_b64 s[30:31]
42;
43; GFX8-LABEL: v_usubsat_i16:
44; GFX8:       ; %bb.0:
45; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
46; GFX8-NEXT:    v_sub_u16_e64 v0, v0, v1 clamp
47; GFX8-NEXT:    s_setpc_b64 s[30:31]
48;
49; GFX9-LABEL: v_usubsat_i16:
50; GFX9:       ; %bb.0:
51; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
52; GFX9-NEXT:    v_sub_u16_e64 v0, v0, v1 clamp
53; GFX9-NEXT:    s_setpc_b64 s[30:31]
54  %result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
55  ret i16 %result
56}
57
58define i32 @v_usubsat_i32(i32 %lhs, i32 %rhs) {
59; GFX6-LABEL: v_usubsat_i32:
60; GFX6:       ; %bb.0:
61; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
62; GFX6-NEXT:    v_max_u32_e32 v0, v0, v1
63; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
64; GFX6-NEXT:    s_setpc_b64 s[30:31]
65;
66; GFX8-LABEL: v_usubsat_i32:
67; GFX8:       ; %bb.0:
68; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
69; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v1 clamp
70; GFX8-NEXT:    s_setpc_b64 s[30:31]
71;
72; GFX9-LABEL: v_usubsat_i32:
73; GFX9:       ; %bb.0:
74; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
75; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v1 clamp
76; GFX9-NEXT:    s_setpc_b64 s[30:31]
77  %result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)
78  ret i32 %result
79}
80
81define <2 x i16> @v_usubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
82; GFX6-LABEL: v_usubsat_v2i16:
83; GFX6:       ; %bb.0:
84; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
85; GFX6-NEXT:    s_mov_b32 s4, 0xffff
86; GFX6-NEXT:    v_and_b32_e32 v4, s4, v2
87; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
88; GFX6-NEXT:    v_and_b32_e32 v5, s4, v3
89; GFX6-NEXT:    v_and_b32_e32 v1, s4, v1
90; GFX6-NEXT:    v_max_u32_e32 v1, v1, v5
91; GFX6-NEXT:    v_max_u32_e32 v0, v0, v4
92; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v3
93; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
94; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
95; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
96; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
97; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
98; GFX6-NEXT:    s_setpc_b64 s[30:31]
99;
100; GFX8-LABEL: v_usubsat_v2i16:
101; GFX8:       ; %bb.0:
102; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
103; GFX8-NEXT:    v_sub_u16_sdwa v2, v0, v1 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
104; GFX8-NEXT:    v_sub_u16_e64 v0, v0, v1 clamp
105; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
106; GFX8-NEXT:    s_setpc_b64 s[30:31]
107;
108; GFX9-LABEL: v_usubsat_v2i16:
109; GFX9:       ; %bb.0:
110; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
111; GFX9-NEXT:    v_pk_sub_u16 v0, v0, v1 clamp
112; GFX9-NEXT:    s_setpc_b64 s[30:31]
113  %result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
114  ret <2 x i16> %result
115}
116
117define <3 x i16> @v_usubsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) {
118; GFX6-LABEL: v_usubsat_v3i16:
119; GFX6:       ; %bb.0:
120; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
121; GFX6-NEXT:    s_mov_b32 s4, 0xffff
122; GFX6-NEXT:    v_and_b32_e32 v6, s4, v3
123; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
124; GFX6-NEXT:    v_and_b32_e32 v7, s4, v4
125; GFX6-NEXT:    v_and_b32_e32 v1, s4, v1
126; GFX6-NEXT:    v_max_u32_e32 v1, v1, v7
127; GFX6-NEXT:    v_max_u32_e32 v0, v0, v6
128; GFX6-NEXT:    v_and_b32_e32 v5, s4, v5
129; GFX6-NEXT:    v_and_b32_e32 v2, s4, v2
130; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v4
131; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v3
132; GFX6-NEXT:    v_max_u32_e32 v2, v2, v5
133; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, v2, v5
134; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
135; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
136; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
137; GFX6-NEXT:    v_and_b32_e32 v2, s4, v3
138; GFX6-NEXT:    v_alignbit_b32 v1, v3, v1, 16
139; GFX6-NEXT:    s_setpc_b64 s[30:31]
140;
141; GFX8-LABEL: v_usubsat_v3i16:
142; GFX8:       ; %bb.0:
143; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
144; GFX8-NEXT:    v_sub_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
145; GFX8-NEXT:    v_sub_u16_e64 v0, v0, v2 clamp
146; GFX8-NEXT:    v_sub_u16_e64 v1, v1, v3 clamp
147; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
148; GFX8-NEXT:    s_setpc_b64 s[30:31]
149;
150; GFX9-LABEL: v_usubsat_v3i16:
151; GFX9:       ; %bb.0:
152; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
153; GFX9-NEXT:    v_pk_sub_u16 v0, v0, v2 clamp
154; GFX9-NEXT:    v_pk_sub_u16 v1, v1, v3 clamp
155; GFX9-NEXT:    s_setpc_b64 s[30:31]
156  %result = call <3 x i16> @llvm.usub.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)
157  ret <3 x i16> %result
158}
159
160define <2 x float> @v_usubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
161; GFX6-LABEL: v_usubsat_v4i16:
162; GFX6:       ; %bb.0:
163; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
164; GFX6-NEXT:    s_mov_b32 s4, 0xffff
165; GFX6-NEXT:    v_and_b32_e32 v10, s4, v4
166; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
167; GFX6-NEXT:    v_and_b32_e32 v11, s4, v5
168; GFX6-NEXT:    v_and_b32_e32 v1, s4, v1
169; GFX6-NEXT:    v_max_u32_e32 v1, v1, v11
170; GFX6-NEXT:    v_max_u32_e32 v0, v0, v10
171; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v5
172; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
173; GFX6-NEXT:    v_and_b32_e32 v8, s4, v6
174; GFX6-NEXT:    v_and_b32_e32 v2, s4, v2
175; GFX6-NEXT:    v_and_b32_e32 v9, s4, v7
176; GFX6-NEXT:    v_and_b32_e32 v3, s4, v3
177; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
178; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
179; GFX6-NEXT:    v_max_u32_e32 v2, v2, v8
180; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
181; GFX6-NEXT:    v_max_u32_e32 v1, v3, v9
182; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v7
183; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
184; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
185; GFX6-NEXT:    v_and_b32_e32 v2, 0xffff, v2
186; GFX6-NEXT:    v_or_b32_e32 v1, v2, v1
187; GFX6-NEXT:    s_setpc_b64 s[30:31]
188;
189; GFX8-LABEL: v_usubsat_v4i16:
190; GFX8:       ; %bb.0:
191; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
192; GFX8-NEXT:    v_sub_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
193; GFX8-NEXT:    v_sub_u16_e64 v0, v0, v2 clamp
194; GFX8-NEXT:    v_sub_u16_sdwa v2, v1, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
195; GFX8-NEXT:    v_sub_u16_e64 v1, v1, v3 clamp
196; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
197; GFX8-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
198; GFX8-NEXT:    s_setpc_b64 s[30:31]
199;
200; GFX9-LABEL: v_usubsat_v4i16:
201; GFX9:       ; %bb.0:
202; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
203; GFX9-NEXT:    v_pk_sub_u16 v0, v0, v2 clamp
204; GFX9-NEXT:    v_pk_sub_u16 v1, v1, v3 clamp
205; GFX9-NEXT:    s_setpc_b64 s[30:31]
206  %result = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
207  %cast = bitcast <4 x i16> %result to <2 x float>
208  ret <2 x float> %cast
209}
210
211define <2 x i32> @v_usubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
212; GFX6-LABEL: v_usubsat_v2i32:
213; GFX6:       ; %bb.0:
214; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
215; GFX6-NEXT:    v_max_u32_e32 v0, v0, v2
216; GFX6-NEXT:    v_max_u32_e32 v1, v1, v3
217; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
218; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v3
219; GFX6-NEXT:    s_setpc_b64 s[30:31]
220;
221; GFX8-LABEL: v_usubsat_v2i32:
222; GFX8:       ; %bb.0:
223; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
224; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v2 clamp
225; GFX8-NEXT:    v_sub_u32_e64 v1, s[4:5], v1, v3 clamp
226; GFX8-NEXT:    s_setpc_b64 s[30:31]
227;
228; GFX9-LABEL: v_usubsat_v2i32:
229; GFX9:       ; %bb.0:
230; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
231; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v2 clamp
232; GFX9-NEXT:    v_sub_u32_e64 v1, v1, v3 clamp
233; GFX9-NEXT:    s_setpc_b64 s[30:31]
234  %result = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
235  ret <2 x i32> %result
236}
237
238define <3 x i32> @v_usubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
239; GFX6-LABEL: v_usubsat_v3i32:
240; GFX6:       ; %bb.0:
241; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
242; GFX6-NEXT:    v_max_u32_e32 v0, v0, v3
243; GFX6-NEXT:    v_max_u32_e32 v1, v1, v4
244; GFX6-NEXT:    v_max_u32_e32 v2, v2, v5
245; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v3
246; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v4
247; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v5
248; GFX6-NEXT:    s_setpc_b64 s[30:31]
249;
250; GFX8-LABEL: v_usubsat_v3i32:
251; GFX8:       ; %bb.0:
252; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
253; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v3 clamp
254; GFX8-NEXT:    v_sub_u32_e64 v1, s[4:5], v1, v4 clamp
255; GFX8-NEXT:    v_sub_u32_e64 v2, s[4:5], v2, v5 clamp
256; GFX8-NEXT:    s_setpc_b64 s[30:31]
257;
258; GFX9-LABEL: v_usubsat_v3i32:
259; GFX9:       ; %bb.0:
260; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
261; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v3 clamp
262; GFX9-NEXT:    v_sub_u32_e64 v1, v1, v4 clamp
263; GFX9-NEXT:    v_sub_u32_e64 v2, v2, v5 clamp
264; GFX9-NEXT:    s_setpc_b64 s[30:31]
265  %result = call <3 x i32> @llvm.usub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
266  ret <3 x i32> %result
267}
268
269define <4 x i32> @v_usubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
270; GFX6-LABEL: v_usubsat_v4i32:
271; GFX6:       ; %bb.0:
272; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
273; GFX6-NEXT:    v_max_u32_e32 v0, v0, v4
274; GFX6-NEXT:    v_max_u32_e32 v1, v1, v5
275; GFX6-NEXT:    v_max_u32_e32 v2, v2, v6
276; GFX6-NEXT:    v_max_u32_e32 v3, v3, v7
277; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
278; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v5
279; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
280; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, v3, v7
281; GFX6-NEXT:    s_setpc_b64 s[30:31]
282;
283; GFX8-LABEL: v_usubsat_v4i32:
284; GFX8:       ; %bb.0:
285; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
286; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v4 clamp
287; GFX8-NEXT:    v_sub_u32_e64 v1, s[4:5], v1, v5 clamp
288; GFX8-NEXT:    v_sub_u32_e64 v2, s[4:5], v2, v6 clamp
289; GFX8-NEXT:    v_sub_u32_e64 v3, s[4:5], v3, v7 clamp
290; GFX8-NEXT:    s_setpc_b64 s[30:31]
291;
292; GFX9-LABEL: v_usubsat_v4i32:
293; GFX9:       ; %bb.0:
294; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
295; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v4 clamp
296; GFX9-NEXT:    v_sub_u32_e64 v1, v1, v5 clamp
297; GFX9-NEXT:    v_sub_u32_e64 v2, v2, v6 clamp
298; GFX9-NEXT:    v_sub_u32_e64 v3, v3, v7 clamp
299; GFX9-NEXT:    s_setpc_b64 s[30:31]
300  %result = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
301  ret <4 x i32> %result
302}
303
304define <8 x i32> @v_usubsat_v8i32(<8 x i32> %lhs, <8 x i32> %rhs) {
305; GFX6-LABEL: v_usubsat_v8i32:
306; GFX6:       ; %bb.0:
307; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
308; GFX6-NEXT:    v_max_u32_e32 v0, v0, v8
309; GFX6-NEXT:    v_max_u32_e32 v1, v1, v9
310; GFX6-NEXT:    v_max_u32_e32 v2, v2, v10
311; GFX6-NEXT:    v_max_u32_e32 v3, v3, v11
312; GFX6-NEXT:    v_max_u32_e32 v4, v4, v12
313; GFX6-NEXT:    v_max_u32_e32 v5, v5, v13
314; GFX6-NEXT:    v_max_u32_e32 v6, v6, v14
315; GFX6-NEXT:    v_max_u32_e32 v7, v7, v15
316; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
317; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v9
318; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v10
319; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, v3, v11
320; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, v4, v12
321; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, v5, v13
322; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, v6, v14
323; GFX6-NEXT:    v_sub_i32_e32 v7, vcc, v7, v15
324; GFX6-NEXT:    s_setpc_b64 s[30:31]
325;
326; GFX8-LABEL: v_usubsat_v8i32:
327; GFX8:       ; %bb.0:
328; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
329; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v8 clamp
330; GFX8-NEXT:    v_sub_u32_e64 v1, s[4:5], v1, v9 clamp
331; GFX8-NEXT:    v_sub_u32_e64 v2, s[4:5], v2, v10 clamp
332; GFX8-NEXT:    v_sub_u32_e64 v3, s[4:5], v3, v11 clamp
333; GFX8-NEXT:    v_sub_u32_e64 v4, s[4:5], v4, v12 clamp
334; GFX8-NEXT:    v_sub_u32_e64 v5, s[4:5], v5, v13 clamp
335; GFX8-NEXT:    v_sub_u32_e64 v6, s[4:5], v6, v14 clamp
336; GFX8-NEXT:    v_sub_u32_e64 v7, s[4:5], v7, v15 clamp
337; GFX8-NEXT:    s_setpc_b64 s[30:31]
338;
339; GFX9-LABEL: v_usubsat_v8i32:
340; GFX9:       ; %bb.0:
341; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
342; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v8 clamp
343; GFX9-NEXT:    v_sub_u32_e64 v1, v1, v9 clamp
344; GFX9-NEXT:    v_sub_u32_e64 v2, v2, v10 clamp
345; GFX9-NEXT:    v_sub_u32_e64 v3, v3, v11 clamp
346; GFX9-NEXT:    v_sub_u32_e64 v4, v4, v12 clamp
347; GFX9-NEXT:    v_sub_u32_e64 v5, v5, v13 clamp
348; GFX9-NEXT:    v_sub_u32_e64 v6, v6, v14 clamp
349; GFX9-NEXT:    v_sub_u32_e64 v7, v7, v15 clamp
350; GFX9-NEXT:    s_setpc_b64 s[30:31]
351  %result = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> %lhs, <8 x i32> %rhs)
352  ret <8 x i32> %result
353}
354
355define <16 x i32> @v_usubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
356; GFX6-LABEL: v_usubsat_v16i32:
357; GFX6:       ; %bb.0:
358; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
359; GFX6-NEXT:    v_max_u32_e32 v0, v0, v16
360; GFX6-NEXT:    v_max_u32_e32 v1, v1, v17
361; GFX6-NEXT:    v_max_u32_e32 v2, v2, v18
362; GFX6-NEXT:    v_max_u32_e32 v3, v3, v19
363; GFX6-NEXT:    v_max_u32_e32 v4, v4, v20
364; GFX6-NEXT:    v_max_u32_e32 v5, v5, v21
365; GFX6-NEXT:    v_max_u32_e32 v6, v6, v22
366; GFX6-NEXT:    v_max_u32_e32 v7, v7, v23
367; GFX6-NEXT:    v_max_u32_e32 v8, v8, v24
368; GFX6-NEXT:    v_max_u32_e32 v9, v9, v25
369; GFX6-NEXT:    v_max_u32_e32 v10, v10, v26
370; GFX6-NEXT:    v_max_u32_e32 v11, v11, v27
371; GFX6-NEXT:    v_max_u32_e32 v12, v12, v28
372; GFX6-NEXT:    v_max_u32_e32 v13, v13, v29
373; GFX6-NEXT:    v_max_u32_e32 v14, v14, v30
374; GFX6-NEXT:    v_max_u32_e32 v15, v15, v31
375; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v16
376; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v17
377; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v18
378; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, v3, v19
379; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, v4, v20
380; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, v5, v21
381; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, v6, v22
382; GFX6-NEXT:    v_sub_i32_e32 v7, vcc, v7, v23
383; GFX6-NEXT:    v_sub_i32_e32 v8, vcc, v8, v24
384; GFX6-NEXT:    v_sub_i32_e32 v9, vcc, v9, v25
385; GFX6-NEXT:    v_sub_i32_e32 v10, vcc, v10, v26
386; GFX6-NEXT:    v_sub_i32_e32 v11, vcc, v11, v27
387; GFX6-NEXT:    v_sub_i32_e32 v12, vcc, v12, v28
388; GFX6-NEXT:    v_sub_i32_e32 v13, vcc, v13, v29
389; GFX6-NEXT:    v_sub_i32_e32 v14, vcc, v14, v30
390; GFX6-NEXT:    v_sub_i32_e32 v15, vcc, v15, v31
391; GFX6-NEXT:    s_setpc_b64 s[30:31]
392;
393; GFX8-LABEL: v_usubsat_v16i32:
394; GFX8:       ; %bb.0:
395; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
396; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v16 clamp
397; GFX8-NEXT:    v_sub_u32_e64 v1, s[4:5], v1, v17 clamp
398; GFX8-NEXT:    v_sub_u32_e64 v2, s[4:5], v2, v18 clamp
399; GFX8-NEXT:    v_sub_u32_e64 v3, s[4:5], v3, v19 clamp
400; GFX8-NEXT:    v_sub_u32_e64 v4, s[4:5], v4, v20 clamp
401; GFX8-NEXT:    v_sub_u32_e64 v5, s[4:5], v5, v21 clamp
402; GFX8-NEXT:    v_sub_u32_e64 v6, s[4:5], v6, v22 clamp
403; GFX8-NEXT:    v_sub_u32_e64 v7, s[4:5], v7, v23 clamp
404; GFX8-NEXT:    v_sub_u32_e64 v8, s[4:5], v8, v24 clamp
405; GFX8-NEXT:    v_sub_u32_e64 v9, s[4:5], v9, v25 clamp
406; GFX8-NEXT:    v_sub_u32_e64 v10, s[4:5], v10, v26 clamp
407; GFX8-NEXT:    v_sub_u32_e64 v11, s[4:5], v11, v27 clamp
408; GFX8-NEXT:    v_sub_u32_e64 v12, s[4:5], v12, v28 clamp
409; GFX8-NEXT:    v_sub_u32_e64 v13, s[4:5], v13, v29 clamp
410; GFX8-NEXT:    v_sub_u32_e64 v14, s[4:5], v14, v30 clamp
411; GFX8-NEXT:    v_sub_u32_e64 v15, s[4:5], v15, v31 clamp
412; GFX8-NEXT:    s_setpc_b64 s[30:31]
413;
414; GFX9-LABEL: v_usubsat_v16i32:
415; GFX9:       ; %bb.0:
416; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
417; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v16 clamp
418; GFX9-NEXT:    v_sub_u32_e64 v1, v1, v17 clamp
419; GFX9-NEXT:    v_sub_u32_e64 v2, v2, v18 clamp
420; GFX9-NEXT:    v_sub_u32_e64 v3, v3, v19 clamp
421; GFX9-NEXT:    v_sub_u32_e64 v4, v4, v20 clamp
422; GFX9-NEXT:    v_sub_u32_e64 v5, v5, v21 clamp
423; GFX9-NEXT:    v_sub_u32_e64 v6, v6, v22 clamp
424; GFX9-NEXT:    v_sub_u32_e64 v7, v7, v23 clamp
425; GFX9-NEXT:    v_sub_u32_e64 v8, v8, v24 clamp
426; GFX9-NEXT:    v_sub_u32_e64 v9, v9, v25 clamp
427; GFX9-NEXT:    v_sub_u32_e64 v10, v10, v26 clamp
428; GFX9-NEXT:    v_sub_u32_e64 v11, v11, v27 clamp
429; GFX9-NEXT:    v_sub_u32_e64 v12, v12, v28 clamp
430; GFX9-NEXT:    v_sub_u32_e64 v13, v13, v29 clamp
431; GFX9-NEXT:    v_sub_u32_e64 v14, v14, v30 clamp
432; GFX9-NEXT:    v_sub_u32_e64 v15, v15, v31 clamp
433; GFX9-NEXT:    s_setpc_b64 s[30:31]
434  %result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
435  ret <16 x i32> %result
436}
437
438
439define i64 @v_usubsat_i64(i64 %lhs, i64 %rhs) {
440; GFX6-LABEL: v_usubsat_i64:
441; GFX6:       ; %bb.0:
442; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
443; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v0, v2
444; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v1, v3, vcc
445; GFX6-NEXT:    v_cmp_gt_u64_e32 vcc, v[2:3], v[0:1]
446; GFX6-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc
447; GFX6-NEXT:    v_cndmask_b32_e64 v1, v3, 0, vcc
448; GFX6-NEXT:    s_setpc_b64 s[30:31]
449;
450; GFX8-LABEL: v_usubsat_i64:
451; GFX8:       ; %bb.0:
452; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
453; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, v0, v2
454; GFX8-NEXT:    v_subb_u32_e32 v3, vcc, v1, v3, vcc
455; GFX8-NEXT:    v_cmp_gt_u64_e32 vcc, v[2:3], v[0:1]
456; GFX8-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc
457; GFX8-NEXT:    v_cndmask_b32_e64 v1, v3, 0, vcc
458; GFX8-NEXT:    s_setpc_b64 s[30:31]
459;
460; GFX9-LABEL: v_usubsat_i64:
461; GFX9:       ; %bb.0:
462; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
463; GFX9-NEXT:    v_sub_co_u32_e32 v2, vcc, v0, v2
464; GFX9-NEXT:    v_subb_co_u32_e32 v3, vcc, v1, v3, vcc
465; GFX9-NEXT:    v_cmp_gt_u64_e32 vcc, v[2:3], v[0:1]
466; GFX9-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc
467; GFX9-NEXT:    v_cndmask_b32_e64 v1, v3, 0, vcc
468; GFX9-NEXT:    s_setpc_b64 s[30:31]
469  %result = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)
470  ret i64 %result
471}
472
473declare i8 @llvm.usub.sat.i8(i8, i8) #0
474declare i16 @llvm.usub.sat.i16(i16, i16) #0
475declare <2 x i16> @llvm.usub.sat.v2i16(<2 x i16>, <2 x i16>) #0
476declare <3 x i16> @llvm.usub.sat.v3i16(<3 x i16>, <3 x i16>) #0
477declare <4 x i16> @llvm.usub.sat.v4i16(<4 x i16>, <4 x i16>) #0
478declare i32 @llvm.usub.sat.i32(i32, i32) #0
479declare <2 x i32> @llvm.usub.sat.v2i32(<2 x i32>, <2 x i32>) #0
480declare <3 x i32> @llvm.usub.sat.v3i32(<3 x i32>, <3 x i32>) #0
481declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>) #0
482declare <8 x i32> @llvm.usub.sat.v8i32(<8 x i32>, <8 x i32>) #0
483declare <16 x i32> @llvm.usub.sat.v16i32(<16 x i32>, <16 x i32>) #0
484declare i64 @llvm.usub.sat.i64(i64, i64) #0
485
486attributes #0 = { nounwind readnone speculatable willreturn }
487