1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck --check-prefix=GFX6 %s
3; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck --check-prefix=GFX8 %s
4; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s
5
6define i8 @v_usubsat_i8(i8 %lhs, i8 %rhs) {
7; GFX6-LABEL: v_usubsat_i8:
8; GFX6:       ; %bb.0:
9; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
10; GFX6-NEXT:    s_movk_i32 s4, 0xff
11; GFX6-NEXT:    v_and_b32_e32 v1, s4, v1
12; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
13; GFX6-NEXT:    v_max_u32_e32 v0, v0, v1
14; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
15; GFX6-NEXT:    s_setpc_b64 s[30:31]
16;
17; GFX8-LABEL: v_usubsat_i8:
18; GFX8:       ; %bb.0:
19; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
20; GFX8-NEXT:    v_sub_u16_sdwa v0, v0, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
21; GFX8-NEXT:    s_setpc_b64 s[30:31]
22;
23; GFX9-LABEL: v_usubsat_i8:
24; GFX9:       ; %bb.0:
25; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
26; GFX9-NEXT:    v_sub_u16_sdwa v0, v0, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
27; GFX9-NEXT:    s_setpc_b64 s[30:31]
28  %result = call i8 @llvm.usub.sat.i8(i8 %lhs, i8 %rhs)
29  ret i8 %result
30}
31
32define i16 @v_usubsat_i16(i16 %lhs, i16 %rhs) {
33; GFX6-LABEL: v_usubsat_i16:
34; GFX6:       ; %bb.0:
35; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
36; GFX6-NEXT:    s_mov_b32 s4, 0xffff
37; GFX6-NEXT:    v_and_b32_e32 v1, s4, v1
38; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
39; GFX6-NEXT:    v_max_u32_e32 v0, v0, v1
40; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
41; GFX6-NEXT:    s_setpc_b64 s[30:31]
42;
43; GFX8-LABEL: v_usubsat_i16:
44; GFX8:       ; %bb.0:
45; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
46; GFX8-NEXT:    v_sub_u16_e64 v0, v0, v1 clamp
47; GFX8-NEXT:    s_setpc_b64 s[30:31]
48;
49; GFX9-LABEL: v_usubsat_i16:
50; GFX9:       ; %bb.0:
51; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
52; GFX9-NEXT:    v_sub_u16_e64 v0, v0, v1 clamp
53; GFX9-NEXT:    s_setpc_b64 s[30:31]
54  %result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
55  ret i16 %result
56}
57
58define i32 @v_usubsat_i32(i32 %lhs, i32 %rhs) {
59; GFX6-LABEL: v_usubsat_i32:
60; GFX6:       ; %bb.0:
61; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
62; GFX6-NEXT:    v_max_u32_e32 v0, v0, v1
63; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
64; GFX6-NEXT:    s_setpc_b64 s[30:31]
65;
66; GFX8-LABEL: v_usubsat_i32:
67; GFX8:       ; %bb.0:
68; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
69; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v1 clamp
70; GFX8-NEXT:    s_setpc_b64 s[30:31]
71;
72; GFX9-LABEL: v_usubsat_i32:
73; GFX9:       ; %bb.0:
74; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
75; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v1 clamp
76; GFX9-NEXT:    s_setpc_b64 s[30:31]
77  %result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)
78  ret i32 %result
79}
80
81define <2 x i16> @v_usubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
82; GFX6-LABEL: v_usubsat_v2i16:
83; GFX6:       ; %bb.0:
84; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
85; GFX6-NEXT:    s_mov_b32 s4, 0xffff
86; GFX6-NEXT:    v_and_b32_e32 v4, s4, v3
87; GFX6-NEXT:    v_and_b32_e32 v1, s4, v1
88; GFX6-NEXT:    v_max_u32_e32 v1, v1, v4
89; GFX6-NEXT:    v_and_b32_e32 v2, s4, v2
90; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
91; GFX6-NEXT:    v_max_u32_e32 v0, v0, v2
92; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v3
93; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
94; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
95; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
96; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
97; GFX6-NEXT:    s_setpc_b64 s[30:31]
98;
99; GFX8-LABEL: v_usubsat_v2i16:
100; GFX8:       ; %bb.0:
101; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
102; GFX8-NEXT:    v_sub_u16_sdwa v2, v0, v1 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
103; GFX8-NEXT:    v_sub_u16_e64 v0, v0, v1 clamp
104; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
105; GFX8-NEXT:    s_setpc_b64 s[30:31]
106;
107; GFX9-LABEL: v_usubsat_v2i16:
108; GFX9:       ; %bb.0:
109; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
110; GFX9-NEXT:    v_pk_sub_u16 v0, v0, v1 clamp
111; GFX9-NEXT:    s_setpc_b64 s[30:31]
112  %result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
113  ret <2 x i16> %result
114}
115
116define <3 x i16> @v_usubsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) {
117; GFX6-LABEL: v_usubsat_v3i16:
118; GFX6:       ; %bb.0:
119; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
120; GFX6-NEXT:    s_mov_b32 s4, 0xffff
121; GFX6-NEXT:    v_and_b32_e32 v6, s4, v4
122; GFX6-NEXT:    v_and_b32_e32 v1, s4, v1
123; GFX6-NEXT:    v_max_u32_e32 v1, v1, v6
124; GFX6-NEXT:    v_and_b32_e32 v3, s4, v3
125; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
126; GFX6-NEXT:    v_max_u32_e32 v0, v0, v3
127; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v4
128; GFX6-NEXT:    v_and_b32_e32 v5, s4, v5
129; GFX6-NEXT:    v_and_b32_e32 v2, s4, v2
130; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v3
131; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
132; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
133; GFX6-NEXT:    v_max_u32_e32 v1, v2, v5
134; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v1, v5
135; GFX6-NEXT:    v_alignbit_b32 v1, v2, v0, 16
136; GFX6-NEXT:    s_setpc_b64 s[30:31]
137;
138; GFX8-LABEL: v_usubsat_v3i16:
139; GFX8:       ; %bb.0:
140; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
141; GFX8-NEXT:    v_sub_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
142; GFX8-NEXT:    v_sub_u16_e64 v0, v0, v2 clamp
143; GFX8-NEXT:    v_sub_u16_e64 v1, v1, v3 clamp
144; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
145; GFX8-NEXT:    s_setpc_b64 s[30:31]
146;
147; GFX9-LABEL: v_usubsat_v3i16:
148; GFX9:       ; %bb.0:
149; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
150; GFX9-NEXT:    v_pk_sub_u16 v1, v1, v3 clamp
151; GFX9-NEXT:    v_pk_sub_u16 v0, v0, v2 clamp
152; GFX9-NEXT:    s_setpc_b64 s[30:31]
153  %result = call <3 x i16> @llvm.usub.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)
154  ret <3 x i16> %result
155}
156
157define <2 x float> @v_usubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
158; GFX6-LABEL: v_usubsat_v4i16:
159; GFX6:       ; %bb.0:
160; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
161; GFX6-NEXT:    s_mov_b32 s4, 0xffff
162; GFX6-NEXT:    v_and_b32_e32 v9, s4, v5
163; GFX6-NEXT:    v_and_b32_e32 v1, s4, v1
164; GFX6-NEXT:    v_max_u32_e32 v1, v1, v9
165; GFX6-NEXT:    v_and_b32_e32 v4, s4, v4
166; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
167; GFX6-NEXT:    v_max_u32_e32 v0, v0, v4
168; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v5
169; GFX6-NEXT:    v_and_b32_e32 v8, s4, v7
170; GFX6-NEXT:    v_and_b32_e32 v3, s4, v3
171; GFX6-NEXT:    v_and_b32_e32 v6, s4, v6
172; GFX6-NEXT:    v_and_b32_e32 v2, s4, v2
173; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
174; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
175; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
176; GFX6-NEXT:    v_max_u32_e32 v1, v2, v6
177; GFX6-NEXT:    v_max_u32_e32 v2, v3, v8
178; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v7
179; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v6
180; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
181; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
182; GFX6-NEXT:    s_setpc_b64 s[30:31]
183;
184; GFX8-LABEL: v_usubsat_v4i16:
185; GFX8:       ; %bb.0:
186; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
187; GFX8-NEXT:    v_sub_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
188; GFX8-NEXT:    v_sub_u16_e64 v0, v0, v2 clamp
189; GFX8-NEXT:    v_sub_u16_sdwa v2, v1, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
190; GFX8-NEXT:    v_sub_u16_e64 v1, v1, v3 clamp
191; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
192; GFX8-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
193; GFX8-NEXT:    s_setpc_b64 s[30:31]
194;
195; GFX9-LABEL: v_usubsat_v4i16:
196; GFX9:       ; %bb.0:
197; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
198; GFX9-NEXT:    v_pk_sub_u16 v0, v0, v2 clamp
199; GFX9-NEXT:    v_pk_sub_u16 v1, v1, v3 clamp
200; GFX9-NEXT:    s_setpc_b64 s[30:31]
201  %result = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
202  %cast = bitcast <4 x i16> %result to <2 x float>
203  ret <2 x float> %cast
204}
205
206define <2 x i32> @v_usubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
207; GFX6-LABEL: v_usubsat_v2i32:
208; GFX6:       ; %bb.0:
209; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
210; GFX6-NEXT:    v_max_u32_e32 v0, v0, v2
211; GFX6-NEXT:    v_max_u32_e32 v1, v1, v3
212; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
213; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v3
214; GFX6-NEXT:    s_setpc_b64 s[30:31]
215;
216; GFX8-LABEL: v_usubsat_v2i32:
217; GFX8:       ; %bb.0:
218; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
219; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v2 clamp
220; GFX8-NEXT:    v_sub_u32_e64 v1, s[4:5], v1, v3 clamp
221; GFX8-NEXT:    s_setpc_b64 s[30:31]
222;
223; GFX9-LABEL: v_usubsat_v2i32:
224; GFX9:       ; %bb.0:
225; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
226; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v2 clamp
227; GFX9-NEXT:    v_sub_u32_e64 v1, v1, v3 clamp
228; GFX9-NEXT:    s_setpc_b64 s[30:31]
229  %result = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
230  ret <2 x i32> %result
231}
232
233define <3 x i32> @v_usubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
234; GFX6-LABEL: v_usubsat_v3i32:
235; GFX6:       ; %bb.0:
236; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
237; GFX6-NEXT:    v_max_u32_e32 v0, v0, v3
238; GFX6-NEXT:    v_max_u32_e32 v1, v1, v4
239; GFX6-NEXT:    v_max_u32_e32 v2, v2, v5
240; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v3
241; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v4
242; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v5
243; GFX6-NEXT:    s_setpc_b64 s[30:31]
244;
245; GFX8-LABEL: v_usubsat_v3i32:
246; GFX8:       ; %bb.0:
247; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
248; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v3 clamp
249; GFX8-NEXT:    v_sub_u32_e64 v1, s[4:5], v1, v4 clamp
250; GFX8-NEXT:    v_sub_u32_e64 v2, s[4:5], v2, v5 clamp
251; GFX8-NEXT:    s_setpc_b64 s[30:31]
252;
253; GFX9-LABEL: v_usubsat_v3i32:
254; GFX9:       ; %bb.0:
255; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
256; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v3 clamp
257; GFX9-NEXT:    v_sub_u32_e64 v1, v1, v4 clamp
258; GFX9-NEXT:    v_sub_u32_e64 v2, v2, v5 clamp
259; GFX9-NEXT:    s_setpc_b64 s[30:31]
260  %result = call <3 x i32> @llvm.usub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
261  ret <3 x i32> %result
262}
263
264define <4 x i32> @v_usubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
265; GFX6-LABEL: v_usubsat_v4i32:
266; GFX6:       ; %bb.0:
267; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
268; GFX6-NEXT:    v_max_u32_e32 v0, v0, v4
269; GFX6-NEXT:    v_max_u32_e32 v1, v1, v5
270; GFX6-NEXT:    v_max_u32_e32 v2, v2, v6
271; GFX6-NEXT:    v_max_u32_e32 v3, v3, v7
272; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
273; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v5
274; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
275; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, v3, v7
276; GFX6-NEXT:    s_setpc_b64 s[30:31]
277;
278; GFX8-LABEL: v_usubsat_v4i32:
279; GFX8:       ; %bb.0:
280; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
281; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v4 clamp
282; GFX8-NEXT:    v_sub_u32_e64 v1, s[4:5], v1, v5 clamp
283; GFX8-NEXT:    v_sub_u32_e64 v2, s[4:5], v2, v6 clamp
284; GFX8-NEXT:    v_sub_u32_e64 v3, s[4:5], v3, v7 clamp
285; GFX8-NEXT:    s_setpc_b64 s[30:31]
286;
287; GFX9-LABEL: v_usubsat_v4i32:
288; GFX9:       ; %bb.0:
289; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
290; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v4 clamp
291; GFX9-NEXT:    v_sub_u32_e64 v1, v1, v5 clamp
292; GFX9-NEXT:    v_sub_u32_e64 v2, v2, v6 clamp
293; GFX9-NEXT:    v_sub_u32_e64 v3, v3, v7 clamp
294; GFX9-NEXT:    s_setpc_b64 s[30:31]
295  %result = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
296  ret <4 x i32> %result
297}
298
299define <8 x i32> @v_usubsat_v8i32(<8 x i32> %lhs, <8 x i32> %rhs) {
300; GFX6-LABEL: v_usubsat_v8i32:
301; GFX6:       ; %bb.0:
302; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
303; GFX6-NEXT:    v_max_u32_e32 v0, v0, v8
304; GFX6-NEXT:    v_max_u32_e32 v1, v1, v9
305; GFX6-NEXT:    v_max_u32_e32 v2, v2, v10
306; GFX6-NEXT:    v_max_u32_e32 v3, v3, v11
307; GFX6-NEXT:    v_max_u32_e32 v4, v4, v12
308; GFX6-NEXT:    v_max_u32_e32 v5, v5, v13
309; GFX6-NEXT:    v_max_u32_e32 v6, v6, v14
310; GFX6-NEXT:    v_max_u32_e32 v7, v7, v15
311; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
312; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v9
313; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v10
314; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, v3, v11
315; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, v4, v12
316; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, v5, v13
317; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, v6, v14
318; GFX6-NEXT:    v_sub_i32_e32 v7, vcc, v7, v15
319; GFX6-NEXT:    s_setpc_b64 s[30:31]
320;
321; GFX8-LABEL: v_usubsat_v8i32:
322; GFX8:       ; %bb.0:
323; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
324; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v8 clamp
325; GFX8-NEXT:    v_sub_u32_e64 v1, s[4:5], v1, v9 clamp
326; GFX8-NEXT:    v_sub_u32_e64 v2, s[4:5], v2, v10 clamp
327; GFX8-NEXT:    v_sub_u32_e64 v3, s[4:5], v3, v11 clamp
328; GFX8-NEXT:    v_sub_u32_e64 v4, s[4:5], v4, v12 clamp
329; GFX8-NEXT:    v_sub_u32_e64 v5, s[4:5], v5, v13 clamp
330; GFX8-NEXT:    v_sub_u32_e64 v6, s[4:5], v6, v14 clamp
331; GFX8-NEXT:    v_sub_u32_e64 v7, s[4:5], v7, v15 clamp
332; GFX8-NEXT:    s_setpc_b64 s[30:31]
333;
334; GFX9-LABEL: v_usubsat_v8i32:
335; GFX9:       ; %bb.0:
336; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
337; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v8 clamp
338; GFX9-NEXT:    v_sub_u32_e64 v1, v1, v9 clamp
339; GFX9-NEXT:    v_sub_u32_e64 v2, v2, v10 clamp
340; GFX9-NEXT:    v_sub_u32_e64 v3, v3, v11 clamp
341; GFX9-NEXT:    v_sub_u32_e64 v4, v4, v12 clamp
342; GFX9-NEXT:    v_sub_u32_e64 v5, v5, v13 clamp
343; GFX9-NEXT:    v_sub_u32_e64 v6, v6, v14 clamp
344; GFX9-NEXT:    v_sub_u32_e64 v7, v7, v15 clamp
345; GFX9-NEXT:    s_setpc_b64 s[30:31]
346  %result = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> %lhs, <8 x i32> %rhs)
347  ret <8 x i32> %result
348}
349
350define <16 x i32> @v_usubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
351; GFX6-LABEL: v_usubsat_v16i32:
352; GFX6:       ; %bb.0:
353; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
354; GFX6-NEXT:    v_max_u32_e32 v0, v0, v16
355; GFX6-NEXT:    v_max_u32_e32 v1, v1, v17
356; GFX6-NEXT:    v_max_u32_e32 v2, v2, v18
357; GFX6-NEXT:    v_max_u32_e32 v3, v3, v19
358; GFX6-NEXT:    v_max_u32_e32 v4, v4, v20
359; GFX6-NEXT:    v_max_u32_e32 v5, v5, v21
360; GFX6-NEXT:    v_max_u32_e32 v6, v6, v22
361; GFX6-NEXT:    v_max_u32_e32 v7, v7, v23
362; GFX6-NEXT:    v_max_u32_e32 v8, v8, v24
363; GFX6-NEXT:    v_max_u32_e32 v9, v9, v25
364; GFX6-NEXT:    v_max_u32_e32 v10, v10, v26
365; GFX6-NEXT:    v_max_u32_e32 v11, v11, v27
366; GFX6-NEXT:    v_max_u32_e32 v12, v12, v28
367; GFX6-NEXT:    v_max_u32_e32 v13, v13, v29
368; GFX6-NEXT:    v_max_u32_e32 v14, v14, v30
369; GFX6-NEXT:    v_max_u32_e32 v15, v15, v31
370; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v16
371; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v17
372; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v18
373; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, v3, v19
374; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, v4, v20
375; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, v5, v21
376; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, v6, v22
377; GFX6-NEXT:    v_sub_i32_e32 v7, vcc, v7, v23
378; GFX6-NEXT:    v_sub_i32_e32 v8, vcc, v8, v24
379; GFX6-NEXT:    v_sub_i32_e32 v9, vcc, v9, v25
380; GFX6-NEXT:    v_sub_i32_e32 v10, vcc, v10, v26
381; GFX6-NEXT:    v_sub_i32_e32 v11, vcc, v11, v27
382; GFX6-NEXT:    v_sub_i32_e32 v12, vcc, v12, v28
383; GFX6-NEXT:    v_sub_i32_e32 v13, vcc, v13, v29
384; GFX6-NEXT:    v_sub_i32_e32 v14, vcc, v14, v30
385; GFX6-NEXT:    v_sub_i32_e32 v15, vcc, v15, v31
386; GFX6-NEXT:    s_setpc_b64 s[30:31]
387;
388; GFX8-LABEL: v_usubsat_v16i32:
389; GFX8:       ; %bb.0:
390; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
391; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v16 clamp
392; GFX8-NEXT:    v_sub_u32_e64 v1, s[4:5], v1, v17 clamp
393; GFX8-NEXT:    v_sub_u32_e64 v2, s[4:5], v2, v18 clamp
394; GFX8-NEXT:    v_sub_u32_e64 v3, s[4:5], v3, v19 clamp
395; GFX8-NEXT:    v_sub_u32_e64 v4, s[4:5], v4, v20 clamp
396; GFX8-NEXT:    v_sub_u32_e64 v5, s[4:5], v5, v21 clamp
397; GFX8-NEXT:    v_sub_u32_e64 v6, s[4:5], v6, v22 clamp
398; GFX8-NEXT:    v_sub_u32_e64 v7, s[4:5], v7, v23 clamp
399; GFX8-NEXT:    v_sub_u32_e64 v8, s[4:5], v8, v24 clamp
400; GFX8-NEXT:    v_sub_u32_e64 v9, s[4:5], v9, v25 clamp
401; GFX8-NEXT:    v_sub_u32_e64 v10, s[4:5], v10, v26 clamp
402; GFX8-NEXT:    v_sub_u32_e64 v11, s[4:5], v11, v27 clamp
403; GFX8-NEXT:    v_sub_u32_e64 v12, s[4:5], v12, v28 clamp
404; GFX8-NEXT:    v_sub_u32_e64 v13, s[4:5], v13, v29 clamp
405; GFX8-NEXT:    v_sub_u32_e64 v14, s[4:5], v14, v30 clamp
406; GFX8-NEXT:    v_sub_u32_e64 v15, s[4:5], v15, v31 clamp
407; GFX8-NEXT:    s_setpc_b64 s[30:31]
408;
409; GFX9-LABEL: v_usubsat_v16i32:
410; GFX9:       ; %bb.0:
411; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
412; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v16 clamp
413; GFX9-NEXT:    v_sub_u32_e64 v1, v1, v17 clamp
414; GFX9-NEXT:    v_sub_u32_e64 v2, v2, v18 clamp
415; GFX9-NEXT:    v_sub_u32_e64 v3, v3, v19 clamp
416; GFX9-NEXT:    v_sub_u32_e64 v4, v4, v20 clamp
417; GFX9-NEXT:    v_sub_u32_e64 v5, v5, v21 clamp
418; GFX9-NEXT:    v_sub_u32_e64 v6, v6, v22 clamp
419; GFX9-NEXT:    v_sub_u32_e64 v7, v7, v23 clamp
420; GFX9-NEXT:    v_sub_u32_e64 v8, v8, v24 clamp
421; GFX9-NEXT:    v_sub_u32_e64 v9, v9, v25 clamp
422; GFX9-NEXT:    v_sub_u32_e64 v10, v10, v26 clamp
423; GFX9-NEXT:    v_sub_u32_e64 v11, v11, v27 clamp
424; GFX9-NEXT:    v_sub_u32_e64 v12, v12, v28 clamp
425; GFX9-NEXT:    v_sub_u32_e64 v13, v13, v29 clamp
426; GFX9-NEXT:    v_sub_u32_e64 v14, v14, v30 clamp
427; GFX9-NEXT:    v_sub_u32_e64 v15, v15, v31 clamp
428; GFX9-NEXT:    s_setpc_b64 s[30:31]
429  %result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
430  ret <16 x i32> %result
431}
432
433
434define i64 @v_usubsat_i64(i64 %lhs, i64 %rhs) {
435; GFX6-LABEL: v_usubsat_i64:
436; GFX6:       ; %bb.0:
437; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
438; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v0, v2
439; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v1, v3, vcc
440; GFX6-NEXT:    v_cmp_gt_u64_e32 vcc, v[2:3], v[0:1]
441; GFX6-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc
442; GFX6-NEXT:    v_cndmask_b32_e64 v1, v3, 0, vcc
443; GFX6-NEXT:    s_setpc_b64 s[30:31]
444;
445; GFX8-LABEL: v_usubsat_i64:
446; GFX8:       ; %bb.0:
447; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
448; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, v0, v2
449; GFX8-NEXT:    v_subb_u32_e32 v3, vcc, v1, v3, vcc
450; GFX8-NEXT:    v_cmp_gt_u64_e32 vcc, v[2:3], v[0:1]
451; GFX8-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc
452; GFX8-NEXT:    v_cndmask_b32_e64 v1, v3, 0, vcc
453; GFX8-NEXT:    s_setpc_b64 s[30:31]
454;
455; GFX9-LABEL: v_usubsat_i64:
456; GFX9:       ; %bb.0:
457; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
458; GFX9-NEXT:    v_sub_co_u32_e32 v2, vcc, v0, v2
459; GFX9-NEXT:    v_subb_co_u32_e32 v3, vcc, v1, v3, vcc
460; GFX9-NEXT:    v_cmp_gt_u64_e32 vcc, v[2:3], v[0:1]
461; GFX9-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc
462; GFX9-NEXT:    v_cndmask_b32_e64 v1, v3, 0, vcc
463; GFX9-NEXT:    s_setpc_b64 s[30:31]
464  %result = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)
465  ret i64 %result
466}
467
468declare i8 @llvm.usub.sat.i8(i8, i8) #0
469declare i16 @llvm.usub.sat.i16(i16, i16) #0
470declare <2 x i16> @llvm.usub.sat.v2i16(<2 x i16>, <2 x i16>) #0
471declare <3 x i16> @llvm.usub.sat.v3i16(<3 x i16>, <3 x i16>) #0
472declare <4 x i16> @llvm.usub.sat.v4i16(<4 x i16>, <4 x i16>) #0
473declare i32 @llvm.usub.sat.i32(i32, i32) #0
474declare <2 x i32> @llvm.usub.sat.v2i32(<2 x i32>, <2 x i32>) #0
475declare <3 x i32> @llvm.usub.sat.v3i32(<3 x i32>, <3 x i32>) #0
476declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>) #0
477declare <8 x i32> @llvm.usub.sat.v8i32(<8 x i32>, <8 x i32>) #0
478declare <16 x i32> @llvm.usub.sat.v16i32(<16 x i32>, <16 x i32>) #0
479declare i64 @llvm.usub.sat.i64(i64, i64) #0
480
481attributes #0 = { nounwind readnone speculatable willreturn }
482