1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck --check-prefix=GFX6 %s
3; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck --check-prefix=GFX8 %s
4; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s
5; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s
6
7define i8 @v_usubsat_i8(i8 %lhs, i8 %rhs) {
8; GFX6-LABEL: v_usubsat_i8:
9; GFX6:       ; %bb.0:
10; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
11; GFX6-NEXT:    s_movk_i32 s4, 0xff
12; GFX6-NEXT:    v_and_b32_e32 v1, s4, v1
13; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
14; GFX6-NEXT:    v_max_u32_e32 v0, v0, v1
15; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
16; GFX6-NEXT:    s_setpc_b64 s[30:31]
17;
18; GFX8-LABEL: v_usubsat_i8:
19; GFX8:       ; %bb.0:
20; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
21; GFX8-NEXT:    v_sub_u16_sdwa v0, v0, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
22; GFX8-NEXT:    s_setpc_b64 s[30:31]
23;
24; GFX9-LABEL: v_usubsat_i8:
25; GFX9:       ; %bb.0:
26; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
27; GFX9-NEXT:    v_sub_u16_sdwa v0, v0, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
28; GFX9-NEXT:    s_setpc_b64 s[30:31]
29;
30; GFX10-LABEL: v_usubsat_i8:
31; GFX10:       ; %bb.0:
32; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
33; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
34; GFX10-NEXT:    s_movk_i32 s4, 0xff
35; GFX10-NEXT:    v_and_b32_e32 v1, s4, v1
36; GFX10-NEXT:    v_and_b32_e32 v0, s4, v0
37; GFX10-NEXT:    v_sub_nc_u16 v0, v0, v1 clamp
38; GFX10-NEXT:    s_setpc_b64 s[30:31]
39  %result = call i8 @llvm.usub.sat.i8(i8 %lhs, i8 %rhs)
40  ret i8 %result
41}
42
43define i16 @v_usubsat_i16(i16 %lhs, i16 %rhs) {
44; GFX6-LABEL: v_usubsat_i16:
45; GFX6:       ; %bb.0:
46; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
47; GFX6-NEXT:    s_mov_b32 s4, 0xffff
48; GFX6-NEXT:    v_and_b32_e32 v1, s4, v1
49; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
50; GFX6-NEXT:    v_max_u32_e32 v0, v0, v1
51; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
52; GFX6-NEXT:    s_setpc_b64 s[30:31]
53;
54; GFX8-LABEL: v_usubsat_i16:
55; GFX8:       ; %bb.0:
56; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
57; GFX8-NEXT:    v_sub_u16_e64 v0, v0, v1 clamp
58; GFX8-NEXT:    s_setpc_b64 s[30:31]
59;
60; GFX9-LABEL: v_usubsat_i16:
61; GFX9:       ; %bb.0:
62; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
63; GFX9-NEXT:    v_sub_u16_e64 v0, v0, v1 clamp
64; GFX9-NEXT:    s_setpc_b64 s[30:31]
65;
66; GFX10-LABEL: v_usubsat_i16:
67; GFX10:       ; %bb.0:
68; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
69; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
70; GFX10-NEXT:    v_sub_nc_u16 v0, v0, v1 clamp
71; GFX10-NEXT:    s_setpc_b64 s[30:31]
72  %result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
73  ret i16 %result
74}
75
76define i16 @usubsat_as_bithack_i16(i16 %x) {
77; GFX6-LABEL: usubsat_as_bithack_i16:
78; GFX6:       ; %bb.0:
79; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
80; GFX6-NEXT:    v_bfe_i32 v1, v0, 0, 16
81; GFX6-NEXT:    v_ashrrev_i32_e32 v1, 15, v1
82; GFX6-NEXT:    v_xor_b32_e32 v0, 0xffff8000, v0
83; GFX6-NEXT:    v_and_b32_e32 v0, v1, v0
84; GFX6-NEXT:    s_setpc_b64 s[30:31]
85;
86; GFX8-LABEL: usubsat_as_bithack_i16:
87; GFX8:       ; %bb.0:
88; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
89; GFX8-NEXT:    s_movk_i32 s4, 0x8000
90; GFX8-NEXT:    v_sub_u16_e64 v0, v0, s4 clamp
91; GFX8-NEXT:    s_setpc_b64 s[30:31]
92;
93; GFX9-LABEL: usubsat_as_bithack_i16:
94; GFX9:       ; %bb.0:
95; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
96; GFX9-NEXT:    s_movk_i32 s4, 0x8000
97; GFX9-NEXT:    v_sub_u16_e64 v0, v0, s4 clamp
98; GFX9-NEXT:    s_setpc_b64 s[30:31]
99;
100; GFX10-LABEL: usubsat_as_bithack_i16:
101; GFX10:       ; %bb.0:
102; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
103; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
104; GFX10-NEXT:    v_sub_nc_u16 v0, v0, 0x8000 clamp
105; GFX10-NEXT:    s_setpc_b64 s[30:31]
106  %signsplat = ashr i16 %x, 15
107  %flipsign = xor i16 %x, 32768
108  %result = and i16 %signsplat, %flipsign
109  ret i16 %result
110}
111
112define i32 @v_usubsat_i32(i32 %lhs, i32 %rhs) {
113; GFX6-LABEL: v_usubsat_i32:
114; GFX6:       ; %bb.0:
115; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
116; GFX6-NEXT:    v_max_u32_e32 v0, v0, v1
117; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
118; GFX6-NEXT:    s_setpc_b64 s[30:31]
119;
120; GFX8-LABEL: v_usubsat_i32:
121; GFX8:       ; %bb.0:
122; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
123; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v1 clamp
124; GFX8-NEXT:    s_setpc_b64 s[30:31]
125;
126; GFX9-LABEL: v_usubsat_i32:
127; GFX9:       ; %bb.0:
128; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
129; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v1 clamp
130; GFX9-NEXT:    s_setpc_b64 s[30:31]
131;
132; GFX10-LABEL: v_usubsat_i32:
133; GFX10:       ; %bb.0:
134; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
135; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
136; GFX10-NEXT:    v_sub_nc_u32_e64 v0, v0, v1 clamp
137; GFX10-NEXT:    s_setpc_b64 s[30:31]
138  %result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)
139  ret i32 %result
140}
141
142define <2 x i16> @v_usubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
143; GFX6-LABEL: v_usubsat_v2i16:
144; GFX6:       ; %bb.0:
145; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
146; GFX6-NEXT:    s_mov_b32 s4, 0xffff
147; GFX6-NEXT:    v_and_b32_e32 v4, s4, v3
148; GFX6-NEXT:    v_and_b32_e32 v1, s4, v1
149; GFX6-NEXT:    v_and_b32_e32 v2, s4, v2
150; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
151; GFX6-NEXT:    v_max_u32_e32 v1, v1, v4
152; GFX6-NEXT:    v_max_u32_e32 v0, v0, v2
153; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v3
154; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
155; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
156; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
157; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
158; GFX6-NEXT:    s_setpc_b64 s[30:31]
159;
160; GFX8-LABEL: v_usubsat_v2i16:
161; GFX8:       ; %bb.0:
162; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
163; GFX8-NEXT:    v_sub_u16_sdwa v2, v0, v1 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
164; GFX8-NEXT:    v_sub_u16_e64 v0, v0, v1 clamp
165; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
166; GFX8-NEXT:    s_setpc_b64 s[30:31]
167;
168; GFX9-LABEL: v_usubsat_v2i16:
169; GFX9:       ; %bb.0:
170; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
171; GFX9-NEXT:    v_pk_sub_u16 v0, v0, v1 clamp
172; GFX9-NEXT:    s_setpc_b64 s[30:31]
173;
174; GFX10-LABEL: v_usubsat_v2i16:
175; GFX10:       ; %bb.0:
176; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
177; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
178; GFX10-NEXT:    v_pk_sub_u16 v0, v0, v1 clamp
179; GFX10-NEXT:    s_setpc_b64 s[30:31]
180  %result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
181  ret <2 x i16> %result
182}
183
184define <3 x i16> @v_usubsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) {
185; GFX6-LABEL: v_usubsat_v3i16:
186; GFX6:       ; %bb.0:
187; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
188; GFX6-NEXT:    s_mov_b32 s4, 0xffff
189; GFX6-NEXT:    v_and_b32_e32 v6, s4, v4
190; GFX6-NEXT:    v_and_b32_e32 v1, s4, v1
191; GFX6-NEXT:    v_and_b32_e32 v3, s4, v3
192; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
193; GFX6-NEXT:    v_max_u32_e32 v1, v1, v6
194; GFX6-NEXT:    v_max_u32_e32 v0, v0, v3
195; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v4
196; GFX6-NEXT:    v_and_b32_e32 v5, s4, v5
197; GFX6-NEXT:    v_and_b32_e32 v2, s4, v2
198; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v3
199; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
200; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
201; GFX6-NEXT:    v_max_u32_e32 v1, v2, v5
202; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v1, v5
203; GFX6-NEXT:    v_alignbit_b32 v1, v2, v0, 16
204; GFX6-NEXT:    s_setpc_b64 s[30:31]
205;
206; GFX8-LABEL: v_usubsat_v3i16:
207; GFX8:       ; %bb.0:
208; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
209; GFX8-NEXT:    v_sub_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
210; GFX8-NEXT:    v_sub_u16_e64 v0, v0, v2 clamp
211; GFX8-NEXT:    v_sub_u16_e64 v1, v1, v3 clamp
212; GFX8-NEXT:    v_or_b32_e32 v0, v0, v4
213; GFX8-NEXT:    s_setpc_b64 s[30:31]
214;
215; GFX9-LABEL: v_usubsat_v3i16:
216; GFX9:       ; %bb.0:
217; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
218; GFX9-NEXT:    v_pk_sub_u16 v1, v1, v3 clamp
219; GFX9-NEXT:    v_pk_sub_u16 v0, v0, v2 clamp
220; GFX9-NEXT:    s_setpc_b64 s[30:31]
221;
222; GFX10-LABEL: v_usubsat_v3i16:
223; GFX10:       ; %bb.0:
224; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
225; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
226; GFX10-NEXT:    v_pk_sub_u16 v0, v0, v2 clamp
227; GFX10-NEXT:    v_pk_sub_u16 v1, v1, v3 clamp
228; GFX10-NEXT:    s_setpc_b64 s[30:31]
229  %result = call <3 x i16> @llvm.usub.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)
230  ret <3 x i16> %result
231}
232
233define <2 x float> @v_usubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
234; GFX6-LABEL: v_usubsat_v4i16:
235; GFX6:       ; %bb.0:
236; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
237; GFX6-NEXT:    s_mov_b32 s4, 0xffff
238; GFX6-NEXT:    v_and_b32_e32 v9, s4, v5
239; GFX6-NEXT:    v_and_b32_e32 v1, s4, v1
240; GFX6-NEXT:    v_and_b32_e32 v4, s4, v4
241; GFX6-NEXT:    v_and_b32_e32 v0, s4, v0
242; GFX6-NEXT:    v_max_u32_e32 v1, v1, v9
243; GFX6-NEXT:    v_max_u32_e32 v0, v0, v4
244; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v5
245; GFX6-NEXT:    v_and_b32_e32 v8, s4, v7
246; GFX6-NEXT:    v_and_b32_e32 v3, s4, v3
247; GFX6-NEXT:    v_and_b32_e32 v6, s4, v6
248; GFX6-NEXT:    v_and_b32_e32 v2, s4, v2
249; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
250; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
251; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
252; GFX6-NEXT:    v_max_u32_e32 v1, v2, v6
253; GFX6-NEXT:    v_max_u32_e32 v2, v3, v8
254; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v7
255; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v6
256; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
257; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
258; GFX6-NEXT:    s_setpc_b64 s[30:31]
259;
260; GFX8-LABEL: v_usubsat_v4i16:
261; GFX8:       ; %bb.0:
262; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
263; GFX8-NEXT:    v_sub_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
264; GFX8-NEXT:    v_sub_u16_e64 v0, v0, v2 clamp
265; GFX8-NEXT:    v_sub_u16_sdwa v2, v1, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
266; GFX8-NEXT:    v_sub_u16_e64 v1, v1, v3 clamp
267; GFX8-NEXT:    v_or_b32_e32 v0, v0, v4
268; GFX8-NEXT:    v_or_b32_e32 v1, v1, v2
269; GFX8-NEXT:    s_setpc_b64 s[30:31]
270;
271; GFX9-LABEL: v_usubsat_v4i16:
272; GFX9:       ; %bb.0:
273; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
274; GFX9-NEXT:    v_pk_sub_u16 v0, v0, v2 clamp
275; GFX9-NEXT:    v_pk_sub_u16 v1, v1, v3 clamp
276; GFX9-NEXT:    s_setpc_b64 s[30:31]
277;
278; GFX10-LABEL: v_usubsat_v4i16:
279; GFX10:       ; %bb.0:
280; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
281; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
282; GFX10-NEXT:    v_pk_sub_u16 v0, v0, v2 clamp
283; GFX10-NEXT:    v_pk_sub_u16 v1, v1, v3 clamp
284; GFX10-NEXT:    s_setpc_b64 s[30:31]
285  %result = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
286  %cast = bitcast <4 x i16> %result to <2 x float>
287  ret <2 x float> %cast
288}
289
290define <2 x i32> @v_usubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
291; GFX6-LABEL: v_usubsat_v2i32:
292; GFX6:       ; %bb.0:
293; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
294; GFX6-NEXT:    v_max_u32_e32 v0, v0, v2
295; GFX6-NEXT:    v_max_u32_e32 v1, v1, v3
296; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
297; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v3
298; GFX6-NEXT:    s_setpc_b64 s[30:31]
299;
300; GFX8-LABEL: v_usubsat_v2i32:
301; GFX8:       ; %bb.0:
302; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
303; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v2 clamp
304; GFX8-NEXT:    v_sub_u32_e64 v1, s[4:5], v1, v3 clamp
305; GFX8-NEXT:    s_setpc_b64 s[30:31]
306;
307; GFX9-LABEL: v_usubsat_v2i32:
308; GFX9:       ; %bb.0:
309; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
310; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v2 clamp
311; GFX9-NEXT:    v_sub_u32_e64 v1, v1, v3 clamp
312; GFX9-NEXT:    s_setpc_b64 s[30:31]
313;
314; GFX10-LABEL: v_usubsat_v2i32:
315; GFX10:       ; %bb.0:
316; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
317; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
318; GFX10-NEXT:    v_sub_nc_u32_e64 v0, v0, v2 clamp
319; GFX10-NEXT:    v_sub_nc_u32_e64 v1, v1, v3 clamp
320; GFX10-NEXT:    s_setpc_b64 s[30:31]
321  %result = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
322  ret <2 x i32> %result
323}
324
325define <3 x i32> @v_usubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
326; GFX6-LABEL: v_usubsat_v3i32:
327; GFX6:       ; %bb.0:
328; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
329; GFX6-NEXT:    v_max_u32_e32 v0, v0, v3
330; GFX6-NEXT:    v_max_u32_e32 v1, v1, v4
331; GFX6-NEXT:    v_max_u32_e32 v2, v2, v5
332; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v3
333; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v4
334; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v5
335; GFX6-NEXT:    s_setpc_b64 s[30:31]
336;
337; GFX8-LABEL: v_usubsat_v3i32:
338; GFX8:       ; %bb.0:
339; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
340; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v3 clamp
341; GFX8-NEXT:    v_sub_u32_e64 v1, s[4:5], v1, v4 clamp
342; GFX8-NEXT:    v_sub_u32_e64 v2, s[4:5], v2, v5 clamp
343; GFX8-NEXT:    s_setpc_b64 s[30:31]
344;
345; GFX9-LABEL: v_usubsat_v3i32:
346; GFX9:       ; %bb.0:
347; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
348; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v3 clamp
349; GFX9-NEXT:    v_sub_u32_e64 v1, v1, v4 clamp
350; GFX9-NEXT:    v_sub_u32_e64 v2, v2, v5 clamp
351; GFX9-NEXT:    s_setpc_b64 s[30:31]
352;
353; GFX10-LABEL: v_usubsat_v3i32:
354; GFX10:       ; %bb.0:
355; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
356; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
357; GFX10-NEXT:    v_sub_nc_u32_e64 v0, v0, v3 clamp
358; GFX10-NEXT:    v_sub_nc_u32_e64 v1, v1, v4 clamp
359; GFX10-NEXT:    v_sub_nc_u32_e64 v2, v2, v5 clamp
360; GFX10-NEXT:    s_setpc_b64 s[30:31]
361  %result = call <3 x i32> @llvm.usub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
362  ret <3 x i32> %result
363}
364
365define <4 x i32> @v_usubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
366; GFX6-LABEL: v_usubsat_v4i32:
367; GFX6:       ; %bb.0:
368; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
369; GFX6-NEXT:    v_max_u32_e32 v0, v0, v4
370; GFX6-NEXT:    v_max_u32_e32 v1, v1, v5
371; GFX6-NEXT:    v_max_u32_e32 v2, v2, v6
372; GFX6-NEXT:    v_max_u32_e32 v3, v3, v7
373; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
374; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v5
375; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
376; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, v3, v7
377; GFX6-NEXT:    s_setpc_b64 s[30:31]
378;
379; GFX8-LABEL: v_usubsat_v4i32:
380; GFX8:       ; %bb.0:
381; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
382; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v4 clamp
383; GFX8-NEXT:    v_sub_u32_e64 v1, s[4:5], v1, v5 clamp
384; GFX8-NEXT:    v_sub_u32_e64 v2, s[4:5], v2, v6 clamp
385; GFX8-NEXT:    v_sub_u32_e64 v3, s[4:5], v3, v7 clamp
386; GFX8-NEXT:    s_setpc_b64 s[30:31]
387;
388; GFX9-LABEL: v_usubsat_v4i32:
389; GFX9:       ; %bb.0:
390; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
391; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v4 clamp
392; GFX9-NEXT:    v_sub_u32_e64 v1, v1, v5 clamp
393; GFX9-NEXT:    v_sub_u32_e64 v2, v2, v6 clamp
394; GFX9-NEXT:    v_sub_u32_e64 v3, v3, v7 clamp
395; GFX9-NEXT:    s_setpc_b64 s[30:31]
396;
397; GFX10-LABEL: v_usubsat_v4i32:
398; GFX10:       ; %bb.0:
399; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
400; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
401; GFX10-NEXT:    v_sub_nc_u32_e64 v0, v0, v4 clamp
402; GFX10-NEXT:    v_sub_nc_u32_e64 v1, v1, v5 clamp
403; GFX10-NEXT:    v_sub_nc_u32_e64 v2, v2, v6 clamp
404; GFX10-NEXT:    v_sub_nc_u32_e64 v3, v3, v7 clamp
405; GFX10-NEXT:    s_setpc_b64 s[30:31]
406  %result = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
407  ret <4 x i32> %result
408}
409
410define <8 x i32> @v_usubsat_v8i32(<8 x i32> %lhs, <8 x i32> %rhs) {
411; GFX6-LABEL: v_usubsat_v8i32:
412; GFX6:       ; %bb.0:
413; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
414; GFX6-NEXT:    v_max_u32_e32 v0, v0, v8
415; GFX6-NEXT:    v_max_u32_e32 v1, v1, v9
416; GFX6-NEXT:    v_max_u32_e32 v2, v2, v10
417; GFX6-NEXT:    v_max_u32_e32 v3, v3, v11
418; GFX6-NEXT:    v_max_u32_e32 v4, v4, v12
419; GFX6-NEXT:    v_max_u32_e32 v5, v5, v13
420; GFX6-NEXT:    v_max_u32_e32 v6, v6, v14
421; GFX6-NEXT:    v_max_u32_e32 v7, v7, v15
422; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
423; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v9
424; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v10
425; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, v3, v11
426; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, v4, v12
427; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, v5, v13
428; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, v6, v14
429; GFX6-NEXT:    v_sub_i32_e32 v7, vcc, v7, v15
430; GFX6-NEXT:    s_setpc_b64 s[30:31]
431;
432; GFX8-LABEL: v_usubsat_v8i32:
433; GFX8:       ; %bb.0:
434; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
435; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v8 clamp
436; GFX8-NEXT:    v_sub_u32_e64 v1, s[4:5], v1, v9 clamp
437; GFX8-NEXT:    v_sub_u32_e64 v2, s[4:5], v2, v10 clamp
438; GFX8-NEXT:    v_sub_u32_e64 v3, s[4:5], v3, v11 clamp
439; GFX8-NEXT:    v_sub_u32_e64 v4, s[4:5], v4, v12 clamp
440; GFX8-NEXT:    v_sub_u32_e64 v5, s[4:5], v5, v13 clamp
441; GFX8-NEXT:    v_sub_u32_e64 v6, s[4:5], v6, v14 clamp
442; GFX8-NEXT:    v_sub_u32_e64 v7, s[4:5], v7, v15 clamp
443; GFX8-NEXT:    s_setpc_b64 s[30:31]
444;
445; GFX9-LABEL: v_usubsat_v8i32:
446; GFX9:       ; %bb.0:
447; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
448; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v8 clamp
449; GFX9-NEXT:    v_sub_u32_e64 v1, v1, v9 clamp
450; GFX9-NEXT:    v_sub_u32_e64 v2, v2, v10 clamp
451; GFX9-NEXT:    v_sub_u32_e64 v3, v3, v11 clamp
452; GFX9-NEXT:    v_sub_u32_e64 v4, v4, v12 clamp
453; GFX9-NEXT:    v_sub_u32_e64 v5, v5, v13 clamp
454; GFX9-NEXT:    v_sub_u32_e64 v6, v6, v14 clamp
455; GFX9-NEXT:    v_sub_u32_e64 v7, v7, v15 clamp
456; GFX9-NEXT:    s_setpc_b64 s[30:31]
457;
458; GFX10-LABEL: v_usubsat_v8i32:
459; GFX10:       ; %bb.0:
460; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
461; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
462; GFX10-NEXT:    v_sub_nc_u32_e64 v0, v0, v8 clamp
463; GFX10-NEXT:    v_sub_nc_u32_e64 v1, v1, v9 clamp
464; GFX10-NEXT:    v_sub_nc_u32_e64 v2, v2, v10 clamp
465; GFX10-NEXT:    v_sub_nc_u32_e64 v3, v3, v11 clamp
466; GFX10-NEXT:    v_sub_nc_u32_e64 v4, v4, v12 clamp
467; GFX10-NEXT:    v_sub_nc_u32_e64 v5, v5, v13 clamp
468; GFX10-NEXT:    v_sub_nc_u32_e64 v6, v6, v14 clamp
469; GFX10-NEXT:    v_sub_nc_u32_e64 v7, v7, v15 clamp
470; GFX10-NEXT:    s_setpc_b64 s[30:31]
471  %result = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> %lhs, <8 x i32> %rhs)
472  ret <8 x i32> %result
473}
474
475define <16 x i32> @v_usubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
476; GFX6-LABEL: v_usubsat_v16i32:
477; GFX6:       ; %bb.0:
478; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
479; GFX6-NEXT:    v_max_u32_e32 v0, v0, v16
480; GFX6-NEXT:    v_max_u32_e32 v1, v1, v17
481; GFX6-NEXT:    v_max_u32_e32 v2, v2, v18
482; GFX6-NEXT:    v_max_u32_e32 v3, v3, v19
483; GFX6-NEXT:    v_max_u32_e32 v4, v4, v20
484; GFX6-NEXT:    v_max_u32_e32 v5, v5, v21
485; GFX6-NEXT:    v_max_u32_e32 v6, v6, v22
486; GFX6-NEXT:    v_max_u32_e32 v7, v7, v23
487; GFX6-NEXT:    v_max_u32_e32 v8, v8, v24
488; GFX6-NEXT:    v_max_u32_e32 v9, v9, v25
489; GFX6-NEXT:    v_max_u32_e32 v10, v10, v26
490; GFX6-NEXT:    v_max_u32_e32 v11, v11, v27
491; GFX6-NEXT:    v_max_u32_e32 v12, v12, v28
492; GFX6-NEXT:    v_max_u32_e32 v13, v13, v29
493; GFX6-NEXT:    v_max_u32_e32 v14, v14, v30
494; GFX6-NEXT:    v_max_u32_e32 v15, v15, v31
495; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v16
496; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v17
497; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v18
498; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, v3, v19
499; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, v4, v20
500; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, v5, v21
501; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, v6, v22
502; GFX6-NEXT:    v_sub_i32_e32 v7, vcc, v7, v23
503; GFX6-NEXT:    v_sub_i32_e32 v8, vcc, v8, v24
504; GFX6-NEXT:    v_sub_i32_e32 v9, vcc, v9, v25
505; GFX6-NEXT:    v_sub_i32_e32 v10, vcc, v10, v26
506; GFX6-NEXT:    v_sub_i32_e32 v11, vcc, v11, v27
507; GFX6-NEXT:    v_sub_i32_e32 v12, vcc, v12, v28
508; GFX6-NEXT:    v_sub_i32_e32 v13, vcc, v13, v29
509; GFX6-NEXT:    v_sub_i32_e32 v14, vcc, v14, v30
510; GFX6-NEXT:    v_sub_i32_e32 v15, vcc, v15, v31
511; GFX6-NEXT:    s_setpc_b64 s[30:31]
512;
513; GFX8-LABEL: v_usubsat_v16i32:
514; GFX8:       ; %bb.0:
515; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
516; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v16 clamp
517; GFX8-NEXT:    v_sub_u32_e64 v1, s[4:5], v1, v17 clamp
518; GFX8-NEXT:    v_sub_u32_e64 v2, s[4:5], v2, v18 clamp
519; GFX8-NEXT:    v_sub_u32_e64 v3, s[4:5], v3, v19 clamp
520; GFX8-NEXT:    v_sub_u32_e64 v4, s[4:5], v4, v20 clamp
521; GFX8-NEXT:    v_sub_u32_e64 v5, s[4:5], v5, v21 clamp
522; GFX8-NEXT:    v_sub_u32_e64 v6, s[4:5], v6, v22 clamp
523; GFX8-NEXT:    v_sub_u32_e64 v7, s[4:5], v7, v23 clamp
524; GFX8-NEXT:    v_sub_u32_e64 v8, s[4:5], v8, v24 clamp
525; GFX8-NEXT:    v_sub_u32_e64 v9, s[4:5], v9, v25 clamp
526; GFX8-NEXT:    v_sub_u32_e64 v10, s[4:5], v10, v26 clamp
527; GFX8-NEXT:    v_sub_u32_e64 v11, s[4:5], v11, v27 clamp
528; GFX8-NEXT:    v_sub_u32_e64 v12, s[4:5], v12, v28 clamp
529; GFX8-NEXT:    v_sub_u32_e64 v13, s[4:5], v13, v29 clamp
530; GFX8-NEXT:    v_sub_u32_e64 v14, s[4:5], v14, v30 clamp
531; GFX8-NEXT:    v_sub_u32_e64 v15, s[4:5], v15, v31 clamp
532; GFX8-NEXT:    s_setpc_b64 s[30:31]
533;
534; GFX9-LABEL: v_usubsat_v16i32:
535; GFX9:       ; %bb.0:
536; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
537; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v16 clamp
538; GFX9-NEXT:    v_sub_u32_e64 v1, v1, v17 clamp
539; GFX9-NEXT:    v_sub_u32_e64 v2, v2, v18 clamp
540; GFX9-NEXT:    v_sub_u32_e64 v3, v3, v19 clamp
541; GFX9-NEXT:    v_sub_u32_e64 v4, v4, v20 clamp
542; GFX9-NEXT:    v_sub_u32_e64 v5, v5, v21 clamp
543; GFX9-NEXT:    v_sub_u32_e64 v6, v6, v22 clamp
544; GFX9-NEXT:    v_sub_u32_e64 v7, v7, v23 clamp
545; GFX9-NEXT:    v_sub_u32_e64 v8, v8, v24 clamp
546; GFX9-NEXT:    v_sub_u32_e64 v9, v9, v25 clamp
547; GFX9-NEXT:    v_sub_u32_e64 v10, v10, v26 clamp
548; GFX9-NEXT:    v_sub_u32_e64 v11, v11, v27 clamp
549; GFX9-NEXT:    v_sub_u32_e64 v12, v12, v28 clamp
550; GFX9-NEXT:    v_sub_u32_e64 v13, v13, v29 clamp
551; GFX9-NEXT:    v_sub_u32_e64 v14, v14, v30 clamp
552; GFX9-NEXT:    v_sub_u32_e64 v15, v15, v31 clamp
553; GFX9-NEXT:    s_setpc_b64 s[30:31]
554;
555; GFX10-LABEL: v_usubsat_v16i32:
556; GFX10:       ; %bb.0:
557; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
558; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
559; GFX10-NEXT:    v_sub_nc_u32_e64 v0, v0, v16 clamp
560; GFX10-NEXT:    v_sub_nc_u32_e64 v1, v1, v17 clamp
561; GFX10-NEXT:    v_sub_nc_u32_e64 v2, v2, v18 clamp
562; GFX10-NEXT:    v_sub_nc_u32_e64 v3, v3, v19 clamp
563; GFX10-NEXT:    v_sub_nc_u32_e64 v4, v4, v20 clamp
564; GFX10-NEXT:    v_sub_nc_u32_e64 v5, v5, v21 clamp
565; GFX10-NEXT:    v_sub_nc_u32_e64 v6, v6, v22 clamp
566; GFX10-NEXT:    v_sub_nc_u32_e64 v7, v7, v23 clamp
567; GFX10-NEXT:    v_sub_nc_u32_e64 v8, v8, v24 clamp
568; GFX10-NEXT:    v_sub_nc_u32_e64 v9, v9, v25 clamp
569; GFX10-NEXT:    v_sub_nc_u32_e64 v10, v10, v26 clamp
570; GFX10-NEXT:    v_sub_nc_u32_e64 v11, v11, v27 clamp
571; GFX10-NEXT:    v_sub_nc_u32_e64 v12, v12, v28 clamp
572; GFX10-NEXT:    v_sub_nc_u32_e64 v13, v13, v29 clamp
573; GFX10-NEXT:    v_sub_nc_u32_e64 v14, v14, v30 clamp
574; GFX10-NEXT:    v_sub_nc_u32_e64 v15, v15, v31 clamp
575; GFX10-NEXT:    s_setpc_b64 s[30:31]
576  %result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
577  ret <16 x i32> %result
578}
579
580
581define i64 @v_usubsat_i64(i64 %lhs, i64 %rhs) {
582; GFX6-LABEL: v_usubsat_i64:
583; GFX6:       ; %bb.0:
584; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
585; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v0, v2
586; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v1, v3, vcc
587; GFX6-NEXT:    v_cmp_gt_u64_e32 vcc, v[2:3], v[0:1]
588; GFX6-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc
589; GFX6-NEXT:    v_cndmask_b32_e64 v1, v3, 0, vcc
590; GFX6-NEXT:    s_setpc_b64 s[30:31]
591;
592; GFX8-LABEL: v_usubsat_i64:
593; GFX8:       ; %bb.0:
594; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
595; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, v0, v2
596; GFX8-NEXT:    v_subb_u32_e32 v3, vcc, v1, v3, vcc
597; GFX8-NEXT:    v_cmp_gt_u64_e32 vcc, v[2:3], v[0:1]
598; GFX8-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc
599; GFX8-NEXT:    v_cndmask_b32_e64 v1, v3, 0, vcc
600; GFX8-NEXT:    s_setpc_b64 s[30:31]
601;
602; GFX9-LABEL: v_usubsat_i64:
603; GFX9:       ; %bb.0:
604; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
605; GFX9-NEXT:    v_sub_co_u32_e32 v2, vcc, v0, v2
606; GFX9-NEXT:    v_subb_co_u32_e32 v3, vcc, v1, v3, vcc
607; GFX9-NEXT:    v_cmp_gt_u64_e32 vcc, v[2:3], v[0:1]
608; GFX9-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc
609; GFX9-NEXT:    v_cndmask_b32_e64 v1, v3, 0, vcc
610; GFX9-NEXT:    s_setpc_b64 s[30:31]
611;
612; GFX10-LABEL: v_usubsat_i64:
613; GFX10:       ; %bb.0:
614; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
615; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
616; GFX10-NEXT:    v_sub_co_u32 v2, vcc_lo, v0, v2
617; GFX10-NEXT:    v_sub_co_ci_u32_e32 v3, vcc_lo, v1, v3, vcc_lo
618; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[0:1]
619; GFX10-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc_lo
620; GFX10-NEXT:    v_cndmask_b32_e64 v1, v3, 0, vcc_lo
621; GFX10-NEXT:    s_setpc_b64 s[30:31]
622  %result = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)
623  ret i64 %result
624}
625
626declare i8 @llvm.usub.sat.i8(i8, i8) #0
627declare i16 @llvm.usub.sat.i16(i16, i16) #0
628declare <2 x i16> @llvm.usub.sat.v2i16(<2 x i16>, <2 x i16>) #0
629declare <3 x i16> @llvm.usub.sat.v3i16(<3 x i16>, <3 x i16>) #0
630declare <4 x i16> @llvm.usub.sat.v4i16(<4 x i16>, <4 x i16>) #0
631declare i32 @llvm.usub.sat.i32(i32, i32) #0
632declare <2 x i32> @llvm.usub.sat.v2i32(<2 x i32>, <2 x i32>) #0
633declare <3 x i32> @llvm.usub.sat.v3i32(<3 x i32>, <3 x i32>) #0
634declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>) #0
635declare <8 x i32> @llvm.usub.sat.v8i32(<8 x i32>, <8 x i32>) #0
636declare <16 x i32> @llvm.usub.sat.v16i32(<16 x i32>, <16 x i32>) #0
637declare i64 @llvm.usub.sat.i64(i64, i64) #0
638
639attributes #0 = { nounwind readnone speculatable willreturn }
640