1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck --check-prefix=GFX6 %s
3; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck --check-prefix=GFX8 %s
4; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s
5; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s
6
7define i8 @v_usubsat_i8(i8 %lhs, i8 %rhs) {
8; GFX6-LABEL: v_usubsat_i8:
9; GFX6:       ; %bb.0:
10; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
11; GFX6-NEXT:    v_and_b32_e32 v1, 0xff, v1
12; GFX6-NEXT:    v_and_b32_e32 v0, 0xff, v0
13; GFX6-NEXT:    v_max_u32_e32 v0, v0, v1
14; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
15; GFX6-NEXT:    s_setpc_b64 s[30:31]
16;
17; GFX8-LABEL: v_usubsat_i8:
18; GFX8:       ; %bb.0:
19; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
20; GFX8-NEXT:    v_sub_u16_sdwa v0, v0, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
21; GFX8-NEXT:    s_setpc_b64 s[30:31]
22;
23; GFX9-LABEL: v_usubsat_i8:
24; GFX9:       ; %bb.0:
25; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
26; GFX9-NEXT:    v_sub_u16_sdwa v0, v0, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
27; GFX9-NEXT:    s_setpc_b64 s[30:31]
28;
29; GFX10-LABEL: v_usubsat_i8:
30; GFX10:       ; %bb.0:
31; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
32; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
33; GFX10-NEXT:    v_and_b32_e32 v1, 0xff, v1
34; GFX10-NEXT:    v_and_b32_e32 v0, 0xff, v0
35; GFX10-NEXT:    v_sub_nc_u16 v0, v0, v1 clamp
36; GFX10-NEXT:    s_setpc_b64 s[30:31]
37  %result = call i8 @llvm.usub.sat.i8(i8 %lhs, i8 %rhs)
38  ret i8 %result
39}
40
41define i16 @v_usubsat_i16(i16 %lhs, i16 %rhs) {
42; GFX6-LABEL: v_usubsat_i16:
43; GFX6:       ; %bb.0:
44; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
45; GFX6-NEXT:    v_and_b32_e32 v1, 0xffff, v1
46; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v0
47; GFX6-NEXT:    v_max_u32_e32 v0, v0, v1
48; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
49; GFX6-NEXT:    s_setpc_b64 s[30:31]
50;
51; GFX8-LABEL: v_usubsat_i16:
52; GFX8:       ; %bb.0:
53; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
54; GFX8-NEXT:    v_sub_u16_e64 v0, v0, v1 clamp
55; GFX8-NEXT:    s_setpc_b64 s[30:31]
56;
57; GFX9-LABEL: v_usubsat_i16:
58; GFX9:       ; %bb.0:
59; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
60; GFX9-NEXT:    v_sub_u16_e64 v0, v0, v1 clamp
61; GFX9-NEXT:    s_setpc_b64 s[30:31]
62;
63; GFX10-LABEL: v_usubsat_i16:
64; GFX10:       ; %bb.0:
65; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
66; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
67; GFX10-NEXT:    v_sub_nc_u16 v0, v0, v1 clamp
68; GFX10-NEXT:    s_setpc_b64 s[30:31]
69  %result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
70  ret i16 %result
71}
72
73define i16 @usubsat_as_bithack_i16(i16 %x) {
74; GFX6-LABEL: usubsat_as_bithack_i16:
75; GFX6:       ; %bb.0:
76; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
77; GFX6-NEXT:    v_bfe_i32 v1, v0, 0, 16
78; GFX6-NEXT:    v_ashrrev_i32_e32 v1, 15, v1
79; GFX6-NEXT:    v_xor_b32_e32 v0, 0xffff8000, v0
80; GFX6-NEXT:    v_and_b32_e32 v0, v1, v0
81; GFX6-NEXT:    s_setpc_b64 s[30:31]
82;
83; GFX8-LABEL: usubsat_as_bithack_i16:
84; GFX8:       ; %bb.0:
85; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
86; GFX8-NEXT:    s_movk_i32 s4, 0x8000
87; GFX8-NEXT:    v_sub_u16_e64 v0, v0, s4 clamp
88; GFX8-NEXT:    s_setpc_b64 s[30:31]
89;
90; GFX9-LABEL: usubsat_as_bithack_i16:
91; GFX9:       ; %bb.0:
92; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
93; GFX9-NEXT:    s_movk_i32 s4, 0x8000
94; GFX9-NEXT:    v_sub_u16_e64 v0, v0, s4 clamp
95; GFX9-NEXT:    s_setpc_b64 s[30:31]
96;
97; GFX10-LABEL: usubsat_as_bithack_i16:
98; GFX10:       ; %bb.0:
99; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
100; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
101; GFX10-NEXT:    v_sub_nc_u16 v0, v0, 0x8000 clamp
102; GFX10-NEXT:    s_setpc_b64 s[30:31]
103  %signsplat = ashr i16 %x, 15
104  %flipsign = xor i16 %x, 32768
105  %result = and i16 %signsplat, %flipsign
106  ret i16 %result
107}
108
109define i16 @usubsat_as_bithack2_i16(i16 %x) {
110; GFX6-LABEL: usubsat_as_bithack2_i16:
111; GFX6:       ; %bb.0:
112; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
113; GFX6-NEXT:    v_bfe_i32 v1, v0, 0, 16
114; GFX6-NEXT:    v_ashrrev_i32_e32 v1, 15, v1
115; GFX6-NEXT:    v_add_i32_e32 v0, vcc, 0xffff8000, v0
116; GFX6-NEXT:    v_and_b32_e32 v0, v1, v0
117; GFX6-NEXT:    s_setpc_b64 s[30:31]
118;
119; GFX8-LABEL: usubsat_as_bithack2_i16:
120; GFX8:       ; %bb.0:
121; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
122; GFX8-NEXT:    s_movk_i32 s4, 0x8000
123; GFX8-NEXT:    v_sub_u16_e64 v0, v0, s4 clamp
124; GFX8-NEXT:    s_setpc_b64 s[30:31]
125;
126; GFX9-LABEL: usubsat_as_bithack2_i16:
127; GFX9:       ; %bb.0:
128; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
129; GFX9-NEXT:    s_movk_i32 s4, 0x8000
130; GFX9-NEXT:    v_sub_u16_e64 v0, v0, s4 clamp
131; GFX9-NEXT:    s_setpc_b64 s[30:31]
132;
133; GFX10-LABEL: usubsat_as_bithack2_i16:
134; GFX10:       ; %bb.0:
135; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
136; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
137; GFX10-NEXT:    v_sub_nc_u16 v0, v0, 0x8000 clamp
138; GFX10-NEXT:    s_setpc_b64 s[30:31]
139  %signsplat = ashr i16 %x, 15
140  %flipsign = add i16 %x, 32768
141  %result = and i16 %signsplat, %flipsign
142  ret i16 %result
143}
144
145define i16 @usubsat_as_bithack_commute_i16(i16 %x) {
146; GFX6-LABEL: usubsat_as_bithack_commute_i16:
147; GFX6:       ; %bb.0:
148; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
149; GFX6-NEXT:    v_bfe_i32 v1, v0, 0, 16
150; GFX6-NEXT:    v_ashrrev_i32_e32 v1, 15, v1
151; GFX6-NEXT:    v_add_i32_e32 v0, vcc, 0xffff8000, v0
152; GFX6-NEXT:    v_and_b32_e32 v0, v0, v1
153; GFX6-NEXT:    s_setpc_b64 s[30:31]
154;
155; GFX8-LABEL: usubsat_as_bithack_commute_i16:
156; GFX8:       ; %bb.0:
157; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
158; GFX8-NEXT:    s_movk_i32 s4, 0x8000
159; GFX8-NEXT:    v_sub_u16_e64 v0, v0, s4 clamp
160; GFX8-NEXT:    s_setpc_b64 s[30:31]
161;
162; GFX9-LABEL: usubsat_as_bithack_commute_i16:
163; GFX9:       ; %bb.0:
164; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
165; GFX9-NEXT:    s_movk_i32 s4, 0x8000
166; GFX9-NEXT:    v_sub_u16_e64 v0, v0, s4 clamp
167; GFX9-NEXT:    s_setpc_b64 s[30:31]
168;
169; GFX10-LABEL: usubsat_as_bithack_commute_i16:
170; GFX10:       ; %bb.0:
171; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
172; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
173; GFX10-NEXT:    v_sub_nc_u16 v0, v0, 0x8000 clamp
174; GFX10-NEXT:    s_setpc_b64 s[30:31]
175  %signsplat = ashr i16 %x, 15
176  %flipsign = add i16 %x, 32768
177  %result = and i16 %flipsign, %signsplat
178  ret i16 %result
179}
180
181define i32 @v_usubsat_i32(i32 %lhs, i32 %rhs) {
182; GFX6-LABEL: v_usubsat_i32:
183; GFX6:       ; %bb.0:
184; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
185; GFX6-NEXT:    v_max_u32_e32 v0, v0, v1
186; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
187; GFX6-NEXT:    s_setpc_b64 s[30:31]
188;
189; GFX8-LABEL: v_usubsat_i32:
190; GFX8:       ; %bb.0:
191; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
192; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v1 clamp
193; GFX8-NEXT:    s_setpc_b64 s[30:31]
194;
195; GFX9-LABEL: v_usubsat_i32:
196; GFX9:       ; %bb.0:
197; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
198; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v1 clamp
199; GFX9-NEXT:    s_setpc_b64 s[30:31]
200;
201; GFX10-LABEL: v_usubsat_i32:
202; GFX10:       ; %bb.0:
203; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
204; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
205; GFX10-NEXT:    v_sub_nc_u32_e64 v0, v0, v1 clamp
206; GFX10-NEXT:    s_setpc_b64 s[30:31]
207  %result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)
208  ret i32 %result
209}
210
211define <2 x i16> @v_usubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
212; GFX6-LABEL: v_usubsat_v2i16:
213; GFX6:       ; %bb.0:
214; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
215; GFX6-NEXT:    v_and_b32_e32 v4, 0xffff, v3
216; GFX6-NEXT:    v_and_b32_e32 v1, 0xffff, v1
217; GFX6-NEXT:    v_and_b32_e32 v2, 0xffff, v2
218; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v0
219; GFX6-NEXT:    v_max_u32_e32 v1, v1, v4
220; GFX6-NEXT:    v_max_u32_e32 v0, v0, v2
221; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v3
222; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
223; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
224; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
225; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
226; GFX6-NEXT:    s_setpc_b64 s[30:31]
227;
228; GFX8-LABEL: v_usubsat_v2i16:
229; GFX8:       ; %bb.0:
230; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
231; GFX8-NEXT:    v_sub_u16_sdwa v2, v0, v1 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
232; GFX8-NEXT:    v_sub_u16_e64 v0, v0, v1 clamp
233; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
234; GFX8-NEXT:    s_setpc_b64 s[30:31]
235;
236; GFX9-LABEL: v_usubsat_v2i16:
237; GFX9:       ; %bb.0:
238; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
239; GFX9-NEXT:    v_pk_sub_u16 v0, v0, v1 clamp
240; GFX9-NEXT:    s_setpc_b64 s[30:31]
241;
242; GFX10-LABEL: v_usubsat_v2i16:
243; GFX10:       ; %bb.0:
244; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
245; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
246; GFX10-NEXT:    v_pk_sub_u16 v0, v0, v1 clamp
247; GFX10-NEXT:    s_setpc_b64 s[30:31]
248  %result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
249  ret <2 x i16> %result
250}
251
252define <3 x i16> @v_usubsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) {
253; GFX6-LABEL: v_usubsat_v3i16:
254; GFX6:       ; %bb.0:
255; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
256; GFX6-NEXT:    v_and_b32_e32 v6, 0xffff, v4
257; GFX6-NEXT:    v_and_b32_e32 v1, 0xffff, v1
258; GFX6-NEXT:    v_and_b32_e32 v3, 0xffff, v3
259; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v0
260; GFX6-NEXT:    v_max_u32_e32 v1, v1, v6
261; GFX6-NEXT:    v_max_u32_e32 v0, v0, v3
262; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v4
263; GFX6-NEXT:    v_and_b32_e32 v5, 0xffff, v5
264; GFX6-NEXT:    v_and_b32_e32 v2, 0xffff, v2
265; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v3
266; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
267; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
268; GFX6-NEXT:    v_max_u32_e32 v1, v2, v5
269; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v1, v5
270; GFX6-NEXT:    v_alignbit_b32 v1, v2, v0, 16
271; GFX6-NEXT:    s_setpc_b64 s[30:31]
272;
273; GFX8-LABEL: v_usubsat_v3i16:
274; GFX8:       ; %bb.0:
275; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
276; GFX8-NEXT:    v_sub_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
277; GFX8-NEXT:    v_sub_u16_e64 v0, v0, v2 clamp
278; GFX8-NEXT:    v_sub_u16_e64 v1, v1, v3 clamp
279; GFX8-NEXT:    v_or_b32_e32 v0, v0, v4
280; GFX8-NEXT:    s_setpc_b64 s[30:31]
281;
282; GFX9-LABEL: v_usubsat_v3i16:
283; GFX9:       ; %bb.0:
284; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
285; GFX9-NEXT:    v_pk_sub_u16 v1, v1, v3 clamp
286; GFX9-NEXT:    v_pk_sub_u16 v0, v0, v2 clamp
287; GFX9-NEXT:    s_setpc_b64 s[30:31]
288;
289; GFX10-LABEL: v_usubsat_v3i16:
290; GFX10:       ; %bb.0:
291; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
292; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
293; GFX10-NEXT:    v_pk_sub_u16 v0, v0, v2 clamp
294; GFX10-NEXT:    v_pk_sub_u16 v1, v1, v3 clamp
295; GFX10-NEXT:    s_setpc_b64 s[30:31]
296  %result = call <3 x i16> @llvm.usub.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)
297  ret <3 x i16> %result
298}
299
300define <2 x float> @v_usubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
301; GFX6-LABEL: v_usubsat_v4i16:
302; GFX6:       ; %bb.0:
303; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
304; GFX6-NEXT:    v_and_b32_e32 v9, 0xffff, v5
305; GFX6-NEXT:    v_and_b32_e32 v1, 0xffff, v1
306; GFX6-NEXT:    v_and_b32_e32 v4, 0xffff, v4
307; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v0
308; GFX6-NEXT:    v_max_u32_e32 v1, v1, v9
309; GFX6-NEXT:    v_max_u32_e32 v0, v0, v4
310; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v5
311; GFX6-NEXT:    v_and_b32_e32 v8, 0xffff, v7
312; GFX6-NEXT:    v_and_b32_e32 v3, 0xffff, v3
313; GFX6-NEXT:    v_and_b32_e32 v6, 0xffff, v6
314; GFX6-NEXT:    v_and_b32_e32 v2, 0xffff, v2
315; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
316; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
317; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
318; GFX6-NEXT:    v_max_u32_e32 v1, v2, v6
319; GFX6-NEXT:    v_max_u32_e32 v2, v3, v8
320; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v7
321; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v6
322; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
323; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
324; GFX6-NEXT:    s_setpc_b64 s[30:31]
325;
326; GFX8-LABEL: v_usubsat_v4i16:
327; GFX8:       ; %bb.0:
328; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
329; GFX8-NEXT:    v_sub_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
330; GFX8-NEXT:    v_sub_u16_e64 v0, v0, v2 clamp
331; GFX8-NEXT:    v_sub_u16_sdwa v2, v1, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
332; GFX8-NEXT:    v_sub_u16_e64 v1, v1, v3 clamp
333; GFX8-NEXT:    v_or_b32_e32 v0, v0, v4
334; GFX8-NEXT:    v_or_b32_e32 v1, v1, v2
335; GFX8-NEXT:    s_setpc_b64 s[30:31]
336;
337; GFX9-LABEL: v_usubsat_v4i16:
338; GFX9:       ; %bb.0:
339; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
340; GFX9-NEXT:    v_pk_sub_u16 v0, v0, v2 clamp
341; GFX9-NEXT:    v_pk_sub_u16 v1, v1, v3 clamp
342; GFX9-NEXT:    s_setpc_b64 s[30:31]
343;
344; GFX10-LABEL: v_usubsat_v4i16:
345; GFX10:       ; %bb.0:
346; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
347; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
348; GFX10-NEXT:    v_pk_sub_u16 v0, v0, v2 clamp
349; GFX10-NEXT:    v_pk_sub_u16 v1, v1, v3 clamp
350; GFX10-NEXT:    s_setpc_b64 s[30:31]
351  %result = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
352  %cast = bitcast <4 x i16> %result to <2 x float>
353  ret <2 x float> %cast
354}
355
356define <2 x i32> @v_usubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
357; GFX6-LABEL: v_usubsat_v2i32:
358; GFX6:       ; %bb.0:
359; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
360; GFX6-NEXT:    v_max_u32_e32 v0, v0, v2
361; GFX6-NEXT:    v_max_u32_e32 v1, v1, v3
362; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
363; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v3
364; GFX6-NEXT:    s_setpc_b64 s[30:31]
365;
366; GFX8-LABEL: v_usubsat_v2i32:
367; GFX8:       ; %bb.0:
368; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
369; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v2 clamp
370; GFX8-NEXT:    v_sub_u32_e64 v1, s[4:5], v1, v3 clamp
371; GFX8-NEXT:    s_setpc_b64 s[30:31]
372;
373; GFX9-LABEL: v_usubsat_v2i32:
374; GFX9:       ; %bb.0:
375; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
376; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v2 clamp
377; GFX9-NEXT:    v_sub_u32_e64 v1, v1, v3 clamp
378; GFX9-NEXT:    s_setpc_b64 s[30:31]
379;
380; GFX10-LABEL: v_usubsat_v2i32:
381; GFX10:       ; %bb.0:
382; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
383; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
384; GFX10-NEXT:    v_sub_nc_u32_e64 v0, v0, v2 clamp
385; GFX10-NEXT:    v_sub_nc_u32_e64 v1, v1, v3 clamp
386; GFX10-NEXT:    s_setpc_b64 s[30:31]
387  %result = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
388  ret <2 x i32> %result
389}
390
391define <3 x i32> @v_usubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
392; GFX6-LABEL: v_usubsat_v3i32:
393; GFX6:       ; %bb.0:
394; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
395; GFX6-NEXT:    v_max_u32_e32 v0, v0, v3
396; GFX6-NEXT:    v_max_u32_e32 v1, v1, v4
397; GFX6-NEXT:    v_max_u32_e32 v2, v2, v5
398; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v3
399; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v4
400; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v5
401; GFX6-NEXT:    s_setpc_b64 s[30:31]
402;
403; GFX8-LABEL: v_usubsat_v3i32:
404; GFX8:       ; %bb.0:
405; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
406; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v3 clamp
407; GFX8-NEXT:    v_sub_u32_e64 v1, s[4:5], v1, v4 clamp
408; GFX8-NEXT:    v_sub_u32_e64 v2, s[4:5], v2, v5 clamp
409; GFX8-NEXT:    s_setpc_b64 s[30:31]
410;
411; GFX9-LABEL: v_usubsat_v3i32:
412; GFX9:       ; %bb.0:
413; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
414; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v3 clamp
415; GFX9-NEXT:    v_sub_u32_e64 v1, v1, v4 clamp
416; GFX9-NEXT:    v_sub_u32_e64 v2, v2, v5 clamp
417; GFX9-NEXT:    s_setpc_b64 s[30:31]
418;
419; GFX10-LABEL: v_usubsat_v3i32:
420; GFX10:       ; %bb.0:
421; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
422; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
423; GFX10-NEXT:    v_sub_nc_u32_e64 v0, v0, v3 clamp
424; GFX10-NEXT:    v_sub_nc_u32_e64 v1, v1, v4 clamp
425; GFX10-NEXT:    v_sub_nc_u32_e64 v2, v2, v5 clamp
426; GFX10-NEXT:    s_setpc_b64 s[30:31]
427  %result = call <3 x i32> @llvm.usub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
428  ret <3 x i32> %result
429}
430
431define <4 x i32> @v_usubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
432; GFX6-LABEL: v_usubsat_v4i32:
433; GFX6:       ; %bb.0:
434; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
435; GFX6-NEXT:    v_max_u32_e32 v0, v0, v4
436; GFX6-NEXT:    v_max_u32_e32 v1, v1, v5
437; GFX6-NEXT:    v_max_u32_e32 v2, v2, v6
438; GFX6-NEXT:    v_max_u32_e32 v3, v3, v7
439; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
440; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v5
441; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
442; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, v3, v7
443; GFX6-NEXT:    s_setpc_b64 s[30:31]
444;
445; GFX8-LABEL: v_usubsat_v4i32:
446; GFX8:       ; %bb.0:
447; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
448; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v4 clamp
449; GFX8-NEXT:    v_sub_u32_e64 v1, s[4:5], v1, v5 clamp
450; GFX8-NEXT:    v_sub_u32_e64 v2, s[4:5], v2, v6 clamp
451; GFX8-NEXT:    v_sub_u32_e64 v3, s[4:5], v3, v7 clamp
452; GFX8-NEXT:    s_setpc_b64 s[30:31]
453;
454; GFX9-LABEL: v_usubsat_v4i32:
455; GFX9:       ; %bb.0:
456; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
457; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v4 clamp
458; GFX9-NEXT:    v_sub_u32_e64 v1, v1, v5 clamp
459; GFX9-NEXT:    v_sub_u32_e64 v2, v2, v6 clamp
460; GFX9-NEXT:    v_sub_u32_e64 v3, v3, v7 clamp
461; GFX9-NEXT:    s_setpc_b64 s[30:31]
462;
463; GFX10-LABEL: v_usubsat_v4i32:
464; GFX10:       ; %bb.0:
465; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
466; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
467; GFX10-NEXT:    v_sub_nc_u32_e64 v0, v0, v4 clamp
468; GFX10-NEXT:    v_sub_nc_u32_e64 v1, v1, v5 clamp
469; GFX10-NEXT:    v_sub_nc_u32_e64 v2, v2, v6 clamp
470; GFX10-NEXT:    v_sub_nc_u32_e64 v3, v3, v7 clamp
471; GFX10-NEXT:    s_setpc_b64 s[30:31]
472  %result = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
473  ret <4 x i32> %result
474}
475
476define <8 x i32> @v_usubsat_v8i32(<8 x i32> %lhs, <8 x i32> %rhs) {
477; GFX6-LABEL: v_usubsat_v8i32:
478; GFX6:       ; %bb.0:
479; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
480; GFX6-NEXT:    v_max_u32_e32 v0, v0, v8
481; GFX6-NEXT:    v_max_u32_e32 v1, v1, v9
482; GFX6-NEXT:    v_max_u32_e32 v2, v2, v10
483; GFX6-NEXT:    v_max_u32_e32 v3, v3, v11
484; GFX6-NEXT:    v_max_u32_e32 v4, v4, v12
485; GFX6-NEXT:    v_max_u32_e32 v5, v5, v13
486; GFX6-NEXT:    v_max_u32_e32 v6, v6, v14
487; GFX6-NEXT:    v_max_u32_e32 v7, v7, v15
488; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
489; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v9
490; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v10
491; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, v3, v11
492; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, v4, v12
493; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, v5, v13
494; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, v6, v14
495; GFX6-NEXT:    v_sub_i32_e32 v7, vcc, v7, v15
496; GFX6-NEXT:    s_setpc_b64 s[30:31]
497;
498; GFX8-LABEL: v_usubsat_v8i32:
499; GFX8:       ; %bb.0:
500; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
501; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v8 clamp
502; GFX8-NEXT:    v_sub_u32_e64 v1, s[4:5], v1, v9 clamp
503; GFX8-NEXT:    v_sub_u32_e64 v2, s[4:5], v2, v10 clamp
504; GFX8-NEXT:    v_sub_u32_e64 v3, s[4:5], v3, v11 clamp
505; GFX8-NEXT:    v_sub_u32_e64 v4, s[4:5], v4, v12 clamp
506; GFX8-NEXT:    v_sub_u32_e64 v5, s[4:5], v5, v13 clamp
507; GFX8-NEXT:    v_sub_u32_e64 v6, s[4:5], v6, v14 clamp
508; GFX8-NEXT:    v_sub_u32_e64 v7, s[4:5], v7, v15 clamp
509; GFX8-NEXT:    s_setpc_b64 s[30:31]
510;
511; GFX9-LABEL: v_usubsat_v8i32:
512; GFX9:       ; %bb.0:
513; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
514; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v8 clamp
515; GFX9-NEXT:    v_sub_u32_e64 v1, v1, v9 clamp
516; GFX9-NEXT:    v_sub_u32_e64 v2, v2, v10 clamp
517; GFX9-NEXT:    v_sub_u32_e64 v3, v3, v11 clamp
518; GFX9-NEXT:    v_sub_u32_e64 v4, v4, v12 clamp
519; GFX9-NEXT:    v_sub_u32_e64 v5, v5, v13 clamp
520; GFX9-NEXT:    v_sub_u32_e64 v6, v6, v14 clamp
521; GFX9-NEXT:    v_sub_u32_e64 v7, v7, v15 clamp
522; GFX9-NEXT:    s_setpc_b64 s[30:31]
523;
524; GFX10-LABEL: v_usubsat_v8i32:
525; GFX10:       ; %bb.0:
526; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
527; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
528; GFX10-NEXT:    v_sub_nc_u32_e64 v0, v0, v8 clamp
529; GFX10-NEXT:    v_sub_nc_u32_e64 v1, v1, v9 clamp
530; GFX10-NEXT:    v_sub_nc_u32_e64 v2, v2, v10 clamp
531; GFX10-NEXT:    v_sub_nc_u32_e64 v3, v3, v11 clamp
532; GFX10-NEXT:    v_sub_nc_u32_e64 v4, v4, v12 clamp
533; GFX10-NEXT:    v_sub_nc_u32_e64 v5, v5, v13 clamp
534; GFX10-NEXT:    v_sub_nc_u32_e64 v6, v6, v14 clamp
535; GFX10-NEXT:    v_sub_nc_u32_e64 v7, v7, v15 clamp
536; GFX10-NEXT:    s_setpc_b64 s[30:31]
537  %result = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> %lhs, <8 x i32> %rhs)
538  ret <8 x i32> %result
539}
540
541define <16 x i32> @v_usubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
542; GFX6-LABEL: v_usubsat_v16i32:
543; GFX6:       ; %bb.0:
544; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
545; GFX6-NEXT:    v_max_u32_e32 v0, v0, v16
546; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v16
547; GFX6-NEXT:    buffer_load_dword v16, off, s[0:3], s32
548; GFX6-NEXT:    v_max_u32_e32 v1, v1, v17
549; GFX6-NEXT:    v_max_u32_e32 v2, v2, v18
550; GFX6-NEXT:    v_max_u32_e32 v3, v3, v19
551; GFX6-NEXT:    v_max_u32_e32 v4, v4, v20
552; GFX6-NEXT:    v_max_u32_e32 v5, v5, v21
553; GFX6-NEXT:    v_max_u32_e32 v6, v6, v22
554; GFX6-NEXT:    v_max_u32_e32 v7, v7, v23
555; GFX6-NEXT:    v_max_u32_e32 v8, v8, v24
556; GFX6-NEXT:    v_max_u32_e32 v9, v9, v25
557; GFX6-NEXT:    v_max_u32_e32 v10, v10, v26
558; GFX6-NEXT:    v_max_u32_e32 v11, v11, v27
559; GFX6-NEXT:    v_max_u32_e32 v12, v12, v28
560; GFX6-NEXT:    v_max_u32_e32 v13, v13, v29
561; GFX6-NEXT:    v_max_u32_e32 v14, v14, v30
562; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v17
563; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v18
564; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, v3, v19
565; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, v4, v20
566; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, v5, v21
567; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, v6, v22
568; GFX6-NEXT:    v_sub_i32_e32 v7, vcc, v7, v23
569; GFX6-NEXT:    v_sub_i32_e32 v8, vcc, v8, v24
570; GFX6-NEXT:    v_sub_i32_e32 v9, vcc, v9, v25
571; GFX6-NEXT:    v_sub_i32_e32 v10, vcc, v10, v26
572; GFX6-NEXT:    v_sub_i32_e32 v11, vcc, v11, v27
573; GFX6-NEXT:    v_sub_i32_e32 v12, vcc, v12, v28
574; GFX6-NEXT:    v_sub_i32_e32 v13, vcc, v13, v29
575; GFX6-NEXT:    v_sub_i32_e32 v14, vcc, v14, v30
576; GFX6-NEXT:    s_waitcnt vmcnt(0)
577; GFX6-NEXT:    v_max_u32_e32 v15, v15, v16
578; GFX6-NEXT:    v_sub_i32_e32 v15, vcc, v15, v16
579; GFX6-NEXT:    s_setpc_b64 s[30:31]
580;
581; GFX8-LABEL: v_usubsat_v16i32:
582; GFX8:       ; %bb.0:
583; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
584; GFX8-NEXT:    v_sub_u32_e64 v0, s[4:5], v0, v16 clamp
585; GFX8-NEXT:    buffer_load_dword v16, off, s[0:3], s32
586; GFX8-NEXT:    v_sub_u32_e64 v1, s[4:5], v1, v17 clamp
587; GFX8-NEXT:    v_sub_u32_e64 v2, s[4:5], v2, v18 clamp
588; GFX8-NEXT:    v_sub_u32_e64 v3, s[4:5], v3, v19 clamp
589; GFX8-NEXT:    v_sub_u32_e64 v4, s[4:5], v4, v20 clamp
590; GFX8-NEXT:    v_sub_u32_e64 v5, s[4:5], v5, v21 clamp
591; GFX8-NEXT:    v_sub_u32_e64 v6, s[4:5], v6, v22 clamp
592; GFX8-NEXT:    v_sub_u32_e64 v7, s[4:5], v7, v23 clamp
593; GFX8-NEXT:    v_sub_u32_e64 v8, s[4:5], v8, v24 clamp
594; GFX8-NEXT:    v_sub_u32_e64 v9, s[4:5], v9, v25 clamp
595; GFX8-NEXT:    v_sub_u32_e64 v10, s[4:5], v10, v26 clamp
596; GFX8-NEXT:    v_sub_u32_e64 v11, s[4:5], v11, v27 clamp
597; GFX8-NEXT:    v_sub_u32_e64 v12, s[4:5], v12, v28 clamp
598; GFX8-NEXT:    v_sub_u32_e64 v13, s[4:5], v13, v29 clamp
599; GFX8-NEXT:    v_sub_u32_e64 v14, s[4:5], v14, v30 clamp
600; GFX8-NEXT:    s_waitcnt vmcnt(0)
601; GFX8-NEXT:    v_sub_u32_e64 v15, s[4:5], v15, v16 clamp
602; GFX8-NEXT:    s_setpc_b64 s[30:31]
603;
604; GFX9-LABEL: v_usubsat_v16i32:
605; GFX9:       ; %bb.0:
606; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
607; GFX9-NEXT:    v_sub_u32_e64 v0, v0, v16 clamp
608; GFX9-NEXT:    buffer_load_dword v16, off, s[0:3], s32
609; GFX9-NEXT:    v_sub_u32_e64 v1, v1, v17 clamp
610; GFX9-NEXT:    v_sub_u32_e64 v2, v2, v18 clamp
611; GFX9-NEXT:    v_sub_u32_e64 v3, v3, v19 clamp
612; GFX9-NEXT:    v_sub_u32_e64 v4, v4, v20 clamp
613; GFX9-NEXT:    v_sub_u32_e64 v5, v5, v21 clamp
614; GFX9-NEXT:    v_sub_u32_e64 v6, v6, v22 clamp
615; GFX9-NEXT:    v_sub_u32_e64 v7, v7, v23 clamp
616; GFX9-NEXT:    v_sub_u32_e64 v8, v8, v24 clamp
617; GFX9-NEXT:    v_sub_u32_e64 v9, v9, v25 clamp
618; GFX9-NEXT:    v_sub_u32_e64 v10, v10, v26 clamp
619; GFX9-NEXT:    v_sub_u32_e64 v11, v11, v27 clamp
620; GFX9-NEXT:    v_sub_u32_e64 v12, v12, v28 clamp
621; GFX9-NEXT:    v_sub_u32_e64 v13, v13, v29 clamp
622; GFX9-NEXT:    v_sub_u32_e64 v14, v14, v30 clamp
623; GFX9-NEXT:    s_waitcnt vmcnt(0)
624; GFX9-NEXT:    v_sub_u32_e64 v15, v15, v16 clamp
625; GFX9-NEXT:    s_setpc_b64 s[30:31]
626;
627; GFX10-LABEL: v_usubsat_v16i32:
628; GFX10:       ; %bb.0:
629; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
630; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
631; GFX10-NEXT:    buffer_load_dword v31, off, s[0:3], s32
632; GFX10-NEXT:    v_sub_nc_u32_e64 v0, v0, v16 clamp
633; GFX10-NEXT:    v_sub_nc_u32_e64 v1, v1, v17 clamp
634; GFX10-NEXT:    v_sub_nc_u32_e64 v2, v2, v18 clamp
635; GFX10-NEXT:    v_sub_nc_u32_e64 v3, v3, v19 clamp
636; GFX10-NEXT:    v_sub_nc_u32_e64 v4, v4, v20 clamp
637; GFX10-NEXT:    v_sub_nc_u32_e64 v5, v5, v21 clamp
638; GFX10-NEXT:    v_sub_nc_u32_e64 v6, v6, v22 clamp
639; GFX10-NEXT:    v_sub_nc_u32_e64 v7, v7, v23 clamp
640; GFX10-NEXT:    v_sub_nc_u32_e64 v8, v8, v24 clamp
641; GFX10-NEXT:    v_sub_nc_u32_e64 v9, v9, v25 clamp
642; GFX10-NEXT:    v_sub_nc_u32_e64 v10, v10, v26 clamp
643; GFX10-NEXT:    v_sub_nc_u32_e64 v11, v11, v27 clamp
644; GFX10-NEXT:    v_sub_nc_u32_e64 v12, v12, v28 clamp
645; GFX10-NEXT:    v_sub_nc_u32_e64 v13, v13, v29 clamp
646; GFX10-NEXT:    v_sub_nc_u32_e64 v14, v14, v30 clamp
647; GFX10-NEXT:    s_waitcnt vmcnt(0)
648; GFX10-NEXT:    v_sub_nc_u32_e64 v15, v15, v31 clamp
649; GFX10-NEXT:    s_setpc_b64 s[30:31]
650  %result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
651  ret <16 x i32> %result
652}
653
654
655define i64 @v_usubsat_i64(i64 %lhs, i64 %rhs) {
656; GFX6-LABEL: v_usubsat_i64:
657; GFX6:       ; %bb.0:
658; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
659; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v0, v2
660; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v1, v3, vcc
661; GFX6-NEXT:    v_cmp_gt_u64_e32 vcc, v[2:3], v[0:1]
662; GFX6-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc
663; GFX6-NEXT:    v_cndmask_b32_e64 v1, v3, 0, vcc
664; GFX6-NEXT:    s_setpc_b64 s[30:31]
665;
666; GFX8-LABEL: v_usubsat_i64:
667; GFX8:       ; %bb.0:
668; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
669; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, v0, v2
670; GFX8-NEXT:    v_subb_u32_e32 v3, vcc, v1, v3, vcc
671; GFX8-NEXT:    v_cmp_gt_u64_e32 vcc, v[2:3], v[0:1]
672; GFX8-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc
673; GFX8-NEXT:    v_cndmask_b32_e64 v1, v3, 0, vcc
674; GFX8-NEXT:    s_setpc_b64 s[30:31]
675;
676; GFX9-LABEL: v_usubsat_i64:
677; GFX9:       ; %bb.0:
678; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
679; GFX9-NEXT:    v_sub_co_u32_e32 v2, vcc, v0, v2
680; GFX9-NEXT:    v_subb_co_u32_e32 v3, vcc, v1, v3, vcc
681; GFX9-NEXT:    v_cmp_gt_u64_e32 vcc, v[2:3], v[0:1]
682; GFX9-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc
683; GFX9-NEXT:    v_cndmask_b32_e64 v1, v3, 0, vcc
684; GFX9-NEXT:    s_setpc_b64 s[30:31]
685;
686; GFX10-LABEL: v_usubsat_i64:
687; GFX10:       ; %bb.0:
688; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
689; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
690; GFX10-NEXT:    v_sub_co_u32 v2, vcc_lo, v0, v2
691; GFX10-NEXT:    v_sub_co_ci_u32_e32 v3, vcc_lo, v1, v3, vcc_lo
692; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[0:1]
693; GFX10-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc_lo
694; GFX10-NEXT:    v_cndmask_b32_e64 v1, v3, 0, vcc_lo
695; GFX10-NEXT:    s_setpc_b64 s[30:31]
696  %result = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)
697  ret i64 %result
698}
699
700declare i8 @llvm.usub.sat.i8(i8, i8) #0
701declare i16 @llvm.usub.sat.i16(i16, i16) #0
702declare <2 x i16> @llvm.usub.sat.v2i16(<2 x i16>, <2 x i16>) #0
703declare <3 x i16> @llvm.usub.sat.v3i16(<3 x i16>, <3 x i16>) #0
704declare <4 x i16> @llvm.usub.sat.v4i16(<4 x i16>, <4 x i16>) #0
705declare i32 @llvm.usub.sat.i32(i32, i32) #0
706declare <2 x i32> @llvm.usub.sat.v2i32(<2 x i32>, <2 x i32>) #0
707declare <3 x i32> @llvm.usub.sat.v3i32(<3 x i32>, <3 x i32>) #0
708declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>) #0
709declare <8 x i32> @llvm.usub.sat.v8i32(<8 x i32>, <8 x i32>) #0
710declare <16 x i32> @llvm.usub.sat.v16i32(<16 x i32>, <16 x i32>) #0
711declare i64 @llvm.usub.sat.i64(i64, i64) #0
712
713attributes #0 = { nounwind readnone speculatable willreturn }
714