1; RUN: llc -march=amdgcn -mcpu=verde -amdgpu-early-ifcvt=0 -machine-sink-split-probability-threshold=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s 2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-early-ifcvt=0 -machine-sink-split-probability-threshold=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s 3 4; GCN-LABEL: {{^}}uniform_if_scc: 5; GCN-DAG: s_cmp_eq_u32 s{{[0-9]+}}, 0 6; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 7; GCN: s_cbranch_scc1 [[IF_LABEL:[0-9_A-Za-z]+]] 8 9; Fall-through to the else 10; GCN: s_mov_b32 [[S_VAL]], 1 11 12; GCN: [[IF_LABEL]]: 13; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] 14; GCN: buffer_store_dword [[V_VAL]] 15define amdgpu_kernel void @uniform_if_scc(i32 %cond, i32 addrspace(1)* %out) { 16entry: 17 %cmp0 = icmp eq i32 %cond, 0 18 br i1 %cmp0, label %if, label %else 19 20if: 21 br label %done 22 23else: 24 br label %done 25 26done: 27 %value = phi i32 [0, %if], [1, %else] 28 store i32 %value, i32 addrspace(1)* %out 29 ret void 30} 31 32; GCN-LABEL: {{^}}uniform_if_vcc: 33; GCN-DAG: v_cmp_eq_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0{{$}} 34; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 35; GCN: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]] 36 37; Fall-through to the else 38; GCN: s_mov_b32 [[S_VAL]], 1 39 40; GCN: [[IF_LABEL]]: 41; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] 42; GCN: buffer_store_dword [[V_VAL]] 43define amdgpu_kernel void @uniform_if_vcc(float %cond, i32 addrspace(1)* %out) { 44entry: 45 %cmp0 = fcmp oeq float %cond, 0.0 46 br i1 %cmp0, label %if, label %else 47 48if: 49 br label %done 50 51else: 52 br label %done 53 54done: 55 %value = phi i32 [0, %if], [1, %else] 56 store i32 %value, i32 addrspace(1)* %out 57 ret void 58} 59 60; GCN-LABEL: {{^}}uniform_if_swap_br_targets_scc: 61; GCN-DAG: s_cmp_lg_u32 s{{[0-9]+}}, 0 62; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 63; GCN: s_cbranch_scc1 [[IF_LABEL:[0-9_A-Za-z]+]] 64 65; Fall-through to the else 66; GCN: s_mov_b32 [[S_VAL]], 1 67 68; GCN: [[IF_LABEL]]: 69; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] 70; GCN: buffer_store_dword [[V_VAL]] 71define amdgpu_kernel void @uniform_if_swap_br_targets_scc(i32 %cond, i32 addrspace(1)* %out) { 72entry: 73 %cmp0 = icmp eq i32 %cond, 0 74 br i1 %cmp0, label %else, label %if 75 76if: 77 br label %done 78 79else: 80 br label %done 81 82done: 83 %value = phi i32 [0, %if], [1, %else] 84 store i32 %value, i32 addrspace(1)* %out 85 ret void 86} 87 88; GCN-LABEL: {{^}}uniform_if_swap_br_targets_vcc: 89; GCN-DAG: v_cmp_neq_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0{{$}} 90; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 91; GCN: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]] 92 93; Fall-through to the else 94; GCN: s_mov_b32 [[S_VAL]], 1 95 96; GCN: [[IF_LABEL]]: 97; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] 98; GCN: buffer_store_dword [[V_VAL]] 99define amdgpu_kernel void @uniform_if_swap_br_targets_vcc(float %cond, i32 addrspace(1)* %out) { 100entry: 101 %cmp0 = fcmp oeq float %cond, 0.0 102 br i1 %cmp0, label %else, label %if 103 104if: 105 br label %done 106 107else: 108 br label %done 109 110done: 111 %value = phi i32 [0, %if], [1, %else] 112 store i32 %value, i32 addrspace(1)* %out 113 ret void 114} 115 116; GCN-LABEL: {{^}}uniform_if_move_valu: 117; GCN: v_add_f32_e32 [[CMP:v[0-9]+]] 118; Using a floating-point value in an integer compare will cause the compare to 119; be selected for the SALU and then later moved to the VALU. 120; GCN: v_cmp_ne_u32_e32 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 5, [[CMP]] 121; GCN: s_and_b64 vcc, exec, [[COND]] 122; GCN: s_cbranch_vccnz [[ENDIF_LABEL:[0-9_A-Za-z]+]] 123; GCN: buffer_store_dword 124; GCN: [[ENDIF_LABEL]]: 125; GCN: s_endpgm 126define amdgpu_kernel void @uniform_if_move_valu(i32 addrspace(1)* %out, float %a) { 127entry: 128 %a.0 = fadd float %a, 10.0 129 %cond = bitcast float %a.0 to i32 130 %cmp = icmp eq i32 %cond, 5 131 br i1 %cmp, label %if, label %endif 132 133if: 134 store i32 0, i32 addrspace(1)* %out 135 br label %endif 136 137endif: 138 ret void 139} 140 141; GCN-LABEL: {{^}}uniform_if_move_valu_commute: 142; GCN: v_add_f32_e32 [[CMP:v[0-9]+]] 143; Using a floating-point value in an integer compare will cause the compare to 144; be selected for the SALU and then later moved to the VALU. 145; GCN: v_cmp_gt_u32_e32 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 6, [[CMP]] 146; GCN: s_and_b64 vcc, exec, [[COND]] 147; GCN: s_cbranch_vccnz [[ENDIF_LABEL:[0-9_A-Za-z]+]] 148; GCN: buffer_store_dword 149; GCN: [[ENDIF_LABEL]]: 150; GCN: s_endpgm 151define amdgpu_kernel void @uniform_if_move_valu_commute(i32 addrspace(1)* %out, float %a) { 152entry: 153 %a.0 = fadd float %a, 10.0 154 %cond = bitcast float %a.0 to i32 155 %cmp = icmp ugt i32 %cond, 5 156 br i1 %cmp, label %if, label %endif 157 158if: 159 store i32 0, i32 addrspace(1)* %out 160 br label %endif 161 162endif: 163 ret void 164} 165 166 167; GCN-LABEL: {{^}}uniform_if_else_ret: 168; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0 169; GCN: s_cbranch_scc0 [[IF_LABEL:[0-9_A-Za-z]+]] 170 171; GCN: v_mov_b32_e32 [[TWO:v[0-9]+]], 2 172; GCN: buffer_store_dword [[TWO]] 173; GCN: s_endpgm 174 175; GCN: {{^}}[[IF_LABEL]]: 176; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 177; GCN: buffer_store_dword [[ONE]] 178; GCN: s_endpgm 179define amdgpu_kernel void @uniform_if_else_ret(i32 addrspace(1)* nocapture %out, i32 %a) { 180entry: 181 %cmp = icmp eq i32 %a, 0 182 br i1 %cmp, label %if.then, label %if.else 183 184if.then: ; preds = %entry 185 store i32 1, i32 addrspace(1)* %out 186 br label %if.end 187 188if.else: ; preds = %entry 189 store i32 2, i32 addrspace(1)* %out 190 br label %if.end 191 192if.end: ; preds = %if.else, %if.then 193 ret void 194} 195 196; GCN-LABEL: {{^}}uniform_if_else: 197; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0 198; GCN: s_cbranch_scc0 [[IF_LABEL:[0-9_A-Za-z]+]] 199 200; GCN: v_mov_b32_e32 [[IMM_REG:v[0-9]+]], 2 201; GCN: s_branch [[ENDIF_LABEL:[0-9_A-Za-z]+]] 202 203; GCN: [[IF_LABEL]]: 204; GCN-NEXT: v_mov_b32_e32 [[IMM_REG]], 1 205 206; GCN-NEXT: [[ENDIF_LABEL]]: 207; GCN: buffer_store_dword [[IMM_REG]] 208 209; GCN: v_mov_b32_e32 [[THREE:v[0-9]+]], 3 210; GCN: buffer_store_dword [[THREE]] 211; GCN: s_endpgm 212define amdgpu_kernel void @uniform_if_else(i32 addrspace(1)* nocapture %out0, i32 addrspace(1)* nocapture %out1, i32 %a) { 213entry: 214 %cmp = icmp eq i32 %a, 0 215 br i1 %cmp, label %if.then, label %if.else 216 217if.then: ; preds = %entry 218 store i32 1, i32 addrspace(1)* %out0 219 br label %if.end 220 221if.else: ; preds = %entry 222 store i32 2, i32 addrspace(1)* %out0 223 br label %if.end 224 225if.end: ; preds = %if.else, %if.then 226 store i32 3, i32 addrspace(1)* %out1 227 ret void 228} 229 230; GCN-LABEL: {{^}}icmp_2_users: 231; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 1 232; GCN: s_cbranch_scc1 [[LABEL:[a-zA-Z0-9_]+]] 233; GCN: buffer_store_dword 234; GCN: [[LABEL]]: 235; GCN: s_endpgm 236define amdgpu_kernel void @icmp_2_users(i32 addrspace(1)* %out, i32 %cond) { 237main_body: 238 %0 = icmp sgt i32 %cond, 0 239 %1 = sext i1 %0 to i32 240 br i1 %0, label %IF, label %ENDIF 241 242IF: 243 store i32 %1, i32 addrspace(1)* %out 244 br label %ENDIF 245 246ENDIF: ; preds = %IF, %main_body 247 ret void 248} 249 250; GCN-LABEL: {{^}}icmp_users_different_blocks: 251; GCN: s_load_dwordx2 s{{\[}}[[COND0:[0-9]+]]:[[COND1:[0-9]+]]{{\]}} 252; GCN: s_cmp_lt_i32 s[[COND0]], 1 253; GCN: s_cbranch_scc1 [[EXIT:[A-Za-z0-9_]+]] 254; GCN: v_cmp_gt_i32_e64 {{[^,]*}}, s[[COND1]], 0{{$}} 255; GCN: s_cbranch_vccz [[BODY:[A-Za-z0-9_]+]] 256; GCN: {{^}}[[EXIT]]: 257; GCN: s_endpgm 258; GCN: {{^}}[[BODY]]: 259; GCN: buffer_store 260; GCN: s_endpgm 261define amdgpu_kernel void @icmp_users_different_blocks(i32 %cond0, i32 %cond1, i32 addrspace(1)* %out) { 262bb: 263 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0 264 %cmp0 = icmp sgt i32 %cond0, 0 265 %cmp1 = icmp sgt i32 %cond1, 0 266 br i1 %cmp0, label %bb2, label %bb9 267 268bb2: ; preds = %bb 269 %tmp2 = sext i1 %cmp1 to i32 270 %tmp3 = add i32 %tmp2, %tmp 271 br i1 %cmp1, label %bb9, label %bb7 272 273bb7: ; preds = %bb5 274 store i32 %tmp3, i32 addrspace(1)* %out 275 br label %bb9 276 277bb9: ; preds = %bb8, %bb4 278 ret void 279} 280 281; SI-LABEL: {{^}}uniform_loop: 282; SI: {{^}}[[LOOP_LABEL:[A-Z0-9_a-z]+]]: 283; SI: s_add_i32 [[I:s[0-9]+]], s{{[0-9]+}}, -1 284; SI: s_cmp_lg_u32 [[I]], 0 285; SI: s_cbranch_scc1 [[LOOP_LABEL]] 286; SI: s_endpgm 287define amdgpu_kernel void @uniform_loop(i32 addrspace(1)* %out, i32 %a) { 288entry: 289 br label %loop 290 291loop: 292 %i = phi i32 [0, %entry], [%i.i, %loop] 293 %i.i = add i32 %i, 1 294 %cmp = icmp eq i32 %a, %i.i 295 br i1 %cmp, label %done, label %loop 296 297done: 298 ret void 299} 300 301; Test uniform and divergent. 302 303; GCN-LABEL: {{^}}uniform_inside_divergent: 304; GCN: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}} 305; GCN: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc 306; GCN: s_cmp_lg_u32 {{s[0-9]+}}, 0 307; GCN: s_cbranch_scc0 [[IF_UNIFORM_LABEL:[A-Z0-9_a-z]+]] 308; GCN: s_endpgm 309; GCN: {{^}}[[IF_UNIFORM_LABEL]]: 310; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 311; GCN: buffer_store_dword [[ONE]] 312define amdgpu_kernel void @uniform_inside_divergent(i32 addrspace(1)* %out, i32 %cond) { 313entry: 314 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 315 %d_cmp = icmp ult i32 %tid, 16 316 br i1 %d_cmp, label %if, label %endif 317 318if: 319 store i32 0, i32 addrspace(1)* %out 320 %u_cmp = icmp eq i32 %cond, 0 321 br i1 %u_cmp, label %if_uniform, label %endif 322 323if_uniform: 324 store i32 1, i32 addrspace(1)* %out 325 br label %endif 326 327endif: 328 ret void 329} 330 331; GCN-LABEL: {{^}}divergent_inside_uniform: 332; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0 333; GCN: s_cbranch_scc0 [[IF_LABEL:[0-9_A-Za-z]+]] 334; GCN: [[ENDIF_LABEL:[0-9_A-Za-z]+]]: 335; GCN: [[IF_LABEL]]: 336; GCN: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}} 337; GCN: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc 338; GCN: s_cbranch_execz [[ENDIF_LABEL]] 339; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 340; GCN: buffer_store_dword [[ONE]] 341; GCN: s_endpgm 342define amdgpu_kernel void @divergent_inside_uniform(i32 addrspace(1)* %out, i32 %cond) { 343entry: 344 %u_cmp = icmp eq i32 %cond, 0 345 br i1 %u_cmp, label %if, label %endif 346 347if: 348 store i32 0, i32 addrspace(1)* %out 349 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 350 %d_cmp = icmp ult i32 %tid, 16 351 br i1 %d_cmp, label %if_uniform, label %endif 352 353if_uniform: 354 store i32 1, i32 addrspace(1)* %out 355 br label %endif 356 357endif: 358 ret void 359} 360 361; GCN-LABEL: {{^}}divergent_if_uniform_if: 362; GCN: v_cmp_eq_u32_e32 vcc, 0, v0 363; GCN: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc 364; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 365; GCN: buffer_store_dword [[ONE]] 366; GCN: s_or_b64 exec, exec, [[MASK]] 367; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0 368; GCN: s_cbranch_scc0 [[IF_UNIFORM:[A-Z0-9_]+]] 369; GCN: s_endpgm 370; GCN: [[IF_UNIFORM]]: 371; GCN: v_mov_b32_e32 [[TWO:v[0-9]+]], 2 372; GCN: buffer_store_dword [[TWO]] 373define amdgpu_kernel void @divergent_if_uniform_if(i32 addrspace(1)* %out, i32 %cond) { 374entry: 375 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 376 %d_cmp = icmp eq i32 %tid, 0 377 br i1 %d_cmp, label %if, label %endif 378 379if: 380 store i32 1, i32 addrspace(1)* %out 381 br label %endif 382 383endif: 384 %u_cmp = icmp eq i32 %cond, 0 385 br i1 %u_cmp, label %if_uniform, label %exit 386 387if_uniform: 388 store i32 2, i32 addrspace(1)* %out 389 br label %exit 390 391exit: 392 ret void 393} 394 395; The condition of the branches in the two blocks are 396; uniform. MachineCSE replaces the 2nd condition with the inverse of 397; the first, leaving an scc use in a different block than it was 398; defed. 399 400; GCN-LABEL: {{^}}cse_uniform_condition_different_blocks: 401; GCN: s_load_dword [[COND:s[0-9]+]] 402; GCN: s_cmp_lt_i32 [[COND]], 1 403; GCN: s_cbranch_scc1 BB[[FNNUM:[0-9]+]]_3 404 405; GCN: %bb.1: 406; GCN-NOT: cmp 407; GCN: buffer_load_dword 408; GCN: buffer_store_dword 409; GCN: s_cbranch_scc1 BB[[FNNUM]]_3 410 411; GCN: BB[[FNNUM]]_3: 412; GCN: s_endpgm 413define amdgpu_kernel void @cse_uniform_condition_different_blocks(i32 %cond, i32 addrspace(1)* %out) { 414bb: 415 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0 416 %tmp1 = icmp sgt i32 %cond, 0 417 br i1 %tmp1, label %bb2, label %bb9 418 419bb2: ; preds = %bb 420 %tmp3 = load volatile i32, i32 addrspace(1)* undef 421 store volatile i32 0, i32 addrspace(1)* undef 422 %tmp9 = icmp sle i32 %cond, 0 423 br i1 %tmp9, label %bb9, label %bb7 424 425bb7: ; preds = %bb5 426 store i32 %tmp3, i32 addrspace(1)* %out 427 br label %bb9 428 429bb9: ; preds = %bb8, %bb4 430 ret void 431} 432 433; GCN-LABEL: {{^}}uniform_if_scc_i64_eq: 434; VI-DAG: s_cmp_eq_u64 s{{\[[0-9]+:[0-9]+\]}}, 0 435; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 436; SI-DAG: v_cmp_eq_u64_e64 437; SI: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]] 438 439; VI: s_cbranch_scc1 [[IF_LABEL:[0-9_A-Za-z]+]] 440 441; Fall-through to the else 442; GCN: s_mov_b32 [[S_VAL]], 1 443 444; GCN: [[IF_LABEL]]: 445; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] 446; GCN: buffer_store_dword [[V_VAL]] 447define amdgpu_kernel void @uniform_if_scc_i64_eq(i64 %cond, i32 addrspace(1)* %out) { 448entry: 449 %cmp0 = icmp eq i64 %cond, 0 450 br i1 %cmp0, label %if, label %else 451 452if: 453 br label %done 454 455else: 456 br label %done 457 458done: 459 %value = phi i32 [0, %if], [1, %else] 460 store i32 %value, i32 addrspace(1)* %out 461 ret void 462} 463 464; GCN-LABEL: {{^}}uniform_if_scc_i64_ne: 465; VI-DAG: s_cmp_lg_u64 s{{\[[0-9]+:[0-9]+\]}}, 0 466; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 467 468; SI-DAG: v_cmp_ne_u64_e64 469; SI: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]] 470 471; VI: s_cbranch_scc1 [[IF_LABEL:[0-9_A-Za-z]+]] 472 473; Fall-through to the else 474; GCN: s_mov_b32 [[S_VAL]], 1 475 476; GCN: [[IF_LABEL]]: 477; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] 478; GCN: buffer_store_dword [[V_VAL]] 479define amdgpu_kernel void @uniform_if_scc_i64_ne(i64 %cond, i32 addrspace(1)* %out) { 480entry: 481 %cmp0 = icmp ne i64 %cond, 0 482 br i1 %cmp0, label %if, label %else 483 484if: 485 br label %done 486 487else: 488 br label %done 489 490done: 491 %value = phi i32 [0, %if], [1, %else] 492 store i32 %value, i32 addrspace(1)* %out 493 ret void 494} 495 496; GCN-LABEL: {{^}}uniform_if_scc_i64_sgt: 497; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 498; GCN-DAG: v_cmp_gt_i64_e64 499; GCN: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]] 500 501; Fall-through to the else 502; GCN: s_mov_b32 [[S_VAL]], 1 503 504; GCN: [[IF_LABEL]]: 505; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] 506; GCN: buffer_store_dword [[V_VAL]] 507define amdgpu_kernel void @uniform_if_scc_i64_sgt(i64 %cond, i32 addrspace(1)* %out) { 508entry: 509 %cmp0 = icmp sgt i64 %cond, 0 510 br i1 %cmp0, label %if, label %else 511 512if: 513 br label %done 514 515else: 516 br label %done 517 518done: 519 %value = phi i32 [0, %if], [1, %else] 520 store i32 %value, i32 addrspace(1)* %out 521 ret void 522} 523 524; GCN-LABEL: {{^}}move_to_valu_i64_eq: 525; GCN: v_cmp_eq_u64_e32 526define amdgpu_kernel void @move_to_valu_i64_eq(i32 addrspace(1)* %out) { 527 %cond = load volatile i64, i64 addrspace(3)* undef 528 %cmp0 = icmp eq i64 %cond, 0 529 br i1 %cmp0, label %if, label %else 530 531if: 532 br label %done 533 534else: 535 br label %done 536 537done: 538 %value = phi i32 [0, %if], [1, %else] 539 store i32 %value, i32 addrspace(1)* %out 540 ret void 541} 542 543; GCN-LABEL: {{^}}move_to_valu_i64_ne: 544; GCN: v_cmp_ne_u64_e32 545define amdgpu_kernel void @move_to_valu_i64_ne(i32 addrspace(1)* %out) { 546 %cond = load volatile i64, i64 addrspace(3)* undef 547 %cmp0 = icmp ne i64 %cond, 0 548 br i1 %cmp0, label %if, label %else 549 550if: 551 br label %done 552 553else: 554 br label %done 555 556done: 557 %value = phi i32 [0, %if], [1, %else] 558 store i32 %value, i32 addrspace(1)* %out 559 ret void 560} 561 562; GCN-LABEL: {{^}}move_to_valu_vgpr_operand_phi: 563; GCN: v_add_{{[iu]}}32_e32 564; GCN: ds_write_b32 565define void @move_to_valu_vgpr_operand_phi(i32 addrspace(3)* %out) { 566bb0: 567 br label %bb1 568 569bb1: ; preds = %bb3, %bb0 570 %tmp0 = phi i32 [ 8, %bb0 ], [ %tmp4, %bb3 ] 571 %tmp1 = add nsw i32 %tmp0, -1 572 %tmp2 = getelementptr inbounds i32, i32 addrspace(3)* %out, i32 %tmp1 573 br i1 undef, label %bb2, label %bb3 574 575bb2: ; preds = %bb1 576 store volatile i32 1, i32 addrspace(3)* %tmp2, align 4 577 br label %bb3 578 579bb3: ; preds = %bb2, %bb1 580 %tmp4 = add nsw i32 %tmp0, 2 581 br label %bb1 582} 583 584declare i32 @llvm.amdgcn.workitem.id.x() #0 585 586attributes #0 = { nounwind readnone } 587