1; RUN: llc -march=amdgcn -mcpu=verde -amdgpu-early-ifcvt=0 -machine-sink-split-probability-threshold=0 -structurizecfg-skip-uniform-regions -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s 2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-early-ifcvt=0 -machine-sink-split-probability-threshold=0 -structurizecfg-skip-uniform-regions -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s 3 4; GCN-LABEL: {{^}}uniform_if_scc: 5; GCN-DAG: s_cmp_eq_u32 s{{[0-9]+}}, 0 6; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 7; GCN: s_cbranch_scc1 [[IF_LABEL:.L[0-9_A-Za-z]+]] 8 9; Fall-through to the else 10; GCN: s_mov_b32 [[S_VAL]], 1 11 12; GCN: [[IF_LABEL]]: 13; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] 14; GCN: buffer_store_dword [[V_VAL]] 15define amdgpu_kernel void @uniform_if_scc(i32 %cond, i32 addrspace(1)* %out) { 16entry: 17 %cmp0 = icmp eq i32 %cond, 0 18 br i1 %cmp0, label %if, label %else 19 20if: 21 br label %done 22 23else: 24 br label %done 25 26done: 27 %value = phi i32 [0, %if], [1, %else] 28 store i32 %value, i32 addrspace(1)* %out 29 ret void 30} 31 32; GCN-LABEL: {{^}}uniform_if_vcc: 33; GCN-DAG: v_cmp_eq_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0{{$}} 34; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 35; GCN: s_cbranch_vccnz [[IF_LABEL:.L[0-9_A-Za-z]+]] 36 37; Fall-through to the else 38; GCN: s_mov_b32 [[S_VAL]], 1 39 40; GCN: [[IF_LABEL]]: 41; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] 42; GCN: buffer_store_dword [[V_VAL]] 43define amdgpu_kernel void @uniform_if_vcc(float %cond, i32 addrspace(1)* %out) { 44entry: 45 %cmp0 = fcmp oeq float %cond, 0.0 46 br i1 %cmp0, label %if, label %else 47 48if: 49 br label %done 50 51else: 52 br label %done 53 54done: 55 %value = phi i32 [0, %if], [1, %else] 56 store i32 %value, i32 addrspace(1)* %out 57 ret void 58} 59 60; GCN-LABEL: {{^}}uniform_if_swap_br_targets_scc: 61; GCN-DAG: s_cmp_lg_u32 s{{[0-9]+}}, 0 62; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 63; GCN: s_cbranch_scc1 [[IF_LABEL:.L[0-9_A-Za-z]+]] 64 65; Fall-through to the else 66; GCN: s_mov_b32 [[S_VAL]], 1 67 68; GCN: [[IF_LABEL]]: 69; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] 70; GCN: buffer_store_dword [[V_VAL]] 71define amdgpu_kernel void @uniform_if_swap_br_targets_scc(i32 %cond, i32 addrspace(1)* %out) { 72entry: 73 %cmp0 = icmp eq i32 %cond, 0 74 br i1 %cmp0, label %else, label %if 75 76if: 77 br label %done 78 79else: 80 br label %done 81 82done: 83 %value = phi i32 [0, %if], [1, %else] 84 store i32 %value, i32 addrspace(1)* %out 85 ret void 86} 87 88; GCN-LABEL: {{^}}uniform_if_swap_br_targets_vcc: 89; GCN-DAG: v_cmp_neq_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0{{$}} 90; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 91; GCN: s_cbranch_vccnz [[IF_LABEL:.L[0-9_A-Za-z]+]] 92 93; Fall-through to the else 94; GCN: s_mov_b32 [[S_VAL]], 1 95 96; GCN: [[IF_LABEL]]: 97; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] 98; GCN: buffer_store_dword [[V_VAL]] 99define amdgpu_kernel void @uniform_if_swap_br_targets_vcc(float %cond, i32 addrspace(1)* %out) { 100entry: 101 %cmp0 = fcmp oeq float %cond, 0.0 102 br i1 %cmp0, label %else, label %if 103 104if: 105 br label %done 106 107else: 108 br label %done 109 110done: 111 %value = phi i32 [0, %if], [1, %else] 112 store i32 %value, i32 addrspace(1)* %out 113 ret void 114} 115 116; GCN-LABEL: {{^}}uniform_if_move_valu: 117; GCN: v_add_f32_e32 [[CMP:v[0-9]+]] 118; Using a floating-point value in an integer compare will cause the compare to 119; be selected for the SALU and then later moved to the VALU. 120; GCN: v_cmp_ne_u32_e32 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 5, [[CMP]] 121; GCN: s_cbranch_vccnz [[ENDIF_LABEL:.L[0-9_A-Za-z]+]] 122; GCN: buffer_store_dword 123; GCN: [[ENDIF_LABEL]]: 124; GCN: s_endpgm 125define amdgpu_kernel void @uniform_if_move_valu(i32 addrspace(1)* %out, float %a) { 126entry: 127 %a.0 = fadd float %a, 10.0 128 %cond = bitcast float %a.0 to i32 129 %cmp = icmp eq i32 %cond, 5 130 br i1 %cmp, label %if, label %endif 131 132if: 133 store i32 0, i32 addrspace(1)* %out 134 br label %endif 135 136endif: 137 ret void 138} 139 140; GCN-LABEL: {{^}}uniform_if_move_valu_commute: 141; GCN: v_add_f32_e32 [[CMP:v[0-9]+]] 142; Using a floating-point value in an integer compare will cause the compare to 143; be selected for the SALU and then later moved to the VALU. 144; GCN: v_cmp_gt_u32_e32 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 6, [[CMP]] 145; GCN: s_cbranch_vccnz [[ENDIF_LABEL:.L[0-9_A-Za-z]+]] 146; GCN: buffer_store_dword 147; GCN: [[ENDIF_LABEL]]: 148; GCN: s_endpgm 149define amdgpu_kernel void @uniform_if_move_valu_commute(i32 addrspace(1)* %out, float %a) { 150entry: 151 %a.0 = fadd float %a, 10.0 152 %cond = bitcast float %a.0 to i32 153 %cmp = icmp ugt i32 %cond, 5 154 br i1 %cmp, label %if, label %endif 155 156if: 157 store i32 0, i32 addrspace(1)* %out 158 br label %endif 159 160endif: 161 ret void 162} 163 164 165; GCN-LABEL: {{^}}uniform_if_else_ret: 166; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0 167; GCN: s_cbranch_scc0 [[IF_LABEL:.L[0-9_A-Za-z]+]] 168 169; GCN: v_mov_b32_e32 [[TWO:v[0-9]+]], 2 170; GCN: buffer_store_dword [[TWO]] 171; GCN: s_endpgm 172 173; GCN: {{^}}[[IF_LABEL]]: 174; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 175; GCN: buffer_store_dword [[ONE]] 176; GCN: s_endpgm 177define amdgpu_kernel void @uniform_if_else_ret(i32 addrspace(1)* nocapture %out, i32 %a) { 178entry: 179 %cmp = icmp eq i32 %a, 0 180 br i1 %cmp, label %if.then, label %if.else 181 182if.then: ; preds = %entry 183 store i32 1, i32 addrspace(1)* %out 184 br label %if.end 185 186if.else: ; preds = %entry 187 store i32 2, i32 addrspace(1)* %out 188 br label %if.end 189 190if.end: ; preds = %if.else, %if.then 191 ret void 192} 193 194; GCN-LABEL: {{^}}uniform_if_else: 195; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0 196; GCN: s_cbranch_scc0 [[IF_LABEL:.L[0-9_A-Za-z]+]] 197 198; GCN: v_mov_b32_e32 [[IMM_REG:v[0-9]+]], 2 199; GCN: s_branch [[ENDIF_LABEL:.L[0-9_A-Za-z]+]] 200 201; GCN: [[IF_LABEL]]: 202; GCN: v_mov_b32_e32 [[IMM_REG]], 1 203 204; GCN-NEXT: [[ENDIF_LABEL]]: 205; GCN: buffer_store_dword [[IMM_REG]] 206 207; GCN: v_mov_b32_e32 [[THREE:v[0-9]+]], 3 208; GCN: buffer_store_dword [[THREE]] 209; GCN: s_endpgm 210define amdgpu_kernel void @uniform_if_else(i32 addrspace(1)* nocapture %out0, i32 addrspace(1)* nocapture %out1, i32 %a) { 211entry: 212 %cmp = icmp eq i32 %a, 0 213 br i1 %cmp, label %if.then, label %if.else 214 215if.then: ; preds = %entry 216 store i32 1, i32 addrspace(1)* %out0 217 br label %if.end 218 219if.else: ; preds = %entry 220 store i32 2, i32 addrspace(1)* %out0 221 br label %if.end 222 223if.end: ; preds = %if.else, %if.then 224 store i32 3, i32 addrspace(1)* %out1 225 ret void 226} 227 228; GCN-LABEL: {{^}}icmp_2_users: 229; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 1 230; GCN: s_cbranch_scc1 [[LABEL:.L[0-9_A-Za-z]+]] 231; GCN: buffer_store_dword 232; GCN: [[LABEL]]: 233; GCN: s_endpgm 234define amdgpu_kernel void @icmp_2_users(i32 addrspace(1)* %out, i32 %cond) { 235main_body: 236 %0 = icmp sgt i32 %cond, 0 237 %1 = sext i1 %0 to i32 238 br i1 %0, label %IF, label %ENDIF 239 240IF: 241 store i32 %1, i32 addrspace(1)* %out 242 br label %ENDIF 243 244ENDIF: ; preds = %IF, %main_body 245 ret void 246} 247 248; GCN-LABEL: {{^}}icmp_users_different_blocks: 249; GCN: s_load_dwordx2 s[[[COND0:[0-9]+]]:[[COND1:[0-9]+]]] 250; GCN: s_cmp_lt_i32 s[[COND0]], 1 251; GCN: s_cbranch_scc1 [[EXIT:.L[0-9_A-Za-z]+]] 252; GCN: s_cmp_gt_i32 s[[COND1]], 0{{$}} 253; GCN: s_cbranch_vccz [[BODY:.L[0-9_A-Za-z]+]] 254; GCN: {{^}}[[EXIT]]: 255; GCN: s_endpgm 256; GCN: {{^}}[[BODY]]: 257; GCN: buffer_store 258; GCN: s_endpgm 259define amdgpu_kernel void @icmp_users_different_blocks(i32 %cond0, i32 %cond1, i32 addrspace(1)* %out) { 260bb: 261 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0 262 %cmp0 = icmp sgt i32 %cond0, 0 263 br i1 %cmp0, label %bb2, label %bb9 264 265bb2: ; preds = %bb 266 %cmp1 = icmp sgt i32 %cond1, 0 267 %tmp2 = sext i1 %cmp1 to i32 268 %tmp3 = add i32 %tmp2, %tmp 269 br i1 %cmp1, label %bb9, label %bb7 270 271bb7: ; preds = %bb5 272 store i32 %tmp3, i32 addrspace(1)* %out 273 br label %bb9 274 275bb9: ; preds = %bb8, %bb4 276 ret void 277} 278 279; SI-LABEL: {{^}}uniform_loop: 280; SI: {{^}}[[LOOP_LABEL:.L[0-9_A-Za-z]+]]: 281; SI: s_add_i32 [[I:s[0-9]+]], s{{[0-9]+}}, -1 282; SI: s_cmp_lg_u32 [[I]], 0 283; SI: s_cbranch_scc1 [[LOOP_LABEL]] 284; SI: s_endpgm 285define amdgpu_kernel void @uniform_loop(i32 addrspace(1)* %out, i32 %a) { 286entry: 287 br label %loop 288 289loop: 290 %i = phi i32 [0, %entry], [%i.i, %loop] 291 %i.i = add i32 %i, 1 292 %cmp = icmp eq i32 %a, %i.i 293 br i1 %cmp, label %done, label %loop 294 295done: 296 ret void 297} 298 299; Test uniform and divergent. 300 301; GCN-LABEL: {{^}}uniform_inside_divergent: 302; GCN: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}} 303; GCN: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc 304; GCN: s_cmp_lg_u32 {{s[0-9]+}}, 0 305; GCN: s_cbranch_scc0 [[IF_UNIFORM_LABEL:.L[0-9_A-Za-z]+]] 306; GCN: s_endpgm 307; GCN: {{^}}[[IF_UNIFORM_LABEL]]: 308; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 309; GCN: buffer_store_dword [[ONE]] 310define amdgpu_kernel void @uniform_inside_divergent(i32 addrspace(1)* %out, i32 %cond) { 311entry: 312 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 313 %d_cmp = icmp ult i32 %tid, 16 314 br i1 %d_cmp, label %if, label %endif 315 316if: 317 store i32 0, i32 addrspace(1)* %out 318 %u_cmp = icmp eq i32 %cond, 0 319 br i1 %u_cmp, label %if_uniform, label %endif 320 321if_uniform: 322 store i32 1, i32 addrspace(1)* %out 323 br label %endif 324 325endif: 326 ret void 327} 328 329; GCN-LABEL: {{^}}divergent_inside_uniform: 330; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0 331; GCN: s_cbranch_scc0 [[IF_LABEL:.L[0-9_A-Za-z]+]] 332; GCN: [[ENDIF_LABEL:.L[0-9_A-Za-z]+]]: 333; GCN: [[IF_LABEL]]: 334; GCN: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}} 335; GCN: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc 336; GCN: s_cbranch_execz [[ENDIF_LABEL]] 337; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 338; GCN: buffer_store_dword [[ONE]] 339; GCN: s_endpgm 340define amdgpu_kernel void @divergent_inside_uniform(i32 addrspace(1)* %out, i32 %cond) { 341entry: 342 %u_cmp = icmp eq i32 %cond, 0 343 br i1 %u_cmp, label %if, label %endif 344 345if: 346 store i32 0, i32 addrspace(1)* %out 347 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 348 %d_cmp = icmp ult i32 %tid, 16 349 br i1 %d_cmp, label %if_uniform, label %endif 350 351if_uniform: 352 store i32 1, i32 addrspace(1)* %out 353 br label %endif 354 355endif: 356 ret void 357} 358 359; GCN-LABEL: {{^}}divergent_if_uniform_if: 360; GCN: v_cmp_eq_u32_e32 vcc, 0, v0 361; GCN: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc 362; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 363; GCN: buffer_store_dword [[ONE]] 364; GCN: s_or_b64 exec, exec, [[MASK]] 365; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0 366; GCN: s_cbranch_scc0 [[IF_UNIFORM:.L[0-9_A-Za-z]+]] 367; GCN: s_endpgm 368; GCN: [[IF_UNIFORM]]: 369; GCN: v_mov_b32_e32 [[TWO:v[0-9]+]], 2 370; GCN: buffer_store_dword [[TWO]] 371define amdgpu_kernel void @divergent_if_uniform_if(i32 addrspace(1)* %out, i32 %cond) { 372entry: 373 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 374 %d_cmp = icmp eq i32 %tid, 0 375 br i1 %d_cmp, label %if, label %endif 376 377if: 378 store i32 1, i32 addrspace(1)* %out 379 br label %endif 380 381endif: 382 %u_cmp = icmp eq i32 %cond, 0 383 br i1 %u_cmp, label %if_uniform, label %exit 384 385if_uniform: 386 store i32 2, i32 addrspace(1)* %out 387 br label %exit 388 389exit: 390 ret void 391} 392 393; The condition of the branches in the two blocks are 394; uniform. MachineCSE replaces the 2nd condition with the inverse of 395; the first, leaving an scc use in a different block than it was 396; defed. 397 398; GCN-LABEL: {{^}}cse_uniform_condition_different_blocks: 399; GCN: s_load_dword [[COND:s[0-9]+]] 400; GCN: s_cmp_lt_i32 [[COND]], 1 401; GCN: s_cbranch_scc1 .LBB[[FNNUM:[0-9]+]]_3 402 403; GCN: %bb.1: 404; GCN-NOT: cmp 405; GCN: buffer_load_dword 406; GCN: buffer_store_dword 407; GCN: s_cbranch_scc1 .LBB[[FNNUM]]_3 408 409; GCN: .LBB[[FNNUM]]_3: 410; GCN: s_endpgm 411define amdgpu_kernel void @cse_uniform_condition_different_blocks(i32 %cond, i32 addrspace(1)* %out) { 412bb: 413 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0 414 %tmp1 = icmp sgt i32 %cond, 0 415 br i1 %tmp1, label %bb2, label %bb9 416 417bb2: ; preds = %bb 418 %tmp3 = load volatile i32, i32 addrspace(1)* undef 419 store volatile i32 0, i32 addrspace(1)* undef 420 %tmp9 = icmp sle i32 %cond, 0 421 br i1 %tmp9, label %bb9, label %bb7 422 423bb7: ; preds = %bb5 424 store i32 %tmp3, i32 addrspace(1)* %out 425 br label %bb9 426 427bb9: ; preds = %bb8, %bb4 428 ret void 429} 430 431; GCN-LABEL: {{^}}uniform_if_scc_i64_eq: 432; VI-DAG: s_cmp_eq_u64 s{{\[[0-9]+:[0-9]+\]}}, 0 433; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 434; SI-DAG: v_cmp_eq_u64_e64 435; SI: s_cbranch_vccnz [[IF_LABEL:.L[0-9_A-Za-z]+]] 436 437; VI: s_cbranch_scc1 [[IF_LABEL:.L[0-9_A-Za-z]+]] 438 439; Fall-through to the else 440; GCN: s_mov_b32 [[S_VAL]], 1 441 442; GCN: [[IF_LABEL]]: 443; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] 444; GCN: buffer_store_dword [[V_VAL]] 445define amdgpu_kernel void @uniform_if_scc_i64_eq(i64 %cond, i32 addrspace(1)* %out) { 446entry: 447 %cmp0 = icmp eq i64 %cond, 0 448 br i1 %cmp0, label %if, label %else 449 450if: 451 br label %done 452 453else: 454 br label %done 455 456done: 457 %value = phi i32 [0, %if], [1, %else] 458 store i32 %value, i32 addrspace(1)* %out 459 ret void 460} 461 462; GCN-LABEL: {{^}}uniform_if_scc_i64_ne: 463; VI-DAG: s_cmp_lg_u64 s{{\[[0-9]+:[0-9]+\]}}, 0 464; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 465 466; SI-DAG: v_cmp_ne_u64_e64 467; SI: s_cbranch_vccnz [[IF_LABEL:.L[0-9_A-Za-z]+]] 468 469; VI: s_cbranch_scc1 [[IF_LABEL:.L[0-9_A-Za-z]+]] 470 471; Fall-through to the else 472; GCN: s_mov_b32 [[S_VAL]], 1 473 474; GCN: [[IF_LABEL]]: 475; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] 476; GCN: buffer_store_dword [[V_VAL]] 477define amdgpu_kernel void @uniform_if_scc_i64_ne(i64 %cond, i32 addrspace(1)* %out) { 478entry: 479 %cmp0 = icmp ne i64 %cond, 0 480 br i1 %cmp0, label %if, label %else 481 482if: 483 br label %done 484 485else: 486 br label %done 487 488done: 489 %value = phi i32 [0, %if], [1, %else] 490 store i32 %value, i32 addrspace(1)* %out 491 ret void 492} 493 494; GCN-LABEL: {{^}}uniform_if_scc_i64_sgt: 495; GCN-DAG: s_mov_b32 [[S_VAL:s[0-9]+]], 0 496; GCN-DAG: v_cmp_gt_i64_e64 497; GCN: s_cbranch_vccnz [[IF_LABEL:.L[0-9_A-Za-z]+]] 498 499; Fall-through to the else 500; GCN: s_mov_b32 [[S_VAL]], 1 501 502; GCN: [[IF_LABEL]]: 503; GCN: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[S_VAL]] 504; GCN: buffer_store_dword [[V_VAL]] 505define amdgpu_kernel void @uniform_if_scc_i64_sgt(i64 %cond, i32 addrspace(1)* %out) { 506entry: 507 %cmp0 = icmp sgt i64 %cond, 0 508 br i1 %cmp0, label %if, label %else 509 510if: 511 br label %done 512 513else: 514 br label %done 515 516done: 517 %value = phi i32 [0, %if], [1, %else] 518 store i32 %value, i32 addrspace(1)* %out 519 ret void 520} 521 522; GCN-LABEL: {{^}}move_to_valu_i64_eq: 523; GCN: v_cmp_eq_u64_e32 524define amdgpu_kernel void @move_to_valu_i64_eq(i32 addrspace(1)* %out) { 525 %cond = load volatile i64, i64 addrspace(3)* undef 526 %cmp0 = icmp eq i64 %cond, 0 527 br i1 %cmp0, label %if, label %else 528 529if: 530 br label %done 531 532else: 533 br label %done 534 535done: 536 %value = phi i32 [0, %if], [1, %else] 537 store i32 %value, i32 addrspace(1)* %out 538 ret void 539} 540 541; GCN-LABEL: {{^}}move_to_valu_i64_ne: 542; GCN: v_cmp_ne_u64_e32 543define amdgpu_kernel void @move_to_valu_i64_ne(i32 addrspace(1)* %out) { 544 %cond = load volatile i64, i64 addrspace(3)* undef 545 %cmp0 = icmp ne i64 %cond, 0 546 br i1 %cmp0, label %if, label %else 547 548if: 549 br label %done 550 551else: 552 br label %done 553 554done: 555 %value = phi i32 [0, %if], [1, %else] 556 store i32 %value, i32 addrspace(1)* %out 557 ret void 558} 559 560; GCN-LABEL: {{^}}move_to_valu_vgpr_operand_phi: 561; GCN: v_add_{{[iu]}}32_e32 562; GCN: ds_write_b32 563define void @move_to_valu_vgpr_operand_phi(i32 addrspace(3)* %out) { 564bb0: 565 br label %bb1 566 567bb1: ; preds = %bb3, %bb0 568 %tmp0 = phi i32 [ 8, %bb0 ], [ %tmp4, %bb3 ] 569 %tmp1 = add nsw i32 %tmp0, -1 570 %tmp2 = getelementptr inbounds i32, i32 addrspace(3)* %out, i32 %tmp1 571 br i1 undef, label %bb2, label %bb3 572 573bb2: ; preds = %bb1 574 store volatile i32 1, i32 addrspace(3)* %tmp2, align 4 575 br label %bb3 576 577bb3: ; preds = %bb2, %bb1 578 %tmp4 = add nsw i32 %tmp0, 2 579 br label %bb1 580} 581 582declare i32 @llvm.amdgcn.workitem.id.x() #0 583 584attributes #0 = { nounwind readnone } 585