1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
3; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX8 %s
4
5; FIXME: This should be merged with uint_to_fp.ll, but s_uint_to_fp_v2i64 crashes on r600
6
7define amdgpu_kernel void @s_uint_to_fp_i64_to_f16(half addrspace(1)* %out, i64 %in) #0 {
8; GFX6-LABEL: s_uint_to_fp_i64_to_f16:
9; GFX6:       ; %bb.0:
10; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
11; GFX6-NEXT:    s_mov_b32 s7, 0xf000
12; GFX6-NEXT:    s_mov_b32 s6, -1
13; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
14; GFX6-NEXT:    s_mov_b32 s4, s0
15; GFX6-NEXT:    s_mov_b32 s5, s1
16; GFX6-NEXT:    s_flbit_i32_b32 s0, s3
17; GFX6-NEXT:    s_min_u32 s8, s0, 32
18; GFX6-NEXT:    s_lshl_b64 s[0:1], s[2:3], s8
19; GFX6-NEXT:    s_min_u32 s0, s0, 1
20; GFX6-NEXT:    s_or_b32 s0, s1, s0
21; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s0
22; GFX6-NEXT:    s_sub_i32 s0, 32, s8
23; GFX6-NEXT:    v_ldexp_f32_e64 v0, v0, s0
24; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
25; GFX6-NEXT:    buffer_store_short v0, off, s[4:7], 0
26; GFX6-NEXT:    s_endpgm
27;
28; GFX8-LABEL: s_uint_to_fp_i64_to_f16:
29; GFX8:       ; %bb.0:
30; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
31; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
32; GFX8-NEXT:    s_flbit_i32_b32 s4, s3
33; GFX8-NEXT:    s_min_u32 s4, s4, 32
34; GFX8-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
35; GFX8-NEXT:    s_min_u32 s2, s2, 1
36; GFX8-NEXT:    s_or_b32 s2, s3, s2
37; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s2
38; GFX8-NEXT:    s_sub_i32 s2, 32, s4
39; GFX8-NEXT:    v_mov_b32_e32 v1, s1
40; GFX8-NEXT:    v_ldexp_f32 v0, v0, s2
41; GFX8-NEXT:    v_cvt_f16_f32_e32 v2, v0
42; GFX8-NEXT:    v_mov_b32_e32 v0, s0
43; GFX8-NEXT:    flat_store_short v[0:1], v2
44; GFX8-NEXT:    s_endpgm
45  %result = uitofp i64 %in to half
46  store half %result, half addrspace(1)* %out
47  ret void
48}
49
50define amdgpu_kernel void @v_uint_to_fp_i64_to_f16(half addrspace(1)* %out, i64 addrspace(1)* %in) #0 {
51; GFX6-LABEL: v_uint_to_fp_i64_to_f16:
52; GFX6:       ; %bb.0:
53; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
54; GFX6-NEXT:    s_mov_b32 s7, 0xf000
55; GFX6-NEXT:    s_mov_b32 s6, 0
56; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 3, v0
57; GFX6-NEXT:    v_mov_b32_e32 v2, 0
58; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
59; GFX6-NEXT:    s_mov_b64 s[4:5], s[2:3]
60; GFX6-NEXT:    buffer_load_dwordx2 v[3:4], v[1:2], s[4:7], 0 addr64
61; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 1, v0
62; GFX6-NEXT:    s_mov_b64 s[2:3], s[6:7]
63; GFX6-NEXT:    s_waitcnt vmcnt(0)
64; GFX6-NEXT:    v_ffbh_u32_e32 v0, v4
65; GFX6-NEXT:    v_min_u32_e32 v0, 32, v0
66; GFX6-NEXT:    v_lshl_b64 v[3:4], v[3:4], v0
67; GFX6-NEXT:    v_min_u32_e32 v3, 1, v3
68; GFX6-NEXT:    v_or_b32_e32 v3, v4, v3
69; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, v3
70; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, 32, v0
71; GFX6-NEXT:    v_ldexp_f32_e32 v0, v3, v0
72; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
73; GFX6-NEXT:    buffer_store_short v0, v[1:2], s[0:3], 0 addr64
74; GFX6-NEXT:    s_endpgm
75;
76; GFX8-LABEL: v_uint_to_fp_i64_to_f16:
77; GFX8:       ; %bb.0:
78; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
79; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 3, v0
80; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
81; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
82; GFX8-NEXT:    v_mov_b32_e32 v2, s3
83; GFX8-NEXT:    v_add_u32_e32 v1, vcc, s2, v1
84; GFX8-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
85; GFX8-NEXT:    flat_load_dwordx2 v[1:2], v[1:2]
86; GFX8-NEXT:    s_waitcnt vmcnt(0)
87; GFX8-NEXT:    v_ffbh_u32_e32 v3, v2
88; GFX8-NEXT:    v_min_u32_e32 v3, 32, v3
89; GFX8-NEXT:    v_lshlrev_b64 v[1:2], v3, v[1:2]
90; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, 32, v3
91; GFX8-NEXT:    v_min_u32_e32 v1, 1, v1
92; GFX8-NEXT:    v_or_b32_e32 v1, v2, v1
93; GFX8-NEXT:    v_cvt_f32_u32_e32 v1, v1
94; GFX8-NEXT:    v_mov_b32_e32 v2, s1
95; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
96; GFX8-NEXT:    v_ldexp_f32 v1, v1, v3
97; GFX8-NEXT:    v_cvt_f16_f32_e32 v3, v1
98; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
99; GFX8-NEXT:    flat_store_short v[0:1], v3
100; GFX8-NEXT:    s_endpgm
101  %tid = call i32 @llvm.amdgcn.workitem.id.x()
102  %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
103  %out.gep = getelementptr half, half addrspace(1)* %out, i32 %tid
104  %val = load i64, i64 addrspace(1)* %in.gep
105  %result = uitofp i64 %val to half
106  store half %result, half addrspace(1)* %out.gep
107  ret void
108}
109
110define amdgpu_kernel void @s_uint_to_fp_i64_to_f32(float addrspace(1)* %out, i64 %in) #0 {
111; GFX6-LABEL: s_uint_to_fp_i64_to_f32:
112; GFX6:       ; %bb.0:
113; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
114; GFX6-NEXT:    s_mov_b32 s7, 0xf000
115; GFX6-NEXT:    s_mov_b32 s6, -1
116; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
117; GFX6-NEXT:    s_mov_b32 s4, s0
118; GFX6-NEXT:    s_mov_b32 s5, s1
119; GFX6-NEXT:    s_flbit_i32_b32 s0, s3
120; GFX6-NEXT:    s_min_u32 s8, s0, 32
121; GFX6-NEXT:    s_lshl_b64 s[0:1], s[2:3], s8
122; GFX6-NEXT:    s_min_u32 s0, s0, 1
123; GFX6-NEXT:    s_or_b32 s0, s1, s0
124; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s0
125; GFX6-NEXT:    s_sub_i32 s0, 32, s8
126; GFX6-NEXT:    v_ldexp_f32_e64 v0, v0, s0
127; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
128; GFX6-NEXT:    s_endpgm
129;
130; GFX8-LABEL: s_uint_to_fp_i64_to_f32:
131; GFX8:       ; %bb.0:
132; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
133; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
134; GFX8-NEXT:    s_flbit_i32_b32 s4, s3
135; GFX8-NEXT:    s_min_u32 s4, s4, 32
136; GFX8-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
137; GFX8-NEXT:    s_min_u32 s2, s2, 1
138; GFX8-NEXT:    s_or_b32 s2, s3, s2
139; GFX8-NEXT:    v_cvt_f32_u32_e32 v2, s2
140; GFX8-NEXT:    v_mov_b32_e32 v0, s0
141; GFX8-NEXT:    s_sub_i32 s0, 32, s4
142; GFX8-NEXT:    v_mov_b32_e32 v1, s1
143; GFX8-NEXT:    v_ldexp_f32 v2, v2, s0
144; GFX8-NEXT:    flat_store_dword v[0:1], v2
145; GFX8-NEXT:    s_endpgm
146  %result = uitofp i64 %in to float
147  store float %result, float addrspace(1)* %out
148  ret void
149}
150
151define amdgpu_kernel void @v_uint_to_fp_i64_to_f32(float addrspace(1)* %out, i64 addrspace(1)* %in) #0 {
152; GFX6-LABEL: v_uint_to_fp_i64_to_f32:
153; GFX6:       ; %bb.0:
154; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
155; GFX6-NEXT:    s_mov_b32 s7, 0xf000
156; GFX6-NEXT:    s_mov_b32 s6, 0
157; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 3, v0
158; GFX6-NEXT:    v_mov_b32_e32 v2, 0
159; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
160; GFX6-NEXT:    s_mov_b64 s[4:5], s[2:3]
161; GFX6-NEXT:    buffer_load_dwordx2 v[3:4], v[1:2], s[4:7], 0 addr64
162; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 2, v0
163; GFX6-NEXT:    s_mov_b64 s[2:3], s[6:7]
164; GFX6-NEXT:    s_waitcnt vmcnt(0)
165; GFX6-NEXT:    v_ffbh_u32_e32 v0, v4
166; GFX6-NEXT:    v_min_u32_e32 v0, 32, v0
167; GFX6-NEXT:    v_lshl_b64 v[3:4], v[3:4], v0
168; GFX6-NEXT:    v_min_u32_e32 v3, 1, v3
169; GFX6-NEXT:    v_or_b32_e32 v3, v4, v3
170; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, v3
171; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, 32, v0
172; GFX6-NEXT:    v_ldexp_f32_e32 v0, v3, v0
173; GFX6-NEXT:    buffer_store_dword v0, v[1:2], s[0:3], 0 addr64
174; GFX6-NEXT:    s_endpgm
175;
176; GFX8-LABEL: v_uint_to_fp_i64_to_f32:
177; GFX8:       ; %bb.0:
178; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
179; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 3, v0
180; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 2, v0
181; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
182; GFX8-NEXT:    v_mov_b32_e32 v2, s3
183; GFX8-NEXT:    v_add_u32_e32 v1, vcc, s2, v1
184; GFX8-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
185; GFX8-NEXT:    flat_load_dwordx2 v[1:2], v[1:2]
186; GFX8-NEXT:    s_waitcnt vmcnt(0)
187; GFX8-NEXT:    v_ffbh_u32_e32 v0, v2
188; GFX8-NEXT:    v_min_u32_e32 v4, 32, v0
189; GFX8-NEXT:    v_lshlrev_b64 v[0:1], v4, v[1:2]
190; GFX8-NEXT:    v_mov_b32_e32 v2, s1
191; GFX8-NEXT:    v_min_u32_e32 v0, 1, v0
192; GFX8-NEXT:    v_or_b32_e32 v0, v1, v0
193; GFX8-NEXT:    v_cvt_f32_u32_e32 v5, v0
194; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v3
195; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
196; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, 32, v4
197; GFX8-NEXT:    v_ldexp_f32 v2, v5, v2
198; GFX8-NEXT:    flat_store_dword v[0:1], v2
199; GFX8-NEXT:    s_endpgm
200  %tid = call i32 @llvm.amdgcn.workitem.id.x()
201  %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
202  %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
203  %val = load i64, i64 addrspace(1)* %in.gep
204  %result = uitofp i64 %val to float
205  store float %result, float addrspace(1)* %out.gep
206  ret void
207}
208
209define amdgpu_kernel void @s_uint_to_fp_v2i64_to_v2f32(<2 x float> addrspace(1)* %out, <2 x i64> %in) #0{
210; GFX6-LABEL: s_uint_to_fp_v2i64_to_v2f32:
211; GFX6:       ; %bb.0:
212; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
213; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
214; GFX6-NEXT:    s_mov_b32 s3, 0xf000
215; GFX6-NEXT:    s_mov_b32 s2, -1
216; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
217; GFX6-NEXT:    s_flbit_i32_b32 s8, s7
218; GFX6-NEXT:    s_flbit_i32_b32 s9, s5
219; GFX6-NEXT:    s_min_u32 s8, s8, 32
220; GFX6-NEXT:    s_min_u32 s9, s9, 32
221; GFX6-NEXT:    s_lshl_b64 s[6:7], s[6:7], s8
222; GFX6-NEXT:    s_sub_i32 s8, 32, s8
223; GFX6-NEXT:    s_lshl_b64 s[4:5], s[4:5], s9
224; GFX6-NEXT:    s_sub_i32 s9, 32, s9
225; GFX6-NEXT:    s_min_u32 s6, s6, 1
226; GFX6-NEXT:    s_min_u32 s4, s4, 1
227; GFX6-NEXT:    s_or_b32 s6, s7, s6
228; GFX6-NEXT:    s_or_b32 s4, s5, s4
229; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s6
230; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s4
231; GFX6-NEXT:    v_ldexp_f32_e64 v1, v0, s8
232; GFX6-NEXT:    v_ldexp_f32_e64 v0, v2, s9
233; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
234; GFX6-NEXT:    s_endpgm
235;
236; GFX8-LABEL: s_uint_to_fp_v2i64_to_v2f32:
237; GFX8:       ; %bb.0:
238; GFX8-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
239; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x34
240; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
241; GFX8-NEXT:    s_flbit_i32_b32 s6, s3
242; GFX8-NEXT:    s_flbit_i32_b32 s7, s1
243; GFX8-NEXT:    s_min_u32 s6, s6, 32
244; GFX8-NEXT:    s_min_u32 s7, s7, 32
245; GFX8-NEXT:    s_lshl_b64 s[2:3], s[2:3], s6
246; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], s7
247; GFX8-NEXT:    s_min_u32 s2, s2, 1
248; GFX8-NEXT:    s_or_b32 s2, s3, s2
249; GFX8-NEXT:    s_min_u32 s0, s0, 1
250; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s2
251; GFX8-NEXT:    s_or_b32 s0, s1, s0
252; GFX8-NEXT:    v_cvt_f32_u32_e32 v2, s0
253; GFX8-NEXT:    s_sub_i32 s0, 32, s6
254; GFX8-NEXT:    v_ldexp_f32 v1, v0, s0
255; GFX8-NEXT:    s_sub_i32 s0, 32, s7
256; GFX8-NEXT:    v_ldexp_f32 v0, v2, s0
257; GFX8-NEXT:    v_mov_b32_e32 v2, s4
258; GFX8-NEXT:    v_mov_b32_e32 v3, s5
259; GFX8-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
260; GFX8-NEXT:    s_endpgm
261  %result = uitofp <2 x i64> %in to <2 x float>
262  store <2 x float> %result, <2 x float> addrspace(1)* %out
263  ret void
264}
265
266define amdgpu_kernel void @v_uint_to_fp_v4i64_to_v4f32(<4 x float> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) #0 {
267; GFX6-LABEL: v_uint_to_fp_v4i64_to_v4f32:
268; GFX6:       ; %bb.0:
269; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
270; GFX6-NEXT:    s_mov_b32 s7, 0xf000
271; GFX6-NEXT:    s_mov_b32 s6, 0
272; GFX6-NEXT:    v_lshlrev_b32_e32 v8, 5, v0
273; GFX6-NEXT:    v_mov_b32_e32 v9, 0
274; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
275; GFX6-NEXT:    s_mov_b64 s[4:5], s[2:3]
276; GFX6-NEXT:    buffer_load_dwordx4 v[1:4], v[8:9], s[4:7], 0 addr64 offset:16
277; GFX6-NEXT:    buffer_load_dwordx4 v[5:8], v[8:9], s[4:7], 0 addr64
278; GFX6-NEXT:    v_lshlrev_b32_e32 v10, 4, v0
279; GFX6-NEXT:    v_mov_b32_e32 v11, v9
280; GFX6-NEXT:    s_mov_b64 s[2:3], s[6:7]
281; GFX6-NEXT:    s_waitcnt vmcnt(1)
282; GFX6-NEXT:    v_ffbh_u32_e32 v0, v4
283; GFX6-NEXT:    v_ffbh_u32_e32 v9, v2
284; GFX6-NEXT:    s_waitcnt vmcnt(0)
285; GFX6-NEXT:    v_ffbh_u32_e32 v12, v8
286; GFX6-NEXT:    v_ffbh_u32_e32 v13, v6
287; GFX6-NEXT:    v_min_u32_e32 v0, 32, v0
288; GFX6-NEXT:    v_min_u32_e32 v9, 32, v9
289; GFX6-NEXT:    v_min_u32_e32 v12, 32, v12
290; GFX6-NEXT:    v_min_u32_e32 v13, 32, v13
291; GFX6-NEXT:    v_lshl_b64 v[3:4], v[3:4], v0
292; GFX6-NEXT:    v_sub_i32_e32 v14, vcc, 32, v0
293; GFX6-NEXT:    v_lshl_b64 v[0:1], v[1:2], v9
294; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 32, v9
295; GFX6-NEXT:    v_lshl_b64 v[7:8], v[7:8], v12
296; GFX6-NEXT:    v_sub_i32_e32 v9, vcc, 32, v12
297; GFX6-NEXT:    v_lshl_b64 v[5:6], v[5:6], v13
298; GFX6-NEXT:    v_sub_i32_e32 v12, vcc, 32, v13
299; GFX6-NEXT:    v_min_u32_e32 v3, 1, v3
300; GFX6-NEXT:    v_min_u32_e32 v0, 1, v0
301; GFX6-NEXT:    v_min_u32_e32 v7, 1, v7
302; GFX6-NEXT:    v_min_u32_e32 v5, 1, v5
303; GFX6-NEXT:    v_or_b32_e32 v3, v4, v3
304; GFX6-NEXT:    v_or_b32_e32 v0, v1, v0
305; GFX6-NEXT:    v_or_b32_e32 v1, v8, v7
306; GFX6-NEXT:    v_or_b32_e32 v4, v6, v5
307; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, v3
308; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, v0
309; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, v1
310; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, v4
311; GFX6-NEXT:    v_ldexp_f32_e32 v3, v3, v14
312; GFX6-NEXT:    v_ldexp_f32_e32 v2, v0, v2
313; GFX6-NEXT:    v_ldexp_f32_e32 v1, v1, v9
314; GFX6-NEXT:    v_ldexp_f32_e32 v0, v4, v12
315; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], v[10:11], s[0:3], 0 addr64
316; GFX6-NEXT:    s_endpgm
317;
318; GFX8-LABEL: v_uint_to_fp_v4i64_to_v4f32:
319; GFX8:       ; %bb.0:
320; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
321; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 5, v0
322; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 4, v0
323; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
324; GFX8-NEXT:    v_mov_b32_e32 v2, s3
325; GFX8-NEXT:    v_add_u32_e32 v5, vcc, s2, v1
326; GFX8-NEXT:    v_addc_u32_e32 v6, vcc, 0, v2, vcc
327; GFX8-NEXT:    v_add_u32_e32 v1, vcc, 16, v5
328; GFX8-NEXT:    v_addc_u32_e32 v2, vcc, 0, v6, vcc
329; GFX8-NEXT:    flat_load_dwordx4 v[1:4], v[1:2]
330; GFX8-NEXT:    flat_load_dwordx4 v[5:8], v[5:6]
331; GFX8-NEXT:    v_add_u32_e32 v9, vcc, s0, v0
332; GFX8-NEXT:    v_mov_b32_e32 v10, s1
333; GFX8-NEXT:    v_addc_u32_e32 v10, vcc, 0, v10, vcc
334; GFX8-NEXT:    s_waitcnt vmcnt(1)
335; GFX8-NEXT:    v_ffbh_u32_e32 v12, v4
336; GFX8-NEXT:    s_waitcnt vmcnt(0)
337; GFX8-NEXT:    v_ffbh_u32_e32 v0, v8
338; GFX8-NEXT:    v_ffbh_u32_e32 v11, v6
339; GFX8-NEXT:    v_ffbh_u32_e32 v13, v2
340; GFX8-NEXT:    v_min_u32_e32 v0, 32, v0
341; GFX8-NEXT:    v_min_u32_e32 v11, 32, v11
342; GFX8-NEXT:    v_min_u32_e32 v12, 32, v12
343; GFX8-NEXT:    v_min_u32_e32 v13, 32, v13
344; GFX8-NEXT:    v_lshlrev_b64 v[7:8], v0, v[7:8]
345; GFX8-NEXT:    v_sub_u32_e32 v14, vcc, 32, v0
346; GFX8-NEXT:    v_lshlrev_b64 v[5:6], v11, v[5:6]
347; GFX8-NEXT:    v_lshlrev_b64 v[3:4], v12, v[3:4]
348; GFX8-NEXT:    v_lshlrev_b64 v[0:1], v13, v[1:2]
349; GFX8-NEXT:    v_min_u32_e32 v7, 1, v7
350; GFX8-NEXT:    v_min_u32_e32 v5, 1, v5
351; GFX8-NEXT:    v_min_u32_e32 v3, 1, v3
352; GFX8-NEXT:    v_min_u32_e32 v0, 1, v0
353; GFX8-NEXT:    v_or_b32_e32 v7, v8, v7
354; GFX8-NEXT:    v_or_b32_e32 v5, v6, v5
355; GFX8-NEXT:    v_or_b32_e32 v3, v4, v3
356; GFX8-NEXT:    v_or_b32_e32 v0, v1, v0
357; GFX8-NEXT:    v_cvt_f32_u32_e32 v1, v7
358; GFX8-NEXT:    v_cvt_f32_u32_e32 v4, v5
359; GFX8-NEXT:    v_cvt_f32_u32_e32 v3, v3
360; GFX8-NEXT:    v_cvt_f32_u32_e32 v5, v0
361; GFX8-NEXT:    v_sub_u32_e32 v11, vcc, 32, v11
362; GFX8-NEXT:    v_sub_u32_e32 v12, vcc, 32, v12
363; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, 32, v13
364; GFX8-NEXT:    v_ldexp_f32 v1, v1, v14
365; GFX8-NEXT:    v_ldexp_f32 v0, v4, v11
366; GFX8-NEXT:    v_ldexp_f32 v3, v3, v12
367; GFX8-NEXT:    v_ldexp_f32 v2, v5, v2
368; GFX8-NEXT:    flat_store_dwordx4 v[9:10], v[0:3]
369; GFX8-NEXT:    s_endpgm
370  %tid = call i32 @llvm.amdgcn.workitem.id.x()
371  %in.gep = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i32 %tid
372  %out.gep = getelementptr <4 x float>, <4 x float> addrspace(1)* %out, i32 %tid
373  %value = load <4 x i64>, <4 x i64> addrspace(1)* %in.gep
374  %result = uitofp <4 x i64> %value to <4 x float>
375  store <4 x float> %result, <4 x float> addrspace(1)* %out.gep
376  ret void
377}
378
379define amdgpu_kernel void @s_uint_to_fp_v2i64_to_v2f16(<2 x half> addrspace(1)* %out, <2 x i64> %in) #0{
380; GFX6-LABEL: s_uint_to_fp_v2i64_to_v2f16:
381; GFX6:       ; %bb.0:
382; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
383; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
384; GFX6-NEXT:    s_mov_b32 s3, 0xf000
385; GFX6-NEXT:    s_mov_b32 s2, -1
386; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
387; GFX6-NEXT:    s_flbit_i32_b32 s8, s7
388; GFX6-NEXT:    s_flbit_i32_b32 s9, s5
389; GFX6-NEXT:    s_min_u32 s8, s8, 32
390; GFX6-NEXT:    s_min_u32 s9, s9, 32
391; GFX6-NEXT:    s_lshl_b64 s[6:7], s[6:7], s8
392; GFX6-NEXT:    s_sub_i32 s8, 32, s8
393; GFX6-NEXT:    s_lshl_b64 s[4:5], s[4:5], s9
394; GFX6-NEXT:    s_sub_i32 s9, 32, s9
395; GFX6-NEXT:    s_min_u32 s6, s6, 1
396; GFX6-NEXT:    s_min_u32 s4, s4, 1
397; GFX6-NEXT:    s_or_b32 s6, s7, s6
398; GFX6-NEXT:    s_or_b32 s4, s5, s4
399; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s6
400; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s4
401; GFX6-NEXT:    v_ldexp_f32_e64 v0, v0, s8
402; GFX6-NEXT:    v_ldexp_f32_e64 v1, v1, s9
403; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
404; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
405; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
406; GFX6-NEXT:    v_or_b32_e32 v0, v1, v0
407; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
408; GFX6-NEXT:    s_endpgm
409;
410; GFX8-LABEL: s_uint_to_fp_v2i64_to_v2f16:
411; GFX8:       ; %bb.0:
412; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
413; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
414; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
415; GFX8-NEXT:    s_flbit_i32_b32 s2, s7
416; GFX8-NEXT:    s_flbit_i32_b32 s3, s5
417; GFX8-NEXT:    s_min_u32 s8, s2, 32
418; GFX8-NEXT:    s_min_u32 s9, s3, 32
419; GFX8-NEXT:    s_lshl_b64 s[2:3], s[6:7], s8
420; GFX8-NEXT:    s_min_u32 s2, s2, 1
421; GFX8-NEXT:    s_lshl_b64 s[4:5], s[4:5], s9
422; GFX8-NEXT:    s_or_b32 s2, s3, s2
423; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s2
424; GFX8-NEXT:    s_min_u32 s2, s4, 1
425; GFX8-NEXT:    s_or_b32 s2, s5, s2
426; GFX8-NEXT:    v_cvt_f32_u32_e32 v1, s2
427; GFX8-NEXT:    s_sub_i32 s6, 32, s8
428; GFX8-NEXT:    s_sub_i32 s2, 32, s9
429; GFX8-NEXT:    v_ldexp_f32 v0, v0, s6
430; GFX8-NEXT:    v_ldexp_f32 v1, v1, s2
431; GFX8-NEXT:    v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
432; GFX8-NEXT:    v_cvt_f16_f32_e32 v1, v1
433; GFX8-NEXT:    v_or_b32_e32 v2, v1, v0
434; GFX8-NEXT:    v_mov_b32_e32 v0, s0
435; GFX8-NEXT:    v_mov_b32_e32 v1, s1
436; GFX8-NEXT:    flat_store_dword v[0:1], v2
437; GFX8-NEXT:    s_endpgm
438  %result = uitofp <2 x i64> %in to <2 x half>
439  store <2 x half> %result, <2 x half> addrspace(1)* %out
440  ret void
441}
442
443define amdgpu_kernel void @v_uint_to_fp_v4i64_to_v4f16(<4 x half> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) #0 {
444; GFX6-LABEL: v_uint_to_fp_v4i64_to_v4f16:
445; GFX6:       ; %bb.0:
446; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
447; GFX6-NEXT:    s_mov_b32 s7, 0xf000
448; GFX6-NEXT:    s_mov_b32 s6, 0
449; GFX6-NEXT:    v_lshlrev_b32_e32 v8, 5, v0
450; GFX6-NEXT:    v_mov_b32_e32 v9, 0
451; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
452; GFX6-NEXT:    s_mov_b64 s[4:5], s[2:3]
453; GFX6-NEXT:    buffer_load_dwordx4 v[1:4], v[8:9], s[4:7], 0 addr64 offset:16
454; GFX6-NEXT:    buffer_load_dwordx4 v[5:8], v[8:9], s[4:7], 0 addr64
455; GFX6-NEXT:    v_lshlrev_b32_e32 v10, 3, v0
456; GFX6-NEXT:    v_mov_b32_e32 v11, v9
457; GFX6-NEXT:    s_mov_b64 s[2:3], s[6:7]
458; GFX6-NEXT:    s_waitcnt vmcnt(1)
459; GFX6-NEXT:    v_ffbh_u32_e32 v0, v4
460; GFX6-NEXT:    v_ffbh_u32_e32 v9, v2
461; GFX6-NEXT:    s_waitcnt vmcnt(0)
462; GFX6-NEXT:    v_ffbh_u32_e32 v12, v8
463; GFX6-NEXT:    v_ffbh_u32_e32 v13, v6
464; GFX6-NEXT:    v_min_u32_e32 v0, 32, v0
465; GFX6-NEXT:    v_min_u32_e32 v9, 32, v9
466; GFX6-NEXT:    v_min_u32_e32 v12, 32, v12
467; GFX6-NEXT:    v_min_u32_e32 v13, 32, v13
468; GFX6-NEXT:    v_lshl_b64 v[3:4], v[3:4], v0
469; GFX6-NEXT:    v_sub_i32_e32 v14, vcc, 32, v0
470; GFX6-NEXT:    v_lshl_b64 v[0:1], v[1:2], v9
471; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 32, v9
472; GFX6-NEXT:    v_lshl_b64 v[7:8], v[7:8], v12
473; GFX6-NEXT:    v_sub_i32_e32 v9, vcc, 32, v12
474; GFX6-NEXT:    v_lshl_b64 v[5:6], v[5:6], v13
475; GFX6-NEXT:    v_sub_i32_e32 v12, vcc, 32, v13
476; GFX6-NEXT:    v_min_u32_e32 v3, 1, v3
477; GFX6-NEXT:    v_min_u32_e32 v0, 1, v0
478; GFX6-NEXT:    v_min_u32_e32 v7, 1, v7
479; GFX6-NEXT:    v_min_u32_e32 v5, 1, v5
480; GFX6-NEXT:    v_or_b32_e32 v3, v4, v3
481; GFX6-NEXT:    v_or_b32_e32 v0, v1, v0
482; GFX6-NEXT:    v_or_b32_e32 v1, v8, v7
483; GFX6-NEXT:    v_or_b32_e32 v4, v6, v5
484; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, v3
485; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, v0
486; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, v1
487; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, v4
488; GFX6-NEXT:    v_ldexp_f32_e32 v3, v3, v14
489; GFX6-NEXT:    v_ldexp_f32_e32 v0, v0, v2
490; GFX6-NEXT:    v_ldexp_f32_e32 v1, v1, v9
491; GFX6-NEXT:    v_ldexp_f32_e32 v2, v4, v12
492; GFX6-NEXT:    v_cvt_f16_f32_e32 v3, v3
493; GFX6-NEXT:    v_cvt_f16_f32_e32 v0, v0
494; GFX6-NEXT:    v_cvt_f16_f32_e32 v1, v1
495; GFX6-NEXT:    v_cvt_f16_f32_e32 v2, v2
496; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
497; GFX6-NEXT:    v_lshlrev_b32_e32 v4, 16, v1
498; GFX6-NEXT:    v_or_b32_e32 v1, v0, v3
499; GFX6-NEXT:    v_or_b32_e32 v0, v2, v4
500; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], v[10:11], s[0:3], 0 addr64
501; GFX6-NEXT:    s_endpgm
502;
503; GFX8-LABEL: v_uint_to_fp_v4i64_to_v4f16:
504; GFX8:       ; %bb.0:
505; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
506; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 5, v0
507; GFX8-NEXT:    v_lshlrev_b32_e32 v9, 3, v0
508; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
509; GFX8-NEXT:    v_mov_b32_e32 v2, s3
510; GFX8-NEXT:    v_add_u32_e32 v5, vcc, s2, v1
511; GFX8-NEXT:    v_addc_u32_e32 v6, vcc, 0, v2, vcc
512; GFX8-NEXT:    v_add_u32_e32 v1, vcc, 16, v5
513; GFX8-NEXT:    v_addc_u32_e32 v2, vcc, 0, v6, vcc
514; GFX8-NEXT:    flat_load_dwordx4 v[1:4], v[1:2]
515; GFX8-NEXT:    flat_load_dwordx4 v[5:8], v[5:6]
516; GFX8-NEXT:    v_mov_b32_e32 v10, s1
517; GFX8-NEXT:    s_waitcnt vmcnt(1)
518; GFX8-NEXT:    v_ffbh_u32_e32 v12, v4
519; GFX8-NEXT:    s_waitcnt vmcnt(0)
520; GFX8-NEXT:    v_ffbh_u32_e32 v0, v8
521; GFX8-NEXT:    v_ffbh_u32_e32 v11, v6
522; GFX8-NEXT:    v_ffbh_u32_e32 v13, v2
523; GFX8-NEXT:    v_min_u32_e32 v0, 32, v0
524; GFX8-NEXT:    v_min_u32_e32 v11, 32, v11
525; GFX8-NEXT:    v_min_u32_e32 v12, 32, v12
526; GFX8-NEXT:    v_min_u32_e32 v13, 32, v13
527; GFX8-NEXT:    v_lshlrev_b64 v[7:8], v0, v[7:8]
528; GFX8-NEXT:    v_sub_u32_e32 v14, vcc, 32, v0
529; GFX8-NEXT:    v_lshlrev_b64 v[5:6], v11, v[5:6]
530; GFX8-NEXT:    v_lshlrev_b64 v[3:4], v12, v[3:4]
531; GFX8-NEXT:    v_lshlrev_b64 v[0:1], v13, v[1:2]
532; GFX8-NEXT:    v_min_u32_e32 v7, 1, v7
533; GFX8-NEXT:    v_min_u32_e32 v5, 1, v5
534; GFX8-NEXT:    v_min_u32_e32 v3, 1, v3
535; GFX8-NEXT:    v_min_u32_e32 v0, 1, v0
536; GFX8-NEXT:    v_or_b32_e32 v7, v8, v7
537; GFX8-NEXT:    v_or_b32_e32 v5, v6, v5
538; GFX8-NEXT:    v_or_b32_e32 v3, v4, v3
539; GFX8-NEXT:    v_or_b32_e32 v0, v1, v0
540; GFX8-NEXT:    v_cvt_f32_u32_e32 v1, v7
541; GFX8-NEXT:    v_cvt_f32_u32_e32 v4, v5
542; GFX8-NEXT:    v_cvt_f32_u32_e32 v3, v3
543; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, v0
544; GFX8-NEXT:    v_sub_u32_e32 v11, vcc, 32, v11
545; GFX8-NEXT:    v_sub_u32_e32 v12, vcc, 32, v12
546; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, 32, v13
547; GFX8-NEXT:    v_ldexp_f32 v1, v1, v14
548; GFX8-NEXT:    v_ldexp_f32 v4, v4, v11
549; GFX8-NEXT:    v_ldexp_f32 v3, v3, v12
550; GFX8-NEXT:    v_ldexp_f32 v0, v0, v2
551; GFX8-NEXT:    v_cvt_f16_f32_sdwa v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
552; GFX8-NEXT:    v_cvt_f16_f32_e32 v4, v4
553; GFX8-NEXT:    v_cvt_f16_f32_sdwa v3, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
554; GFX8-NEXT:    v_cvt_f16_f32_e32 v5, v0
555; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v9
556; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v10, vcc
557; GFX8-NEXT:    v_or_b32_e32 v2, v4, v2
558; GFX8-NEXT:    v_or_b32_e32 v3, v5, v3
559; GFX8-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
560; GFX8-NEXT:    s_endpgm
561  %tid = call i32 @llvm.amdgcn.workitem.id.x()
562  %in.gep = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i32 %tid
563  %out.gep = getelementptr <4 x half>, <4 x half> addrspace(1)* %out, i32 %tid
564  %value = load <4 x i64>, <4 x i64> addrspace(1)* %in.gep
565  %result = uitofp <4 x i64> %value to <4 x half>
566  store <4 x half> %result, <4 x half> addrspace(1)* %out.gep
567  ret void
568}
569
570declare i32 @llvm.amdgcn.workitem.id.x() #1
571
572attributes #0 = { nounwind }
573attributes #1 = { nounwind readnone }
574