1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_udiv_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_udiv_i64:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
9; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
10; GCN-NEXT:    s_mov_b32 s7, 0xf000
11; GCN-NEXT:    s_mov_b32 s6, -1
12; GCN-NEXT:    s_waitcnt lgkmcnt(0)
13; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
14; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s9
15; GCN-NEXT:    s_sub_u32 s4, 0, s8
16; GCN-NEXT:    s_subb_u32 s5, 0, s9
17; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
18; GCN-NEXT:    v_rcp_f32_e32 v0, v0
19; GCN-NEXT:    v_mov_b32_e32 v1, 0
20; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
21; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
22; GCN-NEXT:    v_trunc_f32_e32 v2, v2
23; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
24; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
25; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
26; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
27; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
28; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
29; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
30; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
31; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
32; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
33; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
34; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
35; GCN-NEXT:    v_mul_lo_u32 v7, v2, v5
36; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
37; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
38; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
39; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
40; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
41; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
42; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
43; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
44; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
45; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
46; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
47; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
48; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
49; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
50; GCN-NEXT:    v_mul_lo_u32 v5, s5, v0
51; GCN-NEXT:    s_mov_b32 s5, s1
52; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
53; GCN-NEXT:    v_mul_lo_u32 v4, s4, v0
54; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
55; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
56; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
57; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
58; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
59; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
60; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
61; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
62; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
63; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
64; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
65; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
66; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v1, vcc
67; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
68; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
69; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
70; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
71; GCN-NEXT:    v_mul_lo_u32 v3, s2, v2
72; GCN-NEXT:    v_mul_hi_u32 v4, s2, v0
73; GCN-NEXT:    v_mul_hi_u32 v5, s2, v2
74; GCN-NEXT:    v_mul_hi_u32 v6, s3, v2
75; GCN-NEXT:    v_mul_lo_u32 v2, s3, v2
76; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
77; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
78; GCN-NEXT:    v_mul_lo_u32 v5, s3, v0
79; GCN-NEXT:    v_mul_hi_u32 v0, s3, v0
80; GCN-NEXT:    s_mov_b32 s4, s0
81; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
82; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
83; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
84; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
85; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
86; GCN-NEXT:    v_mul_lo_u32 v2, s8, v1
87; GCN-NEXT:    v_mul_hi_u32 v3, s8, v0
88; GCN-NEXT:    v_mul_lo_u32 v4, s9, v0
89; GCN-NEXT:    v_mov_b32_e32 v5, s9
90; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
91; GCN-NEXT:    v_mul_lo_u32 v3, s8, v0
92; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
93; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s3, v2
94; GCN-NEXT:    v_sub_i32_e32 v3, vcc, s2, v3
95; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
96; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s8, v3
97; GCN-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
98; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v4
99; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
100; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v5
101; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
102; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v4
103; GCN-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
104; GCN-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
105; GCN-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
106; GCN-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
107; GCN-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
108; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
109; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
110; GCN-NEXT:    v_mov_b32_e32 v6, s3
111; GCN-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
112; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
113; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
114; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
115; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
116; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v2
117; GCN-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
118; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
119; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
120; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
121; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
122; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
123; GCN-NEXT:    s_endpgm
124;
125; GCN-IR-LABEL: s_test_udiv_i64:
126; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
127; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
128; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
129; GCN-IR-NEXT:    s_mov_b64 s[6:7], 0
130; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
131; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[4:5], 0
132; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
133; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s4
134; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
135; GCN-IR-NEXT:    s_or_b64 s[14:15], s[8:9], s[10:11]
136; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s5
137; GCN-IR-NEXT:    s_min_u32 s10, s12, s8
138; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s2
139; GCN-IR-NEXT:    s_add_i32 s8, s8, 32
140; GCN-IR-NEXT:    s_flbit_i32_b32 s9, s3
141; GCN-IR-NEXT:    s_min_u32 s12, s8, s9
142; GCN-IR-NEXT:    s_sub_u32 s8, s10, s12
143; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
144; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[16:17], s[8:9], 63
145; GCN-IR-NEXT:    s_mov_b32 s11, 0
146; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[16:17]
147; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[16:17], s[8:9], 63
148; GCN-IR-NEXT:    s_xor_b64 s[18:19], s[14:15], -1
149; GCN-IR-NEXT:    s_and_b64 s[16:17], s[18:19], s[16:17]
150; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[16:17]
151; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_5
152; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
153; GCN-IR-NEXT:    s_add_u32 s14, s8, 1
154; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
155; GCN-IR-NEXT:    s_addc_u32 s15, s9, 0
156; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
157; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[14:15], v[0:1]
158; GCN-IR-NEXT:    s_sub_i32 s8, 63, s8
159; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
160; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[2:3], s8
161; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_4
162; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
163; GCN-IR-NEXT:    s_lshr_b64 s[14:15], s[2:3], s14
164; GCN-IR-NEXT:    s_add_u32 s16, s4, -1
165; GCN-IR-NEXT:    s_addc_u32 s17, s5, -1
166; GCN-IR-NEXT:    s_not_b64 s[2:3], s[10:11]
167; GCN-IR-NEXT:    s_add_u32 s2, s2, s12
168; GCN-IR-NEXT:    s_mov_b32 s13, s11
169; GCN-IR-NEXT:    s_addc_u32 s3, s3, s11
170; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
171; GCN-IR-NEXT:    s_mov_b32 s7, 0
172; GCN-IR-NEXT:  .LBB0_3: ; %udiv-do-while
173; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
174; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[14:15], 1
175; GCN-IR-NEXT:    s_lshr_b32 s6, s9, 31
176; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
177; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[6:7]
178; GCN-IR-NEXT:    s_or_b64 s[8:9], s[10:11], s[8:9]
179; GCN-IR-NEXT:    s_sub_u32 s6, s16, s12
180; GCN-IR-NEXT:    s_subb_u32 s6, s17, s13
181; GCN-IR-NEXT:    s_ashr_i32 s10, s6, 31
182; GCN-IR-NEXT:    s_mov_b32 s11, s10
183; GCN-IR-NEXT:    s_and_b32 s6, s10, 1
184; GCN-IR-NEXT:    s_and_b64 s[14:15], s[10:11], s[4:5]
185; GCN-IR-NEXT:    s_sub_u32 s14, s12, s14
186; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
187; GCN-IR-NEXT:    s_subb_u32 s15, s13, s15
188; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
189; GCN-IR-NEXT:    s_add_u32 s2, s2, 1
190; GCN-IR-NEXT:    s_addc_u32 s3, s3, 0
191; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1]
192; GCN-IR-NEXT:    s_mov_b64 s[10:11], s[6:7]
193; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_3
194; GCN-IR-NEXT:  .LBB0_4: ; %Flow6
195; GCN-IR-NEXT:    s_lshl_b64 s[2:3], s[8:9], 1
196; GCN-IR-NEXT:    s_or_b64 s[2:3], s[6:7], s[2:3]
197; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
198; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
199; GCN-IR-NEXT:    s_branch .LBB0_6
200; GCN-IR-NEXT:  .LBB0_5:
201; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
202; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[14:15]
203; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
204; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[14:15]
205; GCN-IR-NEXT:  .LBB0_6: ; %udiv-end
206; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
207; GCN-IR-NEXT:    s_mov_b32 s2, -1
208; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
209; GCN-IR-NEXT:    s_endpgm
210  %result = udiv i64 %x, %y
211  store i64 %result, i64 addrspace(1)* %out
212  ret void
213}
214
215define i64 @v_test_udiv_i64(i64 %x, i64 %y) {
216; GCN-LABEL: v_test_udiv_i64:
217; GCN:       ; %bb.0:
218; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
219; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v2
220; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v3
221; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v2
222; GCN-NEXT:    v_subb_u32_e32 v7, vcc, 0, v3, vcc
223; GCN-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
224; GCN-NEXT:    v_rcp_f32_e32 v4, v4
225; GCN-NEXT:    v_mov_b32_e32 v13, 0
226; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
227; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
228; GCN-NEXT:    v_trunc_f32_e32 v5, v5
229; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
230; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
231; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
232; GCN-NEXT:    v_mul_lo_u32 v8, v6, v5
233; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
234; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
235; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
236; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
237; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
238; GCN-NEXT:    v_mul_lo_u32 v10, v4, v8
239; GCN-NEXT:    v_mul_hi_u32 v11, v4, v9
240; GCN-NEXT:    v_mul_hi_u32 v12, v4, v8
241; GCN-NEXT:    v_mul_hi_u32 v14, v5, v8
242; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
243; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
244; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
245; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
246; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
247; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
248; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v11, v9, vcc
249; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v13, vcc
250; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
251; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
252; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
253; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v9, vcc
254; GCN-NEXT:    v_mul_lo_u32 v8, v6, v5
255; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
256; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
257; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
258; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
259; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
260; GCN-NEXT:    v_mul_lo_u32 v10, v4, v7
261; GCN-NEXT:    v_mul_hi_u32 v11, v4, v6
262; GCN-NEXT:    v_mul_hi_u32 v12, v4, v7
263; GCN-NEXT:    v_mul_hi_u32 v9, v5, v6
264; GCN-NEXT:    v_mul_lo_u32 v6, v5, v6
265; GCN-NEXT:    v_mul_hi_u32 v8, v5, v7
266; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
267; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
268; GCN-NEXT:    v_mul_lo_u32 v7, v5, v7
269; GCN-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
270; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
271; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v8, v13, vcc
272; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
273; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
274; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
275; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
276; GCN-NEXT:    v_mul_lo_u32 v6, v0, v5
277; GCN-NEXT:    v_mul_hi_u32 v7, v0, v4
278; GCN-NEXT:    v_mul_hi_u32 v8, v0, v5
279; GCN-NEXT:    v_mul_hi_u32 v9, v1, v5
280; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
281; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
282; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
283; GCN-NEXT:    v_mul_lo_u32 v8, v1, v4
284; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
285; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
286; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v4, vcc
287; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v13, vcc
288; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
289; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
290; GCN-NEXT:    v_mul_lo_u32 v6, v2, v5
291; GCN-NEXT:    v_mul_hi_u32 v7, v2, v4
292; GCN-NEXT:    v_mul_lo_u32 v8, v3, v4
293; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
294; GCN-NEXT:    v_mul_lo_u32 v7, v2, v4
295; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
296; GCN-NEXT:    v_sub_i32_e32 v8, vcc, v1, v6
297; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v7
298; GCN-NEXT:    v_subb_u32_e64 v7, s[4:5], v8, v3, vcc
299; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v0, v2
300; GCN-NEXT:    v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5]
301; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v3
302; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
303; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v2
304; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
305; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v3
306; GCN-NEXT:    v_cndmask_b32_e64 v7, v9, v8, s[4:5]
307; GCN-NEXT:    v_add_i32_e64 v8, s[4:5], 2, v4
308; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
309; GCN-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, v5, s[4:5]
310; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
311; GCN-NEXT:    v_add_i32_e64 v10, s[4:5], 1, v4
312; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
313; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
314; GCN-NEXT:    v_addc_u32_e64 v11, s[4:5], 0, v5, s[4:5]
315; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
316; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
317; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
318; GCN-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
319; GCN-NEXT:    v_cndmask_b32_e64 v7, v10, v8, s[4:5]
320; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
321; GCN-NEXT:    v_cndmask_b32_e64 v1, v11, v9, s[4:5]
322; GCN-NEXT:    v_cndmask_b32_e32 v0, v4, v7, vcc
323; GCN-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
324; GCN-NEXT:    s_setpc_b64 s[30:31]
325;
326; GCN-IR-LABEL: v_test_udiv_i64:
327; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
328; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
329; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[2:3]
330; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
331; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v2
332; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
333; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
334; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v3
335; GCN-IR-NEXT:    v_min_u32_e32 v8, v4, v5
336; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
337; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
338; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
339; GCN-IR-NEXT:    v_min_u32_e32 v10, v4, v5
340; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v8, v10
341; GCN-IR-NEXT:    v_subb_u32_e64 v7, s[6:7], 0, 0, vcc
342; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[6:7]
343; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
344; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
345; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[6:7]
346; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
347; GCN-IR-NEXT:    v_mov_b32_e32 v11, v9
348; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v1, 0, s[4:5]
349; GCN-IR-NEXT:    v_cndmask_b32_e64 v5, v0, 0, s[4:5]
350; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
351; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
352; GCN-IR-NEXT:    s_cbranch_execz .LBB1_6
353; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
354; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v6
355; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v7, vcc
356; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v6
357; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[12:13], v[6:7]
358; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[0:1], v4
359; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
360; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
361; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
362; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
363; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
364; GCN-IR-NEXT:    s_cbranch_execz .LBB1_5
365; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
366; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, -1, v2
367; GCN-IR-NEXT:    v_lshr_b64 v[12:13], v[0:1], v12
368; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, -1, v3, vcc
369; GCN-IR-NEXT:    v_not_b32_e32 v0, v8
370; GCN-IR-NEXT:    v_not_b32_e32 v1, v9
371; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v10
372; GCN-IR-NEXT:    v_mov_b32_e32 v8, 0
373; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, v1, v11, vcc
374; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
375; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
376; GCN-IR-NEXT:  .LBB1_3: ; %udiv-do-while
377; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
378; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[12:13], 1
379; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
380; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v6
381; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
382; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v14, v10
383; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v15, v11, vcc
384; GCN-IR-NEXT:    v_or_b32_e32 v4, v8, v4
385; GCN-IR-NEXT:    v_ashrrev_i32_e32 v8, 31, v6
386; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v8
387; GCN-IR-NEXT:    v_and_b32_e32 v13, v8, v3
388; GCN-IR-NEXT:    v_and_b32_e32 v12, v8, v2
389; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v0
390; GCN-IR-NEXT:    v_or_b32_e32 v5, v9, v5
391; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v1, vcc
392; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[8:9], v[0:1]
393; GCN-IR-NEXT:    v_mov_b32_e32 v0, v8
394; GCN-IR-NEXT:    v_sub_i32_e64 v12, s[4:5], v10, v12
395; GCN-IR-NEXT:    v_mov_b32_e32 v1, v9
396; GCN-IR-NEXT:    v_mov_b32_e32 v9, v7
397; GCN-IR-NEXT:    v_subb_u32_e64 v13, s[4:5], v11, v13, s[4:5]
398; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
399; GCN-IR-NEXT:    v_mov_b32_e32 v8, v6
400; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
401; GCN-IR-NEXT:    s_cbranch_execnz .LBB1_3
402; GCN-IR-NEXT:  ; %bb.4: ; %Flow
403; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
404; GCN-IR-NEXT:  .LBB1_5: ; %Flow3
405; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
406; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[4:5], 1
407; GCN-IR-NEXT:    v_or_b32_e32 v4, v7, v1
408; GCN-IR-NEXT:    v_or_b32_e32 v5, v6, v0
409; GCN-IR-NEXT:  .LBB1_6: ; %Flow4
410; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
411; GCN-IR-NEXT:    v_mov_b32_e32 v0, v5
412; GCN-IR-NEXT:    v_mov_b32_e32 v1, v4
413; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
414  %result = udiv i64 %x, %y
415  ret i64 %result
416}
417
418define amdgpu_kernel void @s_test_udiv24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
419; GCN-LABEL: s_test_udiv24_64:
420; GCN:       ; %bb.0:
421; GCN-NEXT:    s_load_dword s4, s[0:1], 0xe
422; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
423; GCN-NEXT:    s_mov_b32 s7, 0xf000
424; GCN-NEXT:    s_mov_b32 s6, -1
425; GCN-NEXT:    s_waitcnt lgkmcnt(0)
426; GCN-NEXT:    s_lshr_b32 s2, s4, 8
427; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
428; GCN-NEXT:    s_lshr_b32 s2, s3, 8
429; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s2
430; GCN-NEXT:    s_mov_b32 s4, s0
431; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
432; GCN-NEXT:    s_mov_b32 s5, s1
433; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
434; GCN-NEXT:    v_trunc_f32_e32 v2, v2
435; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
436; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
437; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
438; GCN-NEXT:    v_mov_b32_e32 v1, 0
439; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
440; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
441; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
442; GCN-NEXT:    s_endpgm
443;
444; GCN-IR-LABEL: s_test_udiv24_64:
445; GCN-IR:       ; %bb.0:
446; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xe
447; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
448; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
449; GCN-IR-NEXT:    s_mov_b32 s6, -1
450; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
451; GCN-IR-NEXT:    s_lshr_b32 s2, s4, 8
452; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
453; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 8
454; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s2
455; GCN-IR-NEXT:    s_mov_b32 s4, s0
456; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
457; GCN-IR-NEXT:    s_mov_b32 s5, s1
458; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
459; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
460; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
461; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
462; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
463; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
464; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
465; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
466; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
467; GCN-IR-NEXT:    s_endpgm
468  %1 = lshr i64 %x, 40
469  %2 = lshr i64 %y, 40
470  %result = udiv i64 %1, %2
471  store i64 %result, i64 addrspace(1)* %out
472  ret void
473}
474
475define i64 @v_test_udiv24_i64(i64 %x, i64 %y) {
476; GCN-LABEL: v_test_udiv24_i64:
477; GCN:       ; %bb.0:
478; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
479; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v3
480; GCN-NEXT:    v_cvt_f32_u32_e32 v0, v0
481; GCN-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
482; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v1
483; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
484; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
485; GCN-NEXT:    v_trunc_f32_e32 v2, v2
486; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
487; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
488; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
489; GCN-NEXT:    v_mov_b32_e32 v1, 0
490; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
491; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
492; GCN-NEXT:    s_setpc_b64 s[30:31]
493;
494; GCN-IR-LABEL: v_test_udiv24_i64:
495; GCN-IR:       ; %bb.0:
496; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
497; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v3
498; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, v0
499; GCN-IR-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
500; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, v1
501; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
502; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
503; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
504; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
505; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
506; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
507; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
508; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
509; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
510; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
511  %1 = lshr i64 %x, 40
512  %2 = lshr i64 %y, 40
513  %result = udiv i64 %1, %2
514  ret i64 %result
515}
516
517define amdgpu_kernel void @s_test_udiv32_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
518; GCN-LABEL: s_test_udiv32_i64:
519; GCN:       ; %bb.0:
520; GCN-NEXT:    s_load_dword s4, s[0:1], 0xe
521; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
522; GCN-NEXT:    s_mov_b32 s7, 0xf000
523; GCN-NEXT:    s_mov_b32 s6, -1
524; GCN-NEXT:    s_waitcnt lgkmcnt(0)
525; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
526; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s3
527; GCN-NEXT:    s_mov_b32 s4, s0
528; GCN-NEXT:    s_mov_b32 s5, s1
529; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
530; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
531; GCN-NEXT:    v_trunc_f32_e32 v2, v2
532; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
533; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
534; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
535; GCN-NEXT:    v_mov_b32_e32 v1, 0
536; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
537; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
538; GCN-NEXT:    s_endpgm
539;
540; GCN-IR-LABEL: s_test_udiv32_i64:
541; GCN-IR:       ; %bb.0:
542; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xe
543; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
544; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
545; GCN-IR-NEXT:    s_mov_b32 s6, -1
546; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
547; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
548; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s3
549; GCN-IR-NEXT:    s_mov_b32 s4, s0
550; GCN-IR-NEXT:    s_mov_b32 s5, s1
551; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
552; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
553; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
554; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
555; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
556; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
557; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
558; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
559; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
560; GCN-IR-NEXT:    s_endpgm
561  %1 = lshr i64 %x, 32
562  %2 = lshr i64 %y, 32
563  %result = udiv i64 %1, %2
564  store i64 %result, i64 addrspace(1)* %out
565  ret void
566}
567
568define amdgpu_kernel void @s_test_udiv31_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
569; GCN-LABEL: s_test_udiv31_i64:
570; GCN:       ; %bb.0:
571; GCN-NEXT:    s_load_dword s4, s[0:1], 0xe
572; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
573; GCN-NEXT:    s_mov_b32 s7, 0xf000
574; GCN-NEXT:    s_mov_b32 s6, -1
575; GCN-NEXT:    s_waitcnt lgkmcnt(0)
576; GCN-NEXT:    s_lshr_b32 s2, s4, 1
577; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
578; GCN-NEXT:    s_lshr_b32 s2, s3, 1
579; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s2
580; GCN-NEXT:    s_mov_b32 s4, s0
581; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
582; GCN-NEXT:    s_mov_b32 s5, s1
583; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
584; GCN-NEXT:    v_trunc_f32_e32 v2, v2
585; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
586; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
587; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
588; GCN-NEXT:    v_mov_b32_e32 v1, 0
589; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
590; GCN-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
591; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
592; GCN-NEXT:    s_endpgm
593;
594; GCN-IR-LABEL: s_test_udiv31_i64:
595; GCN-IR:       ; %bb.0:
596; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xe
597; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
598; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
599; GCN-IR-NEXT:    s_mov_b32 s6, -1
600; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
601; GCN-IR-NEXT:    s_lshr_b32 s2, s4, 1
602; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
603; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 1
604; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s2
605; GCN-IR-NEXT:    s_mov_b32 s4, s0
606; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
607; GCN-IR-NEXT:    s_mov_b32 s5, s1
608; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
609; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
610; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
611; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
612; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
613; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
614; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
615; GCN-IR-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
616; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
617; GCN-IR-NEXT:    s_endpgm
618  %1 = lshr i64 %x, 33
619  %2 = lshr i64 %y, 33
620  %result = udiv i64 %1, %2
621  store i64 %result, i64 addrspace(1)* %out
622  ret void
623}
624
625define amdgpu_kernel void @s_test_udiv23_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
626; GCN-LABEL: s_test_udiv23_i64:
627; GCN:       ; %bb.0:
628; GCN-NEXT:    s_load_dword s4, s[0:1], 0xe
629; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
630; GCN-NEXT:    s_mov_b32 s7, 0xf000
631; GCN-NEXT:    s_mov_b32 s6, -1
632; GCN-NEXT:    s_waitcnt lgkmcnt(0)
633; GCN-NEXT:    s_lshr_b32 s2, s4, 9
634; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
635; GCN-NEXT:    s_lshr_b32 s2, s3, 9
636; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s2
637; GCN-NEXT:    s_mov_b32 s4, s0
638; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
639; GCN-NEXT:    s_mov_b32 s5, s1
640; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
641; GCN-NEXT:    v_trunc_f32_e32 v2, v2
642; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
643; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
644; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
645; GCN-NEXT:    v_mov_b32_e32 v1, 0
646; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
647; GCN-NEXT:    v_and_b32_e32 v0, 0x7fffff, v0
648; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
649; GCN-NEXT:    s_endpgm
650;
651; GCN-IR-LABEL: s_test_udiv23_i64:
652; GCN-IR:       ; %bb.0:
653; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xe
654; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
655; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
656; GCN-IR-NEXT:    s_mov_b32 s6, -1
657; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
658; GCN-IR-NEXT:    s_lshr_b32 s2, s4, 9
659; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
660; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 9
661; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s2
662; GCN-IR-NEXT:    s_mov_b32 s4, s0
663; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
664; GCN-IR-NEXT:    s_mov_b32 s5, s1
665; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
666; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
667; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
668; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
669; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
670; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
671; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
672; GCN-IR-NEXT:    v_and_b32_e32 v0, 0x7fffff, v0
673; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
674; GCN-IR-NEXT:    s_endpgm
675  %1 = lshr i64 %x, 41
676  %2 = lshr i64 %y, 41
677  %result = udiv i64 %1, %2
678  store i64 %result, i64 addrspace(1)* %out
679  ret void
680}
681
682define amdgpu_kernel void @s_test_udiv24_i48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
683; GCN-LABEL: s_test_udiv24_i48:
684; GCN:       ; %bb.0:
685; GCN-NEXT:    s_load_dword s2, s[0:1], 0xe
686; GCN-NEXT:    s_load_dword s4, s[0:1], 0xd
687; GCN-NEXT:    s_mov_b32 s6, 0xffff
688; GCN-NEXT:    s_mov_b32 s7, 0xff000000
689; GCN-NEXT:    v_cvt_f32_ubyte3_e32 v2, s6
690; GCN-NEXT:    s_waitcnt lgkmcnt(0)
691; GCN-NEXT:    s_and_b32 s3, s2, s6
692; GCN-NEXT:    s_and_b32 s2, s4, s7
693; GCN-NEXT:    v_mov_b32_e32 v0, s2
694; GCN-NEXT:    v_alignbit_b32 v0, s3, v0, 24
695; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v0
696; GCN-NEXT:    s_load_dword s8, s[0:1], 0xb
697; GCN-NEXT:    s_load_dword s9, s[0:1], 0xc
698; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
699; GCN-NEXT:    s_lshr_b64 s[0:1], s[2:3], 24
700; GCN-NEXT:    v_mac_f32_e32 v1, 0x4f800000, v2
701; GCN-NEXT:    v_rcp_f32_e32 v1, v1
702; GCN-NEXT:    s_waitcnt lgkmcnt(0)
703; GCN-NEXT:    s_and_b32 s6, s9, s6
704; GCN-NEXT:    s_and_b32 s8, s8, s7
705; GCN-NEXT:    s_sub_u32 s0, 0, s0
706; GCN-NEXT:    v_mul_f32_e32 v1, 0x5f7ffffc, v1
707; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v1
708; GCN-NEXT:    v_trunc_f32_e32 v2, v2
709; GCN-NEXT:    v_mac_f32_e32 v1, 0xcf800000, v2
710; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
711; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
712; GCN-NEXT:    s_subb_u32 s1, 0, s1
713; GCN-NEXT:    v_mov_b32_e32 v8, 0
714; GCN-NEXT:    v_mul_hi_u32 v3, s0, v1
715; GCN-NEXT:    v_mul_lo_u32 v4, s0, v2
716; GCN-NEXT:    v_mul_lo_u32 v5, s1, v1
717; GCN-NEXT:    s_mov_b32 s7, 0xf000
718; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
719; GCN-NEXT:    v_mul_lo_u32 v4, s0, v1
720; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
721; GCN-NEXT:    v_mul_lo_u32 v5, v1, v3
722; GCN-NEXT:    v_mul_hi_u32 v6, v1, v4
723; GCN-NEXT:    v_mul_hi_u32 v7, v1, v3
724; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
725; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
726; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
727; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
728; GCN-NEXT:    v_mul_lo_u32 v7, v2, v4
729; GCN-NEXT:    v_mul_hi_u32 v4, v2, v4
730; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
731; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v4, vcc
732; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v8, vcc
733; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
734; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
735; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
736; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
737; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
738; GCN-NEXT:    v_mul_hi_u32 v4, s0, v1
739; GCN-NEXT:    v_mul_lo_u32 v5, s1, v1
740; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
741; GCN-NEXT:    v_mul_lo_u32 v4, s0, v1
742; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
743; GCN-NEXT:    v_mul_lo_u32 v7, v1, v3
744; GCN-NEXT:    v_mul_hi_u32 v9, v1, v4
745; GCN-NEXT:    v_mul_hi_u32 v10, v1, v3
746; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
747; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
748; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
749; GCN-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
750; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
751; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
752; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
753; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v6, vcc
754; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
755; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
756; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
757; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
758; GCN-NEXT:    v_mov_b32_e32 v3, s8
759; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
760; GCN-NEXT:    v_alignbit_b32 v3, s6, v3, 24
761; GCN-NEXT:    v_mul_lo_u32 v4, v3, v2
762; GCN-NEXT:    v_mul_hi_u32 v1, v3, v1
763; GCN-NEXT:    v_mul_hi_u32 v2, v3, v2
764; GCN-NEXT:    s_mov_b32 s6, -1
765; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
766; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
767; GCN-NEXT:    v_add_i32_e32 v1, vcc, 0, v1
768; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
769; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v8, vcc
770; GCN-NEXT:    v_add_i32_e32 v1, vcc, 0, v1
771; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
772; GCN-NEXT:    v_mul_lo_u32 v6, v0, v2
773; GCN-NEXT:    v_mul_hi_u32 v7, v0, v1
774; GCN-NEXT:    v_add_i32_e32 v4, vcc, 2, v1
775; GCN-NEXT:    v_mul_lo_u32 v10, v0, v1
776; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v2, vcc
777; GCN-NEXT:    v_add_i32_e32 v8, vcc, 1, v1
778; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v2, vcc
779; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
780; GCN-NEXT:    v_sub_i32_e32 v3, vcc, v3, v10
781; GCN-NEXT:    v_subb_u32_e32 v6, vcc, 0, v6, vcc
782; GCN-NEXT:    v_sub_i32_e32 v7, vcc, v3, v0
783; GCN-NEXT:    v_subbrev_u32_e32 v10, vcc, 0, v6, vcc
784; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v7, v0
785; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
786; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v10
787; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], v3, v0
788; GCN-NEXT:    v_cndmask_b32_e32 v7, -1, v7, vcc
789; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, s[0:1]
790; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v6
791; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
792; GCN-NEXT:    v_cndmask_b32_e64 v0, -1, v0, s[0:1]
793; GCN-NEXT:    v_cndmask_b32_e32 v4, v8, v4, vcc
794; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v0
795; GCN-NEXT:    v_cndmask_b32_e64 v0, v1, v4, s[0:1]
796; GCN-NEXT:    v_cndmask_b32_e32 v1, v9, v5, vcc
797; GCN-NEXT:    v_cndmask_b32_e64 v1, v2, v1, s[0:1]
798; GCN-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
799; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
800; GCN-NEXT:    s_endpgm
801;
802; GCN-IR-LABEL: s_test_udiv24_i48:
803; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
804; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xc
805; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
806; GCN-IR-NEXT:    s_load_dword s3, s[0:1], 0xb
807; GCN-IR-NEXT:    s_load_dword s6, s[0:1], 0xd
808; GCN-IR-NEXT:    s_load_dword s7, s[0:1], 0xe
809; GCN-IR-NEXT:    s_mov_b32 s8, 0xffff
810; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
811; GCN-IR-NEXT:    s_and_b32 s1, s2, s8
812; GCN-IR-NEXT:    s_mov_b32 s2, 0xff000000
813; GCN-IR-NEXT:    s_and_b32 s0, s3, s2
814; GCN-IR-NEXT:    s_and_b32 s3, s7, s8
815; GCN-IR-NEXT:    s_and_b32 s2, s6, s2
816; GCN-IR-NEXT:    s_lshr_b64 s[6:7], s[0:1], 24
817; GCN-IR-NEXT:    s_lshr_b64 s[2:3], s[2:3], 24
818; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[2:3], 0
819; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
820; GCN-IR-NEXT:    s_mov_b64 s[0:1], 0
821; GCN-IR-NEXT:    s_or_b64 s[14:15], s[8:9], s[10:11]
822; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s2
823; GCN-IR-NEXT:    s_add_i32 s8, s8, 32
824; GCN-IR-NEXT:    s_flbit_i32_b32 s9, s3
825; GCN-IR-NEXT:    s_min_u32 s10, s8, s9
826; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s6
827; GCN-IR-NEXT:    s_add_i32 s8, s8, 32
828; GCN-IR-NEXT:    s_flbit_i32_b32 s9, s7
829; GCN-IR-NEXT:    s_min_u32 s12, s8, s9
830; GCN-IR-NEXT:    s_sub_u32 s8, s10, s12
831; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
832; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[16:17], s[8:9], 63
833; GCN-IR-NEXT:    s_mov_b32 s11, 0
834; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[16:17]
835; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[16:17], s[8:9], 63
836; GCN-IR-NEXT:    s_xor_b64 s[18:19], s[14:15], -1
837; GCN-IR-NEXT:    s_and_b64 s[16:17], s[18:19], s[16:17]
838; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[16:17]
839; GCN-IR-NEXT:    s_cbranch_vccz .LBB7_5
840; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
841; GCN-IR-NEXT:    s_add_u32 s14, s8, 1
842; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
843; GCN-IR-NEXT:    s_addc_u32 s15, s9, 0
844; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
845; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[14:15], v[0:1]
846; GCN-IR-NEXT:    s_sub_i32 s8, 63, s8
847; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
848; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[6:7], s8
849; GCN-IR-NEXT:    s_cbranch_vccz .LBB7_4
850; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
851; GCN-IR-NEXT:    s_lshr_b64 s[14:15], s[6:7], s14
852; GCN-IR-NEXT:    s_add_u32 s16, s2, -1
853; GCN-IR-NEXT:    s_addc_u32 s17, s3, -1
854; GCN-IR-NEXT:    s_not_b64 s[0:1], s[10:11]
855; GCN-IR-NEXT:    s_add_u32 s6, s0, s12
856; GCN-IR-NEXT:    s_mov_b32 s13, s11
857; GCN-IR-NEXT:    s_addc_u32 s7, s1, s11
858; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
859; GCN-IR-NEXT:    s_mov_b32 s1, 0
860; GCN-IR-NEXT:  .LBB7_3: ; %udiv-do-while
861; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
862; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[14:15], 1
863; GCN-IR-NEXT:    s_lshr_b32 s0, s9, 31
864; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
865; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[0:1]
866; GCN-IR-NEXT:    s_or_b64 s[8:9], s[10:11], s[8:9]
867; GCN-IR-NEXT:    s_sub_u32 s0, s16, s12
868; GCN-IR-NEXT:    s_subb_u32 s0, s17, s13
869; GCN-IR-NEXT:    s_ashr_i32 s10, s0, 31
870; GCN-IR-NEXT:    s_mov_b32 s11, s10
871; GCN-IR-NEXT:    s_and_b32 s0, s10, 1
872; GCN-IR-NEXT:    s_and_b64 s[14:15], s[10:11], s[2:3]
873; GCN-IR-NEXT:    s_sub_u32 s14, s12, s14
874; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
875; GCN-IR-NEXT:    s_subb_u32 s15, s13, s15
876; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
877; GCN-IR-NEXT:    s_add_u32 s6, s6, 1
878; GCN-IR-NEXT:    s_addc_u32 s7, s7, 0
879; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1]
880; GCN-IR-NEXT:    s_mov_b64 s[10:11], s[0:1]
881; GCN-IR-NEXT:    s_cbranch_vccz .LBB7_3
882; GCN-IR-NEXT:  .LBB7_4: ; %Flow3
883; GCN-IR-NEXT:    s_lshl_b64 s[2:3], s[8:9], 1
884; GCN-IR-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
885; GCN-IR-NEXT:    v_mov_b32_e32 v0, s0
886; GCN-IR-NEXT:    v_mov_b32_e32 v1, s1
887; GCN-IR-NEXT:    s_branch .LBB7_6
888; GCN-IR-NEXT:  .LBB7_5:
889; GCN-IR-NEXT:    v_mov_b32_e32 v0, s7
890; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[14:15]
891; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
892; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[14:15]
893; GCN-IR-NEXT:  .LBB7_6: ; %udiv-end
894; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
895; GCN-IR-NEXT:    s_mov_b32 s6, -1
896; GCN-IR-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
897; GCN-IR-NEXT:    buffer_store_dword v0, off, s[4:7], 0
898; GCN-IR-NEXT:    s_endpgm
899  %1 = lshr i48 %x, 24
900  %2 = lshr i48 %y, 24
901  %result = udiv i48 %1, %2
902  store i48 %result, i48 addrspace(1)* %out
903  ret void
904}
905
906define amdgpu_kernel void @s_test_udiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
907; GCN-LABEL: s_test_udiv_k_num_i64:
908; GCN:       ; %bb.0:
909; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
910; GCN-NEXT:    s_mov_b32 s7, 0xf000
911; GCN-NEXT:    s_mov_b32 s6, -1
912; GCN-NEXT:    s_waitcnt lgkmcnt(0)
913; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
914; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s3
915; GCN-NEXT:    s_sub_u32 s4, 0, s2
916; GCN-NEXT:    s_subb_u32 s5, 0, s3
917; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
918; GCN-NEXT:    v_rcp_f32_e32 v0, v0
919; GCN-NEXT:    v_mov_b32_e32 v1, 0
920; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
921; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
922; GCN-NEXT:    v_trunc_f32_e32 v2, v2
923; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
924; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
925; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
926; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
927; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
928; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
929; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
930; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
931; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
932; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
933; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
934; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
935; GCN-NEXT:    v_mul_hi_u32 v7, v2, v5
936; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
937; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
938; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
939; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
940; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
941; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
942; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v7, vcc
943; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
944; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
945; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
946; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
947; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
948; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
949; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
950; GCN-NEXT:    v_mul_lo_u32 v5, s5, v0
951; GCN-NEXT:    s_mov_b32 s5, s1
952; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
953; GCN-NEXT:    v_mul_lo_u32 v4, s4, v0
954; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
955; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
956; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
957; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
958; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
959; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
960; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
961; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
962; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
963; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
964; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
965; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
966; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v5, v1, vcc
967; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
968; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
969; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
970; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
971; GCN-NEXT:    v_mul_lo_u32 v2, v1, 24
972; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
973; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
974; GCN-NEXT:    v_mov_b32_e32 v4, s3
975; GCN-NEXT:    s_mov_b32 s4, s0
976; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
977; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v1, vcc
978; GCN-NEXT:    v_mul_lo_u32 v1, s3, v0
979; GCN-NEXT:    v_mul_hi_u32 v2, s2, v0
980; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
981; GCN-NEXT:    v_mul_lo_u32 v2, s2, v0
982; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 0, v1
983; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 24, v2
984; GCN-NEXT:    v_subb_u32_e64 v3, s[0:1], v3, v4, vcc
985; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s2, v2
986; GCN-NEXT:    v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1]
987; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v3
988; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
989; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v4
990; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]
991; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s3, v3
992; GCN-NEXT:    v_cndmask_b32_e64 v3, v5, v4, s[0:1]
993; GCN-NEXT:    v_add_i32_e64 v4, s[0:1], 2, v0
994; GCN-NEXT:    v_addc_u32_e64 v5, s[0:1], 0, 0, s[0:1]
995; GCN-NEXT:    v_add_i32_e64 v6, s[0:1], 1, v0
996; GCN-NEXT:    v_addc_u32_e64 v7, s[0:1], 0, 0, s[0:1]
997; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
998; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v3
999; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
1000; GCN-NEXT:    v_cndmask_b32_e64 v3, v7, v5, s[0:1]
1001; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
1002; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v2
1003; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
1004; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v1
1005; GCN-NEXT:    v_cndmask_b32_e32 v1, v5, v2, vcc
1006; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
1007; GCN-NEXT:    v_cndmask_b32_e64 v2, v6, v4, s[0:1]
1008; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
1009; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1010; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1011; GCN-NEXT:    s_endpgm
1012;
1013; GCN-IR-LABEL: s_test_udiv_k_num_i64:
1014; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1015; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1016; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1017; GCN-IR-NEXT:    s_flbit_i32_b32 s4, s2
1018; GCN-IR-NEXT:    s_flbit_i32_b32 s5, s3
1019; GCN-IR-NEXT:    s_add_i32 s4, s4, 32
1020; GCN-IR-NEXT:    s_min_u32 s6, s4, s5
1021; GCN-IR-NEXT:    s_add_u32 s8, s6, 0xffffffc5
1022; GCN-IR-NEXT:    s_addc_u32 s9, 0, -1
1023; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
1024; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[12:13], s[8:9], 63
1025; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0
1026; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
1027; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[12:13], s[8:9], 63
1028; GCN-IR-NEXT:    s_xor_b64 s[14:15], s[10:11], -1
1029; GCN-IR-NEXT:    s_and_b64 s[12:13], s[14:15], s[12:13]
1030; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
1031; GCN-IR-NEXT:    s_cbranch_vccz .LBB8_5
1032; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1033; GCN-IR-NEXT:    s_add_u32 s10, s8, 1
1034; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
1035; GCN-IR-NEXT:    s_addc_u32 s11, s9, 0
1036; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
1037; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
1038; GCN-IR-NEXT:    s_sub_i32 s7, 63, s8
1039; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1040; GCN-IR-NEXT:    s_lshl_b64 s[8:9], 24, s7
1041; GCN-IR-NEXT:    s_cbranch_vccz .LBB8_4
1042; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1043; GCN-IR-NEXT:    s_lshr_b64 s[12:13], 24, s10
1044; GCN-IR-NEXT:    s_add_u32 s14, s2, -1
1045; GCN-IR-NEXT:    s_addc_u32 s15, s3, -1
1046; GCN-IR-NEXT:    s_sub_u32 s6, 58, s6
1047; GCN-IR-NEXT:    s_subb_u32 s7, 0, 0
1048; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1049; GCN-IR-NEXT:    s_mov_b32 s5, 0
1050; GCN-IR-NEXT:  .LBB8_3: ; %udiv-do-while
1051; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1052; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
1053; GCN-IR-NEXT:    s_lshr_b32 s4, s9, 31
1054; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
1055; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[4:5]
1056; GCN-IR-NEXT:    s_or_b64 s[8:9], s[10:11], s[8:9]
1057; GCN-IR-NEXT:    s_sub_u32 s4, s14, s12
1058; GCN-IR-NEXT:    s_subb_u32 s4, s15, s13
1059; GCN-IR-NEXT:    s_ashr_i32 s10, s4, 31
1060; GCN-IR-NEXT:    s_mov_b32 s11, s10
1061; GCN-IR-NEXT:    s_and_b32 s4, s10, 1
1062; GCN-IR-NEXT:    s_and_b64 s[16:17], s[10:11], s[2:3]
1063; GCN-IR-NEXT:    s_sub_u32 s12, s12, s16
1064; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1065; GCN-IR-NEXT:    s_subb_u32 s13, s13, s17
1066; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
1067; GCN-IR-NEXT:    s_add_u32 s6, s6, 1
1068; GCN-IR-NEXT:    s_addc_u32 s7, s7, 0
1069; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1]
1070; GCN-IR-NEXT:    s_mov_b64 s[10:11], s[4:5]
1071; GCN-IR-NEXT:    s_cbranch_vccz .LBB8_3
1072; GCN-IR-NEXT:  .LBB8_4: ; %Flow5
1073; GCN-IR-NEXT:    s_lshl_b64 s[2:3], s[8:9], 1
1074; GCN-IR-NEXT:    s_or_b64 s[2:3], s[4:5], s[2:3]
1075; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1076; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
1077; GCN-IR-NEXT:    s_branch .LBB8_6
1078; GCN-IR-NEXT:  .LBB8_5:
1079; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1080; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, 24, 0, s[10:11]
1081; GCN-IR-NEXT:  .LBB8_6: ; %udiv-end
1082; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1083; GCN-IR-NEXT:    s_mov_b32 s2, -1
1084; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1085; GCN-IR-NEXT:    s_endpgm
1086  %result = udiv i64 24, %x
1087  store i64 %result, i64 addrspace(1)* %out
1088  ret void
1089}
1090
1091; define i64 @v_test_udiv_k_num_i64(i64 %x) {
1092;   %result = udiv i64 24, %x
1093;   ret i64 %result
1094; }
1095
1096define i64 @v_test_udiv_pow2_k_num_i64(i64 %x) {
1097; GCN-LABEL: v_test_udiv_pow2_k_num_i64:
1098; GCN:       ; %bb.0:
1099; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1100; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1101; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1102; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1103; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1104; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
1105; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1106; GCN-NEXT:    v_mov_b32_e32 v11, 0
1107; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1108; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1109; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1110; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1111; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1112; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1113; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1114; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1115; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1116; GCN-NEXT:    v_mul_lo_u32 v9, v4, v2
1117; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1118; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1119; GCN-NEXT:    v_mul_lo_u32 v7, v2, v6
1120; GCN-NEXT:    v_mul_hi_u32 v8, v2, v9
1121; GCN-NEXT:    v_mul_hi_u32 v10, v2, v6
1122; GCN-NEXT:    v_mul_hi_u32 v12, v3, v6
1123; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1124; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1125; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v10, vcc
1126; GCN-NEXT:    v_mul_lo_u32 v10, v3, v9
1127; GCN-NEXT:    v_mul_hi_u32 v9, v3, v9
1128; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
1129; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v9, vcc
1130; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v11, vcc
1131; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1132; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
1133; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
1134; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v7, vcc
1135; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1136; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1137; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1138; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1139; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1140; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
1141; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
1142; GCN-NEXT:    v_mul_hi_u32 v9, v2, v4
1143; GCN-NEXT:    v_mul_hi_u32 v10, v2, v5
1144; GCN-NEXT:    v_mul_hi_u32 v7, v3, v4
1145; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1146; GCN-NEXT:    v_mul_hi_u32 v6, v3, v5
1147; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1148; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
1149; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
1150; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
1151; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
1152; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v11, vcc
1153; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1154; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
1155; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1156; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v3, v5, vcc
1157; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1158; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
1159; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1160; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1161; GCN-NEXT:    v_mul_lo_u32 v4, v0, v2
1162; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v3
1163; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0x8000, v4
1164; GCN-NEXT:    v_subb_u32_e64 v5, s[4:5], v5, v1, vcc
1165; GCN-NEXT:    v_sub_i32_e64 v6, s[4:5], v4, v0
1166; GCN-NEXT:    v_subbrev_u32_e64 v5, s[4:5], 0, v5, s[4:5]
1167; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v5, v1
1168; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
1169; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v0
1170; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
1171; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v5, v1
1172; GCN-NEXT:    v_cndmask_b32_e64 v5, v7, v6, s[4:5]
1173; GCN-NEXT:    v_add_i32_e64 v6, s[4:5], 2, v2
1174; GCN-NEXT:    v_addc_u32_e64 v7, s[4:5], 0, 0, s[4:5]
1175; GCN-NEXT:    v_add_i32_e64 v8, s[4:5], 1, v2
1176; GCN-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, 0, s[4:5]
1177; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1178; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v5
1179; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1180; GCN-NEXT:    v_cndmask_b32_e64 v5, v8, v6, s[4:5]
1181; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1182; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v0
1183; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1184; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1185; GCN-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
1186; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1187; GCN-NEXT:    v_cndmask_b32_e64 v1, v9, v7, s[4:5]
1188; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1189; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
1190; GCN-NEXT:    s_setpc_b64 s[30:31]
1191;
1192; GCN-IR-LABEL: v_test_udiv_pow2_k_num_i64:
1193; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1194; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1195; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1196; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1197; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1198; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1199; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 0xffffffd0, v6
1200; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[6:7], 0, -1, vcc
1201; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1202; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[4:5]
1203; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0x8000
1204; GCN-IR-NEXT:    v_mov_b32_e32 v2, s8
1205; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1206; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1207; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1208; GCN-IR-NEXT:    v_cndmask_b32_e64 v2, v2, 0, s[4:5]
1209; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1210; GCN-IR-NEXT:    v_mov_b32_e32 v3, v7
1211; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1212; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1213; GCN-IR-NEXT:    s_cbranch_execz .LBB9_6
1214; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1215; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
1216; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
1217; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v4
1218; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[8:9], v[4:5]
1219; GCN-IR-NEXT:    v_lshl_b64 v[2:3], s[8:9], v2
1220; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1221; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1222; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1223; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1224; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1225; GCN-IR-NEXT:    s_cbranch_execz .LBB9_5
1226; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1227; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, -1, v0
1228; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0x8000
1229; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, -1, v1, vcc
1230; GCN-IR-NEXT:    v_lshr_b64 v[8:9], s[4:5], v8
1231; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, 47, v6
1232; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1233; GCN-IR-NEXT:    v_subb_u32_e32 v7, vcc, 0, v7, vcc
1234; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1235; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1236; GCN-IR-NEXT:  .LBB9_3: ; %udiv-do-while
1237; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1238; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1239; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1240; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1241; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1242; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, v12, v8
1243; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, v13, v9, vcc
1244; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1245; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1246; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1247; GCN-IR-NEXT:    v_and_b32_e32 v14, v10, v1
1248; GCN-IR-NEXT:    v_and_b32_e32 v15, v10, v0
1249; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v6
1250; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1251; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v7, vcc
1252; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7]
1253; GCN-IR-NEXT:    v_mov_b32_e32 v6, v10
1254; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v15
1255; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1256; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1257; GCN-IR-NEXT:    v_subb_u32_e64 v9, s[4:5], v9, v14, s[4:5]
1258; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1259; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1260; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1261; GCN-IR-NEXT:    s_cbranch_execnz .LBB9_3
1262; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1263; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1264; GCN-IR-NEXT:  .LBB9_5: ; %Flow3
1265; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1266; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[2:3], 1
1267; GCN-IR-NEXT:    v_or_b32_e32 v3, v5, v1
1268; GCN-IR-NEXT:    v_or_b32_e32 v2, v4, v0
1269; GCN-IR-NEXT:  .LBB9_6: ; %Flow4
1270; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1271; GCN-IR-NEXT:    v_mov_b32_e32 v0, v2
1272; GCN-IR-NEXT:    v_mov_b32_e32 v1, v3
1273; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1274  %result = udiv i64 32768, %x
1275  ret i64 %result
1276}
1277
1278define i64 @v_test_udiv_pow2_k_den_i64(i64 %x) {
1279; GCN-LABEL: v_test_udiv_pow2_k_den_i64:
1280; GCN:       ; %bb.0:
1281; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1282; GCN-NEXT:    v_alignbit_b32 v0, v1, v0, 15
1283; GCN-NEXT:    v_lshrrev_b32_e32 v1, 15, v1
1284; GCN-NEXT:    s_setpc_b64 s[30:31]
1285;
1286; GCN-IR-LABEL: v_test_udiv_pow2_k_den_i64:
1287; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1288; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1289; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1290; GCN-IR-NEXT:    v_add_i32_e64 v2, s[4:5], 32, v2
1291; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1292; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1293; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 48, v6
1294; GCN-IR-NEXT:    v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5]
1295; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1296; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
1297; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1298; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1299; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1300; GCN-IR-NEXT:    v_cndmask_b32_e64 v2, v1, 0, s[4:5]
1301; GCN-IR-NEXT:    v_cndmask_b32_e64 v3, v0, 0, s[4:5]
1302; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1303; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1304; GCN-IR-NEXT:    s_cbranch_execz .LBB10_6
1305; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1306; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 1, v4
1307; GCN-IR-NEXT:    v_addc_u32_e32 v8, vcc, 0, v5, vcc
1308; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v4
1309; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[7:8], v[4:5]
1310; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[0:1], v2
1311; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1312; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1313; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1314; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1315; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1316; GCN-IR-NEXT:    s_cbranch_execz .LBB10_5
1317; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1318; GCN-IR-NEXT:    v_lshr_b64 v[7:8], v[0:1], v7
1319; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, 0xffffffcf, v6
1320; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1321; GCN-IR-NEXT:    v_addc_u32_e64 v1, s[4:5], 0, -1, vcc
1322; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1323; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1324; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
1325; GCN-IR-NEXT:  .LBB10_3: ; %udiv-do-while
1326; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1327; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
1328; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1329; GCN-IR-NEXT:    v_or_b32_e32 v6, v7, v4
1330; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1331; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, s12, v6
1332; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, 0, v8, vcc
1333; GCN-IR-NEXT:    v_or_b32_e32 v2, v9, v2
1334; GCN-IR-NEXT:    v_add_i32_e32 v9, vcc, 1, v0
1335; GCN-IR-NEXT:    v_or_b32_e32 v3, v10, v3
1336; GCN-IR-NEXT:    v_ashrrev_i32_e32 v7, 31, v4
1337; GCN-IR-NEXT:    v_addc_u32_e32 v10, vcc, 0, v1, vcc
1338; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v7
1339; GCN-IR-NEXT:    v_and_b32_e32 v7, 0x8000, v7
1340; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[9:10], v[0:1]
1341; GCN-IR-NEXT:    v_mov_b32_e32 v0, v9
1342; GCN-IR-NEXT:    v_sub_i32_e64 v7, s[4:5], v6, v7
1343; GCN-IR-NEXT:    v_mov_b32_e32 v1, v10
1344; GCN-IR-NEXT:    v_mov_b32_e32 v10, v5
1345; GCN-IR-NEXT:    v_subbrev_u32_e64 v8, s[4:5], 0, v8, s[4:5]
1346; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1347; GCN-IR-NEXT:    v_mov_b32_e32 v9, v4
1348; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1349; GCN-IR-NEXT:    s_cbranch_execnz .LBB10_3
1350; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1351; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1352; GCN-IR-NEXT:  .LBB10_5: ; %Flow3
1353; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1354; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[2:3], 1
1355; GCN-IR-NEXT:    v_or_b32_e32 v2, v5, v1
1356; GCN-IR-NEXT:    v_or_b32_e32 v3, v4, v0
1357; GCN-IR-NEXT:  .LBB10_6: ; %Flow4
1358; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1359; GCN-IR-NEXT:    v_mov_b32_e32 v0, v3
1360; GCN-IR-NEXT:    v_mov_b32_e32 v1, v2
1361; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1362  %result = udiv i64 %x, 32768
1363  ret i64 %result
1364}
1365
1366define amdgpu_kernel void @s_test_udiv_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
1367; GCN-LABEL: s_test_udiv_k_den_i64:
1368; GCN:       ; %bb.0:
1369; GCN-NEXT:    v_mov_b32_e32 v0, 0x4f800000
1370; GCN-NEXT:    v_madak_f32 v0, 0, v0, 0x41c00000
1371; GCN-NEXT:    v_rcp_f32_e32 v0, v0
1372; GCN-NEXT:    s_movk_i32 s4, 0xffe8
1373; GCN-NEXT:    v_mov_b32_e32 v7, 0
1374; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1375; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
1376; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
1377; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1378; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
1379; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
1380; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
1381; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1382; GCN-NEXT:    s_mov_b32 s5, s1
1383; GCN-NEXT:    s_mov_b32 s7, 0xf000
1384; GCN-NEXT:    v_mul_hi_u32 v2, v0, s4
1385; GCN-NEXT:    v_mul_lo_u32 v3, v1, s4
1386; GCN-NEXT:    v_mul_lo_u32 v4, v0, s4
1387; GCN-NEXT:    s_mov_b32 s6, -1
1388; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
1389; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1390; GCN-NEXT:    v_mul_lo_u32 v3, v0, v2
1391; GCN-NEXT:    v_mul_hi_u32 v5, v0, v4
1392; GCN-NEXT:    v_mul_hi_u32 v6, v0, v2
1393; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
1394; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
1395; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
1396; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
1397; GCN-NEXT:    v_mul_lo_u32 v6, v1, v4
1398; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
1399; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
1400; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
1401; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
1402; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1403; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
1404; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1405; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
1406; GCN-NEXT:    v_mul_hi_u32 v2, v0, s4
1407; GCN-NEXT:    v_mul_lo_u32 v3, v1, s4
1408; GCN-NEXT:    v_mul_lo_u32 v4, v0, s4
1409; GCN-NEXT:    s_mov_b32 s4, s0
1410; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
1411; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
1412; GCN-NEXT:    v_mul_lo_u32 v3, v0, v2
1413; GCN-NEXT:    v_mul_hi_u32 v5, v0, v4
1414; GCN-NEXT:    v_mul_hi_u32 v6, v0, v2
1415; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
1416; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
1417; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
1418; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
1419; GCN-NEXT:    v_mul_lo_u32 v6, v1, v4
1420; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
1421; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
1422; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
1423; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
1424; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1425; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
1426; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1427; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
1428; GCN-NEXT:    v_mul_lo_u32 v2, s2, v1
1429; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
1430; GCN-NEXT:    v_mul_hi_u32 v4, s2, v1
1431; GCN-NEXT:    v_mul_hi_u32 v5, s3, v1
1432; GCN-NEXT:    v_mul_lo_u32 v1, s3, v1
1433; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1434; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
1435; GCN-NEXT:    v_mul_lo_u32 v4, s3, v0
1436; GCN-NEXT:    v_mul_hi_u32 v0, s3, v0
1437; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1438; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
1439; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
1440; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1441; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
1442; GCN-NEXT:    v_mul_lo_u32 v4, v1, 24
1443; GCN-NEXT:    v_mul_hi_u32 v5, v0, 24
1444; GCN-NEXT:    v_add_i32_e32 v2, vcc, 2, v0
1445; GCN-NEXT:    v_mul_lo_u32 v8, v0, 24
1446; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
1447; GCN-NEXT:    v_add_i32_e32 v6, vcc, 1, v0
1448; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v1, vcc
1449; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1450; GCN-NEXT:    v_mov_b32_e32 v5, s3
1451; GCN-NEXT:    v_sub_i32_e32 v8, vcc, s2, v8
1452; GCN-NEXT:    v_subb_u32_e32 v4, vcc, v5, v4, vcc
1453; GCN-NEXT:    v_subrev_i32_e32 v5, vcc, 24, v8
1454; GCN-NEXT:    v_subbrev_u32_e32 v9, vcc, 0, v4, vcc
1455; GCN-NEXT:    v_cmp_lt_u32_e32 vcc, 23, v5
1456; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
1457; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v9
1458; GCN-NEXT:    v_cndmask_b32_e32 v5, -1, v5, vcc
1459; GCN-NEXT:    v_cmp_lt_u32_e64 s[0:1], 23, v8
1460; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
1461; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
1462; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v4
1463; GCN-NEXT:    v_cndmask_b32_e64 v4, -1, v5, s[0:1]
1464; GCN-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
1465; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
1466; GCN-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
1467; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
1468; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
1469; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1470; GCN-NEXT:    s_endpgm
1471;
1472; GCN-IR-LABEL: s_test_udiv_k_den_i64:
1473; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1474; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1475; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1476; GCN-IR-NEXT:    s_flbit_i32_b32 s4, s2
1477; GCN-IR-NEXT:    s_flbit_i32_b32 s5, s3
1478; GCN-IR-NEXT:    s_add_i32 s4, s4, 32
1479; GCN-IR-NEXT:    s_min_u32 s8, s4, s5
1480; GCN-IR-NEXT:    s_sub_u32 s6, 59, s8
1481; GCN-IR-NEXT:    s_subb_u32 s7, 0, 0
1482; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
1483; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[12:13], s[6:7], 63
1484; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0
1485; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
1486; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[12:13], s[6:7], 63
1487; GCN-IR-NEXT:    s_xor_b64 s[14:15], s[10:11], -1
1488; GCN-IR-NEXT:    s_and_b64 s[12:13], s[14:15], s[12:13]
1489; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
1490; GCN-IR-NEXT:    s_cbranch_vccz .LBB11_5
1491; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1492; GCN-IR-NEXT:    s_add_u32 s10, s6, 1
1493; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1494; GCN-IR-NEXT:    s_addc_u32 s11, s7, 0
1495; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
1496; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
1497; GCN-IR-NEXT:    s_sub_i32 s6, 63, s6
1498; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1499; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[2:3], s6
1500; GCN-IR-NEXT:    s_cbranch_vccz .LBB11_4
1501; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1502; GCN-IR-NEXT:    s_lshr_b64 s[10:11], s[2:3], s10
1503; GCN-IR-NEXT:    s_add_u32 s2, s8, 0xffffffc4
1504; GCN-IR-NEXT:    s_addc_u32 s3, 0, -1
1505; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1506; GCN-IR-NEXT:    s_mov_b32 s5, 0
1507; GCN-IR-NEXT:  .LBB11_3: ; %udiv-do-while
1508; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1509; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
1510; GCN-IR-NEXT:    s_lshr_b32 s4, s7, 31
1511; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[6:7], 1
1512; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[4:5]
1513; GCN-IR-NEXT:    s_or_b64 s[6:7], s[8:9], s[6:7]
1514; GCN-IR-NEXT:    s_sub_u32 s4, 23, s10
1515; GCN-IR-NEXT:    s_subb_u32 s4, 0, s11
1516; GCN-IR-NEXT:    s_ashr_i32 s8, s4, 31
1517; GCN-IR-NEXT:    s_and_b32 s4, s8, 1
1518; GCN-IR-NEXT:    s_and_b32 s8, s8, 24
1519; GCN-IR-NEXT:    s_sub_u32 s10, s10, s8
1520; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1521; GCN-IR-NEXT:    s_subb_u32 s11, s11, 0
1522; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
1523; GCN-IR-NEXT:    s_add_u32 s2, s2, 1
1524; GCN-IR-NEXT:    s_addc_u32 s3, s3, 0
1525; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1]
1526; GCN-IR-NEXT:    s_mov_b64 s[8:9], s[4:5]
1527; GCN-IR-NEXT:    s_cbranch_vccz .LBB11_3
1528; GCN-IR-NEXT:  .LBB11_4: ; %Flow5
1529; GCN-IR-NEXT:    s_lshl_b64 s[2:3], s[6:7], 1
1530; GCN-IR-NEXT:    s_or_b64 s[2:3], s[4:5], s[2:3]
1531; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1532; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
1533; GCN-IR-NEXT:    s_branch .LBB11_6
1534; GCN-IR-NEXT:  .LBB11_5:
1535; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
1536; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[10:11]
1537; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1538; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[10:11]
1539; GCN-IR-NEXT:  .LBB11_6: ; %udiv-end
1540; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1541; GCN-IR-NEXT:    s_mov_b32 s2, -1
1542; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1543; GCN-IR-NEXT:    s_endpgm
1544  %result = udiv i64 %x, 24
1545  store i64 %result, i64 addrspace(1)* %out
1546  ret void
1547}
1548
1549define i64 @v_test_udiv_k_den_i64(i64 %x) {
1550; GCN-LABEL: v_test_udiv_k_den_i64:
1551; GCN:       ; %bb.0:
1552; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1553; GCN-NEXT:    v_mov_b32_e32 v2, 0x4f800000
1554; GCN-NEXT:    v_madak_f32 v2, 0, v2, 0x41c00000
1555; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1556; GCN-NEXT:    s_movk_i32 s4, 0xffe8
1557; GCN-NEXT:    v_mov_b32_e32 v8, 0
1558; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1559; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1560; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1561; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1562; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1563; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1564; GCN-NEXT:    v_mul_hi_u32 v4, v2, s4
1565; GCN-NEXT:    v_mul_lo_u32 v6, v3, s4
1566; GCN-NEXT:    v_mul_lo_u32 v5, v2, s4
1567; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, v2, v4
1568; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
1569; GCN-NEXT:    v_mul_hi_u32 v7, v2, v5
1570; GCN-NEXT:    v_mul_lo_u32 v6, v2, v4
1571; GCN-NEXT:    v_mul_hi_u32 v9, v2, v4
1572; GCN-NEXT:    v_mul_hi_u32 v10, v3, v4
1573; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1574; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1575; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v9, vcc
1576; GCN-NEXT:    v_mul_lo_u32 v9, v3, v5
1577; GCN-NEXT:    v_mul_hi_u32 v5, v3, v5
1578; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
1579; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v5, vcc
1580; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v8, vcc
1581; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1582; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
1583; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1584; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
1585; GCN-NEXT:    v_mul_hi_u32 v4, v2, s4
1586; GCN-NEXT:    v_mul_lo_u32 v5, v3, s4
1587; GCN-NEXT:    v_mul_lo_u32 v6, v2, s4
1588; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, v2, v4
1589; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1590; GCN-NEXT:    v_mul_lo_u32 v5, v2, v4
1591; GCN-NEXT:    v_mul_hi_u32 v7, v2, v6
1592; GCN-NEXT:    v_mul_hi_u32 v9, v2, v4
1593; GCN-NEXT:    v_mul_hi_u32 v10, v3, v4
1594; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1595; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
1596; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v9, vcc
1597; GCN-NEXT:    v_mul_lo_u32 v9, v3, v6
1598; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
1599; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
1600; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
1601; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v8, vcc
1602; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1603; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
1604; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1605; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
1606; GCN-NEXT:    v_mul_lo_u32 v4, v0, v3
1607; GCN-NEXT:    v_mul_hi_u32 v5, v0, v2
1608; GCN-NEXT:    v_mul_hi_u32 v6, v0, v3
1609; GCN-NEXT:    v_mul_hi_u32 v7, v1, v3
1610; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
1611; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1612; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
1613; GCN-NEXT:    v_mul_lo_u32 v6, v1, v2
1614; GCN-NEXT:    v_mul_hi_u32 v2, v1, v2
1615; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
1616; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v2, vcc
1617; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v8, vcc
1618; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
1619; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
1620; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
1621; GCN-NEXT:    v_mul_hi_u32 v5, v2, 24
1622; GCN-NEXT:    v_mul_lo_u32 v6, v2, 24
1623; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1624; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
1625; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc
1626; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, 24, v0
1627; GCN-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v1, vcc
1628; GCN-NEXT:    v_cmp_lt_u32_e32 vcc, 23, v4
1629; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
1630; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v5
1631; GCN-NEXT:    v_cndmask_b32_e32 v4, -1, v4, vcc
1632; GCN-NEXT:    v_add_i32_e32 v5, vcc, 2, v2
1633; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v3, vcc
1634; GCN-NEXT:    v_add_i32_e32 v7, vcc, 1, v2
1635; GCN-NEXT:    v_cmp_lt_u32_e64 s[4:5], 23, v0
1636; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v3, vcc
1637; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, s[4:5]
1638; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v1
1639; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
1640; GCN-NEXT:    v_cndmask_b32_e64 v0, -1, v0, s[4:5]
1641; GCN-NEXT:    v_cndmask_b32_e32 v4, v7, v5, vcc
1642; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v0
1643; GCN-NEXT:    v_cndmask_b32_e32 v1, v8, v6, vcc
1644; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, v4, s[4:5]
1645; GCN-NEXT:    v_cndmask_b32_e64 v1, v3, v1, s[4:5]
1646; GCN-NEXT:    s_setpc_b64 s[30:31]
1647;
1648; GCN-IR-LABEL: v_test_udiv_k_den_i64:
1649; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1650; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1651; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1652; GCN-IR-NEXT:    v_add_i32_e64 v2, s[4:5], 32, v2
1653; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1654; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1655; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 59, v6
1656; GCN-IR-NEXT:    v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5]
1657; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1658; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
1659; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1660; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1661; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1662; GCN-IR-NEXT:    v_cndmask_b32_e64 v2, v1, 0, s[4:5]
1663; GCN-IR-NEXT:    v_cndmask_b32_e64 v3, v0, 0, s[4:5]
1664; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1665; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1666; GCN-IR-NEXT:    s_cbranch_execz .LBB12_6
1667; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1668; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 1, v4
1669; GCN-IR-NEXT:    v_addc_u32_e32 v8, vcc, 0, v5, vcc
1670; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v4
1671; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[7:8], v[4:5]
1672; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[0:1], v2
1673; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1674; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1675; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1676; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1677; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1678; GCN-IR-NEXT:    s_cbranch_execz .LBB12_5
1679; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1680; GCN-IR-NEXT:    v_lshr_b64 v[7:8], v[0:1], v7
1681; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, 0xffffffc4, v6
1682; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1683; GCN-IR-NEXT:    v_addc_u32_e64 v1, s[4:5], 0, -1, vcc
1684; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1685; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1686; GCN-IR-NEXT:  .LBB12_3: ; %udiv-do-while
1687; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1688; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
1689; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1690; GCN-IR-NEXT:    v_or_b32_e32 v6, v7, v4
1691; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1692; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, 23, v6
1693; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, 0, v8, vcc
1694; GCN-IR-NEXT:    v_or_b32_e32 v2, v9, v2
1695; GCN-IR-NEXT:    v_add_i32_e32 v9, vcc, 1, v0
1696; GCN-IR-NEXT:    v_or_b32_e32 v3, v10, v3
1697; GCN-IR-NEXT:    v_ashrrev_i32_e32 v7, 31, v4
1698; GCN-IR-NEXT:    v_addc_u32_e32 v10, vcc, 0, v1, vcc
1699; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v7
1700; GCN-IR-NEXT:    v_and_b32_e32 v7, 24, v7
1701; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[9:10], v[0:1]
1702; GCN-IR-NEXT:    v_mov_b32_e32 v0, v9
1703; GCN-IR-NEXT:    v_sub_i32_e64 v7, s[4:5], v6, v7
1704; GCN-IR-NEXT:    v_mov_b32_e32 v1, v10
1705; GCN-IR-NEXT:    v_mov_b32_e32 v10, v5
1706; GCN-IR-NEXT:    v_subbrev_u32_e64 v8, s[4:5], 0, v8, s[4:5]
1707; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1708; GCN-IR-NEXT:    v_mov_b32_e32 v9, v4
1709; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1710; GCN-IR-NEXT:    s_cbranch_execnz .LBB12_3
1711; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1712; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1713; GCN-IR-NEXT:  .LBB12_5: ; %Flow3
1714; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1715; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[2:3], 1
1716; GCN-IR-NEXT:    v_or_b32_e32 v2, v5, v1
1717; GCN-IR-NEXT:    v_or_b32_e32 v3, v4, v0
1718; GCN-IR-NEXT:  .LBB12_6: ; %Flow4
1719; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1720; GCN-IR-NEXT:    v_mov_b32_e32 v0, v3
1721; GCN-IR-NEXT:    v_mov_b32_e32 v1, v2
1722; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1723  %result = udiv i64 %x, 24
1724  ret i64 %result
1725}
1726
1727define amdgpu_kernel void @s_test_udiv24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1728; GCN-LABEL: s_test_udiv24_k_num_i64:
1729; GCN:       ; %bb.0:
1730; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1731; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
1732; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1733; GCN-NEXT:    s_lshr_b32 s2, s3, 8
1734; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
1735; GCN-NEXT:    s_mov_b32 s3, 0xf000
1736; GCN-NEXT:    s_mov_b32 s2, -1
1737; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1738; GCN-NEXT:    v_mul_f32_e32 v1, s4, v1
1739; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1740; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1741; GCN-NEXT:    v_mad_f32 v1, -v1, v0, s4
1742; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1743; GCN-NEXT:    v_mov_b32_e32 v1, 0
1744; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1745; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1746; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1747; GCN-NEXT:    s_endpgm
1748;
1749; GCN-IR-LABEL: s_test_udiv24_k_num_i64:
1750; GCN-IR:       ; %bb.0:
1751; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1752; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
1753; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1754; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 8
1755; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
1756; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1757; GCN-IR-NEXT:    s_mov_b32 s2, -1
1758; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1759; GCN-IR-NEXT:    v_mul_f32_e32 v1, s4, v1
1760; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1761; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1762; GCN-IR-NEXT:    v_mad_f32 v1, -v1, v0, s4
1763; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1764; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1765; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1766; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1767; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1768; GCN-IR-NEXT:    s_endpgm
1769  %x.shr = lshr i64 %x, 40
1770  %result = udiv i64 24, %x.shr
1771  store i64 %result, i64 addrspace(1)* %out
1772  ret void
1773}
1774
1775define amdgpu_kernel void @s_test_udiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
1776; GCN-LABEL: s_test_udiv24_k_den_i64:
1777; GCN:       ; %bb.0:
1778; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1779; GCN-NEXT:    s_mov_b32 s7, 0xf000
1780; GCN-NEXT:    s_mov_b32 s6, -1
1781; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1782; GCN-NEXT:    s_lshr_b32 s2, s3, 8
1783; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
1784; GCN-NEXT:    s_mov_b32 s2, 0x46b6fe00
1785; GCN-NEXT:    s_mov_b32 s4, s0
1786; GCN-NEXT:    s_mov_b32 s5, s1
1787; GCN-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1788; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1789; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1790; GCN-NEXT:    v_mad_f32 v0, -v1, s2, v0
1791; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s2
1792; GCN-NEXT:    v_mov_b32_e32 v1, 0
1793; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1794; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1795; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1796; GCN-NEXT:    s_endpgm
1797;
1798; GCN-IR-LABEL: s_test_udiv24_k_den_i64:
1799; GCN-IR:       ; %bb.0:
1800; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1801; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1802; GCN-IR-NEXT:    s_mov_b32 s6, -1
1803; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1804; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 8
1805; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
1806; GCN-IR-NEXT:    s_mov_b32 s2, 0x46b6fe00
1807; GCN-IR-NEXT:    s_mov_b32 s4, s0
1808; GCN-IR-NEXT:    s_mov_b32 s5, s1
1809; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1810; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1811; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1812; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s2, v0
1813; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s2
1814; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1815; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1816; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1817; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1818; GCN-IR-NEXT:    s_endpgm
1819  %x.shr = lshr i64 %x, 40
1820  %result = udiv i64 %x.shr, 23423
1821  store i64 %result, i64 addrspace(1)* %out
1822  ret void
1823}
1824
1825define i64 @v_test_udiv24_k_num_i64(i64 %x) {
1826; GCN-LABEL: v_test_udiv24_k_num_i64:
1827; GCN:       ; %bb.0:
1828; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1829; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1830; GCN-NEXT:    v_cvt_f32_u32_e32 v0, v0
1831; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
1832; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1833; GCN-NEXT:    v_mul_f32_e32 v1, s4, v1
1834; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1835; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1836; GCN-NEXT:    v_mad_f32 v1, -v1, v0, s4
1837; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1838; GCN-NEXT:    v_mov_b32_e32 v1, 0
1839; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1840; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1841; GCN-NEXT:    s_setpc_b64 s[30:31]
1842;
1843; GCN-IR-LABEL: v_test_udiv24_k_num_i64:
1844; GCN-IR:       ; %bb.0:
1845; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1846; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1847; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, v0
1848; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
1849; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1850; GCN-IR-NEXT:    v_mul_f32_e32 v1, s4, v1
1851; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1852; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1853; GCN-IR-NEXT:    v_mad_f32 v1, -v1, v0, s4
1854; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1855; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1856; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1857; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1858; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1859  %x.shr = lshr i64 %x, 40
1860  %result = udiv i64 24, %x.shr
1861  ret i64 %result
1862}
1863
1864define i64 @v_test_udiv24_pow2_k_num_i64(i64 %x) {
1865; GCN-LABEL: v_test_udiv24_pow2_k_num_i64:
1866; GCN:       ; %bb.0:
1867; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1868; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1869; GCN-NEXT:    v_cvt_f32_u32_e32 v0, v0
1870; GCN-NEXT:    s_mov_b32 s4, 0x47000000
1871; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1872; GCN-NEXT:    v_mul_f32_e32 v1, s4, v1
1873; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1874; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1875; GCN-NEXT:    v_mad_f32 v1, -v1, v0, s4
1876; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1877; GCN-NEXT:    v_mov_b32_e32 v1, 0
1878; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1879; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1880; GCN-NEXT:    s_setpc_b64 s[30:31]
1881;
1882; GCN-IR-LABEL: v_test_udiv24_pow2_k_num_i64:
1883; GCN-IR:       ; %bb.0:
1884; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1885; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1886; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, v0
1887; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
1888; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1889; GCN-IR-NEXT:    v_mul_f32_e32 v1, s4, v1
1890; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1891; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1892; GCN-IR-NEXT:    v_mad_f32 v1, -v1, v0, s4
1893; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1894; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1895; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1896; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1897; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1898  %x.shr = lshr i64 %x, 40
1899  %result = udiv i64 32768, %x.shr
1900  ret i64 %result
1901}
1902
1903define i64 @v_test_udiv24_pow2_k_den_i64(i64 %x) {
1904; GCN-LABEL: v_test_udiv24_pow2_k_den_i64:
1905; GCN:       ; %bb.0:
1906; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1907; GCN-NEXT:    v_lshrrev_b32_e32 v0, 23, v1
1908; GCN-NEXT:    v_mov_b32_e32 v1, 0
1909; GCN-NEXT:    s_setpc_b64 s[30:31]
1910;
1911; GCN-IR-LABEL: v_test_udiv24_pow2_k_den_i64:
1912; GCN-IR:       ; %bb.0:
1913; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1914; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1915; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, v0
1916; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
1917; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38000000, v0
1918; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1919; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1920; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s4, v0
1921; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
1922; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1923; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1924; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1925; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1926  %x.shr = lshr i64 %x, 40
1927  %result = udiv i64 %x.shr, 32768
1928  ret i64 %result
1929}
1930