1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_udiv_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_udiv_i64:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
9; GCN-NEXT:    v_mov_b32_e32 v2, 0
10; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
11; GCN-NEXT:    s_mov_b32 s7, 0xf000
12; GCN-NEXT:    s_mov_b32 s6, -1
13; GCN-NEXT:    s_waitcnt lgkmcnt(0)
14; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
15; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s3
16; GCN-NEXT:    s_sub_u32 s4, 0, s2
17; GCN-NEXT:    s_subb_u32 s5, 0, s3
18; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
19; GCN-NEXT:    v_rcp_f32_e32 v0, v0
20; GCN-NEXT:    v_mov_b32_e32 v1, 0
21; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
22; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
23; GCN-NEXT:    v_trunc_f32_e32 v3, v3
24; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
25; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
26; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
27; GCN-NEXT:    v_mul_hi_u32 v5, s4, v0
28; GCN-NEXT:    v_mul_lo_u32 v4, s4, v3
29; GCN-NEXT:    v_mul_lo_u32 v7, s5, v0
30; GCN-NEXT:    v_mul_lo_u32 v6, s4, v0
31; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
32; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
33; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
34; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
35; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
36; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
37; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
38; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
39; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
40; GCN-NEXT:    v_mul_hi_u32 v9, v3, v4
41; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
42; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
43; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
44; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v1, vcc
45; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
46; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
47; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
48; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
49; GCN-NEXT:    v_mul_lo_u32 v6, s4, v4
50; GCN-NEXT:    v_mul_hi_u32 v7, s4, v0
51; GCN-NEXT:    v_mul_lo_u32 v8, s5, v0
52; GCN-NEXT:    s_mov_b32 s5, s9
53; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
54; GCN-NEXT:    v_mul_lo_u32 v7, s4, v0
55; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
56; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
57; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
58; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
59; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
60; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
61; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
62; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
63; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
64; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
65; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
66; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
67; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v1, vcc
68; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
69; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
70; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
71; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
72; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
73; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
74; GCN-NEXT:    v_mul_lo_u32 v4, s10, v3
75; GCN-NEXT:    v_mul_hi_u32 v5, s10, v0
76; GCN-NEXT:    v_mul_hi_u32 v6, s10, v3
77; GCN-NEXT:    v_mul_hi_u32 v7, s11, v3
78; GCN-NEXT:    v_mul_lo_u32 v3, s11, v3
79; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
80; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
81; GCN-NEXT:    v_mul_lo_u32 v6, s11, v0
82; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
83; GCN-NEXT:    s_mov_b32 s4, s8
84; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
85; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
86; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
87; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
88; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
89; GCN-NEXT:    v_mul_lo_u32 v2, s2, v1
90; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
91; GCN-NEXT:    v_mul_lo_u32 v4, s3, v0
92; GCN-NEXT:    v_mov_b32_e32 v5, s3
93; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
94; GCN-NEXT:    v_mul_lo_u32 v3, s2, v0
95; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
96; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s11, v2
97; GCN-NEXT:    v_sub_i32_e32 v3, vcc, s10, v3
98; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
99; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s2, v3
100; GCN-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
101; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v4
102; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
103; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v5
104; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
105; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s3, v4
106; GCN-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
107; GCN-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
108; GCN-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
109; GCN-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
110; GCN-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
111; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
112; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
113; GCN-NEXT:    v_mov_b32_e32 v6, s11
114; GCN-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
115; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s3, v2
116; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
117; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v3
118; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
119; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v2
120; GCN-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
121; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
122; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
123; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
124; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
125; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
126; GCN-NEXT:    s_endpgm
127;
128; GCN-IR-LABEL: s_test_udiv_i64:
129; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
130; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
131; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
132; GCN-IR-NEXT:    s_mov_b64 s[2:3], 0
133; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
134; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
135; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[0:1], 0
136; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s0
137; GCN-IR-NEXT:    s_or_b64 s[14:15], s[8:9], s[10:11]
138; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
139; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s1
140; GCN-IR-NEXT:    s_min_u32 s10, s12, s8
141; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s6
142; GCN-IR-NEXT:    s_add_i32 s8, s8, 32
143; GCN-IR-NEXT:    s_flbit_i32_b32 s9, s7
144; GCN-IR-NEXT:    s_min_u32 s12, s8, s9
145; GCN-IR-NEXT:    s_sub_u32 s8, s10, s12
146; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
147; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[16:17], s[8:9], 63
148; GCN-IR-NEXT:    s_mov_b32 s11, 0
149; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[16:17]
150; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[16:17], s[8:9], 63
151; GCN-IR-NEXT:    s_xor_b64 s[18:19], s[14:15], -1
152; GCN-IR-NEXT:    s_and_b64 s[16:17], s[18:19], s[16:17]
153; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[16:17]
154; GCN-IR-NEXT:    s_cbranch_vccz BB0_5
155; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
156; GCN-IR-NEXT:    s_add_u32 s14, s8, 1
157; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
158; GCN-IR-NEXT:    s_addc_u32 s15, s9, 0
159; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
160; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[14:15], v[0:1]
161; GCN-IR-NEXT:    s_sub_i32 s8, 63, s8
162; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
163; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[6:7], s8
164; GCN-IR-NEXT:    s_cbranch_vccz BB0_4
165; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
166; GCN-IR-NEXT:    s_lshr_b64 s[14:15], s[6:7], s14
167; GCN-IR-NEXT:    s_add_u32 s16, s0, -1
168; GCN-IR-NEXT:    s_addc_u32 s17, s1, -1
169; GCN-IR-NEXT:    s_not_b64 s[2:3], s[10:11]
170; GCN-IR-NEXT:    s_add_u32 s6, s2, s12
171; GCN-IR-NEXT:    s_addc_u32 s7, s3, s11
172; GCN-IR-NEXT:    s_mov_b32 s13, s11
173; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
174; GCN-IR-NEXT:    s_mov_b32 s3, 0
175; GCN-IR-NEXT:  BB0_3: ; %udiv-do-while
176; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
177; GCN-IR-NEXT:    s_lshr_b32 s2, s9, 31
178; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[14:15], 1
179; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
180; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[2:3]
181; GCN-IR-NEXT:    s_or_b64 s[8:9], s[10:11], s[8:9]
182; GCN-IR-NEXT:    s_sub_u32 s2, s16, s12
183; GCN-IR-NEXT:    s_subb_u32 s2, s17, s13
184; GCN-IR-NEXT:    s_ashr_i32 s10, s2, 31
185; GCN-IR-NEXT:    s_mov_b32 s11, s10
186; GCN-IR-NEXT:    s_and_b32 s2, s10, 1
187; GCN-IR-NEXT:    s_and_b64 s[14:15], s[10:11], s[0:1]
188; GCN-IR-NEXT:    s_sub_u32 s14, s12, s14
189; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
190; GCN-IR-NEXT:    s_subb_u32 s15, s13, s15
191; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
192; GCN-IR-NEXT:    s_add_u32 s6, s6, 1
193; GCN-IR-NEXT:    s_addc_u32 s7, s7, 0
194; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1]
195; GCN-IR-NEXT:    s_mov_b64 s[10:11], s[2:3]
196; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
197; GCN-IR-NEXT:    s_cbranch_vccz BB0_3
198; GCN-IR-NEXT:  BB0_4: ; %Flow6
199; GCN-IR-NEXT:    s_lshl_b64 s[0:1], s[8:9], 1
200; GCN-IR-NEXT:    s_or_b64 s[0:1], s[2:3], s[0:1]
201; GCN-IR-NEXT:    v_mov_b32_e32 v0, s0
202; GCN-IR-NEXT:    v_mov_b32_e32 v1, s1
203; GCN-IR-NEXT:    s_branch BB0_6
204; GCN-IR-NEXT:  BB0_5:
205; GCN-IR-NEXT:    v_mov_b32_e32 v0, s7
206; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[14:15]
207; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
208; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[14:15]
209; GCN-IR-NEXT:  BB0_6: ; %udiv-end
210; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
211; GCN-IR-NEXT:    s_mov_b32 s6, -1
212; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
213; GCN-IR-NEXT:    s_endpgm
214  %result = udiv i64 %x, %y
215  store i64 %result, i64 addrspace(1)* %out
216  ret void
217}
218
219define i64 @v_test_udiv_i64(i64 %x, i64 %y) {
220; GCN-LABEL: v_test_udiv_i64:
221; GCN:       ; %bb.0:
222; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
223; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v2
224; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v3
225; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v2
226; GCN-NEXT:    v_subb_u32_e32 v7, vcc, 0, v3, vcc
227; GCN-NEXT:    v_mov_b32_e32 v14, 0
228; GCN-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
229; GCN-NEXT:    v_rcp_f32_e32 v4, v4
230; GCN-NEXT:    v_mov_b32_e32 v13, 0
231; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
232; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
233; GCN-NEXT:    v_trunc_f32_e32 v5, v5
234; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
235; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
236; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
237; GCN-NEXT:    v_mul_hi_u32 v8, v6, v4
238; GCN-NEXT:    v_mul_lo_u32 v9, v6, v5
239; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
240; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
241; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
242; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
243; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
244; GCN-NEXT:    v_mul_hi_u32 v10, v4, v8
245; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
246; GCN-NEXT:    v_mul_hi_u32 v15, v5, v8
247; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
248; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
249; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
250; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
251; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v10, vcc
252; GCN-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
253; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v10, v9, vcc
254; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v15, v13, vcc
255; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
256; GCN-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v8
257; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v10, vcc
258; GCN-NEXT:    v_addc_u32_e64 v8, vcc, v5, v9, s[4:5]
259; GCN-NEXT:    v_mul_lo_u32 v10, v6, v8
260; GCN-NEXT:    v_mul_hi_u32 v11, v6, v4
261; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
262; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
263; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
264; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
265; GCN-NEXT:    v_mul_lo_u32 v12, v4, v7
266; GCN-NEXT:    v_mul_hi_u32 v15, v4, v6
267; GCN-NEXT:    v_mul_hi_u32 v16, v4, v7
268; GCN-NEXT:    v_mul_hi_u32 v11, v8, v6
269; GCN-NEXT:    v_mul_lo_u32 v6, v8, v6
270; GCN-NEXT:    v_add_i32_e32 v12, vcc, v15, v12
271; GCN-NEXT:    v_mul_hi_u32 v10, v8, v7
272; GCN-NEXT:    v_addc_u32_e32 v15, vcc, v14, v16, vcc
273; GCN-NEXT:    v_mul_lo_u32 v7, v8, v7
274; GCN-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
275; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v15, v11, vcc
276; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v13, vcc
277; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
278; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v14, v8, vcc
279; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
280; GCN-NEXT:    v_addc_u32_e64 v5, vcc, v5, v7, s[4:5]
281; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
282; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
283; GCN-NEXT:    v_mul_lo_u32 v6, v0, v5
284; GCN-NEXT:    v_mul_hi_u32 v7, v0, v4
285; GCN-NEXT:    v_mul_hi_u32 v8, v0, v5
286; GCN-NEXT:    v_mul_hi_u32 v9, v1, v5
287; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
288; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
289; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v14, v8, vcc
290; GCN-NEXT:    v_mul_lo_u32 v8, v1, v4
291; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
292; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
293; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v4, vcc
294; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v13, vcc
295; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
296; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v14, v6, vcc
297; GCN-NEXT:    v_mul_lo_u32 v6, v2, v5
298; GCN-NEXT:    v_mul_hi_u32 v7, v2, v4
299; GCN-NEXT:    v_mul_lo_u32 v8, v3, v4
300; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
301; GCN-NEXT:    v_mul_lo_u32 v7, v2, v4
302; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
303; GCN-NEXT:    v_sub_i32_e32 v8, vcc, v1, v6
304; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v7
305; GCN-NEXT:    v_subb_u32_e64 v7, s[4:5], v8, v3, vcc
306; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v0, v2
307; GCN-NEXT:    v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5]
308; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v3
309; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
310; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v2
311; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
312; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v3
313; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
314; GCN-NEXT:    v_cndmask_b32_e64 v7, v9, v8, s[4:5]
315; GCN-NEXT:    v_add_i32_e64 v8, s[4:5], 2, v4
316; GCN-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, v5, s[4:5]
317; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
318; GCN-NEXT:    v_add_i32_e64 v10, s[4:5], 1, v4
319; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
320; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
321; GCN-NEXT:    v_addc_u32_e64 v11, s[4:5], 0, v5, s[4:5]
322; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
323; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
324; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
325; GCN-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
326; GCN-NEXT:    v_cndmask_b32_e64 v7, v10, v8, s[4:5]
327; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
328; GCN-NEXT:    v_cndmask_b32_e64 v1, v11, v9, s[4:5]
329; GCN-NEXT:    v_cndmask_b32_e32 v0, v4, v7, vcc
330; GCN-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
331; GCN-NEXT:    s_setpc_b64 s[30:31]
332;
333; GCN-IR-LABEL: v_test_udiv_i64:
334; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
335; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
336; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[2:3]
337; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
338; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v2
339; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
340; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
341; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v3
342; GCN-IR-NEXT:    v_min_u32_e32 v8, v4, v5
343; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
344; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
345; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
346; GCN-IR-NEXT:    v_min_u32_e32 v10, v4, v5
347; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v8, v10
348; GCN-IR-NEXT:    v_subb_u32_e64 v7, s[6:7], 0, 0, vcc
349; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[6:7]
350; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
351; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
352; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[6:7]
353; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
354; GCN-IR-NEXT:    v_mov_b32_e32 v11, v9
355; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v1, 0, s[4:5]
356; GCN-IR-NEXT:    v_cndmask_b32_e64 v5, v0, 0, s[4:5]
357; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
358; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
359; GCN-IR-NEXT:    s_cbranch_execz BB1_6
360; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
361; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v6
362; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v7, vcc
363; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v6
364; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[12:13], v[6:7]
365; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
366; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[0:1], v4
367; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
368; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
369; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
370; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
371; GCN-IR-NEXT:    s_cbranch_execz BB1_5
372; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
373; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, -1, v2
374; GCN-IR-NEXT:    v_lshr_b64 v[12:13], v[0:1], v12
375; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, -1, v3, vcc
376; GCN-IR-NEXT:    v_not_b32_e32 v0, v8
377; GCN-IR-NEXT:    v_not_b32_e32 v1, v9
378; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v10
379; GCN-IR-NEXT:    v_mov_b32_e32 v8, 0
380; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
381; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, v1, v11, vcc
382; GCN-IR-NEXT:  BB1_3: ; %udiv-do-while
383; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
384; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[12:13], 1
385; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
386; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v6
387; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
388; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v14, v10
389; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v15, v11, vcc
390; GCN-IR-NEXT:    v_or_b32_e32 v4, v8, v4
391; GCN-IR-NEXT:    v_ashrrev_i32_e32 v8, 31, v6
392; GCN-IR-NEXT:    v_and_b32_e32 v12, v8, v2
393; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v8
394; GCN-IR-NEXT:    v_and_b32_e32 v13, v8, v3
395; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v0
396; GCN-IR-NEXT:    v_or_b32_e32 v5, v9, v5
397; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v1, vcc
398; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[8:9], v[0:1]
399; GCN-IR-NEXT:    v_mov_b32_e32 v0, v8
400; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
401; GCN-IR-NEXT:    v_sub_i32_e64 v12, s[4:5], v10, v12
402; GCN-IR-NEXT:    v_mov_b32_e32 v1, v9
403; GCN-IR-NEXT:    v_mov_b32_e32 v9, v7
404; GCN-IR-NEXT:    v_subb_u32_e64 v13, s[4:5], v11, v13, s[4:5]
405; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
406; GCN-IR-NEXT:    v_mov_b32_e32 v8, v6
407; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
408; GCN-IR-NEXT:    s_cbranch_execnz BB1_3
409; GCN-IR-NEXT:  ; %bb.4: ; %Flow
410; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
411; GCN-IR-NEXT:  BB1_5: ; %Flow3
412; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
413; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[4:5], 1
414; GCN-IR-NEXT:    v_or_b32_e32 v4, v7, v1
415; GCN-IR-NEXT:    v_or_b32_e32 v5, v6, v0
416; GCN-IR-NEXT:  BB1_6: ; %Flow4
417; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
418; GCN-IR-NEXT:    v_mov_b32_e32 v0, v5
419; GCN-IR-NEXT:    v_mov_b32_e32 v1, v4
420; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
421  %result = udiv i64 %x, %y
422  ret i64 %result
423}
424
425define amdgpu_kernel void @s_test_udiv24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
426; GCN-LABEL: s_test_udiv24_64:
427; GCN:       ; %bb.0:
428; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
429; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
430; GCN-NEXT:    s_mov_b32 s3, 0xf000
431; GCN-NEXT:    s_mov_b32 s2, -1
432; GCN-NEXT:    s_waitcnt lgkmcnt(0)
433; GCN-NEXT:    s_mov_b32 s1, s5
434; GCN-NEXT:    s_lshr_b32 s0, s0, 8
435; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
436; GCN-NEXT:    s_lshr_b32 s0, s7, 8
437; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s0
438; GCN-NEXT:    s_mov_b32 s0, s4
439; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
440; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
441; GCN-NEXT:    v_trunc_f32_e32 v2, v2
442; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
443; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
444; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
445; GCN-NEXT:    v_mov_b32_e32 v1, 0
446; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
447; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
448; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
449; GCN-NEXT:    s_endpgm
450;
451; GCN-IR-LABEL: s_test_udiv24_64:
452; GCN-IR:       ; %bb.0:
453; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
454; GCN-IR-NEXT:    s_load_dword s0, s[0:1], 0xe
455; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
456; GCN-IR-NEXT:    s_mov_b32 s2, -1
457; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
458; GCN-IR-NEXT:    s_mov_b32 s1, s5
459; GCN-IR-NEXT:    s_lshr_b32 s0, s0, 8
460; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
461; GCN-IR-NEXT:    s_lshr_b32 s0, s7, 8
462; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s0
463; GCN-IR-NEXT:    s_mov_b32 s0, s4
464; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
465; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
466; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
467; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
468; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
469; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
470; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
471; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
472; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
473; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
474; GCN-IR-NEXT:    s_endpgm
475  %1 = lshr i64 %x, 40
476  %2 = lshr i64 %y, 40
477  %result = udiv i64 %1, %2
478  store i64 %result, i64 addrspace(1)* %out
479  ret void
480}
481
482define i64 @v_test_udiv24_i64(i64 %x, i64 %y) {
483; GCN-LABEL: v_test_udiv24_i64:
484; GCN:       ; %bb.0:
485; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
486; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v3
487; GCN-NEXT:    v_cvt_f32_u32_e32 v0, v0
488; GCN-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
489; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v1
490; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
491; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
492; GCN-NEXT:    v_trunc_f32_e32 v2, v2
493; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
494; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
495; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
496; GCN-NEXT:    v_mov_b32_e32 v1, 0
497; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
498; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
499; GCN-NEXT:    s_setpc_b64 s[30:31]
500;
501; GCN-IR-LABEL: v_test_udiv24_i64:
502; GCN-IR:       ; %bb.0:
503; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
504; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v3
505; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, v0
506; GCN-IR-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
507; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, v1
508; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
509; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
510; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
511; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
512; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
513; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
514; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
515; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
516; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
517; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
518  %1 = lshr i64 %x, 40
519  %2 = lshr i64 %y, 40
520  %result = udiv i64 %1, %2
521  ret i64 %result
522}
523
524define amdgpu_kernel void @s_test_udiv32_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
525; GCN-LABEL: s_test_udiv32_i64:
526; GCN:       ; %bb.0:
527; GCN-NEXT:    s_load_dword s2, s[0:1], 0xe
528; GCN-NEXT:    s_mov_b32 s7, 0xf000
529; GCN-NEXT:    s_mov_b32 s6, -1
530; GCN-NEXT:    s_waitcnt lgkmcnt(0)
531; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
532; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
533; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
534; GCN-NEXT:    s_waitcnt lgkmcnt(0)
535; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s3
536; GCN-NEXT:    s_mov_b32 s4, s0
537; GCN-NEXT:    s_mov_b32 s5, s1
538; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
539; GCN-NEXT:    v_trunc_f32_e32 v2, v2
540; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
541; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
542; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
543; GCN-NEXT:    v_mov_b32_e32 v1, 0
544; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
545; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
546; GCN-NEXT:    s_endpgm
547;
548; GCN-IR-LABEL: s_test_udiv32_i64:
549; GCN-IR:       ; %bb.0:
550; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xe
551; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
552; GCN-IR-NEXT:    s_mov_b32 s6, -1
553; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
554; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
555; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
556; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
557; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
558; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s3
559; GCN-IR-NEXT:    s_mov_b32 s4, s0
560; GCN-IR-NEXT:    s_mov_b32 s5, s1
561; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
562; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
563; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
564; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
565; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
566; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
567; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
568; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
569; GCN-IR-NEXT:    s_endpgm
570  %1 = lshr i64 %x, 32
571  %2 = lshr i64 %y, 32
572  %result = udiv i64 %1, %2
573  store i64 %result, i64 addrspace(1)* %out
574  ret void
575}
576
577define amdgpu_kernel void @s_test_udiv31_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
578; GCN-LABEL: s_test_udiv31_i64:
579; GCN:       ; %bb.0:
580; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
581; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
582; GCN-NEXT:    s_mov_b32 s3, 0xf000
583; GCN-NEXT:    s_mov_b32 s2, -1
584; GCN-NEXT:    s_waitcnt lgkmcnt(0)
585; GCN-NEXT:    s_mov_b32 s1, s5
586; GCN-NEXT:    s_lshr_b32 s0, s0, 1
587; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
588; GCN-NEXT:    s_lshr_b32 s0, s7, 1
589; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s0
590; GCN-NEXT:    s_mov_b32 s0, s4
591; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
592; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
593; GCN-NEXT:    v_trunc_f32_e32 v2, v2
594; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
595; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
596; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
597; GCN-NEXT:    v_mov_b32_e32 v1, 0
598; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
599; GCN-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
600; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
601; GCN-NEXT:    s_endpgm
602;
603; GCN-IR-LABEL: s_test_udiv31_i64:
604; GCN-IR:       ; %bb.0:
605; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
606; GCN-IR-NEXT:    s_load_dword s0, s[0:1], 0xe
607; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
608; GCN-IR-NEXT:    s_mov_b32 s2, -1
609; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
610; GCN-IR-NEXT:    s_mov_b32 s1, s5
611; GCN-IR-NEXT:    s_lshr_b32 s0, s0, 1
612; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
613; GCN-IR-NEXT:    s_lshr_b32 s0, s7, 1
614; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s0
615; GCN-IR-NEXT:    s_mov_b32 s0, s4
616; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
617; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
618; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
619; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
620; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
621; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
622; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
623; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
624; GCN-IR-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
625; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
626; GCN-IR-NEXT:    s_endpgm
627  %1 = lshr i64 %x, 33
628  %2 = lshr i64 %y, 33
629  %result = udiv i64 %1, %2
630  store i64 %result, i64 addrspace(1)* %out
631  ret void
632}
633
634define amdgpu_kernel void @s_test_udiv23_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
635; GCN-LABEL: s_test_udiv23_i64:
636; GCN:       ; %bb.0:
637; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
638; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
639; GCN-NEXT:    s_mov_b32 s3, 0xf000
640; GCN-NEXT:    s_mov_b32 s2, -1
641; GCN-NEXT:    s_waitcnt lgkmcnt(0)
642; GCN-NEXT:    s_mov_b32 s1, s5
643; GCN-NEXT:    s_lshr_b32 s0, s0, 9
644; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
645; GCN-NEXT:    s_lshr_b32 s0, s7, 9
646; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s0
647; GCN-NEXT:    s_mov_b32 s0, s4
648; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
649; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
650; GCN-NEXT:    v_trunc_f32_e32 v2, v2
651; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
652; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
653; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
654; GCN-NEXT:    v_mov_b32_e32 v1, 0
655; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
656; GCN-NEXT:    v_and_b32_e32 v0, 0x7fffff, v0
657; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
658; GCN-NEXT:    s_endpgm
659;
660; GCN-IR-LABEL: s_test_udiv23_i64:
661; GCN-IR:       ; %bb.0:
662; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
663; GCN-IR-NEXT:    s_load_dword s0, s[0:1], 0xe
664; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
665; GCN-IR-NEXT:    s_mov_b32 s2, -1
666; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
667; GCN-IR-NEXT:    s_mov_b32 s1, s5
668; GCN-IR-NEXT:    s_lshr_b32 s0, s0, 9
669; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
670; GCN-IR-NEXT:    s_lshr_b32 s0, s7, 9
671; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s0
672; GCN-IR-NEXT:    s_mov_b32 s0, s4
673; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
674; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
675; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
676; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
677; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
678; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
679; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
680; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
681; GCN-IR-NEXT:    v_and_b32_e32 v0, 0x7fffff, v0
682; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
683; GCN-IR-NEXT:    s_endpgm
684  %1 = lshr i64 %x, 41
685  %2 = lshr i64 %y, 41
686  %result = udiv i64 %1, %2
687  store i64 %result, i64 addrspace(1)* %out
688  ret void
689}
690
691define amdgpu_kernel void @s_test_udiv24_i48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
692; GCN-LABEL: s_test_udiv24_i48:
693; GCN:       ; %bb.0:
694; GCN-NEXT:    s_load_dword s2, s[0:1], 0xd
695; GCN-NEXT:    s_load_dword s3, s[0:1], 0xe
696; GCN-NEXT:    s_mov_b32 s5, 0xff000000
697; GCN-NEXT:    s_mov_b32 s4, 0xffff
698; GCN-NEXT:    v_cvt_f32_ubyte3_e32 v2, s4
699; GCN-NEXT:    s_waitcnt lgkmcnt(0)
700; GCN-NEXT:    s_and_b32 s2, s2, s5
701; GCN-NEXT:    s_and_b32 s3, s3, s4
702; GCN-NEXT:    v_mov_b32_e32 v0, s2
703; GCN-NEXT:    v_alignbit_b32 v0, s3, v0, 24
704; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v0
705; GCN-NEXT:    s_load_dword s6, s[0:1], 0xb
706; GCN-NEXT:    s_load_dword s7, s[0:1], 0xc
707; GCN-NEXT:    s_lshr_b64 s[2:3], s[2:3], 24
708; GCN-NEXT:    v_mov_b32_e32 v9, 0
709; GCN-NEXT:    v_mac_f32_e32 v1, 0x4f800000, v2
710; GCN-NEXT:    v_rcp_f32_e32 v1, v1
711; GCN-NEXT:    s_waitcnt lgkmcnt(0)
712; GCN-NEXT:    s_and_b32 s7, s7, s4
713; GCN-NEXT:    s_and_b32 s6, s6, s5
714; GCN-NEXT:    s_sub_u32 s8, 0, s2
715; GCN-NEXT:    v_mul_f32_e32 v1, 0x5f7ffffc, v1
716; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v1
717; GCN-NEXT:    v_trunc_f32_e32 v2, v2
718; GCN-NEXT:    v_mac_f32_e32 v1, 0xcf800000, v2
719; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
720; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
721; GCN-NEXT:    s_subb_u32 s9, 0, s3
722; GCN-NEXT:    v_mov_b32_e32 v8, 0
723; GCN-NEXT:    v_mul_lo_u32 v3, s8, v2
724; GCN-NEXT:    v_mul_hi_u32 v4, s8, v1
725; GCN-NEXT:    v_mul_lo_u32 v5, s9, v1
726; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
727; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
728; GCN-NEXT:    v_mul_lo_u32 v4, s8, v1
729; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
730; GCN-NEXT:    v_mul_lo_u32 v6, v1, v3
731; GCN-NEXT:    v_mul_hi_u32 v5, v1, v3
732; GCN-NEXT:    v_mul_hi_u32 v7, v1, v4
733; GCN-NEXT:    v_mul_hi_u32 v10, v2, v3
734; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
735; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
736; GCN-NEXT:    v_mul_lo_u32 v7, v2, v4
737; GCN-NEXT:    v_mul_hi_u32 v4, v2, v4
738; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
739; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
740; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v5, v4, vcc
741; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v10, v8, vcc
742; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
743; GCN-NEXT:    v_add_i32_e64 v1, s[2:3], v1, v3
744; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v5, vcc
745; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v2, v4, s[2:3]
746; GCN-NEXT:    v_mul_lo_u32 v5, s8, v3
747; GCN-NEXT:    v_mul_hi_u32 v6, s8, v1
748; GCN-NEXT:    v_mul_lo_u32 v7, s9, v1
749; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
750; GCN-NEXT:    v_mul_lo_u32 v6, s8, v1
751; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
752; GCN-NEXT:    v_mul_lo_u32 v11, v1, v5
753; GCN-NEXT:    v_mul_hi_u32 v13, v1, v5
754; GCN-NEXT:    v_mul_hi_u32 v12, v1, v6
755; GCN-NEXT:    v_mul_hi_u32 v10, v3, v6
756; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
757; GCN-NEXT:    v_mul_hi_u32 v7, v3, v5
758; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
759; GCN-NEXT:    v_addc_u32_e32 v12, vcc, v9, v13, vcc
760; GCN-NEXT:    v_mul_lo_u32 v3, v3, v5
761; GCN-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
762; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v12, v10, vcc
763; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
764; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
765; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
766; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
767; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v5, s[2:3]
768; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
769; GCN-NEXT:    v_mov_b32_e32 v3, s6
770; GCN-NEXT:    v_alignbit_b32 v3, s7, v3, 24
771; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
772; GCN-NEXT:    v_mul_lo_u32 v4, v3, v2
773; GCN-NEXT:    v_mul_hi_u32 v1, v3, v1
774; GCN-NEXT:    v_mul_hi_u32 v2, v3, v2
775; GCN-NEXT:    s_mov_b32 s7, 0xf000
776; GCN-NEXT:    s_mov_b32 s6, -1
777; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
778; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v9, v2, vcc
779; GCN-NEXT:    v_add_i32_e32 v1, vcc, 0, v1
780; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
781; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v8, vcc
782; GCN-NEXT:    v_add_i32_e32 v1, vcc, 0, v1
783; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v9, v2, vcc
784; GCN-NEXT:    v_mul_lo_u32 v4, v0, v2
785; GCN-NEXT:    v_mul_hi_u32 v5, v0, v1
786; GCN-NEXT:    v_mul_lo_u32 v6, v0, v1
787; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
788; GCN-NEXT:    v_sub_i32_e32 v3, vcc, v3, v6
789; GCN-NEXT:    v_subb_u32_e32 v4, vcc, 0, v4, vcc
790; GCN-NEXT:    v_sub_i32_e32 v5, vcc, v3, v0
791; GCN-NEXT:    v_subbrev_u32_e32 v6, vcc, 0, v4, vcc
792; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v0
793; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
794; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v6
795; GCN-NEXT:    v_cndmask_b32_e32 v5, -1, v5, vcc
796; GCN-NEXT:    v_add_i32_e32 v6, vcc, 2, v1
797; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v2, vcc
798; GCN-NEXT:    v_add_i32_e32 v8, vcc, 1, v1
799; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], v3, v0
800; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v2, vcc
801; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, s[0:1]
802; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v4
803; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
804; GCN-NEXT:    v_cndmask_b32_e64 v0, -1, v0, s[0:1]
805; GCN-NEXT:    v_cndmask_b32_e32 v5, v8, v6, vcc
806; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v0
807; GCN-NEXT:    v_cndmask_b32_e64 v0, v1, v5, s[0:1]
808; GCN-NEXT:    v_cndmask_b32_e32 v1, v9, v7, vcc
809; GCN-NEXT:    v_cndmask_b32_e64 v1, v2, v1, s[0:1]
810; GCN-NEXT:    s_waitcnt lgkmcnt(0)
811; GCN-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
812; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
813; GCN-NEXT:    s_endpgm
814;
815; GCN-IR-LABEL: s_test_udiv24_i48:
816; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
817; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
818; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xb
819; GCN-IR-NEXT:    s_load_dword s3, s[0:1], 0xc
820; GCN-IR-NEXT:    s_load_dword s6, s[0:1], 0xd
821; GCN-IR-NEXT:    s_load_dword s7, s[0:1], 0xe
822; GCN-IR-NEXT:    s_mov_b32 s8, 0xffff
823; GCN-IR-NEXT:    s_mov_b32 s9, 0xff000000
824; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
825; GCN-IR-NEXT:    s_and_b32 s1, s3, s8
826; GCN-IR-NEXT:    s_and_b32 s0, s2, s9
827; GCN-IR-NEXT:    s_and_b32 s3, s7, s8
828; GCN-IR-NEXT:    s_and_b32 s2, s6, s9
829; GCN-IR-NEXT:    s_lshr_b64 s[6:7], s[0:1], 24
830; GCN-IR-NEXT:    s_lshr_b64 s[2:3], s[2:3], 24
831; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[2:3], 0
832; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
833; GCN-IR-NEXT:    s_mov_b64 s[0:1], 0
834; GCN-IR-NEXT:    s_or_b64 s[14:15], s[8:9], s[10:11]
835; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s2
836; GCN-IR-NEXT:    s_add_i32 s8, s8, 32
837; GCN-IR-NEXT:    s_flbit_i32_b32 s9, s3
838; GCN-IR-NEXT:    s_min_u32 s10, s8, s9
839; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s6
840; GCN-IR-NEXT:    s_add_i32 s8, s8, 32
841; GCN-IR-NEXT:    s_flbit_i32_b32 s9, s7
842; GCN-IR-NEXT:    s_min_u32 s12, s8, s9
843; GCN-IR-NEXT:    s_sub_u32 s8, s10, s12
844; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
845; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[16:17], s[8:9], 63
846; GCN-IR-NEXT:    s_mov_b32 s11, 0
847; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[16:17]
848; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[16:17], s[8:9], 63
849; GCN-IR-NEXT:    s_xor_b64 s[18:19], s[14:15], -1
850; GCN-IR-NEXT:    s_and_b64 s[16:17], s[18:19], s[16:17]
851; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[16:17]
852; GCN-IR-NEXT:    s_cbranch_vccz BB7_5
853; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
854; GCN-IR-NEXT:    s_add_u32 s14, s8, 1
855; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
856; GCN-IR-NEXT:    s_addc_u32 s15, s9, 0
857; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
858; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[14:15], v[0:1]
859; GCN-IR-NEXT:    s_sub_i32 s8, 63, s8
860; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
861; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[6:7], s8
862; GCN-IR-NEXT:    s_cbranch_vccz BB7_4
863; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
864; GCN-IR-NEXT:    s_lshr_b64 s[14:15], s[6:7], s14
865; GCN-IR-NEXT:    s_add_u32 s16, s2, -1
866; GCN-IR-NEXT:    s_addc_u32 s17, s3, -1
867; GCN-IR-NEXT:    s_not_b64 s[0:1], s[10:11]
868; GCN-IR-NEXT:    s_add_u32 s6, s0, s12
869; GCN-IR-NEXT:    s_addc_u32 s7, s1, s11
870; GCN-IR-NEXT:    s_mov_b32 s13, s11
871; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
872; GCN-IR-NEXT:    s_mov_b32 s1, 0
873; GCN-IR-NEXT:  BB7_3: ; %udiv-do-while
874; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
875; GCN-IR-NEXT:    s_lshr_b32 s0, s9, 31
876; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[14:15], 1
877; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
878; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[0:1]
879; GCN-IR-NEXT:    s_or_b64 s[8:9], s[10:11], s[8:9]
880; GCN-IR-NEXT:    s_sub_u32 s0, s16, s12
881; GCN-IR-NEXT:    s_subb_u32 s0, s17, s13
882; GCN-IR-NEXT:    s_ashr_i32 s10, s0, 31
883; GCN-IR-NEXT:    s_mov_b32 s11, s10
884; GCN-IR-NEXT:    s_and_b32 s0, s10, 1
885; GCN-IR-NEXT:    s_and_b64 s[14:15], s[10:11], s[2:3]
886; GCN-IR-NEXT:    s_sub_u32 s14, s12, s14
887; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
888; GCN-IR-NEXT:    s_subb_u32 s15, s13, s15
889; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
890; GCN-IR-NEXT:    s_add_u32 s6, s6, 1
891; GCN-IR-NEXT:    s_addc_u32 s7, s7, 0
892; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1]
893; GCN-IR-NEXT:    s_mov_b64 s[10:11], s[0:1]
894; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
895; GCN-IR-NEXT:    s_cbranch_vccz BB7_3
896; GCN-IR-NEXT:  BB7_4: ; %Flow3
897; GCN-IR-NEXT:    s_lshl_b64 s[2:3], s[8:9], 1
898; GCN-IR-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
899; GCN-IR-NEXT:    v_mov_b32_e32 v0, s0
900; GCN-IR-NEXT:    v_mov_b32_e32 v1, s1
901; GCN-IR-NEXT:    s_branch BB7_6
902; GCN-IR-NEXT:  BB7_5:
903; GCN-IR-NEXT:    v_mov_b32_e32 v0, s7
904; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[14:15]
905; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
906; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[14:15]
907; GCN-IR-NEXT:  BB7_6: ; %udiv-end
908; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
909; GCN-IR-NEXT:    s_mov_b32 s6, -1
910; GCN-IR-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
911; GCN-IR-NEXT:    buffer_store_dword v0, off, s[4:7], 0
912; GCN-IR-NEXT:    s_endpgm
913  %1 = lshr i48 %x, 24
914  %2 = lshr i48 %y, 24
915  %result = udiv i48 %1, %2
916  store i48 %result, i48 addrspace(1)* %out
917  ret void
918}
919
920define amdgpu_kernel void @s_test_udiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
921; GCN-LABEL: s_test_udiv_k_num_i64:
922; GCN:       ; %bb.0:
923; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
924; GCN-NEXT:    v_mov_b32_e32 v2, 0
925; GCN-NEXT:    s_mov_b32 s11, 0xf000
926; GCN-NEXT:    s_mov_b32 s10, -1
927; GCN-NEXT:    s_waitcnt lgkmcnt(0)
928; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s6
929; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s7
930; GCN-NEXT:    s_sub_u32 s2, 0, s6
931; GCN-NEXT:    s_subb_u32 s3, 0, s7
932; GCN-NEXT:    s_mov_b32 s8, s4
933; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
934; GCN-NEXT:    v_rcp_f32_e32 v0, v0
935; GCN-NEXT:    v_mov_b32_e32 v1, 0
936; GCN-NEXT:    s_mov_b32 s9, s5
937; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
938; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
939; GCN-NEXT:    v_trunc_f32_e32 v3, v3
940; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
941; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
942; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
943; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
944; GCN-NEXT:    v_mul_lo_u32 v4, s2, v3
945; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
946; GCN-NEXT:    v_mul_lo_u32 v6, s2, v0
947; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
948; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
949; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
950; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
951; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
952; GCN-NEXT:    v_mul_hi_u32 v8, v3, v6
953; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
954; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
955; GCN-NEXT:    v_mul_hi_u32 v10, v3, v4
956; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
957; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
958; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
959; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
960; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
961; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
962; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
963; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
964; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
965; GCN-NEXT:    v_mul_lo_u32 v6, s2, v4
966; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
967; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
968; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
969; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
970; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
971; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
972; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
973; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
974; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
975; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
976; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
977; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
978; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
979; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
980; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
981; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
982; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v8, v1, vcc
983; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
984; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
985; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
986; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v3, v1, s[0:1]
987; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
988; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
989; GCN-NEXT:    v_mul_lo_u32 v3, v1, 24
990; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
991; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
992; GCN-NEXT:    v_mov_b32_e32 v5, s7
993; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
994; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v2, v1, vcc
995; GCN-NEXT:    v_mul_lo_u32 v1, s7, v0
996; GCN-NEXT:    v_mul_hi_u32 v3, s6, v0
997; GCN-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
998; GCN-NEXT:    v_mul_lo_u32 v3, s6, v0
999; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v1
1000; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 24, v3
1001; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
1002; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s6, v3
1003; GCN-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
1004; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s7, v4
1005; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
1006; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s6, v5
1007; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
1008; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s7, v4
1009; GCN-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
1010; GCN-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
1011; GCN-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v2, s[0:1]
1012; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1013; GCN-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
1014; GCN-NEXT:    v_addc_u32_e64 v2, s[0:1], 0, v2, s[0:1]
1015; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
1016; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
1017; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
1018; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s6, v3
1019; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
1020; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s7, v1
1021; GCN-NEXT:    v_cndmask_b32_e32 v1, v4, v3, vcc
1022; GCN-NEXT:    v_cndmask_b32_e64 v2, v2, v6, s[0:1]
1023; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
1024; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
1025; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
1026; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1027; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
1028; GCN-NEXT:    s_endpgm
1029;
1030; GCN-IR-LABEL: s_test_udiv_k_num_i64:
1031; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1032; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1033; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1034; GCN-IR-NEXT:    s_flbit_i32_b32 s4, s2
1035; GCN-IR-NEXT:    s_flbit_i32_b32 s5, s3
1036; GCN-IR-NEXT:    s_add_i32 s4, s4, 32
1037; GCN-IR-NEXT:    s_min_u32 s6, s4, s5
1038; GCN-IR-NEXT:    s_add_u32 s8, s6, 0xffffffc5
1039; GCN-IR-NEXT:    s_addc_u32 s9, 0, -1
1040; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
1041; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[12:13], s[8:9], 63
1042; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0
1043; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
1044; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[12:13], s[8:9], 63
1045; GCN-IR-NEXT:    s_xor_b64 s[14:15], s[10:11], -1
1046; GCN-IR-NEXT:    s_and_b64 s[12:13], s[14:15], s[12:13]
1047; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
1048; GCN-IR-NEXT:    s_cbranch_vccz BB8_5
1049; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1050; GCN-IR-NEXT:    s_add_u32 s10, s8, 1
1051; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
1052; GCN-IR-NEXT:    s_addc_u32 s11, s9, 0
1053; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
1054; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
1055; GCN-IR-NEXT:    s_sub_i32 s7, 63, s8
1056; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1057; GCN-IR-NEXT:    s_lshl_b64 s[8:9], 24, s7
1058; GCN-IR-NEXT:    s_cbranch_vccz BB8_4
1059; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1060; GCN-IR-NEXT:    s_lshr_b64 s[12:13], 24, s10
1061; GCN-IR-NEXT:    s_add_u32 s14, s2, -1
1062; GCN-IR-NEXT:    s_addc_u32 s15, s3, -1
1063; GCN-IR-NEXT:    s_sub_u32 s6, 58, s6
1064; GCN-IR-NEXT:    s_subb_u32 s7, 0, 0
1065; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1066; GCN-IR-NEXT:    s_mov_b32 s5, 0
1067; GCN-IR-NEXT:  BB8_3: ; %udiv-do-while
1068; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1069; GCN-IR-NEXT:    s_lshr_b32 s4, s9, 31
1070; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
1071; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
1072; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[4:5]
1073; GCN-IR-NEXT:    s_or_b64 s[8:9], s[10:11], s[8:9]
1074; GCN-IR-NEXT:    s_sub_u32 s4, s14, s12
1075; GCN-IR-NEXT:    s_subb_u32 s4, s15, s13
1076; GCN-IR-NEXT:    s_ashr_i32 s10, s4, 31
1077; GCN-IR-NEXT:    s_mov_b32 s11, s10
1078; GCN-IR-NEXT:    s_and_b32 s4, s10, 1
1079; GCN-IR-NEXT:    s_and_b64 s[16:17], s[10:11], s[2:3]
1080; GCN-IR-NEXT:    s_sub_u32 s12, s12, s16
1081; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1082; GCN-IR-NEXT:    s_subb_u32 s13, s13, s17
1083; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
1084; GCN-IR-NEXT:    s_add_u32 s6, s6, 1
1085; GCN-IR-NEXT:    s_addc_u32 s7, s7, 0
1086; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1]
1087; GCN-IR-NEXT:    s_mov_b64 s[10:11], s[4:5]
1088; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1089; GCN-IR-NEXT:    s_cbranch_vccz BB8_3
1090; GCN-IR-NEXT:  BB8_4: ; %Flow5
1091; GCN-IR-NEXT:    s_lshl_b64 s[2:3], s[8:9], 1
1092; GCN-IR-NEXT:    s_or_b64 s[2:3], s[4:5], s[2:3]
1093; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1094; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
1095; GCN-IR-NEXT:    s_branch BB8_6
1096; GCN-IR-NEXT:  BB8_5:
1097; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1098; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, 24, 0, s[10:11]
1099; GCN-IR-NEXT:  BB8_6: ; %udiv-end
1100; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1101; GCN-IR-NEXT:    s_mov_b32 s2, -1
1102; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1103; GCN-IR-NEXT:    s_endpgm
1104  %result = udiv i64 24, %x
1105  store i64 %result, i64 addrspace(1)* %out
1106  ret void
1107}
1108
1109; define i64 @v_test_udiv_k_num_i64(i64 %x) {
1110;   %result = udiv i64 24, %x
1111;   ret i64 %result
1112; }
1113
1114define i64 @v_test_udiv_pow2_k_num_i64(i64 %x) {
1115; GCN-LABEL: v_test_udiv_pow2_k_num_i64:
1116; GCN:       ; %bb.0:
1117; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1118; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1119; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1120; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1121; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1122; GCN-NEXT:    v_mov_b32_e32 v12, 0
1123; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
1124; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1125; GCN-NEXT:    v_mov_b32_e32 v11, 0
1126; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1127; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1128; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1129; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1130; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1131; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1132; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1133; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1134; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1135; GCN-NEXT:    v_mul_lo_u32 v9, v4, v2
1136; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1137; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1138; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
1139; GCN-NEXT:    v_mul_hi_u32 v10, v2, v9
1140; GCN-NEXT:    v_mul_hi_u32 v7, v2, v6
1141; GCN-NEXT:    v_mul_hi_u32 v13, v3, v6
1142; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1143; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
1144; GCN-NEXT:    v_mul_lo_u32 v10, v3, v9
1145; GCN-NEXT:    v_mul_hi_u32 v9, v3, v9
1146; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v7, vcc
1147; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
1148; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v9, vcc
1149; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v11, vcc
1150; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1151; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v6
1152; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v8, vcc
1153; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v3, v7, s[4:5]
1154; GCN-NEXT:    v_mul_lo_u32 v8, v4, v6
1155; GCN-NEXT:    v_mul_hi_u32 v9, v4, v2
1156; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1157; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1158; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1159; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
1160; GCN-NEXT:    v_mul_lo_u32 v10, v2, v5
1161; GCN-NEXT:    v_mul_hi_u32 v13, v2, v4
1162; GCN-NEXT:    v_mul_hi_u32 v14, v2, v5
1163; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
1164; GCN-NEXT:    v_mul_lo_u32 v4, v6, v4
1165; GCN-NEXT:    v_add_i32_e32 v10, vcc, v13, v10
1166; GCN-NEXT:    v_mul_hi_u32 v8, v6, v5
1167; GCN-NEXT:    v_addc_u32_e32 v13, vcc, v12, v14, vcc
1168; GCN-NEXT:    v_mul_lo_u32 v5, v6, v5
1169; GCN-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
1170; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v13, v9, vcc
1171; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v11, vcc
1172; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1173; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
1174; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
1175; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
1176; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1177; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
1178; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1179; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
1180; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1181; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1182; GCN-NEXT:    v_mul_lo_u32 v4, v0, v2
1183; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v3
1184; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0x8000, v4
1185; GCN-NEXT:    v_subb_u32_e64 v5, s[4:5], v5, v1, vcc
1186; GCN-NEXT:    v_sub_i32_e64 v6, s[4:5], v4, v0
1187; GCN-NEXT:    v_subbrev_u32_e64 v5, s[4:5], 0, v5, s[4:5]
1188; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v5, v1
1189; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
1190; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v0
1191; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
1192; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v5, v1
1193; GCN-NEXT:    v_cndmask_b32_e64 v5, v7, v6, s[4:5]
1194; GCN-NEXT:    v_add_i32_e64 v6, s[4:5], 2, v2
1195; GCN-NEXT:    v_addc_u32_e64 v7, s[4:5], 0, v12, s[4:5]
1196; GCN-NEXT:    v_add_i32_e64 v8, s[4:5], 1, v2
1197; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1198; GCN-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, v12, s[4:5]
1199; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v5
1200; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1201; GCN-NEXT:    v_cndmask_b32_e64 v5, v8, v6, s[4:5]
1202; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1203; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v0
1204; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1205; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1206; GCN-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
1207; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1208; GCN-NEXT:    v_cndmask_b32_e64 v1, v9, v7, s[4:5]
1209; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1210; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
1211; GCN-NEXT:    s_setpc_b64 s[30:31]
1212;
1213; GCN-IR-LABEL: v_test_udiv_pow2_k_num_i64:
1214; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1215; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1216; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1217; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1218; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1219; GCN-IR-NEXT:    v_min_u32_e32 v4, v2, v3
1220; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 0xffffffd0, v4
1221; GCN-IR-NEXT:    v_addc_u32_e64 v7, s[6:7], 0, -1, vcc
1222; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1223; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[6:7]
1224; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0x8000
1225; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1226; GCN-IR-NEXT:    v_mov_b32_e32 v2, s8
1227; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[6:7]
1228; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1229; GCN-IR-NEXT:    v_cndmask_b32_e64 v2, v2, 0, s[4:5]
1230; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1231; GCN-IR-NEXT:    v_mov_b32_e32 v3, v5
1232; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1233; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1234; GCN-IR-NEXT:    s_cbranch_execz BB9_6
1235; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1236; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v6
1237; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v7, vcc
1238; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v6
1239; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[8:9], v[6:7]
1240; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1241; GCN-IR-NEXT:    v_lshl_b64 v[2:3], s[8:9], v2
1242; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1243; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1244; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1245; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1246; GCN-IR-NEXT:    s_cbranch_execz BB9_5
1247; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1248; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, -1, v0
1249; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, -1, v1, vcc
1250; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0x8000
1251; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, 47, v4
1252; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1253; GCN-IR-NEXT:    v_lshr_b64 v[8:9], s[4:5], v8
1254; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1255; GCN-IR-NEXT:    v_subb_u32_e32 v5, vcc, 0, v5, vcc
1256; GCN-IR-NEXT:  BB9_3: ; %udiv-do-while
1257; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1258; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1259; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v3
1260; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v6
1261; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1262; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v12, v8
1263; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v13, v9, vcc
1264; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1265; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v6
1266; GCN-IR-NEXT:    v_and_b32_e32 v15, v10, v0
1267; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v10
1268; GCN-IR-NEXT:    v_and_b32_e32 v14, v10, v1
1269; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v4
1270; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1271; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v5, vcc
1272; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[10:11], v[4:5]
1273; GCN-IR-NEXT:    v_mov_b32_e32 v4, v10
1274; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1275; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v15
1276; GCN-IR-NEXT:    v_mov_b32_e32 v5, v11
1277; GCN-IR-NEXT:    v_mov_b32_e32 v11, v7
1278; GCN-IR-NEXT:    v_subb_u32_e64 v9, s[4:5], v9, v14, s[4:5]
1279; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1280; GCN-IR-NEXT:    v_mov_b32_e32 v10, v6
1281; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1282; GCN-IR-NEXT:    s_cbranch_execnz BB9_3
1283; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1284; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1285; GCN-IR-NEXT:  BB9_5: ; %Flow3
1286; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1287; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[2:3], 1
1288; GCN-IR-NEXT:    v_or_b32_e32 v3, v7, v1
1289; GCN-IR-NEXT:    v_or_b32_e32 v2, v6, v0
1290; GCN-IR-NEXT:  BB9_6: ; %Flow4
1291; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1292; GCN-IR-NEXT:    v_mov_b32_e32 v0, v2
1293; GCN-IR-NEXT:    v_mov_b32_e32 v1, v3
1294; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1295  %result = udiv i64 32768, %x
1296  ret i64 %result
1297}
1298
1299define i64 @v_test_udiv_pow2_k_den_i64(i64 %x) {
1300; GCN-LABEL: v_test_udiv_pow2_k_den_i64:
1301; GCN:       ; %bb.0:
1302; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1303; GCN-NEXT:    v_alignbit_b32 v0, v1, v0, 15
1304; GCN-NEXT:    v_lshrrev_b32_e32 v1, 15, v1
1305; GCN-NEXT:    s_setpc_b64 s[30:31]
1306;
1307; GCN-IR-LABEL: v_test_udiv_pow2_k_den_i64:
1308; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1309; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1310; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1311; GCN-IR-NEXT:    v_add_i32_e64 v2, s[4:5], 32, v2
1312; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1313; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1314; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 48, v6
1315; GCN-IR-NEXT:    v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5]
1316; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1317; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
1318; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1319; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1320; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1321; GCN-IR-NEXT:    v_cndmask_b32_e64 v2, v1, 0, s[4:5]
1322; GCN-IR-NEXT:    v_cndmask_b32_e64 v3, v0, 0, s[4:5]
1323; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1324; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1325; GCN-IR-NEXT:    s_cbranch_execz BB10_6
1326; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1327; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 1, v4
1328; GCN-IR-NEXT:    v_addc_u32_e32 v8, vcc, 0, v5, vcc
1329; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v4
1330; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[7:8], v[4:5]
1331; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1332; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[0:1], v2
1333; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1334; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1335; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1336; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1337; GCN-IR-NEXT:    s_cbranch_execz BB10_5
1338; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1339; GCN-IR-NEXT:    v_lshr_b64 v[7:8], v[0:1], v7
1340; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, 0xffffffcf, v6
1341; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1342; GCN-IR-NEXT:    v_addc_u32_e64 v1, s[4:5], 0, -1, vcc
1343; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1344; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
1345; GCN-IR-NEXT:  BB10_3: ; %udiv-do-while
1346; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1347; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
1348; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1349; GCN-IR-NEXT:    v_or_b32_e32 v7, v7, v4
1350; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1351; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, s12, v7
1352; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, 0, v8, vcc
1353; GCN-IR-NEXT:    v_or_b32_e32 v2, v9, v2
1354; GCN-IR-NEXT:    v_ashrrev_i32_e32 v9, 31, v4
1355; GCN-IR-NEXT:    v_and_b32_e32 v11, 0x8000, v9
1356; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v9
1357; GCN-IR-NEXT:    v_add_i32_e32 v9, vcc, 1, v0
1358; GCN-IR-NEXT:    v_or_b32_e32 v3, v10, v3
1359; GCN-IR-NEXT:    v_addc_u32_e32 v10, vcc, 0, v1, vcc
1360; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[9:10], v[0:1]
1361; GCN-IR-NEXT:    v_mov_b32_e32 v0, v9
1362; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1363; GCN-IR-NEXT:    v_mov_b32_e32 v1, v10
1364; GCN-IR-NEXT:    v_mov_b32_e32 v10, v5
1365; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1366; GCN-IR-NEXT:    v_sub_i32_e64 v7, s[4:5], v7, v11
1367; GCN-IR-NEXT:    v_subb_u32_e64 v8, s[4:5], v8, v6, s[4:5]
1368; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1369; GCN-IR-NEXT:    v_mov_b32_e32 v9, v4
1370; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1371; GCN-IR-NEXT:    s_cbranch_execnz BB10_3
1372; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1373; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1374; GCN-IR-NEXT:  BB10_5: ; %Flow3
1375; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1376; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[2:3], 1
1377; GCN-IR-NEXT:    v_or_b32_e32 v2, v5, v1
1378; GCN-IR-NEXT:    v_or_b32_e32 v3, v4, v0
1379; GCN-IR-NEXT:  BB10_6: ; %Flow4
1380; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1381; GCN-IR-NEXT:    v_mov_b32_e32 v0, v3
1382; GCN-IR-NEXT:    v_mov_b32_e32 v1, v2
1383; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1384  %result = udiv i64 %x, 32768
1385  ret i64 %result
1386}
1387
1388define amdgpu_kernel void @s_test_udiv_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
1389; GCN-LABEL: s_test_udiv_k_den_i64:
1390; GCN:       ; %bb.0:
1391; GCN-NEXT:    v_mov_b32_e32 v0, 0x4f800000
1392; GCN-NEXT:    v_madak_f32 v0, 0, v0, 0x41c00000
1393; GCN-NEXT:    v_rcp_f32_e32 v0, v0
1394; GCN-NEXT:    s_movk_i32 s2, 0xffe8
1395; GCN-NEXT:    v_mov_b32_e32 v8, 0
1396; GCN-NEXT:    v_mov_b32_e32 v7, 0
1397; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
1398; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
1399; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1400; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
1401; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
1402; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
1403; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
1404; GCN-NEXT:    s_mov_b32 s7, 0xf000
1405; GCN-NEXT:    v_mul_hi_u32 v2, v0, s2
1406; GCN-NEXT:    v_mul_lo_u32 v3, v1, s2
1407; GCN-NEXT:    v_mul_lo_u32 v4, v0, s2
1408; GCN-NEXT:    s_mov_b32 s6, -1
1409; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
1410; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1411; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
1412; GCN-NEXT:    v_mul_hi_u32 v6, v0, v4
1413; GCN-NEXT:    v_mul_hi_u32 v3, v0, v2
1414; GCN-NEXT:    v_mul_hi_u32 v9, v1, v2
1415; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
1416; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
1417; GCN-NEXT:    v_mul_lo_u32 v6, v1, v4
1418; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
1419; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v3, vcc
1420; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1421; GCN-NEXT:    s_mov_b32 s4, s8
1422; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
1423; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
1424; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
1425; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1426; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
1427; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
1428; GCN-NEXT:    v_mul_hi_u32 v4, v0, s2
1429; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
1430; GCN-NEXT:    v_mul_lo_u32 v5, v2, s2
1431; GCN-NEXT:    v_mul_lo_u32 v6, v0, s2
1432; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, v0, v4
1433; GCN-NEXT:    s_mov_b32 s5, s9
1434; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1435; GCN-NEXT:    v_mul_lo_u32 v5, v0, v4
1436; GCN-NEXT:    v_mul_hi_u32 v9, v0, v6
1437; GCN-NEXT:    v_mul_hi_u32 v10, v0, v4
1438; GCN-NEXT:    v_mul_hi_u32 v11, v2, v4
1439; GCN-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
1440; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v8, v10, vcc
1441; GCN-NEXT:    v_mul_lo_u32 v10, v2, v6
1442; GCN-NEXT:    v_mul_hi_u32 v6, v2, v6
1443; GCN-NEXT:    v_mul_lo_u32 v2, v2, v4
1444; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v10
1445; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v6, vcc
1446; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v11, v7, vcc
1447; GCN-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
1448; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
1449; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1450; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
1451; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1452; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1453; GCN-NEXT:    v_mul_lo_u32 v2, s10, v1
1454; GCN-NEXT:    v_mul_hi_u32 v3, s10, v0
1455; GCN-NEXT:    v_mul_hi_u32 v4, s10, v1
1456; GCN-NEXT:    v_mul_hi_u32 v5, s11, v1
1457; GCN-NEXT:    v_mul_lo_u32 v1, s11, v1
1458; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1459; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
1460; GCN-NEXT:    v_mul_lo_u32 v4, s11, v0
1461; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
1462; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1463; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
1464; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
1465; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1466; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v8, v2, vcc
1467; GCN-NEXT:    v_mul_lo_u32 v2, v1, 24
1468; GCN-NEXT:    v_mul_hi_u32 v3, v0, 24
1469; GCN-NEXT:    v_mul_lo_u32 v4, v0, 24
1470; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1471; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s10, v4
1472; GCN-NEXT:    v_mov_b32_e32 v3, s11
1473; GCN-NEXT:    v_subb_u32_e32 v2, vcc, v3, v2, vcc
1474; GCN-NEXT:    v_subrev_i32_e32 v3, vcc, 24, v4
1475; GCN-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
1476; GCN-NEXT:    v_cmp_lt_u32_e32 vcc, 23, v3
1477; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
1478; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v5
1479; GCN-NEXT:    v_cndmask_b32_e32 v3, -1, v3, vcc
1480; GCN-NEXT:    v_add_i32_e32 v5, vcc, 2, v0
1481; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
1482; GCN-NEXT:    v_add_i32_e32 v7, vcc, 1, v0
1483; GCN-NEXT:    v_cmp_lt_u32_e64 s[0:1], 23, v4
1484; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v1, vcc
1485; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]
1486; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v2
1487; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
1488; GCN-NEXT:    v_cndmask_b32_e64 v2, -1, v4, s[0:1]
1489; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v2
1490; GCN-NEXT:    v_cndmask_b32_e32 v3, v8, v6, vcc
1491; GCN-NEXT:    v_cndmask_b32_e32 v2, v7, v5, vcc
1492; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
1493; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
1494; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1495; GCN-NEXT:    s_endpgm
1496;
1497; GCN-IR-LABEL: s_test_udiv_k_den_i64:
1498; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1499; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1500; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1501; GCN-IR-NEXT:    s_flbit_i32_b32 s4, s2
1502; GCN-IR-NEXT:    s_flbit_i32_b32 s5, s3
1503; GCN-IR-NEXT:    s_add_i32 s4, s4, 32
1504; GCN-IR-NEXT:    s_min_u32 s8, s4, s5
1505; GCN-IR-NEXT:    s_sub_u32 s6, 59, s8
1506; GCN-IR-NEXT:    s_subb_u32 s7, 0, 0
1507; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
1508; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[12:13], s[6:7], 63
1509; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0
1510; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
1511; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[12:13], s[6:7], 63
1512; GCN-IR-NEXT:    s_xor_b64 s[14:15], s[10:11], -1
1513; GCN-IR-NEXT:    s_and_b64 s[12:13], s[14:15], s[12:13]
1514; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
1515; GCN-IR-NEXT:    s_cbranch_vccz BB11_5
1516; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1517; GCN-IR-NEXT:    s_add_u32 s10, s6, 1
1518; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1519; GCN-IR-NEXT:    s_addc_u32 s11, s7, 0
1520; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
1521; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
1522; GCN-IR-NEXT:    s_sub_i32 s6, 63, s6
1523; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1524; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[2:3], s6
1525; GCN-IR-NEXT:    s_cbranch_vccz BB11_4
1526; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1527; GCN-IR-NEXT:    s_lshr_b64 s[10:11], s[2:3], s10
1528; GCN-IR-NEXT:    s_add_u32 s2, s8, 0xffffffc4
1529; GCN-IR-NEXT:    s_addc_u32 s3, 0, -1
1530; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1531; GCN-IR-NEXT:    s_mov_b32 s5, 0
1532; GCN-IR-NEXT:  BB11_3: ; %udiv-do-while
1533; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1534; GCN-IR-NEXT:    s_lshr_b32 s4, s7, 31
1535; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
1536; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[6:7], 1
1537; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[4:5]
1538; GCN-IR-NEXT:    s_or_b64 s[6:7], s[8:9], s[6:7]
1539; GCN-IR-NEXT:    s_sub_u32 s4, 23, s10
1540; GCN-IR-NEXT:    s_subb_u32 s4, 0, s11
1541; GCN-IR-NEXT:    s_ashr_i32 s8, s4, 31
1542; GCN-IR-NEXT:    s_and_b32 s4, s8, 1
1543; GCN-IR-NEXT:    s_and_b32 s8, s8, 24
1544; GCN-IR-NEXT:    s_sub_u32 s10, s10, s8
1545; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1546; GCN-IR-NEXT:    s_subb_u32 s11, s11, 0
1547; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
1548; GCN-IR-NEXT:    s_add_u32 s2, s2, 1
1549; GCN-IR-NEXT:    s_addc_u32 s3, s3, 0
1550; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1]
1551; GCN-IR-NEXT:    s_mov_b64 s[8:9], s[4:5]
1552; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1553; GCN-IR-NEXT:    s_cbranch_vccz BB11_3
1554; GCN-IR-NEXT:  BB11_4: ; %Flow5
1555; GCN-IR-NEXT:    s_lshl_b64 s[2:3], s[6:7], 1
1556; GCN-IR-NEXT:    s_or_b64 s[2:3], s[4:5], s[2:3]
1557; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1558; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
1559; GCN-IR-NEXT:    s_branch BB11_6
1560; GCN-IR-NEXT:  BB11_5:
1561; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
1562; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[10:11]
1563; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1564; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[10:11]
1565; GCN-IR-NEXT:  BB11_6: ; %udiv-end
1566; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1567; GCN-IR-NEXT:    s_mov_b32 s2, -1
1568; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1569; GCN-IR-NEXT:    s_endpgm
1570  %result = udiv i64 %x, 24
1571  store i64 %result, i64 addrspace(1)* %out
1572  ret void
1573}
1574
1575define i64 @v_test_udiv_k_den_i64(i64 %x) {
1576; GCN-LABEL: v_test_udiv_k_den_i64:
1577; GCN:       ; %bb.0:
1578; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1579; GCN-NEXT:    v_mov_b32_e32 v2, 0x4f800000
1580; GCN-NEXT:    v_madak_f32 v2, 0, v2, 0x41c00000
1581; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1582; GCN-NEXT:    s_movk_i32 s6, 0xffe8
1583; GCN-NEXT:    v_mov_b32_e32 v10, 0
1584; GCN-NEXT:    v_mov_b32_e32 v9, 0
1585; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1586; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1587; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1588; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1589; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1590; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1591; GCN-NEXT:    v_mul_hi_u32 v4, v2, s6
1592; GCN-NEXT:    v_mul_lo_u32 v5, v3, s6
1593; GCN-NEXT:    v_mul_lo_u32 v6, v2, s6
1594; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, v2, v4
1595; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1596; GCN-NEXT:    v_mul_lo_u32 v7, v2, v4
1597; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
1598; GCN-NEXT:    v_mul_hi_u32 v5, v2, v4
1599; GCN-NEXT:    v_mul_hi_u32 v11, v3, v4
1600; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1601; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1602; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
1603; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
1604; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v10, v5, vcc
1605; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
1606; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v6, vcc
1607; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
1608; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1609; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v4
1610; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v10, v6, vcc
1611; GCN-NEXT:    v_mul_hi_u32 v6, v2, s6
1612; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[4:5]
1613; GCN-NEXT:    v_mul_lo_u32 v7, v4, s6
1614; GCN-NEXT:    v_mul_lo_u32 v8, v2, s6
1615; GCN-NEXT:    v_subrev_i32_e32 v6, vcc, v2, v6
1616; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
1617; GCN-NEXT:    v_mul_lo_u32 v7, v2, v6
1618; GCN-NEXT:    v_mul_hi_u32 v11, v2, v8
1619; GCN-NEXT:    v_mul_hi_u32 v12, v2, v6
1620; GCN-NEXT:    v_mul_hi_u32 v13, v4, v6
1621; GCN-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
1622; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v10, v12, vcc
1623; GCN-NEXT:    v_mul_lo_u32 v12, v4, v8
1624; GCN-NEXT:    v_mul_hi_u32 v8, v4, v8
1625; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
1626; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
1627; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v8, vcc
1628; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v13, v9, vcc
1629; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
1630; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v6, vcc
1631; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1632; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[4:5]
1633; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1634; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1635; GCN-NEXT:    v_mul_lo_u32 v4, v0, v3
1636; GCN-NEXT:    v_mul_hi_u32 v5, v0, v2
1637; GCN-NEXT:    v_mul_hi_u32 v6, v0, v3
1638; GCN-NEXT:    v_mul_hi_u32 v7, v1, v3
1639; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
1640; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1641; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v10, v6, vcc
1642; GCN-NEXT:    v_mul_lo_u32 v6, v1, v2
1643; GCN-NEXT:    v_mul_hi_u32 v2, v1, v2
1644; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
1645; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v2, vcc
1646; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v9, vcc
1647; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
1648; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v10, v4, vcc
1649; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
1650; GCN-NEXT:    v_mul_hi_u32 v5, v2, 24
1651; GCN-NEXT:    v_mul_lo_u32 v6, v2, 24
1652; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1653; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
1654; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc
1655; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, 24, v0
1656; GCN-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v1, vcc
1657; GCN-NEXT:    v_cmp_lt_u32_e32 vcc, 23, v4
1658; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
1659; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v5
1660; GCN-NEXT:    v_cndmask_b32_e32 v4, -1, v4, vcc
1661; GCN-NEXT:    v_add_i32_e32 v5, vcc, 2, v2
1662; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v3, vcc
1663; GCN-NEXT:    v_add_i32_e32 v7, vcc, 1, v2
1664; GCN-NEXT:    v_cmp_lt_u32_e64 s[4:5], 23, v0
1665; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v3, vcc
1666; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, s[4:5]
1667; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v1
1668; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
1669; GCN-NEXT:    v_cndmask_b32_e64 v0, -1, v0, s[4:5]
1670; GCN-NEXT:    v_cndmask_b32_e32 v4, v7, v5, vcc
1671; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v0
1672; GCN-NEXT:    v_cndmask_b32_e32 v1, v8, v6, vcc
1673; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, v4, s[4:5]
1674; GCN-NEXT:    v_cndmask_b32_e64 v1, v3, v1, s[4:5]
1675; GCN-NEXT:    s_setpc_b64 s[30:31]
1676;
1677; GCN-IR-LABEL: v_test_udiv_k_den_i64:
1678; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1679; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1680; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1681; GCN-IR-NEXT:    v_add_i32_e64 v2, s[4:5], 32, v2
1682; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1683; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1684; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 59, v6
1685; GCN-IR-NEXT:    v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5]
1686; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1687; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
1688; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1689; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1690; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1691; GCN-IR-NEXT:    v_cndmask_b32_e64 v2, v1, 0, s[4:5]
1692; GCN-IR-NEXT:    v_cndmask_b32_e64 v3, v0, 0, s[4:5]
1693; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1694; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1695; GCN-IR-NEXT:    s_cbranch_execz BB12_6
1696; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1697; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 1, v4
1698; GCN-IR-NEXT:    v_addc_u32_e32 v8, vcc, 0, v5, vcc
1699; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v4
1700; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[7:8], v[4:5]
1701; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1702; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[0:1], v2
1703; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1704; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1705; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1706; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1707; GCN-IR-NEXT:    s_cbranch_execz BB12_5
1708; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1709; GCN-IR-NEXT:    v_lshr_b64 v[7:8], v[0:1], v7
1710; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, 0xffffffc4, v6
1711; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1712; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1713; GCN-IR-NEXT:    v_addc_u32_e64 v1, s[4:5], 0, -1, vcc
1714; GCN-IR-NEXT:  BB12_3: ; %udiv-do-while
1715; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1716; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
1717; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1718; GCN-IR-NEXT:    v_or_b32_e32 v6, v7, v4
1719; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1720; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, 23, v6
1721; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, 0, v8, vcc
1722; GCN-IR-NEXT:    v_or_b32_e32 v2, v9, v2
1723; GCN-IR-NEXT:    v_add_i32_e32 v9, vcc, 1, v0
1724; GCN-IR-NEXT:    v_ashrrev_i32_e32 v7, 31, v4
1725; GCN-IR-NEXT:    v_or_b32_e32 v3, v10, v3
1726; GCN-IR-NEXT:    v_addc_u32_e32 v10, vcc, 0, v1, vcc
1727; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[9:10], v[0:1]
1728; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v7
1729; GCN-IR-NEXT:    v_and_b32_e32 v7, 24, v7
1730; GCN-IR-NEXT:    v_mov_b32_e32 v0, v9
1731; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1732; GCN-IR-NEXT:    v_sub_i32_e64 v7, s[4:5], v6, v7
1733; GCN-IR-NEXT:    v_mov_b32_e32 v1, v10
1734; GCN-IR-NEXT:    v_mov_b32_e32 v10, v5
1735; GCN-IR-NEXT:    v_subbrev_u32_e64 v8, s[4:5], 0, v8, s[4:5]
1736; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1737; GCN-IR-NEXT:    v_mov_b32_e32 v9, v4
1738; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1739; GCN-IR-NEXT:    s_cbranch_execnz BB12_3
1740; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1741; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1742; GCN-IR-NEXT:  BB12_5: ; %Flow3
1743; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1744; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[2:3], 1
1745; GCN-IR-NEXT:    v_or_b32_e32 v2, v5, v1
1746; GCN-IR-NEXT:    v_or_b32_e32 v3, v4, v0
1747; GCN-IR-NEXT:  BB12_6: ; %Flow4
1748; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1749; GCN-IR-NEXT:    v_mov_b32_e32 v0, v3
1750; GCN-IR-NEXT:    v_mov_b32_e32 v1, v2
1751; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1752  %result = udiv i64 %x, 24
1753  ret i64 %result
1754}
1755
1756define amdgpu_kernel void @s_test_udiv24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1757; GCN-LABEL: s_test_udiv24_k_num_i64:
1758; GCN:       ; %bb.0:
1759; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1760; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
1761; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1762; GCN-NEXT:    s_lshr_b32 s2, s3, 8
1763; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
1764; GCN-NEXT:    s_mov_b32 s3, 0xf000
1765; GCN-NEXT:    s_mov_b32 s2, -1
1766; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1767; GCN-NEXT:    v_mul_f32_e32 v1, s4, v1
1768; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1769; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1770; GCN-NEXT:    v_mad_f32 v1, -v1, v0, s4
1771; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1772; GCN-NEXT:    v_mov_b32_e32 v1, 0
1773; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1774; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1775; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1776; GCN-NEXT:    s_endpgm
1777;
1778; GCN-IR-LABEL: s_test_udiv24_k_num_i64:
1779; GCN-IR:       ; %bb.0:
1780; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1781; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
1782; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1783; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 8
1784; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
1785; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1786; GCN-IR-NEXT:    s_mov_b32 s2, -1
1787; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1788; GCN-IR-NEXT:    v_mul_f32_e32 v1, s4, v1
1789; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1790; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1791; GCN-IR-NEXT:    v_mad_f32 v1, -v1, v0, s4
1792; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1793; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1794; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1795; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1796; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1797; GCN-IR-NEXT:    s_endpgm
1798  %x.shr = lshr i64 %x, 40
1799  %result = udiv i64 24, %x.shr
1800  store i64 %result, i64 addrspace(1)* %out
1801  ret void
1802}
1803
1804define amdgpu_kernel void @s_test_udiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
1805; GCN-LABEL: s_test_udiv24_k_den_i64:
1806; GCN:       ; %bb.0:
1807; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1808; GCN-NEXT:    s_mov_b32 s7, 0xf000
1809; GCN-NEXT:    s_mov_b32 s6, -1
1810; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1811; GCN-NEXT:    s_lshr_b32 s2, s3, 8
1812; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
1813; GCN-NEXT:    s_mov_b32 s2, 0x46b6fe00
1814; GCN-NEXT:    s_mov_b32 s4, s0
1815; GCN-NEXT:    s_mov_b32 s5, s1
1816; GCN-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1817; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1818; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1819; GCN-NEXT:    v_mad_f32 v0, -v1, s2, v0
1820; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s2
1821; GCN-NEXT:    v_mov_b32_e32 v1, 0
1822; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1823; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1824; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1825; GCN-NEXT:    s_endpgm
1826;
1827; GCN-IR-LABEL: s_test_udiv24_k_den_i64:
1828; GCN-IR:       ; %bb.0:
1829; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1830; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1831; GCN-IR-NEXT:    s_mov_b32 s6, -1
1832; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1833; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 8
1834; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
1835; GCN-IR-NEXT:    s_mov_b32 s2, 0x46b6fe00
1836; GCN-IR-NEXT:    s_mov_b32 s4, s0
1837; GCN-IR-NEXT:    s_mov_b32 s5, s1
1838; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1839; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1840; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1841; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s2, v0
1842; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s2
1843; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1844; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1845; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1846; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1847; GCN-IR-NEXT:    s_endpgm
1848  %x.shr = lshr i64 %x, 40
1849  %result = udiv i64 %x.shr, 23423
1850  store i64 %result, i64 addrspace(1)* %out
1851  ret void
1852}
1853
1854define i64 @v_test_udiv24_k_num_i64(i64 %x) {
1855; GCN-LABEL: v_test_udiv24_k_num_i64:
1856; GCN:       ; %bb.0:
1857; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1858; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1859; GCN-NEXT:    v_cvt_f32_u32_e32 v0, v0
1860; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
1861; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1862; GCN-NEXT:    v_mul_f32_e32 v1, s4, v1
1863; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1864; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1865; GCN-NEXT:    v_mad_f32 v1, -v1, v0, s4
1866; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1867; GCN-NEXT:    v_mov_b32_e32 v1, 0
1868; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1869; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1870; GCN-NEXT:    s_setpc_b64 s[30:31]
1871;
1872; GCN-IR-LABEL: v_test_udiv24_k_num_i64:
1873; GCN-IR:       ; %bb.0:
1874; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1875; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1876; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, v0
1877; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
1878; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1879; GCN-IR-NEXT:    v_mul_f32_e32 v1, s4, v1
1880; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1881; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1882; GCN-IR-NEXT:    v_mad_f32 v1, -v1, v0, s4
1883; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1884; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1885; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1886; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1887; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1888  %x.shr = lshr i64 %x, 40
1889  %result = udiv i64 24, %x.shr
1890  ret i64 %result
1891}
1892
1893define i64 @v_test_udiv24_pow2_k_num_i64(i64 %x) {
1894; GCN-LABEL: v_test_udiv24_pow2_k_num_i64:
1895; GCN:       ; %bb.0:
1896; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1897; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1898; GCN-NEXT:    v_cvt_f32_u32_e32 v0, v0
1899; GCN-NEXT:    s_mov_b32 s4, 0x47000000
1900; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1901; GCN-NEXT:    v_mul_f32_e32 v1, s4, v1
1902; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1903; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1904; GCN-NEXT:    v_mad_f32 v1, -v1, v0, s4
1905; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1906; GCN-NEXT:    v_mov_b32_e32 v1, 0
1907; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1908; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1909; GCN-NEXT:    s_setpc_b64 s[30:31]
1910;
1911; GCN-IR-LABEL: v_test_udiv24_pow2_k_num_i64:
1912; GCN-IR:       ; %bb.0:
1913; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1914; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1915; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, v0
1916; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
1917; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1918; GCN-IR-NEXT:    v_mul_f32_e32 v1, s4, v1
1919; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1920; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1921; GCN-IR-NEXT:    v_mad_f32 v1, -v1, v0, s4
1922; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1923; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1924; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1925; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1926; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1927  %x.shr = lshr i64 %x, 40
1928  %result = udiv i64 32768, %x.shr
1929  ret i64 %result
1930}
1931
1932define i64 @v_test_udiv24_pow2_k_den_i64(i64 %x) {
1933; GCN-LABEL: v_test_udiv24_pow2_k_den_i64:
1934; GCN:       ; %bb.0:
1935; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1936; GCN-NEXT:    v_lshrrev_b32_e32 v0, 23, v1
1937; GCN-NEXT:    v_mov_b32_e32 v1, 0
1938; GCN-NEXT:    s_setpc_b64 s[30:31]
1939;
1940; GCN-IR-LABEL: v_test_udiv24_pow2_k_den_i64:
1941; GCN-IR:       ; %bb.0:
1942; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1943; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1944; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, v0
1945; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
1946; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38000000, v0
1947; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1948; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1949; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s4, v0
1950; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
1951; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1952; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1953; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1954; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1955  %x.shr = lshr i64 %x, 40
1956  %result = udiv i64 %x.shr, 32768
1957  ret i64 %result
1958}
1959