1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3
4define amdgpu_kernel void @s_test_udiv_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
5; GCN-LABEL: s_test_udiv_i64:
6; GCN:       ; %bb.0:
7; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
8; GCN-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
9; GCN-NEXT:    s_mov_b32 s7, 0xf000
10; GCN-NEXT:    s_mov_b32 s6, -1
11; GCN-NEXT:    v_mov_b32_e32 v0, 0
12; GCN-NEXT:    v_mov_b32_e32 v1, 0
13; GCN-NEXT:    s_waitcnt lgkmcnt(0)
14; GCN-NEXT:    s_mov_b32 s4, s8
15; GCN-NEXT:    s_mov_b32 s5, s9
16; GCN-NEXT:    v_cvt_f32_u32_e32 v2, s2
17; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s3
18; GCN-NEXT:    s_sub_u32 s8, 0, s2
19; GCN-NEXT:    v_mov_b32_e32 v4, s3
20; GCN-NEXT:    v_mov_b32_e32 v5, s11
21; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
22; GCN-NEXT:    s_subb_u32 s9, 0, s3
23; GCN-NEXT:    v_rcp_f32_e32 v2, v2
24; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
25; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
26; GCN-NEXT:    v_trunc_f32_e32 v3, v3
27; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
28; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
29; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
30; GCN-NEXT:    v_mul_lo_u32 v6, s8, v3
31; GCN-NEXT:    v_mul_lo_u32 v7, s9, v2
32; GCN-NEXT:    v_mul_hi_u32 v8, s8, v2
33; GCN-NEXT:    v_mul_lo_u32 v9, s8, v2
34; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
35; GCN-NEXT:    v_mul_hi_u32 v8, v2, v9
36; GCN-NEXT:    v_mul_hi_u32 v10, v3, v9
37; GCN-NEXT:    v_mul_lo_u32 v9, v3, v9
38; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
39; GCN-NEXT:    v_mul_hi_u32 v7, v2, v6
40; GCN-NEXT:    v_mul_lo_u32 v11, v2, v6
41; GCN-NEXT:    v_mul_hi_u32 v12, v3, v6
42; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
43; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
44; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v1, v7, vcc
45; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
46; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v10, vcc
47; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v0, vcc
48; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
49; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v1, v8, vcc
50; GCN-NEXT:    v_add_i32_e64 v2, s[0:1], v2, v6
51; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v3, v7, s[0:1]
52; GCN-NEXT:    v_mul_hi_u32 v8, s8, v2
53; GCN-NEXT:    v_mul_lo_u32 v9, s9, v2
54; GCN-NEXT:    v_mul_lo_u32 v10, s8, v2
55; GCN-NEXT:    v_mul_lo_u32 v11, s8, v6
56; GCN-NEXT:    v_mul_hi_u32 v12, v6, v10
57; GCN-NEXT:    v_mul_lo_u32 v13, v6, v10
58; GCN-NEXT:    v_mul_hi_u32 v10, v2, v10
59; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
60; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
61; GCN-NEXT:    v_mul_hi_u32 v9, v6, v8
62; GCN-NEXT:    v_mul_hi_u32 v11, v2, v8
63; GCN-NEXT:    v_mul_lo_u32 v14, v2, v8
64; GCN-NEXT:    v_mul_lo_u32 v6, v6, v8
65; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v14
66; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v1, v11, vcc
67; GCN-NEXT:    v_add_i32_e32 v8, vcc, v13, v8
68; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v12, vcc
69; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v9, v0, vcc
70; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
71; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
72; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v1, v9, vcc
73; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v7, s[0:1]
74; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
75; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
76; GCN-NEXT:    v_mul_hi_u32 v6, s10, v2
77; GCN-NEXT:    v_mul_hi_u32 v7, s11, v2
78; GCN-NEXT:    v_mul_lo_u32 v2, s11, v2
79; GCN-NEXT:    v_mul_hi_u32 v8, s10, v3
80; GCN-NEXT:    v_mul_lo_u32 v9, s10, v3
81; GCN-NEXT:    v_mul_hi_u32 v10, s11, v3
82; GCN-NEXT:    v_mul_lo_u32 v3, s11, v3
83; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
84; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v1, v8, vcc
85; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
86; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v8, v7, vcc
87; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v10, v0, vcc
88; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
89; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v1, v0, vcc
90; GCN-NEXT:    v_mul_hi_u32 v1, s2, v2
91; GCN-NEXT:    v_mul_lo_u32 v3, s3, v2
92; GCN-NEXT:    v_mul_lo_u32 v6, s2, v2
93; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
94; GCN-NEXT:    v_add_i32_e32 v8, vcc, 2, v2
95; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v0, vcc
96; GCN-NEXT:    v_add_i32_e32 v10, vcc, 1, v2
97; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v0, vcc
98; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v7
99; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
100; GCN-NEXT:    v_sub_i32_e32 v3, vcc, s11, v1
101; GCN-NEXT:    v_sub_i32_e32 v6, vcc, s10, v6
102; GCN-NEXT:    v_subb_u32_e64 v3, s[0:1], v3, v4, vcc
103; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s2, v6
104; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
105; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v6
106; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
107; GCN-NEXT:    v_subbrev_u32_e64 v3, vcc, 0, v3, s[0:1]
108; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v4
109; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
110; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
111; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
112; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s3, v3
113; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
114; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v1
115; GCN-NEXT:    v_cndmask_b32_e32 v1, v6, v5, vcc
116; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v3
117; GCN-NEXT:    v_cndmask_b32_e32 v3, v7, v4, vcc
118; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
119; GCN-NEXT:    v_cndmask_b32_e32 v3, v11, v9, vcc
120; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v1
121; GCN-NEXT:    v_cndmask_b32_e64 v1, v0, v3, s[0:1]
122; GCN-NEXT:    v_cndmask_b32_e32 v0, v10, v8, vcc
123; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, v0, s[0:1]
124; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
125; GCN-NEXT:    s_endpgm
126  %result = udiv i64 %x, %y
127  store i64 %result, i64 addrspace(1)* %out
128  ret void
129}
130
131define i64 @v_test_udiv_i64(i64 %x, i64 %y) {
132; GCN-LABEL: v_test_udiv_i64:
133; GCN:       ; %bb.0:
134; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
135; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v2
136; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v3
137; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v2
138; GCN-NEXT:    v_subb_u32_e32 v7, vcc, 0, v3, vcc
139; GCN-NEXT:    v_mov_b32_e32 v8, 0
140; GCN-NEXT:    v_mov_b32_e32 v9, 0
141; GCN-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
142; GCN-NEXT:    v_rcp_f32_e32 v4, v4
143; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
144; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
145; GCN-NEXT:    v_trunc_f32_e32 v5, v5
146; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
147; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
148; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
149; GCN-NEXT:    v_mul_lo_u32 v10, v6, v5
150; GCN-NEXT:    v_mul_lo_u32 v11, v7, v4
151; GCN-NEXT:    v_mul_hi_u32 v12, v6, v4
152; GCN-NEXT:    v_mul_lo_u32 v13, v6, v4
153; GCN-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
154; GCN-NEXT:    v_mul_hi_u32 v12, v4, v13
155; GCN-NEXT:    v_mul_hi_u32 v14, v5, v13
156; GCN-NEXT:    v_mul_lo_u32 v13, v5, v13
157; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
158; GCN-NEXT:    v_mul_hi_u32 v11, v4, v10
159; GCN-NEXT:    v_mul_lo_u32 v15, v4, v10
160; GCN-NEXT:    v_mul_hi_u32 v16, v5, v10
161; GCN-NEXT:    v_mul_lo_u32 v10, v5, v10
162; GCN-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
163; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v9, v11, vcc
164; GCN-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
165; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v11, v14, vcc
166; GCN-NEXT:    v_addc_u32_e32 v12, vcc, v16, v8, vcc
167; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
168; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v9, v12, vcc
169; GCN-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v10
170; GCN-NEXT:    v_addc_u32_e64 v10, vcc, v5, v11, s[4:5]
171; GCN-NEXT:    v_mul_hi_u32 v12, v6, v4
172; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
173; GCN-NEXT:    v_mul_lo_u32 v13, v6, v4
174; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v11
175; GCN-NEXT:    v_mul_lo_u32 v6, v6, v10
176; GCN-NEXT:    v_mul_hi_u32 v11, v10, v13
177; GCN-NEXT:    v_mul_lo_u32 v14, v10, v13
178; GCN-NEXT:    v_mul_hi_u32 v13, v4, v13
179; GCN-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
180; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
181; GCN-NEXT:    v_mul_hi_u32 v7, v10, v6
182; GCN-NEXT:    v_mul_hi_u32 v12, v4, v6
183; GCN-NEXT:    v_mul_lo_u32 v15, v4, v6
184; GCN-NEXT:    v_mul_lo_u32 v6, v10, v6
185; GCN-NEXT:    v_add_i32_e32 v10, vcc, v13, v15
186; GCN-NEXT:    v_addc_u32_e32 v12, vcc, v9, v12, vcc
187; GCN-NEXT:    v_add_i32_e32 v10, vcc, v14, v10
188; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v12, v11, vcc
189; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v8, vcc
190; GCN-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
191; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v7, vcc
192; GCN-NEXT:    v_addc_u32_e64 v5, vcc, v5, v7, s[4:5]
193; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
194; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
195; GCN-NEXT:    v_mul_hi_u32 v6, v0, v4
196; GCN-NEXT:    v_mul_hi_u32 v7, v1, v4
197; GCN-NEXT:    v_mul_lo_u32 v4, v1, v4
198; GCN-NEXT:    v_mul_hi_u32 v10, v0, v5
199; GCN-NEXT:    v_mul_lo_u32 v11, v0, v5
200; GCN-NEXT:    v_mul_hi_u32 v12, v1, v5
201; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
202; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
203; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v9, v10, vcc
204; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
205; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v10, v7, vcc
206; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v12, v8, vcc
207; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
208; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v6, vcc
209; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
210; GCN-NEXT:    v_mul_lo_u32 v7, v3, v4
211; GCN-NEXT:    v_mul_lo_u32 v8, v2, v4
212; GCN-NEXT:    v_mul_lo_u32 v9, v2, v5
213; GCN-NEXT:    v_add_i32_e32 v10, vcc, 2, v4
214; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v5, vcc
215; GCN-NEXT:    v_add_i32_e32 v12, vcc, 1, v4
216; GCN-NEXT:    v_addc_u32_e32 v13, vcc, 0, v5, vcc
217; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
218; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
219; GCN-NEXT:    v_sub_i32_e32 v7, vcc, v1, v6
220; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
221; GCN-NEXT:    v_subb_u32_e64 v7, s[4:5], v7, v3, vcc
222; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v0, v2
223; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
224; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
225; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
226; GCN-NEXT:    v_subbrev_u32_e64 v6, vcc, 0, v7, s[4:5]
227; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v8, v2
228; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
229; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
230; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
231; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v6, v3
232; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
233; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
234; GCN-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
235; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v6, v3
236; GCN-NEXT:    v_cndmask_b32_e32 v1, v8, v2, vcc
237; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
238; GCN-NEXT:    v_cndmask_b32_e32 v1, v12, v10, vcc
239; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v0
240; GCN-NEXT:    v_cndmask_b32_e64 v0, v4, v1, s[4:5]
241; GCN-NEXT:    v_cndmask_b32_e32 v1, v13, v11, vcc
242; GCN-NEXT:    v_cndmask_b32_e64 v1, v5, v1, s[4:5]
243; GCN-NEXT:    s_setpc_b64 s[30:31]
244  %result = udiv i64 %x, %y
245  ret i64 %result
246}
247
248define amdgpu_kernel void @s_test_udiv24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
249; GCN-LABEL: s_test_udiv24_64:
250; GCN:       ; %bb.0:
251; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
252; GCN-NEXT:    s_load_dword s2, s[0:1], 0xe
253; GCN-NEXT:    s_mov_b32 s11, 0xf000
254; GCN-NEXT:    s_mov_b32 s10, -1
255; GCN-NEXT:    s_waitcnt lgkmcnt(0)
256; GCN-NEXT:    s_mov_b32 s8, s4
257; GCN-NEXT:    s_mov_b32 s9, s5
258; GCN-NEXT:    s_lshr_b32 s3, s7, 8
259; GCN-NEXT:    s_lshr_b32 s2, s2, 8
260; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
261; GCN-NEXT:    v_rcp_iflag_f32_e32 v0, v0
262; GCN-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0
263; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
264; GCN-NEXT:    v_mul_hi_u32 v1, v0, s2
265; GCN-NEXT:    v_mul_lo_u32 v2, v0, s2
266; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 0, v2
267; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
268; GCN-NEXT:    v_cndmask_b32_e64 v1, v2, v3, s[0:1]
269; GCN-NEXT:    v_mul_hi_u32 v1, v1, v0
270; GCN-NEXT:    v_add_i32_e32 v2, vcc, v1, v0
271; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, v1, v0
272; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
273; GCN-NEXT:    v_mul_hi_u32 v0, v0, s3
274; GCN-NEXT:    v_mul_lo_u32 v1, v0, s2
275; GCN-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
276; GCN-NEXT:    v_add_i32_e32 v3, vcc, -1, v0
277; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], s3, v1
278; GCN-NEXT:    v_sub_i32_e32 v1, vcc, s3, v1
279; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v1
280; GCN-NEXT:    s_and_b64 vcc, vcc, s[0:1]
281; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
282; GCN-NEXT:    v_cndmask_b32_e64 v0, v3, v0, s[0:1]
283; GCN-NEXT:    v_mov_b32_e32 v1, 0
284; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
285; GCN-NEXT:    s_endpgm
286  %1 = lshr i64 %x, 40
287  %2 = lshr i64 %y, 40
288  %result = udiv i64 %1, %2
289  store i64 %result, i64 addrspace(1)* %out
290  ret void
291}
292
293define i64 @v_test_udiv24_i64(i64 %x, i64 %y) {
294; GCN-LABEL: v_test_udiv24_i64:
295; GCN:       ; %bb.0:
296; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
297; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
298; GCN-NEXT:    v_lshrrev_b32_e32 v1, 8, v3
299; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v1
300; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v2
301; GCN-NEXT:    v_mul_f32_e32 v2, 0x4f800000, v2
302; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
303; GCN-NEXT:    v_mul_hi_u32 v3, v2, v1
304; GCN-NEXT:    v_mul_lo_u32 v4, v2, v1
305; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v4
306; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
307; GCN-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc
308; GCN-NEXT:    v_mul_hi_u32 v3, v3, v2
309; GCN-NEXT:    v_add_i32_e64 v4, s[4:5], v2, v3
310; GCN-NEXT:    v_sub_i32_e64 v2, s[4:5], v2, v3
311; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
312; GCN-NEXT:    v_mul_hi_u32 v2, v2, v0
313; GCN-NEXT:    v_mul_lo_u32 v3, v2, v1
314; GCN-NEXT:    v_add_i32_e32 v4, vcc, 1, v2
315; GCN-NEXT:    v_add_i32_e32 v5, vcc, -1, v2
316; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v3
317; GCN-NEXT:    v_sub_i32_e64 v0, s[4:5], v0, v3
318; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v0, v1
319; GCN-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
320; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, v4, s[4:5]
321; GCN-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
322; GCN-NEXT:    v_mov_b32_e32 v1, 0
323; GCN-NEXT:    s_setpc_b64 s[30:31]
324  %1 = lshr i64 %x, 40
325  %2 = lshr i64 %y, 40
326  %result = udiv i64 %1, %2
327  ret i64 %result
328}
329
330define amdgpu_kernel void @s_test_udiv32_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
331; GCN-LABEL: s_test_udiv32_i64:
332; GCN:       ; %bb.0:
333; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
334; GCN-NEXT:    s_load_dword s2, s[0:1], 0xe
335; GCN-NEXT:    s_mov_b32 s11, 0xf000
336; GCN-NEXT:    s_mov_b32 s10, -1
337; GCN-NEXT:    s_waitcnt lgkmcnt(0)
338; GCN-NEXT:    s_mov_b32 s8, s4
339; GCN-NEXT:    s_mov_b32 s9, s5
340; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
341; GCN-NEXT:    v_rcp_iflag_f32_e32 v0, v0
342; GCN-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0
343; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
344; GCN-NEXT:    v_mul_hi_u32 v1, v0, s2
345; GCN-NEXT:    v_mul_lo_u32 v2, v0, s2
346; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 0, v2
347; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
348; GCN-NEXT:    v_cndmask_b32_e64 v1, v2, v3, s[0:1]
349; GCN-NEXT:    v_mul_hi_u32 v1, v1, v0
350; GCN-NEXT:    v_add_i32_e32 v2, vcc, v1, v0
351; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, v1, v0
352; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
353; GCN-NEXT:    v_mul_hi_u32 v0, v0, s7
354; GCN-NEXT:    v_mul_lo_u32 v1, v0, s2
355; GCN-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
356; GCN-NEXT:    v_add_i32_e32 v3, vcc, -1, v0
357; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], s7, v1
358; GCN-NEXT:    v_sub_i32_e32 v1, vcc, s7, v1
359; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v1
360; GCN-NEXT:    s_and_b64 vcc, vcc, s[0:1]
361; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
362; GCN-NEXT:    v_cndmask_b32_e64 v0, v3, v0, s[0:1]
363; GCN-NEXT:    v_mov_b32_e32 v1, 0
364; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
365; GCN-NEXT:    s_endpgm
366  %1 = lshr i64 %x, 32
367  %2 = lshr i64 %y, 32
368  %result = udiv i64 %1, %2
369  store i64 %result, i64 addrspace(1)* %out
370  ret void
371}
372
373define amdgpu_kernel void @s_test_udiv31_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
374; GCN-LABEL: s_test_udiv31_i64:
375; GCN:       ; %bb.0:
376; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
377; GCN-NEXT:    s_load_dword s2, s[0:1], 0xe
378; GCN-NEXT:    s_mov_b32 s11, 0xf000
379; GCN-NEXT:    s_mov_b32 s10, -1
380; GCN-NEXT:    s_waitcnt lgkmcnt(0)
381; GCN-NEXT:    s_mov_b32 s8, s4
382; GCN-NEXT:    s_mov_b32 s9, s5
383; GCN-NEXT:    s_lshr_b32 s3, s7, 1
384; GCN-NEXT:    s_lshr_b32 s2, s2, 1
385; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
386; GCN-NEXT:    v_rcp_iflag_f32_e32 v0, v0
387; GCN-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0
388; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
389; GCN-NEXT:    v_mul_hi_u32 v1, v0, s2
390; GCN-NEXT:    v_mul_lo_u32 v2, v0, s2
391; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 0, v2
392; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
393; GCN-NEXT:    v_cndmask_b32_e64 v1, v2, v3, s[0:1]
394; GCN-NEXT:    v_mul_hi_u32 v1, v1, v0
395; GCN-NEXT:    v_add_i32_e32 v2, vcc, v1, v0
396; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, v1, v0
397; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
398; GCN-NEXT:    v_mul_hi_u32 v0, v0, s3
399; GCN-NEXT:    v_mul_lo_u32 v1, v0, s2
400; GCN-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
401; GCN-NEXT:    v_add_i32_e32 v3, vcc, -1, v0
402; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], s3, v1
403; GCN-NEXT:    v_sub_i32_e32 v1, vcc, s3, v1
404; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v1
405; GCN-NEXT:    s_and_b64 vcc, vcc, s[0:1]
406; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
407; GCN-NEXT:    v_cndmask_b32_e64 v0, v3, v0, s[0:1]
408; GCN-NEXT:    v_mov_b32_e32 v1, 0
409; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
410; GCN-NEXT:    s_endpgm
411  %1 = lshr i64 %x, 33
412  %2 = lshr i64 %y, 33
413  %result = udiv i64 %1, %2
414  store i64 %result, i64 addrspace(1)* %out
415  ret void
416}
417
418define amdgpu_kernel void @s_test_udiv23_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
419; GCN-LABEL: s_test_udiv23_i64:
420; GCN:       ; %bb.0:
421; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
422; GCN-NEXT:    s_load_dword s8, s[0:1], 0xe
423; GCN-NEXT:    s_mov_b32 s3, 0xf000
424; GCN-NEXT:    s_mov_b32 s2, -1
425; GCN-NEXT:    v_mov_b32_e32 v1, 0
426; GCN-NEXT:    s_waitcnt lgkmcnt(0)
427; GCN-NEXT:    s_mov_b32 s0, s4
428; GCN-NEXT:    s_mov_b32 s1, s5
429; GCN-NEXT:    s_lshr_b32 s4, s7, 9
430; GCN-NEXT:    s_lshr_b32 s5, s8, 9
431; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s5
432; GCN-NEXT:    v_cvt_f32_u32_e32 v2, s4
433; GCN-NEXT:    v_rcp_iflag_f32_e32 v3, v0
434; GCN-NEXT:    v_mul_f32_e32 v3, v2, v3
435; GCN-NEXT:    v_trunc_f32_e32 v3, v3
436; GCN-NEXT:    v_mad_f32 v2, -v3, v0, v2
437; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
438; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
439; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
440; GCN-NEXT:    v_and_b32_e32 v0, 0x7fffff, v0
441; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
442; GCN-NEXT:    s_endpgm
443  %1 = lshr i64 %x, 41
444  %2 = lshr i64 %y, 41
445  %result = udiv i64 %1, %2
446  store i64 %result, i64 addrspace(1)* %out
447  ret void
448}
449
450define amdgpu_kernel void @s_test_udiv24_i48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
451; GCN-LABEL: s_test_udiv24_i48:
452; GCN:       ; %bb.0:
453; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
454; GCN-NEXT:    s_load_dword s2, s[0:1], 0xb
455; GCN-NEXT:    s_load_dword s3, s[0:1], 0xc
456; GCN-NEXT:    s_load_dword s8, s[0:1], 0xd
457; GCN-NEXT:    s_load_dword s9, s[0:1], 0xe
458; GCN-NEXT:    s_mov_b32 s7, 0xf000
459; GCN-NEXT:    s_mov_b32 s6, -1
460; GCN-NEXT:    s_mov_b32 s0, 0xffff
461; GCN-NEXT:    s_mov_b32 s10, 0xff000000
462; GCN-NEXT:    v_mov_b32_e32 v0, 0
463; GCN-NEXT:    v_mov_b32_e32 v1, 0
464; GCN-NEXT:    s_waitcnt lgkmcnt(0)
465; GCN-NEXT:    s_and_b32 s11, s3, s0
466; GCN-NEXT:    s_and_b32 s12, s2, s10
467; GCN-NEXT:    s_and_b32 s1, s9, s0
468; GCN-NEXT:    s_and_b32 s0, s8, s10
469; GCN-NEXT:    s_lshr_b64 s[2:3], s[0:1], 24
470; GCN-NEXT:    v_mov_b32_e32 v2, s0
471; GCN-NEXT:    v_alignbit_b32 v2, s1, v2, 24
472; GCN-NEXT:    v_cvt_f32_ubyte3_e32 v3, s1
473; GCN-NEXT:    v_mov_b32_e32 v4, s12
474; GCN-NEXT:    v_alignbit_b32 v4, s11, v4, 24
475; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v2
476; GCN-NEXT:    s_sub_u32 s2, 0, s2
477; GCN-NEXT:    v_mac_f32_e32 v5, 0x4f800000, v3
478; GCN-NEXT:    s_subb_u32 s3, 0, s3
479; GCN-NEXT:    v_rcp_f32_e32 v3, v5
480; GCN-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v3
481; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v3
482; GCN-NEXT:    v_trunc_f32_e32 v5, v5
483; GCN-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v5
484; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
485; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
486; GCN-NEXT:    v_mul_lo_u32 v6, s2, v5
487; GCN-NEXT:    v_mul_lo_u32 v7, s3, v3
488; GCN-NEXT:    v_mul_hi_u32 v8, s2, v3
489; GCN-NEXT:    v_mul_lo_u32 v9, s2, v3
490; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
491; GCN-NEXT:    v_mul_hi_u32 v8, v3, v9
492; GCN-NEXT:    v_mul_hi_u32 v10, v5, v9
493; GCN-NEXT:    v_mul_lo_u32 v9, v5, v9
494; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
495; GCN-NEXT:    v_mul_hi_u32 v7, v3, v6
496; GCN-NEXT:    v_mul_lo_u32 v11, v3, v6
497; GCN-NEXT:    v_mul_hi_u32 v12, v5, v6
498; GCN-NEXT:    v_mul_lo_u32 v6, v5, v6
499; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
500; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v1, v7, vcc
501; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
502; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v10, vcc
503; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v0, vcc
504; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
505; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v1, v8, vcc
506; GCN-NEXT:    v_add_i32_e64 v3, s[0:1], v3, v6
507; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v5, v7, s[0:1]
508; GCN-NEXT:    v_mul_hi_u32 v8, s2, v3
509; GCN-NEXT:    v_mul_lo_u32 v9, s3, v3
510; GCN-NEXT:    v_mul_lo_u32 v10, s2, v3
511; GCN-NEXT:    v_mul_lo_u32 v11, s2, v6
512; GCN-NEXT:    v_mul_hi_u32 v12, v6, v10
513; GCN-NEXT:    v_mul_lo_u32 v13, v6, v10
514; GCN-NEXT:    v_mul_hi_u32 v10, v3, v10
515; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
516; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
517; GCN-NEXT:    v_mul_hi_u32 v9, v6, v8
518; GCN-NEXT:    v_mul_hi_u32 v11, v3, v8
519; GCN-NEXT:    v_mul_lo_u32 v14, v3, v8
520; GCN-NEXT:    v_mul_lo_u32 v6, v6, v8
521; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v14
522; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v1, v11, vcc
523; GCN-NEXT:    v_add_i32_e32 v8, vcc, v13, v8
524; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v12, vcc
525; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v9, v0, vcc
526; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
527; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
528; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v1, v9, vcc
529; GCN-NEXT:    v_addc_u32_e64 v5, vcc, v5, v7, s[0:1]
530; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
531; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
532; GCN-NEXT:    v_mul_hi_u32 v6, v4, v3
533; GCN-NEXT:    v_mul_hi_u32 v3, 0, v3
534; GCN-NEXT:    v_mul_hi_u32 v7, v4, v5
535; GCN-NEXT:    v_mul_lo_u32 v8, v4, v5
536; GCN-NEXT:    v_mul_hi_u32 v5, 0, v5
537; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
538; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v1, v7, vcc
539; GCN-NEXT:    v_add_i32_e32 v6, vcc, 0, v6
540; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v7, v3, vcc
541; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
542; GCN-NEXT:    v_add_i32_e32 v3, vcc, 0, v3
543; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v1, v0, vcc
544; GCN-NEXT:    v_mul_hi_u32 v1, v2, v3
545; GCN-NEXT:    v_mul_lo_u32 v5, v2, v3
546; GCN-NEXT:    v_mul_lo_u32 v6, v2, v0
547; GCN-NEXT:    v_add_i32_e32 v7, vcc, 2, v3
548; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v0, vcc
549; GCN-NEXT:    v_add_i32_e32 v9, vcc, 1, v3
550; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v0, vcc
551; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v6
552; GCN-NEXT:    v_sub_i32_e32 v4, vcc, v4, v5
553; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
554; GCN-NEXT:    v_sub_i32_e32 v5, vcc, v4, v2
555; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], v4, v2
556; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]
557; GCN-NEXT:    v_subbrev_u32_e32 v6, vcc, 0, v1, vcc
558; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v2
559; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
560; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
561; GCN-NEXT:    v_cndmask_b32_e32 v1, -1, v4, vcc
562; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v6
563; GCN-NEXT:    v_cndmask_b32_e32 v2, -1, v2, vcc
564; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
565; GCN-NEXT:    v_cndmask_b32_e32 v2, v9, v7, vcc
566; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v1
567; GCN-NEXT:    v_cndmask_b32_e64 v1, v3, v2, s[0:1]
568; GCN-NEXT:    v_cndmask_b32_e32 v2, v10, v8, vcc
569; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
570; GCN-NEXT:    buffer_store_short v0, off, s[4:7], 0 offset:4
571; GCN-NEXT:    buffer_store_dword v1, off, s[4:7], 0
572; GCN-NEXT:    s_endpgm
573  %1 = lshr i48 %x, 24
574  %2 = lshr i48 %y, 24
575  %result = udiv i48 %1, %2
576  store i48 %result, i48 addrspace(1)* %out
577  ret void
578}
579
580define amdgpu_kernel void @s_test_udiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
581; GCN-LABEL: s_test_udiv_k_num_i64:
582; GCN:       ; %bb.0:
583; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
584; GCN-NEXT:    s_mov_b32 s7, 0xf000
585; GCN-NEXT:    s_mov_b32 s6, -1
586; GCN-NEXT:    v_mov_b32_e32 v0, 0
587; GCN-NEXT:    v_mov_b32_e32 v1, 0
588; GCN-NEXT:    s_waitcnt lgkmcnt(0)
589; GCN-NEXT:    s_mov_b32 s4, s0
590; GCN-NEXT:    s_mov_b32 s5, s1
591; GCN-NEXT:    v_cvt_f32_u32_e32 v2, s2
592; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s3
593; GCN-NEXT:    s_sub_u32 s8, 0, s2
594; GCN-NEXT:    v_mov_b32_e32 v4, s3
595; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
596; GCN-NEXT:    s_subb_u32 s9, 0, s3
597; GCN-NEXT:    v_rcp_f32_e32 v2, v2
598; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
599; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
600; GCN-NEXT:    v_trunc_f32_e32 v3, v3
601; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
602; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
603; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
604; GCN-NEXT:    v_mul_lo_u32 v5, s8, v3
605; GCN-NEXT:    v_mul_lo_u32 v6, s9, v2
606; GCN-NEXT:    v_mul_hi_u32 v7, s8, v2
607; GCN-NEXT:    v_mul_lo_u32 v8, s8, v2
608; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
609; GCN-NEXT:    v_mul_hi_u32 v7, v2, v8
610; GCN-NEXT:    v_mul_hi_u32 v9, v3, v8
611; GCN-NEXT:    v_mul_lo_u32 v8, v3, v8
612; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
613; GCN-NEXT:    v_mul_hi_u32 v6, v2, v5
614; GCN-NEXT:    v_mul_lo_u32 v10, v2, v5
615; GCN-NEXT:    v_mul_hi_u32 v11, v3, v5
616; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
617; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
618; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v1, v6, vcc
619; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
620; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v9, vcc
621; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v0, vcc
622; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
623; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v1, v7, vcc
624; GCN-NEXT:    v_add_i32_e64 v2, s[0:1], v2, v5
625; GCN-NEXT:    v_addc_u32_e64 v5, vcc, v3, v6, s[0:1]
626; GCN-NEXT:    v_mul_hi_u32 v7, s8, v2
627; GCN-NEXT:    v_mul_lo_u32 v8, s9, v2
628; GCN-NEXT:    v_mul_lo_u32 v9, s8, v2
629; GCN-NEXT:    v_mul_lo_u32 v10, s8, v5
630; GCN-NEXT:    v_mul_hi_u32 v11, v5, v9
631; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
632; GCN-NEXT:    v_mul_hi_u32 v9, v2, v9
633; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
634; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
635; GCN-NEXT:    v_mul_hi_u32 v8, v5, v7
636; GCN-NEXT:    v_mul_hi_u32 v10, v2, v7
637; GCN-NEXT:    v_mul_lo_u32 v13, v2, v7
638; GCN-NEXT:    v_mul_lo_u32 v5, v5, v7
639; GCN-NEXT:    v_add_i32_e32 v7, vcc, v9, v13
640; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v1, v10, vcc
641; GCN-NEXT:    v_add_i32_e32 v7, vcc, v12, v7
642; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v11, vcc
643; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v8, v0, vcc
644; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
645; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
646; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v1, v8, vcc
647; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
648; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
649; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
650; GCN-NEXT:    v_mul_hi_u32 v2, v2, 24
651; GCN-NEXT:    v_mul_hi_u32 v5, v3, 24
652; GCN-NEXT:    v_mul_lo_u32 v3, v3, 24
653; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
654; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v1, v5, vcc
655; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v0, vcc
656; GCN-NEXT:    v_mul_hi_u32 v1, s2, v2
657; GCN-NEXT:    v_mul_lo_u32 v3, s3, v2
658; GCN-NEXT:    v_mul_lo_u32 v5, s2, v2
659; GCN-NEXT:    v_mul_lo_u32 v6, s2, v0
660; GCN-NEXT:    v_add_i32_e32 v7, vcc, 2, v2
661; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v0, vcc
662; GCN-NEXT:    v_add_i32_e32 v9, vcc, 1, v2
663; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v0, vcc
664; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v6
665; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
666; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 0, v1
667; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 24, v5
668; GCN-NEXT:    v_subb_u32_e64 v3, s[0:1], v3, v4, vcc
669; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s2, v5
670; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
671; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v5
672; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
673; GCN-NEXT:    v_subbrev_u32_e64 v3, vcc, 0, v3, s[0:1]
674; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v4
675; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
676; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
677; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
678; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s3, v3
679; GCN-NEXT:    v_cndmask_b32_e64 v11, 0, -1, vcc
680; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v1
681; GCN-NEXT:    v_cndmask_b32_e32 v1, v6, v5, vcc
682; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v3
683; GCN-NEXT:    v_cndmask_b32_e32 v3, v11, v4, vcc
684; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
685; GCN-NEXT:    v_cndmask_b32_e32 v3, v10, v8, vcc
686; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v1
687; GCN-NEXT:    v_cndmask_b32_e64 v1, v0, v3, s[0:1]
688; GCN-NEXT:    v_cndmask_b32_e32 v0, v9, v7, vcc
689; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, v0, s[0:1]
690; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
691; GCN-NEXT:    s_endpgm
692  %result = udiv i64 24, %x
693  store i64 %result, i64 addrspace(1)* %out
694  ret void
695}
696
697; define i64 @v_test_udiv_k_num_i64(i64 %x) {
698;   %result = udiv i64 24, %x
699;   ret i64 %result
700; }
701
702define i64 @v_test_udiv_pow2_k_num_i64(i64 %x) {
703; GCN-LABEL: v_test_udiv_pow2_k_num_i64:
704; GCN:       ; %bb.0:
705; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
706; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
707; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
708; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
709; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
710; GCN-NEXT:    v_mov_b32_e32 v6, 0
711; GCN-NEXT:    v_mov_b32_e32 v7, 0
712; GCN-NEXT:    s_mov_b32 s6, 0x8000
713; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
714; GCN-NEXT:    v_rcp_f32_e32 v2, v2
715; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
716; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
717; GCN-NEXT:    v_trunc_f32_e32 v3, v3
718; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
719; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
720; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
721; GCN-NEXT:    v_mul_lo_u32 v8, v4, v3
722; GCN-NEXT:    v_mul_lo_u32 v9, v5, v2
723; GCN-NEXT:    v_mul_hi_u32 v10, v4, v2
724; GCN-NEXT:    v_mul_lo_u32 v11, v4, v2
725; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
726; GCN-NEXT:    v_mul_hi_u32 v10, v2, v11
727; GCN-NEXT:    v_mul_hi_u32 v12, v3, v11
728; GCN-NEXT:    v_mul_lo_u32 v11, v3, v11
729; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
730; GCN-NEXT:    v_mul_hi_u32 v9, v2, v8
731; GCN-NEXT:    v_mul_lo_u32 v13, v2, v8
732; GCN-NEXT:    v_mul_hi_u32 v14, v3, v8
733; GCN-NEXT:    v_mul_lo_u32 v8, v3, v8
734; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
735; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v7, v9, vcc
736; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
737; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v9, v12, vcc
738; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v6, vcc
739; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
740; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v7, v10, vcc
741; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v8
742; GCN-NEXT:    v_addc_u32_e64 v8, vcc, v3, v9, s[4:5]
743; GCN-NEXT:    v_mul_hi_u32 v10, v4, v2
744; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
745; GCN-NEXT:    v_mul_lo_u32 v11, v4, v2
746; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v9
747; GCN-NEXT:    v_mul_lo_u32 v4, v4, v8
748; GCN-NEXT:    v_mul_hi_u32 v9, v8, v11
749; GCN-NEXT:    v_mul_lo_u32 v12, v8, v11
750; GCN-NEXT:    v_mul_hi_u32 v11, v2, v11
751; GCN-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
752; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
753; GCN-NEXT:    v_mul_hi_u32 v5, v8, v4
754; GCN-NEXT:    v_mul_hi_u32 v10, v2, v4
755; GCN-NEXT:    v_mul_lo_u32 v13, v2, v4
756; GCN-NEXT:    v_mul_lo_u32 v4, v8, v4
757; GCN-NEXT:    v_add_i32_e32 v8, vcc, v11, v13
758; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v7, v10, vcc
759; GCN-NEXT:    v_add_i32_e32 v8, vcc, v12, v8
760; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v9, vcc
761; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v6, vcc
762; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
763; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v5, vcc
764; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
765; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
766; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
767; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
768; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
769; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
770; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
771; GCN-NEXT:    v_add_i32_e32 v6, vcc, 2, v2
772; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v7, vcc
773; GCN-NEXT:    v_add_i32_e32 v9, vcc, 1, v2
774; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
775; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
776; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s6, v5
777; GCN-NEXT:    v_sub_i32_e64 v5, s[4:5], 0, v3
778; GCN-NEXT:    v_sub_i32_e64 v10, s[4:5], v4, v0
779; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v4, v0
780; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[6:7]
781; GCN-NEXT:    v_subb_u32_e64 v5, s[6:7], v5, v1, vcc
782; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v10, v0
783; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, s[6:7]
784; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
785; GCN-NEXT:    v_subbrev_u32_e64 v5, vcc, 0, v5, s[4:5]
786; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
787; GCN-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
788; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v1
789; GCN-NEXT:    v_cndmask_b32_e64 v11, 0, -1, vcc
790; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
791; GCN-NEXT:    v_cndmask_b32_e32 v3, v10, v4, vcc
792; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v5, v1
793; GCN-NEXT:    v_cndmask_b32_e32 v0, v11, v0, vcc
794; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
795; GCN-NEXT:    v_cndmask_b32_e32 v0, v9, v6, vcc
796; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v3
797; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, v0, s[4:5]
798; GCN-NEXT:    v_cndmask_b32_e32 v1, v7, v8, vcc
799; GCN-NEXT:    v_cndmask_b32_e64 v1, 0, v1, s[4:5]
800; GCN-NEXT:    s_setpc_b64 s[30:31]
801  %result = udiv i64 32768, %x
802  ret i64 %result
803}
804
805define i64 @v_test_udiv_pow2_k_den_i64(i64 %x) {
806; GCN-LABEL: v_test_udiv_pow2_k_den_i64:
807; GCN:       ; %bb.0:
808; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
809; GCN-NEXT:    v_alignbit_b32 v0, v1, v0, 15
810; GCN-NEXT:    v_lshrrev_b32_e32 v1, 15, v1
811; GCN-NEXT:    s_setpc_b64 s[30:31]
812  %result = udiv i64 %x, 32768
813  ret i64 %result
814}
815
816define amdgpu_kernel void @s_test_udiv_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
817; GCN-LABEL: s_test_udiv_k_den_i64:
818; GCN:       ; %bb.0:
819; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
820; GCN-NEXT:    s_mov_b32 s7, 0xf000
821; GCN-NEXT:    s_mov_b32 s6, -1
822; GCN-NEXT:    v_mov_b32_e32 v0, 0x4f800000
823; GCN-NEXT:    s_movk_i32 s8, 0xffe8
824; GCN-NEXT:    v_mov_b32_e32 v1, 0
825; GCN-NEXT:    v_mov_b32_e32 v2, 0
826; GCN-NEXT:    v_madak_f32 v0, 0, v0, 0x41c00000
827; GCN-NEXT:    v_rcp_f32_e32 v0, v0
828; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
829; GCN-NEXT:    s_waitcnt lgkmcnt(0)
830; GCN-NEXT:    s_mov_b32 s4, s0
831; GCN-NEXT:    s_mov_b32 s5, s1
832; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
833; GCN-NEXT:    v_mov_b32_e32 v4, s3
834; GCN-NEXT:    v_trunc_f32_e32 v3, v3
835; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
836; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
837; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
838; GCN-NEXT:    v_mul_lo_u32 v5, v3, s8
839; GCN-NEXT:    v_mul_hi_u32 v6, v0, s8
840; GCN-NEXT:    v_mul_lo_u32 v7, v0, s8
841; GCN-NEXT:    v_subrev_i32_e32 v6, vcc, v0, v6
842; GCN-NEXT:    v_mul_hi_u32 v8, v0, v7
843; GCN-NEXT:    v_mul_hi_u32 v9, v3, v7
844; GCN-NEXT:    v_mul_lo_u32 v7, v3, v7
845; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
846; GCN-NEXT:    v_mul_hi_u32 v6, v0, v5
847; GCN-NEXT:    v_mul_lo_u32 v10, v0, v5
848; GCN-NEXT:    v_mul_hi_u32 v11, v3, v5
849; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
850; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
851; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
852; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
853; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v9, vcc
854; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v1, vcc
855; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
856; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v7, vcc
857; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v5
858; GCN-NEXT:    v_addc_u32_e64 v5, vcc, v3, v6, s[0:1]
859; GCN-NEXT:    v_mul_hi_u32 v7, v0, s8
860; GCN-NEXT:    v_mul_lo_u32 v8, v0, s8
861; GCN-NEXT:    v_mul_lo_u32 v9, v5, s8
862; GCN-NEXT:    v_subrev_i32_e32 v7, vcc, v0, v7
863; GCN-NEXT:    v_mul_hi_u32 v10, v0, v8
864; GCN-NEXT:    v_mul_hi_u32 v11, v5, v8
865; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
866; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
867; GCN-NEXT:    v_mul_hi_u32 v9, v0, v7
868; GCN-NEXT:    v_mul_lo_u32 v12, v0, v7
869; GCN-NEXT:    v_mul_hi_u32 v13, v5, v7
870; GCN-NEXT:    v_mul_lo_u32 v5, v5, v7
871; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v12
872; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v2, v9, vcc
873; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
874; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v11, vcc
875; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v1, vcc
876; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
877; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
878; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v8, vcc
879; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
880; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v5
881; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
882; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
883; GCN-NEXT:    v_mul_hi_u32 v6, s3, v0
884; GCN-NEXT:    v_mul_lo_u32 v0, s3, v0
885; GCN-NEXT:    v_mul_hi_u32 v7, s2, v3
886; GCN-NEXT:    v_mul_lo_u32 v8, s2, v3
887; GCN-NEXT:    v_mul_hi_u32 v9, s3, v3
888; GCN-NEXT:    v_mul_lo_u32 v3, s3, v3
889; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
890; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v7, vcc
891; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v5
892; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v7, v6, vcc
893; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v9, v1, vcc
894; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
895; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
896; GCN-NEXT:    v_mul_hi_u32 v2, v0, 24
897; GCN-NEXT:    v_mul_lo_u32 v3, v0, 24
898; GCN-NEXT:    v_mul_lo_u32 v5, v1, 24
899; GCN-NEXT:    v_add_i32_e32 v6, vcc, 2, v0
900; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v1, vcc
901; GCN-NEXT:    v_add_i32_e32 v8, vcc, 1, v0
902; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v1, vcc
903; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
904; GCN-NEXT:    v_sub_i32_e32 v3, vcc, s2, v3
905; GCN-NEXT:    v_subb_u32_e32 v2, vcc, v4, v2, vcc
906; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, 24, v3
907; GCN-NEXT:    v_cmp_lt_u32_e64 s[0:1], 23, v3
908; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, s[0:1]
909; GCN-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
910; GCN-NEXT:    v_cmp_lt_u32_e32 vcc, 23, v4
911; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
912; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v2
913; GCN-NEXT:    v_cndmask_b32_e32 v2, -1, v3, vcc
914; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v5
915; GCN-NEXT:    v_cndmask_b32_e32 v3, -1, v4, vcc
916; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
917; GCN-NEXT:    v_cndmask_b32_e32 v3, v9, v7, vcc
918; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v2
919; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
920; GCN-NEXT:    v_cndmask_b32_e32 v2, v8, v6, vcc
921; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
922; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
923; GCN-NEXT:    s_endpgm
924  %result = udiv i64 %x, 24
925  store i64 %result, i64 addrspace(1)* %out
926  ret void
927}
928
929define i64 @v_test_udiv_k_den_i64(i64 %x) {
930; GCN-LABEL: v_test_udiv_k_den_i64:
931; GCN:       ; %bb.0:
932; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
933; GCN-NEXT:    v_mov_b32_e32 v2, 0x4f800000
934; GCN-NEXT:    s_movk_i32 s6, 0xffe8
935; GCN-NEXT:    v_mov_b32_e32 v3, 0
936; GCN-NEXT:    v_mov_b32_e32 v4, 0
937; GCN-NEXT:    v_madak_f32 v2, 0, v2, 0x41c00000
938; GCN-NEXT:    v_rcp_f32_e32 v2, v2
939; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
940; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v2
941; GCN-NEXT:    v_trunc_f32_e32 v5, v5
942; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v5
943; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
944; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
945; GCN-NEXT:    v_mul_lo_u32 v6, v5, s6
946; GCN-NEXT:    v_mul_hi_u32 v7, v2, s6
947; GCN-NEXT:    v_mul_lo_u32 v8, v2, s6
948; GCN-NEXT:    v_subrev_i32_e32 v7, vcc, v2, v7
949; GCN-NEXT:    v_mul_hi_u32 v9, v2, v8
950; GCN-NEXT:    v_mul_hi_u32 v10, v5, v8
951; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
952; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
953; GCN-NEXT:    v_mul_hi_u32 v7, v2, v6
954; GCN-NEXT:    v_mul_lo_u32 v11, v2, v6
955; GCN-NEXT:    v_mul_hi_u32 v12, v5, v6
956; GCN-NEXT:    v_mul_lo_u32 v6, v5, v6
957; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
958; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v4, v7, vcc
959; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
960; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v10, vcc
961; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v3, vcc
962; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
963; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v4, v8, vcc
964; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v6
965; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v5, v7, s[4:5]
966; GCN-NEXT:    v_mul_hi_u32 v8, v2, s6
967; GCN-NEXT:    v_mul_lo_u32 v9, v2, s6
968; GCN-NEXT:    v_mul_lo_u32 v10, v6, s6
969; GCN-NEXT:    v_subrev_i32_e32 v8, vcc, v2, v8
970; GCN-NEXT:    v_mul_hi_u32 v11, v2, v9
971; GCN-NEXT:    v_mul_hi_u32 v12, v6, v9
972; GCN-NEXT:    v_mul_lo_u32 v9, v6, v9
973; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
974; GCN-NEXT:    v_mul_hi_u32 v10, v2, v8
975; GCN-NEXT:    v_mul_lo_u32 v13, v2, v8
976; GCN-NEXT:    v_mul_hi_u32 v14, v6, v8
977; GCN-NEXT:    v_mul_lo_u32 v6, v6, v8
978; GCN-NEXT:    v_add_i32_e32 v8, vcc, v11, v13
979; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v4, v10, vcc
980; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
981; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v12, vcc
982; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v3, vcc
983; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
984; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
985; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v4, v9, vcc
986; GCN-NEXT:    v_addc_u32_e64 v5, vcc, v5, v7, s[4:5]
987; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
988; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
989; GCN-NEXT:    v_mul_hi_u32 v6, v0, v2
990; GCN-NEXT:    v_mul_hi_u32 v7, v1, v2
991; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
992; GCN-NEXT:    v_mul_hi_u32 v8, v0, v5
993; GCN-NEXT:    v_mul_lo_u32 v9, v0, v5
994; GCN-NEXT:    v_mul_hi_u32 v10, v1, v5
995; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
996; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
997; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v4, v8, vcc
998; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
999; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v8, v7, vcc
1000; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v10, v3, vcc
1001; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
1002; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v4, v3, vcc
1003; GCN-NEXT:    v_mul_hi_u32 v4, v2, 24
1004; GCN-NEXT:    v_mul_lo_u32 v5, v2, 24
1005; GCN-NEXT:    v_mul_lo_u32 v6, v3, 24
1006; GCN-NEXT:    v_add_i32_e32 v7, vcc, 2, v2
1007; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v3, vcc
1008; GCN-NEXT:    v_add_i32_e32 v9, vcc, 1, v2
1009; GCN-NEXT:    v_addc_u32_e32 v10, vcc, 0, v3, vcc
1010; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
1011; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v5
1012; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc
1013; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, 24, v0
1014; GCN-NEXT:    v_cmp_lt_u32_e64 s[4:5], 23, v0
1015; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, s[4:5]
1016; GCN-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v1, vcc
1017; GCN-NEXT:    v_cmp_lt_u32_e32 vcc, 23, v4
1018; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
1019; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
1020; GCN-NEXT:    v_cndmask_b32_e32 v0, -1, v0, vcc
1021; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v5
1022; GCN-NEXT:    v_cndmask_b32_e32 v1, -1, v4, vcc
1023; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
1024; GCN-NEXT:    v_cndmask_b32_e32 v1, v9, v7, vcc
1025; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v0
1026; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, v1, s[4:5]
1027; GCN-NEXT:    v_cndmask_b32_e32 v1, v10, v8, vcc
1028; GCN-NEXT:    v_cndmask_b32_e64 v1, v3, v1, s[4:5]
1029; GCN-NEXT:    s_setpc_b64 s[30:31]
1030  %result = udiv i64 %x, 24
1031  ret i64 %result
1032}
1033
1034define amdgpu_kernel void @s_test_udiv24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1035; GCN-LABEL: s_test_udiv24_k_num_i64:
1036; GCN:       ; %bb.0:
1037; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1038; GCN-NEXT:    s_mov_b32 s7, 0xf000
1039; GCN-NEXT:    s_mov_b32 s6, -1
1040; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1041; GCN-NEXT:    s_mov_b32 s4, s0
1042; GCN-NEXT:    s_mov_b32 s5, s1
1043; GCN-NEXT:    s_lshr_b32 s2, s3, 8
1044; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
1045; GCN-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1046; GCN-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0
1047; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
1048; GCN-NEXT:    v_mul_hi_u32 v1, v0, s2
1049; GCN-NEXT:    v_mul_lo_u32 v2, v0, s2
1050; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 0, v2
1051; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
1052; GCN-NEXT:    v_cndmask_b32_e64 v1, v2, v3, s[0:1]
1053; GCN-NEXT:    v_mul_hi_u32 v1, v1, v0
1054; GCN-NEXT:    v_add_i32_e32 v2, vcc, v1, v0
1055; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, v1, v0
1056; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
1057; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
1058; GCN-NEXT:    v_mul_lo_u32 v1, v0, s2
1059; GCN-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
1060; GCN-NEXT:    v_add_i32_e32 v3, vcc, -1, v0
1061; GCN-NEXT:    v_cmp_gt_u32_e64 s[0:1], 25, v1
1062; GCN-NEXT:    v_sub_i32_e32 v1, vcc, 24, v1
1063; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v1
1064; GCN-NEXT:    s_and_b64 vcc, vcc, s[0:1]
1065; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1066; GCN-NEXT:    v_cndmask_b32_e64 v0, v3, v0, s[0:1]
1067; GCN-NEXT:    v_mov_b32_e32 v1, 0
1068; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1069; GCN-NEXT:    s_endpgm
1070  %x.shr = lshr i64 %x, 40
1071  %result = udiv i64 24, %x.shr
1072  store i64 %result, i64 addrspace(1)* %out
1073  ret void
1074}
1075
1076define amdgpu_kernel void @s_test_udiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
1077; GCN-LABEL: s_test_udiv24_k_den_i64:
1078; GCN:       ; %bb.0:
1079; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1080; GCN-NEXT:    s_mov_b32 s7, 0xf000
1081; GCN-NEXT:    s_mov_b32 s6, -1
1082; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1083; GCN-NEXT:    s_movk_i32 s2, 0x5b7f
1084; GCN-NEXT:    s_movk_i32 s8, 0x5b7e
1085; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
1086; GCN-NEXT:    v_rcp_iflag_f32_e32 v0, v0
1087; GCN-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0
1088; GCN-NEXT:    s_mov_b32 s4, s0
1089; GCN-NEXT:    s_mov_b32 s5, s1
1090; GCN-NEXT:    s_lshr_b32 s3, s3, 8
1091; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
1092; GCN-NEXT:    v_mul_hi_u32 v1, v0, s2
1093; GCN-NEXT:    v_mul_lo_u32 v2, v0, s2
1094; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 0, v2
1095; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
1096; GCN-NEXT:    v_cndmask_b32_e64 v1, v2, v3, s[0:1]
1097; GCN-NEXT:    v_mul_hi_u32 v1, v1, v0
1098; GCN-NEXT:    v_add_i32_e32 v2, vcc, v1, v0
1099; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, v1, v0
1100; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
1101; GCN-NEXT:    v_mul_hi_u32 v0, v0, s3
1102; GCN-NEXT:    v_mul_lo_u32 v1, v0, s2
1103; GCN-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
1104; GCN-NEXT:    v_add_i32_e32 v3, vcc, -1, v0
1105; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], s3, v1
1106; GCN-NEXT:    v_sub_i32_e32 v1, vcc, s3, v1
1107; GCN-NEXT:    v_cmp_lt_u32_e32 vcc, s8, v1
1108; GCN-NEXT:    s_and_b64 vcc, vcc, s[0:1]
1109; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1110; GCN-NEXT:    v_cndmask_b32_e64 v0, v3, v0, s[0:1]
1111; GCN-NEXT:    v_mov_b32_e32 v1, 0
1112; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1113; GCN-NEXT:    s_endpgm
1114  %x.shr = lshr i64 %x, 40
1115  %result = udiv i64 %x.shr, 23423
1116  store i64 %result, i64 addrspace(1)* %out
1117  ret void
1118}
1119
1120define i64 @v_test_udiv24_k_num_i64(i64 %x) {
1121; GCN-LABEL: v_test_udiv24_k_num_i64:
1122; GCN:       ; %bb.0:
1123; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1124; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1125; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v0
1126; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1127; GCN-NEXT:    v_mul_f32_e32 v1, 0x4f800000, v1
1128; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
1129; GCN-NEXT:    v_mul_hi_u32 v2, v1, v0
1130; GCN-NEXT:    v_mul_lo_u32 v3, v1, v0
1131; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
1132; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v2
1133; GCN-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc
1134; GCN-NEXT:    v_mul_hi_u32 v2, v2, v1
1135; GCN-NEXT:    v_add_i32_e64 v3, s[4:5], v1, v2
1136; GCN-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v2
1137; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
1138; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
1139; GCN-NEXT:    v_mul_lo_u32 v2, v1, v0
1140; GCN-NEXT:    v_add_i32_e32 v3, vcc, 1, v1
1141; GCN-NEXT:    v_add_i32_e32 v4, vcc, -1, v1
1142; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, 25, v2
1143; GCN-NEXT:    v_sub_i32_e64 v2, s[4:5], 24, v2
1144; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v0
1145; GCN-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1146; GCN-NEXT:    v_cndmask_b32_e64 v0, v1, v3, s[4:5]
1147; GCN-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
1148; GCN-NEXT:    v_mov_b32_e32 v1, 0
1149; GCN-NEXT:    s_setpc_b64 s[30:31]
1150  %x.shr = lshr i64 %x, 40
1151  %result = udiv i64 24, %x.shr
1152  ret i64 %result
1153}
1154
1155define i64 @v_test_udiv24_pow2_k_num_i64(i64 %x) {
1156; GCN-LABEL: v_test_udiv24_pow2_k_num_i64:
1157; GCN:       ; %bb.0:
1158; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1159; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1160; GCN-NEXT:    s_mov_b32 s6, 0x8001
1161; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v0
1162; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v1
1163; GCN-NEXT:    v_mul_f32_e32 v1, 0x4f800000, v1
1164; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
1165; GCN-NEXT:    v_mul_hi_u32 v2, v1, v0
1166; GCN-NEXT:    v_mul_lo_u32 v3, v1, v0
1167; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
1168; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v2
1169; GCN-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc
1170; GCN-NEXT:    v_mul_hi_u32 v2, v2, v1
1171; GCN-NEXT:    v_add_i32_e64 v3, s[4:5], v1, v2
1172; GCN-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v2
1173; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
1174; GCN-NEXT:    v_lshrrev_b32_e32 v1, 17, v1
1175; GCN-NEXT:    v_mul_u32_u24_e32 v2, v1, v0
1176; GCN-NEXT:    v_add_i32_e32 v3, vcc, 1, v1
1177; GCN-NEXT:    v_add_i32_e32 v4, vcc, -1, v1
1178; GCN-NEXT:    v_cmp_gt_u32_e64 s[4:5], s6, v2
1179; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0x8000, v2
1180; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v0
1181; GCN-NEXT:    s_and_b64 vcc, vcc, s[4:5]
1182; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v3, vcc
1183; GCN-NEXT:    v_cndmask_b32_e64 v0, v4, v0, s[4:5]
1184; GCN-NEXT:    v_mov_b32_e32 v1, 0
1185; GCN-NEXT:    s_setpc_b64 s[30:31]
1186  %x.shr = lshr i64 %x, 40
1187  %result = udiv i64 32768, %x.shr
1188  ret i64 %result
1189}
1190
1191define i64 @v_test_udiv24_pow2_k_den_i64(i64 %x) {
1192; GCN-LABEL: v_test_udiv24_pow2_k_den_i64:
1193; GCN:       ; %bb.0:
1194; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1195; GCN-NEXT:    v_lshrrev_b32_e32 v0, 23, v1
1196; GCN-NEXT:    v_mov_b32_e32 v1, 0
1197; GCN-NEXT:    s_setpc_b64 s[30:31]
1198  %x.shr = lshr i64 %x, 40
1199  %result = udiv i64 %x.shr, 32768
1200  ret i64 %result
1201}
1202