1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_udiv_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_udiv_i64:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
9; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
10; GCN-NEXT:    s_mov_b32 s7, 0xf000
11; GCN-NEXT:    s_mov_b32 s6, -1
12; GCN-NEXT:    s_waitcnt lgkmcnt(0)
13; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
14; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
15; GCN-NEXT:    s_sub_u32 s2, 0, s12
16; GCN-NEXT:    s_subb_u32 s3, 0, s13
17; GCN-NEXT:    s_mov_b32 s4, s8
18; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
19; GCN-NEXT:    v_rcp_f32_e32 v0, v0
20; GCN-NEXT:    s_mov_b32 s5, s9
21; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
22; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
23; GCN-NEXT:    v_trunc_f32_e32 v1, v1
24; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
25; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
26; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
27; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
28; GCN-NEXT:    v_mul_lo_u32 v2, s2, v1
29; GCN-NEXT:    v_mul_lo_u32 v5, s3, v0
30; GCN-NEXT:    v_mul_lo_u32 v4, s2, v0
31; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
32; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
33; GCN-NEXT:    v_mul_hi_u32 v3, v0, v4
34; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
35; GCN-NEXT:    v_mul_hi_u32 v7, v0, v2
36; GCN-NEXT:    v_mul_hi_u32 v6, v1, v4
37; GCN-NEXT:    v_mul_lo_u32 v4, v1, v4
38; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
39; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
40; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
41; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
42; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
43; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v6, vcc
44; GCN-NEXT:    v_mov_b32_e32 v4, 0
45; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v4, vcc
46; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
47; GCN-NEXT:    v_mov_b32_e32 v6, 0
48; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
49; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v6, v5, vcc
50; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
51; GCN-NEXT:    v_mul_lo_u32 v5, s2, v2
52; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
53; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
54; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
55; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
56; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
57; GCN-NEXT:    v_mul_lo_u32 v10, v0, v5
58; GCN-NEXT:    v_mul_hi_u32 v12, v0, v5
59; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
60; GCN-NEXT:    v_mul_hi_u32 v9, v2, v7
61; GCN-NEXT:    v_mul_lo_u32 v7, v2, v7
62; GCN-NEXT:    v_mul_hi_u32 v8, v2, v5
63; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
64; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
65; GCN-NEXT:    v_mul_lo_u32 v2, v2, v5
66; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
67; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
68; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v4, vcc
69; GCN-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
70; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v6, v5, vcc
71; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
72; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[0:1]
73; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
74; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
75; GCN-NEXT:    v_mul_lo_u32 v2, s10, v1
76; GCN-NEXT:    v_mul_hi_u32 v3, s10, v0
77; GCN-NEXT:    v_mul_hi_u32 v5, s10, v1
78; GCN-NEXT:    v_mul_hi_u32 v7, s11, v1
79; GCN-NEXT:    v_mul_lo_u32 v1, s11, v1
80; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
81; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
82; GCN-NEXT:    v_mul_lo_u32 v5, s11, v0
83; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
84; GCN-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
85; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
86; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v7, v4, vcc
87; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
88; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
89; GCN-NEXT:    v_mul_lo_u32 v2, s12, v1
90; GCN-NEXT:    v_mul_hi_u32 v3, s12, v0
91; GCN-NEXT:    v_mul_lo_u32 v4, s13, v0
92; GCN-NEXT:    v_mov_b32_e32 v5, s13
93; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
94; GCN-NEXT:    v_mul_lo_u32 v3, s12, v0
95; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
96; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s11, v2
97; GCN-NEXT:    v_sub_i32_e64 v3, s[0:1], s10, v3
98; GCN-NEXT:    v_subb_u32_e64 v4, vcc, v4, v5, s[0:1]
99; GCN-NEXT:    v_subrev_i32_e32 v5, vcc, s12, v3
100; GCN-NEXT:    v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
101; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v4
102; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
103; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v5
104; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
105; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v4
106; GCN-NEXT:    v_cndmask_b32_e32 v4, v6, v5, vcc
107; GCN-NEXT:    v_add_i32_e32 v5, vcc, 2, v0
108; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
109; GCN-NEXT:    v_add_i32_e32 v7, vcc, 1, v0
110; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v1, vcc
111; GCN-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v4
112; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[2:3]
113; GCN-NEXT:    v_mov_b32_e32 v6, s11
114; GCN-NEXT:    v_subb_u32_e64 v2, vcc, v6, v2, s[0:1]
115; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v2
116; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
117; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v3
118; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
119; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v2
120; GCN-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
121; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
122; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[2:3]
123; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
124; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
125; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
126; GCN-NEXT:    s_endpgm
127;
128; GCN-IR-LABEL: s_test_udiv_i64:
129; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
130; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
131; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
132; GCN-IR-NEXT:    s_mov_b64 s[2:3], 0
133; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
134; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
135; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[0:1], 0
136; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s0
137; GCN-IR-NEXT:    s_or_b64 s[14:15], s[8:9], s[10:11]
138; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
139; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s1
140; GCN-IR-NEXT:    s_cmp_eq_u32 s1, 0
141; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s6
142; GCN-IR-NEXT:    s_cselect_b32 s8, s12, s8
143; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
144; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s7
145; GCN-IR-NEXT:    s_cmp_eq_u32 s7, 0
146; GCN-IR-NEXT:    s_cselect_b32 s12, s10, s11
147; GCN-IR-NEXT:    s_sub_u32 s10, s8, s12
148; GCN-IR-NEXT:    s_subb_u32 s11, 0, 0
149; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[16:17], s[10:11], 63
150; GCN-IR-NEXT:    s_mov_b32 s9, 0
151; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[16:17]
152; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[16:17], s[10:11], 63
153; GCN-IR-NEXT:    s_xor_b64 s[18:19], s[14:15], -1
154; GCN-IR-NEXT:    s_and_b64 s[16:17], s[18:19], s[16:17]
155; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[16:17]
156; GCN-IR-NEXT:    s_cbranch_vccz BB0_5
157; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
158; GCN-IR-NEXT:    s_add_u32 s14, s10, 1
159; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
160; GCN-IR-NEXT:    s_addc_u32 s15, s11, 0
161; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
162; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[14:15], v[0:1]
163; GCN-IR-NEXT:    s_sub_i32 s10, 63, s10
164; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
165; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[6:7], s10
166; GCN-IR-NEXT:    s_cbranch_vccz BB0_4
167; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
168; GCN-IR-NEXT:    s_lshr_b64 s[14:15], s[6:7], s14
169; GCN-IR-NEXT:    s_add_u32 s6, s0, -1
170; GCN-IR-NEXT:    s_addc_u32 s7, s1, -1
171; GCN-IR-NEXT:    s_not_b64 s[2:3], s[8:9]
172; GCN-IR-NEXT:    s_mov_b32 s13, s9
173; GCN-IR-NEXT:    s_add_u32 s8, s2, s12
174; GCN-IR-NEXT:    s_addc_u32 s9, s3, s9
175; GCN-IR-NEXT:    s_mov_b64 s[12:13], 0
176; GCN-IR-NEXT:    s_mov_b32 s3, 0
177; GCN-IR-NEXT:  BB0_3: ; %udiv-do-while
178; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
179; GCN-IR-NEXT:    s_lshr_b32 s2, s11, 31
180; GCN-IR-NEXT:    s_lshl_b64 s[14:15], s[14:15], 1
181; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
182; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[2:3]
183; GCN-IR-NEXT:    s_or_b64 s[10:11], s[12:13], s[10:11]
184; GCN-IR-NEXT:    s_sub_u32 s2, s6, s14
185; GCN-IR-NEXT:    s_subb_u32 s2, s7, s15
186; GCN-IR-NEXT:    s_ashr_i32 s12, s2, 31
187; GCN-IR-NEXT:    s_mov_b32 s13, s12
188; GCN-IR-NEXT:    s_and_b32 s2, s12, 1
189; GCN-IR-NEXT:    s_and_b64 s[16:17], s[12:13], s[0:1]
190; GCN-IR-NEXT:    s_sub_u32 s14, s14, s16
191; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
192; GCN-IR-NEXT:    s_subb_u32 s15, s15, s17
193; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
194; GCN-IR-NEXT:    s_add_u32 s8, s8, 1
195; GCN-IR-NEXT:    s_addc_u32 s9, s9, 0
196; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
197; GCN-IR-NEXT:    s_mov_b64 s[12:13], s[2:3]
198; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
199; GCN-IR-NEXT:    s_cbranch_vccz BB0_3
200; GCN-IR-NEXT:  BB0_4: ; %Flow6
201; GCN-IR-NEXT:    s_lshl_b64 s[0:1], s[10:11], 1
202; GCN-IR-NEXT:    s_or_b64 s[0:1], s[2:3], s[0:1]
203; GCN-IR-NEXT:    v_mov_b32_e32 v0, s0
204; GCN-IR-NEXT:    v_mov_b32_e32 v1, s1
205; GCN-IR-NEXT:    s_branch BB0_6
206; GCN-IR-NEXT:  BB0_5:
207; GCN-IR-NEXT:    v_mov_b32_e32 v0, s7
208; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[14:15]
209; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
210; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[14:15]
211; GCN-IR-NEXT:  BB0_6: ; %udiv-end
212; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
213; GCN-IR-NEXT:    s_mov_b32 s6, -1
214; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
215; GCN-IR-NEXT:    s_endpgm
216  %result = udiv i64 %x, %y
217  store i64 %result, i64 addrspace(1)* %out
218  ret void
219}
220
221define i64 @v_test_udiv_i64(i64 %x, i64 %y) {
222; GCN-LABEL: v_test_udiv_i64:
223; GCN:       ; %bb.0:
224; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
225; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v2
226; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v3
227; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v2
228; GCN-NEXT:    v_subb_u32_e32 v7, vcc, 0, v3, vcc
229; GCN-NEXT:    v_mov_b32_e32 v14, 0
230; GCN-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
231; GCN-NEXT:    v_rcp_f32_e32 v4, v4
232; GCN-NEXT:    v_mov_b32_e32 v13, 0
233; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
234; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
235; GCN-NEXT:    v_trunc_f32_e32 v5, v5
236; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
237; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
238; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
239; GCN-NEXT:    v_mul_hi_u32 v8, v6, v4
240; GCN-NEXT:    v_mul_lo_u32 v9, v6, v5
241; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
242; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
243; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
244; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
245; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
246; GCN-NEXT:    v_mul_hi_u32 v10, v4, v8
247; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
248; GCN-NEXT:    v_mul_hi_u32 v15, v5, v8
249; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
250; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
251; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
252; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
253; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v10, vcc
254; GCN-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
255; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v10, v9, vcc
256; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v15, v13, vcc
257; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
258; GCN-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v8
259; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v10, vcc
260; GCN-NEXT:    v_addc_u32_e64 v8, vcc, v5, v9, s[4:5]
261; GCN-NEXT:    v_mul_lo_u32 v10, v6, v8
262; GCN-NEXT:    v_mul_hi_u32 v11, v6, v4
263; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
264; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
265; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
266; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
267; GCN-NEXT:    v_mul_lo_u32 v12, v4, v7
268; GCN-NEXT:    v_mul_hi_u32 v15, v4, v6
269; GCN-NEXT:    v_mul_hi_u32 v16, v4, v7
270; GCN-NEXT:    v_mul_hi_u32 v11, v8, v6
271; GCN-NEXT:    v_mul_lo_u32 v6, v8, v6
272; GCN-NEXT:    v_add_i32_e32 v12, vcc, v15, v12
273; GCN-NEXT:    v_mul_hi_u32 v10, v8, v7
274; GCN-NEXT:    v_addc_u32_e32 v15, vcc, v14, v16, vcc
275; GCN-NEXT:    v_mul_lo_u32 v7, v8, v7
276; GCN-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
277; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v15, v11, vcc
278; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v13, vcc
279; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
280; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v14, v8, vcc
281; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
282; GCN-NEXT:    v_addc_u32_e64 v5, vcc, v5, v7, s[4:5]
283; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
284; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
285; GCN-NEXT:    v_mul_lo_u32 v6, v0, v5
286; GCN-NEXT:    v_mul_hi_u32 v7, v0, v4
287; GCN-NEXT:    v_mul_hi_u32 v8, v0, v5
288; GCN-NEXT:    v_mul_hi_u32 v9, v1, v5
289; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
290; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
291; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v14, v8, vcc
292; GCN-NEXT:    v_mul_lo_u32 v8, v1, v4
293; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
294; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
295; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v4, vcc
296; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v13, vcc
297; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
298; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v14, v6, vcc
299; GCN-NEXT:    v_mul_lo_u32 v6, v2, v5
300; GCN-NEXT:    v_mul_hi_u32 v7, v2, v4
301; GCN-NEXT:    v_mul_lo_u32 v8, v3, v4
302; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
303; GCN-NEXT:    v_mul_lo_u32 v7, v2, v4
304; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
305; GCN-NEXT:    v_sub_i32_e32 v8, vcc, v1, v6
306; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v7
307; GCN-NEXT:    v_subb_u32_e64 v7, s[4:5], v8, v3, vcc
308; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v0, v2
309; GCN-NEXT:    v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5]
310; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v3
311; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
312; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v2
313; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
314; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v3
315; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
316; GCN-NEXT:    v_cndmask_b32_e64 v7, v9, v8, s[4:5]
317; GCN-NEXT:    v_add_i32_e64 v8, s[4:5], 2, v4
318; GCN-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, v5, s[4:5]
319; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
320; GCN-NEXT:    v_add_i32_e64 v10, s[4:5], 1, v4
321; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
322; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
323; GCN-NEXT:    v_addc_u32_e64 v11, s[4:5], 0, v5, s[4:5]
324; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
325; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
326; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
327; GCN-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
328; GCN-NEXT:    v_cndmask_b32_e64 v7, v10, v8, s[4:5]
329; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
330; GCN-NEXT:    v_cndmask_b32_e64 v1, v11, v9, s[4:5]
331; GCN-NEXT:    v_cndmask_b32_e32 v0, v4, v7, vcc
332; GCN-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
333; GCN-NEXT:    s_setpc_b64 s[30:31]
334;
335; GCN-IR-LABEL: v_test_udiv_i64:
336; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
337; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
338; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[2:3]
339; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
340; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v2
341; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
342; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
343; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v3
344; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
345; GCN-IR-NEXT:    v_cndmask_b32_e32 v8, v5, v4, vcc
346; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
347; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
348; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
349; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
350; GCN-IR-NEXT:    v_cndmask_b32_e32 v10, v5, v4, vcc
351; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v8, v10
352; GCN-IR-NEXT:    v_subb_u32_e64 v7, s[6:7], 0, 0, vcc
353; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[6:7]
354; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
355; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
356; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[6:7]
357; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
358; GCN-IR-NEXT:    v_mov_b32_e32 v11, v9
359; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v1, 0, s[4:5]
360; GCN-IR-NEXT:    v_cndmask_b32_e64 v5, v0, 0, s[4:5]
361; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
362; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
363; GCN-IR-NEXT:    s_cbranch_execz BB1_6
364; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
365; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v6
366; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v7, vcc
367; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v6
368; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[12:13], v[6:7]
369; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
370; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[0:1], v4
371; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
372; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
373; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
374; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
375; GCN-IR-NEXT:    s_cbranch_execz BB1_5
376; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
377; GCN-IR-NEXT:    v_lshr_b64 v[12:13], v[0:1], v12
378; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, -1, v2
379; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, -1, v3, vcc
380; GCN-IR-NEXT:    v_not_b32_e32 v6, v8
381; GCN-IR-NEXT:    v_not_b32_e32 v7, v9
382; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, v6, v10
383; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, v7, v11, vcc
384; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
385; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
386; GCN-IR-NEXT:  BB1_3: ; %udiv-do-while
387; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
388; GCN-IR-NEXT:    v_lshl_b64 v[12:13], v[12:13], 1
389; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
390; GCN-IR-NEXT:    v_or_b32_e32 v12, v12, v6
391; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
392; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v0, v12
393; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v1, v13, vcc
394; GCN-IR-NEXT:    v_or_b32_e32 v4, v10, v4
395; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v6
396; GCN-IR-NEXT:    v_and_b32_e32 v15, v10, v2
397; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v10
398; GCN-IR-NEXT:    v_and_b32_e32 v14, v10, v3
399; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v8
400; GCN-IR-NEXT:    v_or_b32_e32 v5, v11, v5
401; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v9, vcc
402; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[10:11], v[8:9]
403; GCN-IR-NEXT:    v_mov_b32_e32 v8, v10
404; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
405; GCN-IR-NEXT:    v_sub_i32_e64 v12, s[4:5], v12, v15
406; GCN-IR-NEXT:    v_mov_b32_e32 v9, v11
407; GCN-IR-NEXT:    v_mov_b32_e32 v11, v7
408; GCN-IR-NEXT:    v_subb_u32_e64 v13, s[4:5], v13, v14, s[4:5]
409; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
410; GCN-IR-NEXT:    v_mov_b32_e32 v10, v6
411; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
412; GCN-IR-NEXT:    s_cbranch_execnz BB1_3
413; GCN-IR-NEXT:  ; %bb.4: ; %Flow
414; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
415; GCN-IR-NEXT:  BB1_5: ; %Flow3
416; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
417; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[4:5], 1
418; GCN-IR-NEXT:    v_or_b32_e32 v4, v7, v1
419; GCN-IR-NEXT:    v_or_b32_e32 v5, v6, v0
420; GCN-IR-NEXT:  BB1_6: ; %Flow4
421; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
422; GCN-IR-NEXT:    v_mov_b32_e32 v0, v5
423; GCN-IR-NEXT:    v_mov_b32_e32 v1, v4
424; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
425  %result = udiv i64 %x, %y
426  ret i64 %result
427}
428
429define amdgpu_kernel void @s_test_udiv24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
430; GCN-LABEL: s_test_udiv24_64:
431; GCN:       ; %bb.0:
432; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
433; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
434; GCN-NEXT:    s_mov_b32 s3, 0xf000
435; GCN-NEXT:    s_mov_b32 s2, -1
436; GCN-NEXT:    s_waitcnt lgkmcnt(0)
437; GCN-NEXT:    s_mov_b32 s1, s5
438; GCN-NEXT:    s_lshr_b32 s0, s0, 8
439; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
440; GCN-NEXT:    s_lshr_b32 s0, s7, 8
441; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s0
442; GCN-NEXT:    s_mov_b32 s0, s4
443; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
444; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
445; GCN-NEXT:    v_trunc_f32_e32 v2, v2
446; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
447; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
448; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
449; GCN-NEXT:    v_mov_b32_e32 v1, 0
450; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
451; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
452; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
453; GCN-NEXT:    s_endpgm
454;
455; GCN-IR-LABEL: s_test_udiv24_64:
456; GCN-IR:       ; %bb.0:
457; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
458; GCN-IR-NEXT:    s_load_dword s0, s[0:1], 0xe
459; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
460; GCN-IR-NEXT:    s_mov_b32 s2, -1
461; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
462; GCN-IR-NEXT:    s_mov_b32 s1, s5
463; GCN-IR-NEXT:    s_lshr_b32 s0, s0, 8
464; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
465; GCN-IR-NEXT:    s_lshr_b32 s0, s7, 8
466; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s0
467; GCN-IR-NEXT:    s_mov_b32 s0, s4
468; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
469; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
470; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
471; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
472; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
473; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
474; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
475; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
476; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
477; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
478; GCN-IR-NEXT:    s_endpgm
479  %1 = lshr i64 %x, 40
480  %2 = lshr i64 %y, 40
481  %result = udiv i64 %1, %2
482  store i64 %result, i64 addrspace(1)* %out
483  ret void
484}
485
486define i64 @v_test_udiv24_i64(i64 %x, i64 %y) {
487; GCN-LABEL: v_test_udiv24_i64:
488; GCN:       ; %bb.0:
489; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
490; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v3
491; GCN-NEXT:    v_cvt_f32_u32_e32 v0, v0
492; GCN-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
493; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v1
494; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
495; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
496; GCN-NEXT:    v_trunc_f32_e32 v2, v2
497; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
498; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
499; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
500; GCN-NEXT:    v_mov_b32_e32 v1, 0
501; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
502; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
503; GCN-NEXT:    s_setpc_b64 s[30:31]
504;
505; GCN-IR-LABEL: v_test_udiv24_i64:
506; GCN-IR:       ; %bb.0:
507; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
508; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v3
509; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, v0
510; GCN-IR-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
511; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, v1
512; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
513; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
514; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
515; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
516; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
517; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
518; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
519; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
520; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
521; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
522  %1 = lshr i64 %x, 40
523  %2 = lshr i64 %y, 40
524  %result = udiv i64 %1, %2
525  ret i64 %result
526}
527
528define amdgpu_kernel void @s_test_udiv32_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
529; GCN-LABEL: s_test_udiv32_i64:
530; GCN:       ; %bb.0:
531; GCN-NEXT:    s_load_dword s2, s[0:1], 0xe
532; GCN-NEXT:    s_mov_b32 s7, 0xf000
533; GCN-NEXT:    s_mov_b32 s6, -1
534; GCN-NEXT:    s_waitcnt lgkmcnt(0)
535; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
536; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
537; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
538; GCN-NEXT:    s_waitcnt lgkmcnt(0)
539; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s3
540; GCN-NEXT:    s_mov_b32 s4, s0
541; GCN-NEXT:    s_mov_b32 s5, s1
542; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
543; GCN-NEXT:    v_trunc_f32_e32 v2, v2
544; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
545; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
546; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
547; GCN-NEXT:    v_mov_b32_e32 v1, 0
548; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
549; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
550; GCN-NEXT:    s_endpgm
551;
552; GCN-IR-LABEL: s_test_udiv32_i64:
553; GCN-IR:       ; %bb.0:
554; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xe
555; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
556; GCN-IR-NEXT:    s_mov_b32 s6, -1
557; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
558; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
559; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
560; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
561; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
562; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s3
563; GCN-IR-NEXT:    s_mov_b32 s4, s0
564; GCN-IR-NEXT:    s_mov_b32 s5, s1
565; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
566; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
567; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
568; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
569; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
570; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
571; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
572; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
573; GCN-IR-NEXT:    s_endpgm
574  %1 = lshr i64 %x, 32
575  %2 = lshr i64 %y, 32
576  %result = udiv i64 %1, %2
577  store i64 %result, i64 addrspace(1)* %out
578  ret void
579}
580
581define amdgpu_kernel void @s_test_udiv31_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
582; GCN-LABEL: s_test_udiv31_i64:
583; GCN:       ; %bb.0:
584; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
585; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
586; GCN-NEXT:    s_mov_b32 s3, 0xf000
587; GCN-NEXT:    s_mov_b32 s2, -1
588; GCN-NEXT:    s_waitcnt lgkmcnt(0)
589; GCN-NEXT:    s_mov_b32 s1, s5
590; GCN-NEXT:    s_lshr_b32 s0, s0, 1
591; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
592; GCN-NEXT:    s_lshr_b32 s0, s7, 1
593; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s0
594; GCN-NEXT:    s_mov_b32 s0, s4
595; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
596; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
597; GCN-NEXT:    v_trunc_f32_e32 v2, v2
598; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
599; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
600; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
601; GCN-NEXT:    v_mov_b32_e32 v1, 0
602; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
603; GCN-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
604; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
605; GCN-NEXT:    s_endpgm
606;
607; GCN-IR-LABEL: s_test_udiv31_i64:
608; GCN-IR:       ; %bb.0:
609; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
610; GCN-IR-NEXT:    s_load_dword s0, s[0:1], 0xe
611; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
612; GCN-IR-NEXT:    s_mov_b32 s2, -1
613; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
614; GCN-IR-NEXT:    s_mov_b32 s1, s5
615; GCN-IR-NEXT:    s_lshr_b32 s0, s0, 1
616; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
617; GCN-IR-NEXT:    s_lshr_b32 s0, s7, 1
618; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s0
619; GCN-IR-NEXT:    s_mov_b32 s0, s4
620; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
621; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
622; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
623; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
624; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
625; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
626; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
627; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
628; GCN-IR-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
629; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
630; GCN-IR-NEXT:    s_endpgm
631  %1 = lshr i64 %x, 33
632  %2 = lshr i64 %y, 33
633  %result = udiv i64 %1, %2
634  store i64 %result, i64 addrspace(1)* %out
635  ret void
636}
637
638define amdgpu_kernel void @s_test_udiv23_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
639; GCN-LABEL: s_test_udiv23_i64:
640; GCN:       ; %bb.0:
641; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
642; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
643; GCN-NEXT:    s_mov_b32 s3, 0xf000
644; GCN-NEXT:    s_mov_b32 s2, -1
645; GCN-NEXT:    s_waitcnt lgkmcnt(0)
646; GCN-NEXT:    s_mov_b32 s1, s5
647; GCN-NEXT:    s_lshr_b32 s0, s0, 9
648; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
649; GCN-NEXT:    s_lshr_b32 s0, s7, 9
650; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s0
651; GCN-NEXT:    s_mov_b32 s0, s4
652; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
653; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
654; GCN-NEXT:    v_trunc_f32_e32 v2, v2
655; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
656; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
657; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
658; GCN-NEXT:    v_mov_b32_e32 v1, 0
659; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
660; GCN-NEXT:    v_and_b32_e32 v0, 0x7fffff, v0
661; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
662; GCN-NEXT:    s_endpgm
663;
664; GCN-IR-LABEL: s_test_udiv23_i64:
665; GCN-IR:       ; %bb.0:
666; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
667; GCN-IR-NEXT:    s_load_dword s0, s[0:1], 0xe
668; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
669; GCN-IR-NEXT:    s_mov_b32 s2, -1
670; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
671; GCN-IR-NEXT:    s_mov_b32 s1, s5
672; GCN-IR-NEXT:    s_lshr_b32 s0, s0, 9
673; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
674; GCN-IR-NEXT:    s_lshr_b32 s0, s7, 9
675; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s0
676; GCN-IR-NEXT:    s_mov_b32 s0, s4
677; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
678; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
679; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
680; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
681; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
682; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
683; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
684; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
685; GCN-IR-NEXT:    v_and_b32_e32 v0, 0x7fffff, v0
686; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
687; GCN-IR-NEXT:    s_endpgm
688  %1 = lshr i64 %x, 41
689  %2 = lshr i64 %y, 41
690  %result = udiv i64 %1, %2
691  store i64 %result, i64 addrspace(1)* %out
692  ret void
693}
694
695define amdgpu_kernel void @s_test_udiv24_i48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
696; GCN-LABEL: s_test_udiv24_i48:
697; GCN:       ; %bb.0:
698; GCN-NEXT:    s_load_dword s2, s[0:1], 0xd
699; GCN-NEXT:    s_load_dword s3, s[0:1], 0xe
700; GCN-NEXT:    s_mov_b32 s5, 0xff000000
701; GCN-NEXT:    s_mov_b32 s4, 0xffff
702; GCN-NEXT:    v_cvt_f32_ubyte3_e32 v2, s4
703; GCN-NEXT:    s_waitcnt lgkmcnt(0)
704; GCN-NEXT:    s_and_b32 s2, s2, s5
705; GCN-NEXT:    s_and_b32 s3, s3, s4
706; GCN-NEXT:    v_mov_b32_e32 v0, s2
707; GCN-NEXT:    v_alignbit_b32 v0, s3, v0, 24
708; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v0
709; GCN-NEXT:    s_load_dword s6, s[0:1], 0xb
710; GCN-NEXT:    s_load_dword s7, s[0:1], 0xc
711; GCN-NEXT:    s_lshr_b64 s[2:3], s[2:3], 24
712; GCN-NEXT:    v_mov_b32_e32 v9, 0
713; GCN-NEXT:    v_mac_f32_e32 v1, 0x4f800000, v2
714; GCN-NEXT:    v_rcp_f32_e32 v1, v1
715; GCN-NEXT:    s_waitcnt lgkmcnt(0)
716; GCN-NEXT:    s_and_b32 s7, s7, s4
717; GCN-NEXT:    s_and_b32 s6, s6, s5
718; GCN-NEXT:    s_sub_u32 s8, 0, s2
719; GCN-NEXT:    v_mul_f32_e32 v1, 0x5f7ffffc, v1
720; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v1
721; GCN-NEXT:    v_trunc_f32_e32 v2, v2
722; GCN-NEXT:    v_mac_f32_e32 v1, 0xcf800000, v2
723; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
724; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
725; GCN-NEXT:    s_subb_u32 s9, 0, s3
726; GCN-NEXT:    v_mov_b32_e32 v8, 0
727; GCN-NEXT:    v_mul_lo_u32 v3, s8, v2
728; GCN-NEXT:    v_mul_hi_u32 v4, s8, v1
729; GCN-NEXT:    v_mul_lo_u32 v5, s9, v1
730; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
731; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
732; GCN-NEXT:    v_mul_lo_u32 v4, s8, v1
733; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
734; GCN-NEXT:    v_mul_lo_u32 v6, v1, v3
735; GCN-NEXT:    v_mul_hi_u32 v5, v1, v3
736; GCN-NEXT:    v_mul_hi_u32 v7, v1, v4
737; GCN-NEXT:    v_mul_hi_u32 v10, v2, v3
738; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
739; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
740; GCN-NEXT:    v_mul_lo_u32 v7, v2, v4
741; GCN-NEXT:    v_mul_hi_u32 v4, v2, v4
742; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
743; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
744; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v5, v4, vcc
745; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v10, v8, vcc
746; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
747; GCN-NEXT:    v_add_i32_e64 v1, s[2:3], v1, v3
748; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v5, vcc
749; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v2, v4, s[2:3]
750; GCN-NEXT:    v_mul_lo_u32 v5, s8, v3
751; GCN-NEXT:    v_mul_hi_u32 v6, s8, v1
752; GCN-NEXT:    v_mul_lo_u32 v7, s9, v1
753; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
754; GCN-NEXT:    v_mul_lo_u32 v6, s8, v1
755; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
756; GCN-NEXT:    v_mul_lo_u32 v11, v1, v5
757; GCN-NEXT:    v_mul_hi_u32 v13, v1, v5
758; GCN-NEXT:    v_mul_hi_u32 v12, v1, v6
759; GCN-NEXT:    v_mul_hi_u32 v10, v3, v6
760; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
761; GCN-NEXT:    v_mul_hi_u32 v7, v3, v5
762; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
763; GCN-NEXT:    v_addc_u32_e32 v12, vcc, v9, v13, vcc
764; GCN-NEXT:    v_mul_lo_u32 v3, v3, v5
765; GCN-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
766; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v12, v10, vcc
767; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
768; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
769; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
770; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
771; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v5, s[2:3]
772; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
773; GCN-NEXT:    v_mov_b32_e32 v3, s6
774; GCN-NEXT:    v_alignbit_b32 v3, s7, v3, 24
775; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
776; GCN-NEXT:    v_mul_hi_u32 v5, v3, v1
777; GCN-NEXT:    v_mul_lo_u32 v4, v3, v2
778; GCN-NEXT:    v_mul_hi_u32 v6, v3, v2
779; GCN-NEXT:    v_mul_hi_u32 v1, 0, v1
780; GCN-NEXT:    v_mul_hi_u32 v2, 0, v2
781; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
782; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v6, vcc
783; GCN-NEXT:    v_add_i32_e32 v4, vcc, 0, v4
784; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v5, v1, vcc
785; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v8, vcc
786; GCN-NEXT:    v_add_i32_e32 v1, vcc, 0, v1
787; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v9, v2, vcc
788; GCN-NEXT:    v_mul_lo_u32 v4, v0, v2
789; GCN-NEXT:    v_mul_hi_u32 v5, v0, v1
790; GCN-NEXT:    v_mul_lo_u32 v6, v0, v1
791; GCN-NEXT:    s_mov_b32 s7, 0xf000
792; GCN-NEXT:    s_mov_b32 s6, -1
793; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
794; GCN-NEXT:    v_sub_i32_e32 v3, vcc, v3, v6
795; GCN-NEXT:    v_subb_u32_e32 v4, vcc, 0, v4, vcc
796; GCN-NEXT:    v_sub_i32_e32 v5, vcc, v3, v0
797; GCN-NEXT:    v_subbrev_u32_e32 v6, vcc, 0, v4, vcc
798; GCN-NEXT:    v_cmp_le_u32_e32 vcc, v0, v5
799; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
800; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v6
801; GCN-NEXT:    v_cndmask_b32_e32 v5, -1, v5, vcc
802; GCN-NEXT:    v_add_i32_e32 v6, vcc, 2, v1
803; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v2, vcc
804; GCN-NEXT:    v_add_i32_e32 v8, vcc, 1, v1
805; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v2, vcc
806; GCN-NEXT:    v_cmp_le_u32_e32 vcc, v0, v3
807; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
808; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v4
809; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v5
810; GCN-NEXT:    v_cndmask_b32_e32 v0, -1, v0, vcc
811; GCN-NEXT:    v_cndmask_b32_e64 v5, v8, v6, s[0:1]
812; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
813; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v5, vcc
814; GCN-NEXT:    v_cndmask_b32_e64 v1, v9, v7, s[0:1]
815; GCN-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
816; GCN-NEXT:    s_waitcnt lgkmcnt(0)
817; GCN-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
818; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
819; GCN-NEXT:    s_endpgm
820;
821; GCN-IR-LABEL: s_test_udiv24_i48:
822; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
823; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
824; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xb
825; GCN-IR-NEXT:    s_load_dword s3, s[0:1], 0xc
826; GCN-IR-NEXT:    s_load_dword s6, s[0:1], 0xd
827; GCN-IR-NEXT:    s_load_dword s7, s[0:1], 0xe
828; GCN-IR-NEXT:    s_mov_b32 s8, 0xffff
829; GCN-IR-NEXT:    s_mov_b32 s9, 0xff000000
830; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
831; GCN-IR-NEXT:    s_and_b32 s1, s3, s8
832; GCN-IR-NEXT:    s_and_b32 s0, s2, s9
833; GCN-IR-NEXT:    s_and_b32 s3, s7, s8
834; GCN-IR-NEXT:    s_and_b32 s2, s6, s9
835; GCN-IR-NEXT:    s_lshr_b64 s[6:7], s[0:1], 24
836; GCN-IR-NEXT:    s_lshr_b64 s[2:3], s[2:3], 24
837; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[2:3], 0
838; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
839; GCN-IR-NEXT:    s_mov_b64 s[0:1], 0
840; GCN-IR-NEXT:    s_or_b64 s[14:15], s[8:9], s[10:11]
841; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s2
842; GCN-IR-NEXT:    s_add_i32 s8, s8, 32
843; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s3
844; GCN-IR-NEXT:    s_cmp_eq_u32 s3, 0
845; GCN-IR-NEXT:    s_cselect_b32 s8, s8, s10
846; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s6
847; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
848; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s7
849; GCN-IR-NEXT:    s_cmp_eq_u32 s7, 0
850; GCN-IR-NEXT:    s_cselect_b32 s12, s10, s11
851; GCN-IR-NEXT:    s_sub_u32 s10, s8, s12
852; GCN-IR-NEXT:    s_subb_u32 s11, 0, 0
853; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[16:17], s[10:11], 63
854; GCN-IR-NEXT:    s_mov_b32 s9, 0
855; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[16:17]
856; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[16:17], s[10:11], 63
857; GCN-IR-NEXT:    s_xor_b64 s[18:19], s[14:15], -1
858; GCN-IR-NEXT:    s_and_b64 s[16:17], s[18:19], s[16:17]
859; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[16:17]
860; GCN-IR-NEXT:    s_cbranch_vccz BB7_5
861; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
862; GCN-IR-NEXT:    s_add_u32 s14, s10, 1
863; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
864; GCN-IR-NEXT:    s_addc_u32 s15, s11, 0
865; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
866; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[14:15], v[0:1]
867; GCN-IR-NEXT:    s_sub_i32 s10, 63, s10
868; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
869; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[6:7], s10
870; GCN-IR-NEXT:    s_cbranch_vccz BB7_4
871; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
872; GCN-IR-NEXT:    s_lshr_b64 s[14:15], s[6:7], s14
873; GCN-IR-NEXT:    s_add_u32 s6, s2, -1
874; GCN-IR-NEXT:    s_addc_u32 s7, s3, -1
875; GCN-IR-NEXT:    s_not_b64 s[0:1], s[8:9]
876; GCN-IR-NEXT:    s_mov_b32 s13, s9
877; GCN-IR-NEXT:    s_add_u32 s8, s0, s12
878; GCN-IR-NEXT:    s_addc_u32 s9, s1, s9
879; GCN-IR-NEXT:    s_mov_b64 s[12:13], 0
880; GCN-IR-NEXT:    s_mov_b32 s1, 0
881; GCN-IR-NEXT:  BB7_3: ; %udiv-do-while
882; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
883; GCN-IR-NEXT:    s_lshr_b32 s0, s11, 31
884; GCN-IR-NEXT:    s_lshl_b64 s[14:15], s[14:15], 1
885; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
886; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[0:1]
887; GCN-IR-NEXT:    s_or_b64 s[10:11], s[12:13], s[10:11]
888; GCN-IR-NEXT:    s_sub_u32 s0, s6, s14
889; GCN-IR-NEXT:    s_subb_u32 s0, s7, s15
890; GCN-IR-NEXT:    s_ashr_i32 s12, s0, 31
891; GCN-IR-NEXT:    s_mov_b32 s13, s12
892; GCN-IR-NEXT:    s_and_b32 s0, s12, 1
893; GCN-IR-NEXT:    s_and_b64 s[16:17], s[12:13], s[2:3]
894; GCN-IR-NEXT:    s_sub_u32 s14, s14, s16
895; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
896; GCN-IR-NEXT:    s_subb_u32 s15, s15, s17
897; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
898; GCN-IR-NEXT:    s_add_u32 s8, s8, 1
899; GCN-IR-NEXT:    s_addc_u32 s9, s9, 0
900; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
901; GCN-IR-NEXT:    s_mov_b64 s[12:13], s[0:1]
902; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
903; GCN-IR-NEXT:    s_cbranch_vccz BB7_3
904; GCN-IR-NEXT:  BB7_4: ; %Flow3
905; GCN-IR-NEXT:    s_lshl_b64 s[2:3], s[10:11], 1
906; GCN-IR-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
907; GCN-IR-NEXT:    v_mov_b32_e32 v0, s0
908; GCN-IR-NEXT:    v_mov_b32_e32 v1, s1
909; GCN-IR-NEXT:    s_branch BB7_6
910; GCN-IR-NEXT:  BB7_5:
911; GCN-IR-NEXT:    v_mov_b32_e32 v0, s7
912; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[14:15]
913; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
914; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[14:15]
915; GCN-IR-NEXT:  BB7_6: ; %udiv-end
916; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
917; GCN-IR-NEXT:    s_mov_b32 s6, -1
918; GCN-IR-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
919; GCN-IR-NEXT:    buffer_store_dword v0, off, s[4:7], 0
920; GCN-IR-NEXT:    s_endpgm
921  %1 = lshr i48 %x, 24
922  %2 = lshr i48 %y, 24
923  %result = udiv i48 %1, %2
924  store i48 %result, i48 addrspace(1)* %out
925  ret void
926}
927
928define amdgpu_kernel void @s_test_udiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
929; GCN-LABEL: s_test_udiv_k_num_i64:
930; GCN:       ; %bb.0:
931; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
932; GCN-NEXT:    v_mov_b32_e32 v2, 0
933; GCN-NEXT:    s_mov_b32 s11, 0xf000
934; GCN-NEXT:    s_mov_b32 s10, -1
935; GCN-NEXT:    s_waitcnt lgkmcnt(0)
936; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s6
937; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s7
938; GCN-NEXT:    s_sub_u32 s2, 0, s6
939; GCN-NEXT:    s_subb_u32 s3, 0, s7
940; GCN-NEXT:    s_mov_b32 s8, s4
941; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
942; GCN-NEXT:    v_rcp_f32_e32 v0, v0
943; GCN-NEXT:    v_mov_b32_e32 v1, 0
944; GCN-NEXT:    s_mov_b32 s9, s5
945; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
946; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
947; GCN-NEXT:    v_trunc_f32_e32 v3, v3
948; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
949; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
950; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
951; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
952; GCN-NEXT:    v_mul_lo_u32 v4, s2, v3
953; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
954; GCN-NEXT:    v_mul_lo_u32 v6, s2, v0
955; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
956; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
957; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
958; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
959; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
960; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
961; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
962; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
963; GCN-NEXT:    v_mul_hi_u32 v10, v3, v4
964; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
965; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
966; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
967; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
968; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
969; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
970; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
971; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
972; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
973; GCN-NEXT:    v_mul_lo_u32 v6, s2, v4
974; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
975; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
976; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
977; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
978; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
979; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
980; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
981; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
982; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
983; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
984; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
985; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
986; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
987; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
988; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
989; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
990; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v1, vcc
991; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
992; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
993; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
994; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
995; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
996; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
997; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
998; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
999; GCN-NEXT:    v_mul_hi_u32 v3, v3, 24
1000; GCN-NEXT:    v_mov_b32_e32 v5, s7
1001; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
1002; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v2, v3, vcc
1003; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1004; GCN-NEXT:    v_mul_lo_u32 v2, s6, v1
1005; GCN-NEXT:    v_mul_hi_u32 v3, s6, v0
1006; GCN-NEXT:    v_mul_lo_u32 v4, s7, v0
1007; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1008; GCN-NEXT:    v_mul_lo_u32 v3, s6, v0
1009; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1010; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v2
1011; GCN-NEXT:    v_sub_i32_e64 v3, s[0:1], 24, v3
1012; GCN-NEXT:    v_subb_u32_e64 v4, vcc, v4, v5, s[0:1]
1013; GCN-NEXT:    v_subrev_i32_e32 v5, vcc, s6, v3
1014; GCN-NEXT:    v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
1015; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s7, v4
1016; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1017; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s6, v5
1018; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
1019; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s7, v4
1020; GCN-NEXT:    v_cndmask_b32_e32 v4, v6, v5, vcc
1021; GCN-NEXT:    v_add_i32_e32 v5, vcc, 2, v0
1022; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
1023; GCN-NEXT:    v_add_i32_e32 v7, vcc, 1, v0
1024; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v1, vcc
1025; GCN-NEXT:    v_subb_u32_e64 v2, vcc, 0, v2, s[0:1]
1026; GCN-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v4
1027; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s7, v2
1028; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[2:3]
1029; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1030; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s6, v3
1031; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
1032; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s7, v2
1033; GCN-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
1034; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
1035; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[2:3]
1036; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
1037; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1038; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
1039; GCN-NEXT:    s_endpgm
1040;
1041; GCN-IR-LABEL: s_test_udiv_k_num_i64:
1042; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1043; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1044; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1045; GCN-IR-NEXT:    s_flbit_i32_b32 s4, s2
1046; GCN-IR-NEXT:    s_add_i32 s4, s4, 32
1047; GCN-IR-NEXT:    s_flbit_i32_b32 s5, s3
1048; GCN-IR-NEXT:    s_cmp_eq_u32 s3, 0
1049; GCN-IR-NEXT:    s_cselect_b32 s8, s4, s5
1050; GCN-IR-NEXT:    s_add_u32 s6, s8, 0xffffffc5
1051; GCN-IR-NEXT:    s_addc_u32 s7, 0, -1
1052; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
1053; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[12:13], s[6:7], 63
1054; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0
1055; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
1056; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[12:13], s[6:7], 63
1057; GCN-IR-NEXT:    s_xor_b64 s[14:15], s[10:11], -1
1058; GCN-IR-NEXT:    s_and_b64 s[12:13], s[14:15], s[12:13]
1059; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
1060; GCN-IR-NEXT:    s_cbranch_vccz BB8_5
1061; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1062; GCN-IR-NEXT:    s_add_u32 s12, s6, 1
1063; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1064; GCN-IR-NEXT:    s_addc_u32 s13, s7, 0
1065; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
1066; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[12:13], v[0:1]
1067; GCN-IR-NEXT:    s_sub_i32 s6, 63, s6
1068; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1069; GCN-IR-NEXT:    s_lshl_b64 s[10:11], 24, s6
1070; GCN-IR-NEXT:    s_cbranch_vccz BB8_4
1071; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1072; GCN-IR-NEXT:    s_lshr_b64 s[14:15], 24, s12
1073; GCN-IR-NEXT:    s_add_u32 s6, s2, -1
1074; GCN-IR-NEXT:    s_addc_u32 s7, s3, -1
1075; GCN-IR-NEXT:    s_sub_u32 s8, 58, s8
1076; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
1077; GCN-IR-NEXT:    s_mov_b64 s[12:13], 0
1078; GCN-IR-NEXT:    s_mov_b32 s5, 0
1079; GCN-IR-NEXT:  BB8_3: ; %udiv-do-while
1080; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1081; GCN-IR-NEXT:    s_lshr_b32 s4, s11, 31
1082; GCN-IR-NEXT:    s_lshl_b64 s[14:15], s[14:15], 1
1083; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
1084; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[4:5]
1085; GCN-IR-NEXT:    s_or_b64 s[10:11], s[12:13], s[10:11]
1086; GCN-IR-NEXT:    s_sub_u32 s4, s6, s14
1087; GCN-IR-NEXT:    s_subb_u32 s4, s7, s15
1088; GCN-IR-NEXT:    s_ashr_i32 s12, s4, 31
1089; GCN-IR-NEXT:    s_mov_b32 s13, s12
1090; GCN-IR-NEXT:    s_and_b32 s4, s12, 1
1091; GCN-IR-NEXT:    s_and_b64 s[16:17], s[12:13], s[2:3]
1092; GCN-IR-NEXT:    s_sub_u32 s14, s14, s16
1093; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
1094; GCN-IR-NEXT:    s_subb_u32 s15, s15, s17
1095; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
1096; GCN-IR-NEXT:    s_add_u32 s8, s8, 1
1097; GCN-IR-NEXT:    s_addc_u32 s9, s9, 0
1098; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
1099; GCN-IR-NEXT:    s_mov_b64 s[12:13], s[4:5]
1100; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1101; GCN-IR-NEXT:    s_cbranch_vccz BB8_3
1102; GCN-IR-NEXT:  BB8_4: ; %Flow5
1103; GCN-IR-NEXT:    s_lshl_b64 s[2:3], s[10:11], 1
1104; GCN-IR-NEXT:    s_or_b64 s[2:3], s[4:5], s[2:3]
1105; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1106; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
1107; GCN-IR-NEXT:    s_branch BB8_6
1108; GCN-IR-NEXT:  BB8_5:
1109; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1110; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, 24, 0, s[10:11]
1111; GCN-IR-NEXT:  BB8_6: ; %udiv-end
1112; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1113; GCN-IR-NEXT:    s_mov_b32 s2, -1
1114; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1115; GCN-IR-NEXT:    s_endpgm
1116  %result = udiv i64 24, %x
1117  store i64 %result, i64 addrspace(1)* %out
1118  ret void
1119}
1120
1121; define i64 @v_test_udiv_k_num_i64(i64 %x) {
1122;   %result = udiv i64 24, %x
1123;   ret i64 %result
1124; }
1125
1126define i64 @v_test_udiv_pow2_k_num_i64(i64 %x) {
1127; GCN-LABEL: v_test_udiv_pow2_k_num_i64:
1128; GCN:       ; %bb.0:
1129; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1130; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1131; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1132; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1133; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1134; GCN-NEXT:    v_mov_b32_e32 v12, 0
1135; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
1136; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1137; GCN-NEXT:    v_mov_b32_e32 v11, 0
1138; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1139; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1140; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1141; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1142; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1143; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1144; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1145; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1146; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1147; GCN-NEXT:    v_mul_lo_u32 v9, v4, v2
1148; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1149; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1150; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
1151; GCN-NEXT:    v_mul_hi_u32 v10, v2, v9
1152; GCN-NEXT:    v_mul_hi_u32 v7, v2, v6
1153; GCN-NEXT:    v_mul_hi_u32 v13, v3, v6
1154; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1155; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
1156; GCN-NEXT:    v_mul_lo_u32 v10, v3, v9
1157; GCN-NEXT:    v_mul_hi_u32 v9, v3, v9
1158; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v7, vcc
1159; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
1160; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v9, vcc
1161; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v11, vcc
1162; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1163; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v6
1164; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v8, vcc
1165; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v3, v7, s[4:5]
1166; GCN-NEXT:    v_mul_lo_u32 v8, v4, v6
1167; GCN-NEXT:    v_mul_hi_u32 v9, v4, v2
1168; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1169; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1170; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1171; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
1172; GCN-NEXT:    v_mul_lo_u32 v10, v2, v5
1173; GCN-NEXT:    v_mul_hi_u32 v13, v2, v4
1174; GCN-NEXT:    v_mul_hi_u32 v14, v2, v5
1175; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
1176; GCN-NEXT:    v_mul_lo_u32 v4, v6, v4
1177; GCN-NEXT:    v_add_i32_e32 v10, vcc, v13, v10
1178; GCN-NEXT:    v_mul_hi_u32 v8, v6, v5
1179; GCN-NEXT:    v_addc_u32_e32 v13, vcc, v12, v14, vcc
1180; GCN-NEXT:    v_mul_lo_u32 v5, v6, v5
1181; GCN-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
1182; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v13, v9, vcc
1183; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v11, vcc
1184; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1185; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
1186; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
1187; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
1188; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1189; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
1190; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1191; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
1192; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1193; GCN-NEXT:    s_mov_b32 s4, 0x8000
1194; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1195; GCN-NEXT:    v_mul_lo_u32 v4, v0, v2
1196; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v3
1197; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s4, v4
1198; GCN-NEXT:    v_subb_u32_e64 v5, s[4:5], v5, v1, vcc
1199; GCN-NEXT:    v_sub_i32_e64 v6, s[4:5], v4, v0
1200; GCN-NEXT:    v_subbrev_u32_e64 v5, s[4:5], 0, v5, s[4:5]
1201; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v5, v1
1202; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
1203; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v0
1204; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
1205; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v5, v1
1206; GCN-NEXT:    v_cndmask_b32_e64 v5, v7, v6, s[4:5]
1207; GCN-NEXT:    v_add_i32_e64 v6, s[4:5], 2, v2
1208; GCN-NEXT:    v_addc_u32_e64 v7, s[4:5], 0, v12, s[4:5]
1209; GCN-NEXT:    v_add_i32_e64 v8, s[4:5], 1, v2
1210; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1211; GCN-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, v12, s[4:5]
1212; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v5
1213; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1214; GCN-NEXT:    v_cndmask_b32_e64 v5, v8, v6, s[4:5]
1215; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1216; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v0
1217; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1218; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1219; GCN-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
1220; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1221; GCN-NEXT:    v_cndmask_b32_e64 v1, v9, v7, s[4:5]
1222; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1223; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
1224; GCN-NEXT:    s_setpc_b64 s[30:31]
1225;
1226; GCN-IR-LABEL: v_test_udiv_pow2_k_num_i64:
1227; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1228; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1229; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1230; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1231; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1232; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
1233; GCN-IR-NEXT:    v_cndmask_b32_e32 v8, v3, v2, vcc
1234; GCN-IR-NEXT:    s_movk_i32 s6, 0xffd0
1235; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, s6, v8
1236; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[6:7], 0, -1, vcc
1237; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1238; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[4:5]
1239; GCN-IR-NEXT:    s_mov_b32 s8, 0x8000
1240; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1241; GCN-IR-NEXT:    v_mov_b32_e32 v2, s8
1242; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1243; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1244; GCN-IR-NEXT:    v_cndmask_b32_e64 v2, v2, 0, s[4:5]
1245; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1246; GCN-IR-NEXT:    s_mov_b32 s9, 0
1247; GCN-IR-NEXT:    v_mov_b32_e32 v3, v9
1248; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1249; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1250; GCN-IR-NEXT:    s_cbranch_execz BB9_6
1251; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1252; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 1, v4
1253; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, 0, v5, vcc
1254; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v4
1255; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[6:7], v[4:5]
1256; GCN-IR-NEXT:    v_lshl_b64 v[2:3], s[8:9], v2
1257; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1258; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1259; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1260; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1261; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
1262; GCN-IR-NEXT:    s_cbranch_execz BB9_5
1263; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1264; GCN-IR-NEXT:    s_mov_b32 s5, 0
1265; GCN-IR-NEXT:    s_mov_b32 s4, 0x8000
1266; GCN-IR-NEXT:    v_lshr_b64 v[10:11], s[4:5], v6
1267; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, -1, v0
1268; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, -1, v1, vcc
1269; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, 47, v8
1270; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1271; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, 0, v9, vcc
1272; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1273; GCN-IR-NEXT:  BB9_3: ; %udiv-do-while
1274; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1275; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
1276; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1277; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v4
1278; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1279; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, v6, v10
1280; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, v7, v11, vcc
1281; GCN-IR-NEXT:    v_or_b32_e32 v2, v12, v2
1282; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v4
1283; GCN-IR-NEXT:    v_and_b32_e32 v15, v12, v0
1284; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v12
1285; GCN-IR-NEXT:    v_and_b32_e32 v14, v12, v1
1286; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
1287; GCN-IR-NEXT:    v_or_b32_e32 v3, v13, v3
1288; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
1289; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
1290; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
1291; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1292; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v15
1293; GCN-IR-NEXT:    v_mov_b32_e32 v9, v13
1294; GCN-IR-NEXT:    v_mov_b32_e32 v13, v5
1295; GCN-IR-NEXT:    v_subb_u32_e64 v11, s[4:5], v11, v14, s[4:5]
1296; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
1297; GCN-IR-NEXT:    v_mov_b32_e32 v12, v4
1298; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
1299; GCN-IR-NEXT:    s_cbranch_execnz BB9_3
1300; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1301; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1302; GCN-IR-NEXT:  BB9_5: ; %Flow3
1303; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1304; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[2:3], 1
1305; GCN-IR-NEXT:    v_or_b32_e32 v3, v5, v1
1306; GCN-IR-NEXT:    v_or_b32_e32 v2, v4, v0
1307; GCN-IR-NEXT:  BB9_6: ; %Flow4
1308; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1309; GCN-IR-NEXT:    v_mov_b32_e32 v0, v2
1310; GCN-IR-NEXT:    v_mov_b32_e32 v1, v3
1311; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1312  %result = udiv i64 32768, %x
1313  ret i64 %result
1314}
1315
1316define i64 @v_test_udiv_pow2_k_den_i64(i64 %x) {
1317; GCN-LABEL: v_test_udiv_pow2_k_den_i64:
1318; GCN:       ; %bb.0:
1319; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1320; GCN-NEXT:    v_alignbit_b32 v0, v1, v0, 15
1321; GCN-NEXT:    v_lshrrev_b32_e32 v1, 15, v1
1322; GCN-NEXT:    s_setpc_b64 s[30:31]
1323;
1324; GCN-IR-LABEL: v_test_udiv_pow2_k_den_i64:
1325; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1326; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1327; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1328; GCN-IR-NEXT:    v_add_i32_e64 v2, s[4:5], 32, v2
1329; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1330; GCN-IR-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v1
1331; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v3, v2, s[4:5]
1332; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 48, v6
1333; GCN-IR-NEXT:    v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5]
1334; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1335; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
1336; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1337; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1338; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1339; GCN-IR-NEXT:    v_cndmask_b32_e64 v2, v1, 0, s[4:5]
1340; GCN-IR-NEXT:    v_cndmask_b32_e64 v3, v0, 0, s[4:5]
1341; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1342; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1343; GCN-IR-NEXT:    s_cbranch_execz BB10_6
1344; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1345; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 1, v4
1346; GCN-IR-NEXT:    v_addc_u32_e32 v8, vcc, 0, v5, vcc
1347; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v4
1348; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[7:8], v[4:5]
1349; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1350; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[0:1], v2
1351; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1352; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1353; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1354; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
1355; GCN-IR-NEXT:    s_cbranch_execz BB10_5
1356; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1357; GCN-IR-NEXT:    v_lshr_b64 v[7:8], v[0:1], v7
1358; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, 0xffffffcf, v6
1359; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1360; GCN-IR-NEXT:    v_addc_u32_e64 v1, s[4:5], 0, -1, vcc
1361; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1362; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
1363; GCN-IR-NEXT:  BB10_3: ; %udiv-do-while
1364; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1365; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
1366; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1367; GCN-IR-NEXT:    v_or_b32_e32 v6, v7, v4
1368; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1369; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, s12, v6
1370; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, 0, v8, vcc
1371; GCN-IR-NEXT:    v_or_b32_e32 v2, v9, v2
1372; GCN-IR-NEXT:    v_add_i32_e32 v9, vcc, 1, v0
1373; GCN-IR-NEXT:    v_ashrrev_i32_e32 v7, 31, v4
1374; GCN-IR-NEXT:    v_or_b32_e32 v3, v10, v3
1375; GCN-IR-NEXT:    v_addc_u32_e32 v10, vcc, 0, v1, vcc
1376; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[9:10], v[0:1]
1377; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v7
1378; GCN-IR-NEXT:    v_and_b32_e32 v7, 0x8000, v7
1379; GCN-IR-NEXT:    v_mov_b32_e32 v0, v9
1380; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1381; GCN-IR-NEXT:    v_mov_b32_e32 v1, v10
1382; GCN-IR-NEXT:    v_mov_b32_e32 v10, v5
1383; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1384; GCN-IR-NEXT:    v_sub_i32_e64 v7, s[4:5], v6, v7
1385; GCN-IR-NEXT:    v_subb_u32_e64 v8, s[4:5], v8, v11, s[4:5]
1386; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
1387; GCN-IR-NEXT:    v_mov_b32_e32 v9, v4
1388; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
1389; GCN-IR-NEXT:    s_cbranch_execnz BB10_3
1390; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1391; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1392; GCN-IR-NEXT:  BB10_5: ; %Flow3
1393; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1394; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[2:3], 1
1395; GCN-IR-NEXT:    v_or_b32_e32 v2, v5, v1
1396; GCN-IR-NEXT:    v_or_b32_e32 v3, v4, v0
1397; GCN-IR-NEXT:  BB10_6: ; %Flow4
1398; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1399; GCN-IR-NEXT:    v_mov_b32_e32 v0, v3
1400; GCN-IR-NEXT:    v_mov_b32_e32 v1, v2
1401; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1402  %result = udiv i64 %x, 32768
1403  ret i64 %result
1404}
1405
1406define amdgpu_kernel void @s_test_udiv_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
1407; GCN-LABEL: s_test_udiv_k_den_i64:
1408; GCN:       ; %bb.0:
1409; GCN-NEXT:    v_mov_b32_e32 v0, 0x4f800000
1410; GCN-NEXT:    v_madak_f32 v0, 0, v0, 0x41c00000
1411; GCN-NEXT:    v_rcp_f32_e32 v0, v0
1412; GCN-NEXT:    s_movk_i32 s2, 0xffe8
1413; GCN-NEXT:    v_mov_b32_e32 v8, 0
1414; GCN-NEXT:    v_mov_b32_e32 v7, 0
1415; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
1416; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
1417; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1418; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
1419; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
1420; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
1421; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
1422; GCN-NEXT:    s_mov_b32 s7, 0xf000
1423; GCN-NEXT:    v_mul_hi_u32 v2, v0, s2
1424; GCN-NEXT:    v_mul_lo_u32 v3, v1, s2
1425; GCN-NEXT:    v_mul_lo_u32 v4, v0, s2
1426; GCN-NEXT:    s_mov_b32 s6, -1
1427; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
1428; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1429; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
1430; GCN-NEXT:    v_mul_hi_u32 v6, v0, v4
1431; GCN-NEXT:    v_mul_hi_u32 v3, v0, v2
1432; GCN-NEXT:    v_mul_hi_u32 v9, v1, v2
1433; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
1434; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
1435; GCN-NEXT:    v_mul_lo_u32 v6, v1, v4
1436; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
1437; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v3, vcc
1438; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1439; GCN-NEXT:    s_mov_b32 s4, s8
1440; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
1441; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
1442; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
1443; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1444; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
1445; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
1446; GCN-NEXT:    v_mul_hi_u32 v4, v0, s2
1447; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
1448; GCN-NEXT:    v_mul_lo_u32 v5, v2, s2
1449; GCN-NEXT:    v_mul_lo_u32 v6, v0, s2
1450; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, v0, v4
1451; GCN-NEXT:    s_mov_b32 s5, s9
1452; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1453; GCN-NEXT:    v_mul_lo_u32 v5, v0, v4
1454; GCN-NEXT:    v_mul_hi_u32 v9, v0, v6
1455; GCN-NEXT:    v_mul_hi_u32 v10, v0, v4
1456; GCN-NEXT:    v_mul_hi_u32 v11, v2, v4
1457; GCN-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
1458; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v8, v10, vcc
1459; GCN-NEXT:    v_mul_lo_u32 v10, v2, v6
1460; GCN-NEXT:    v_mul_hi_u32 v6, v2, v6
1461; GCN-NEXT:    v_mul_lo_u32 v2, v2, v4
1462; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v10
1463; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v6, vcc
1464; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v11, v7, vcc
1465; GCN-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
1466; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
1467; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1468; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
1469; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1470; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1471; GCN-NEXT:    v_mul_lo_u32 v2, s10, v1
1472; GCN-NEXT:    v_mul_hi_u32 v3, s10, v0
1473; GCN-NEXT:    v_mul_hi_u32 v4, s10, v1
1474; GCN-NEXT:    v_mul_hi_u32 v5, s11, v1
1475; GCN-NEXT:    v_mul_lo_u32 v1, s11, v1
1476; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1477; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
1478; GCN-NEXT:    v_mul_lo_u32 v4, s11, v0
1479; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
1480; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
1481; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
1482; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
1483; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1484; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v8, v2, vcc
1485; GCN-NEXT:    v_mul_lo_u32 v2, v1, 24
1486; GCN-NEXT:    v_mul_hi_u32 v3, v0, 24
1487; GCN-NEXT:    v_mul_lo_u32 v4, v0, 24
1488; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1489; GCN-NEXT:    v_mov_b32_e32 v3, s11
1490; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s10, v4
1491; GCN-NEXT:    v_subb_u32_e32 v2, vcc, v3, v2, vcc
1492; GCN-NEXT:    v_subrev_i32_e32 v3, vcc, 24, v4
1493; GCN-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
1494; GCN-NEXT:    v_cmp_lt_u32_e32 vcc, 23, v3
1495; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
1496; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v5
1497; GCN-NEXT:    v_cndmask_b32_e32 v3, -1, v3, vcc
1498; GCN-NEXT:    v_add_i32_e32 v5, vcc, 2, v0
1499; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
1500; GCN-NEXT:    v_add_i32_e32 v7, vcc, 1, v0
1501; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v1, vcc
1502; GCN-NEXT:    v_cmp_lt_u32_e32 vcc, 23, v4
1503; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
1504; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v2
1505; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v3
1506; GCN-NEXT:    v_cndmask_b32_e32 v2, -1, v4, vcc
1507; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
1508; GCN-NEXT:    v_cndmask_b32_e64 v3, v8, v6, s[0:1]
1509; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
1510; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
1511; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1512; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1513; GCN-NEXT:    s_endpgm
1514;
1515; GCN-IR-LABEL: s_test_udiv_k_den_i64:
1516; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1517; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1518; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1519; GCN-IR-NEXT:    s_flbit_i32_b32 s4, s2
1520; GCN-IR-NEXT:    s_add_i32 s4, s4, 32
1521; GCN-IR-NEXT:    s_flbit_i32_b32 s5, s3
1522; GCN-IR-NEXT:    s_cmp_eq_u32 s3, 0
1523; GCN-IR-NEXT:    s_cselect_b32 s8, s4, s5
1524; GCN-IR-NEXT:    s_sub_u32 s6, 59, s8
1525; GCN-IR-NEXT:    s_subb_u32 s7, 0, 0
1526; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
1527; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[12:13], s[6:7], 63
1528; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0
1529; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
1530; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[12:13], s[6:7], 63
1531; GCN-IR-NEXT:    s_xor_b64 s[14:15], s[10:11], -1
1532; GCN-IR-NEXT:    s_and_b64 s[12:13], s[14:15], s[12:13]
1533; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
1534; GCN-IR-NEXT:    s_cbranch_vccz BB11_5
1535; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1536; GCN-IR-NEXT:    s_add_u32 s10, s6, 1
1537; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1538; GCN-IR-NEXT:    s_addc_u32 s11, s7, 0
1539; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
1540; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
1541; GCN-IR-NEXT:    s_sub_i32 s6, 63, s6
1542; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1543; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[2:3], s6
1544; GCN-IR-NEXT:    s_cbranch_vccz BB11_4
1545; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1546; GCN-IR-NEXT:    s_lshr_b64 s[10:11], s[2:3], s10
1547; GCN-IR-NEXT:    s_add_u32 s2, s8, 0xffffffc4
1548; GCN-IR-NEXT:    s_addc_u32 s3, 0, -1
1549; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1550; GCN-IR-NEXT:    s_mov_b32 s5, 0
1551; GCN-IR-NEXT:  BB11_3: ; %udiv-do-while
1552; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1553; GCN-IR-NEXT:    s_lshr_b32 s4, s7, 31
1554; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
1555; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[6:7], 1
1556; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[4:5]
1557; GCN-IR-NEXT:    s_or_b64 s[6:7], s[8:9], s[6:7]
1558; GCN-IR-NEXT:    s_sub_u32 s4, 23, s10
1559; GCN-IR-NEXT:    s_subb_u32 s4, 0, s11
1560; GCN-IR-NEXT:    s_ashr_i32 s8, s4, 31
1561; GCN-IR-NEXT:    s_and_b32 s4, s8, 1
1562; GCN-IR-NEXT:    s_and_b32 s8, s8, 24
1563; GCN-IR-NEXT:    s_sub_u32 s10, s10, s8
1564; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1565; GCN-IR-NEXT:    s_subb_u32 s11, s11, 0
1566; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
1567; GCN-IR-NEXT:    s_add_u32 s2, s2, 1
1568; GCN-IR-NEXT:    s_addc_u32 s3, s3, 0
1569; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1]
1570; GCN-IR-NEXT:    s_mov_b64 s[8:9], s[4:5]
1571; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1572; GCN-IR-NEXT:    s_cbranch_vccz BB11_3
1573; GCN-IR-NEXT:  BB11_4: ; %Flow5
1574; GCN-IR-NEXT:    s_lshl_b64 s[2:3], s[6:7], 1
1575; GCN-IR-NEXT:    s_or_b64 s[2:3], s[4:5], s[2:3]
1576; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1577; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
1578; GCN-IR-NEXT:    s_branch BB11_6
1579; GCN-IR-NEXT:  BB11_5:
1580; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
1581; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[10:11]
1582; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1583; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[10:11]
1584; GCN-IR-NEXT:  BB11_6: ; %udiv-end
1585; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1586; GCN-IR-NEXT:    s_mov_b32 s2, -1
1587; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1588; GCN-IR-NEXT:    s_endpgm
1589  %result = udiv i64 %x, 24
1590  store i64 %result, i64 addrspace(1)* %out
1591  ret void
1592}
1593
1594define i64 @v_test_udiv_k_den_i64(i64 %x) {
1595; GCN-LABEL: v_test_udiv_k_den_i64:
1596; GCN:       ; %bb.0:
1597; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1598; GCN-NEXT:    v_mov_b32_e32 v2, 0x4f800000
1599; GCN-NEXT:    v_madak_f32 v2, 0, v2, 0x41c00000
1600; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1601; GCN-NEXT:    s_movk_i32 s6, 0xffe8
1602; GCN-NEXT:    v_mov_b32_e32 v10, 0
1603; GCN-NEXT:    v_mov_b32_e32 v9, 0
1604; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1605; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1606; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1607; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1608; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1609; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1610; GCN-NEXT:    v_mul_hi_u32 v4, v2, s6
1611; GCN-NEXT:    v_mul_lo_u32 v5, v3, s6
1612; GCN-NEXT:    v_mul_lo_u32 v6, v2, s6
1613; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, v2, v4
1614; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1615; GCN-NEXT:    v_mul_lo_u32 v7, v2, v4
1616; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
1617; GCN-NEXT:    v_mul_hi_u32 v5, v2, v4
1618; GCN-NEXT:    v_mul_hi_u32 v11, v3, v4
1619; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1620; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1621; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
1622; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
1623; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v10, v5, vcc
1624; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1625; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v6, vcc
1626; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
1627; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1628; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v4
1629; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v10, v6, vcc
1630; GCN-NEXT:    v_mul_hi_u32 v6, v2, s6
1631; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[4:5]
1632; GCN-NEXT:    v_mul_lo_u32 v7, v4, s6
1633; GCN-NEXT:    v_mul_lo_u32 v8, v2, s6
1634; GCN-NEXT:    v_subrev_i32_e32 v6, vcc, v2, v6
1635; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
1636; GCN-NEXT:    v_mul_lo_u32 v7, v2, v6
1637; GCN-NEXT:    v_mul_hi_u32 v11, v2, v8
1638; GCN-NEXT:    v_mul_hi_u32 v12, v2, v6
1639; GCN-NEXT:    v_mul_hi_u32 v13, v4, v6
1640; GCN-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
1641; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v10, v12, vcc
1642; GCN-NEXT:    v_mul_lo_u32 v12, v4, v8
1643; GCN-NEXT:    v_mul_hi_u32 v8, v4, v8
1644; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
1645; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
1646; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v8, vcc
1647; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v13, v9, vcc
1648; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
1649; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v6, vcc
1650; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1651; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[4:5]
1652; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1653; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1654; GCN-NEXT:    v_mul_lo_u32 v4, v0, v3
1655; GCN-NEXT:    v_mul_hi_u32 v5, v0, v2
1656; GCN-NEXT:    v_mul_hi_u32 v6, v0, v3
1657; GCN-NEXT:    v_mul_hi_u32 v7, v1, v3
1658; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
1659; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1660; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v10, v6, vcc
1661; GCN-NEXT:    v_mul_lo_u32 v6, v1, v2
1662; GCN-NEXT:    v_mul_hi_u32 v2, v1, v2
1663; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
1664; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v2, vcc
1665; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v9, vcc
1666; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
1667; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v10, v4, vcc
1668; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
1669; GCN-NEXT:    v_mul_hi_u32 v5, v2, 24
1670; GCN-NEXT:    v_mul_lo_u32 v6, v2, 24
1671; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1672; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
1673; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc
1674; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, 24, v0
1675; GCN-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v1, vcc
1676; GCN-NEXT:    v_cmp_lt_u32_e32 vcc, 23, v4
1677; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
1678; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v5
1679; GCN-NEXT:    v_cndmask_b32_e32 v4, -1, v4, vcc
1680; GCN-NEXT:    v_add_i32_e32 v5, vcc, 2, v2
1681; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v3, vcc
1682; GCN-NEXT:    v_add_i32_e32 v7, vcc, 1, v2
1683; GCN-NEXT:    v_cmp_lt_u32_e64 s[4:5], 23, v0
1684; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v3, vcc
1685; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, s[4:5]
1686; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v1
1687; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
1688; GCN-NEXT:    v_cndmask_b32_e64 v0, -1, v0, s[4:5]
1689; GCN-NEXT:    v_cndmask_b32_e32 v4, v7, v5, vcc
1690; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v0
1691; GCN-NEXT:    v_cndmask_b32_e32 v1, v8, v6, vcc
1692; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, v4, s[4:5]
1693; GCN-NEXT:    v_cndmask_b32_e64 v1, v3, v1, s[4:5]
1694; GCN-NEXT:    s_setpc_b64 s[30:31]
1695;
1696; GCN-IR-LABEL: v_test_udiv_k_den_i64:
1697; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1698; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1699; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1700; GCN-IR-NEXT:    v_add_i32_e64 v2, s[4:5], 32, v2
1701; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1702; GCN-IR-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v1
1703; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v3, v2, s[4:5]
1704; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 59, v6
1705; GCN-IR-NEXT:    v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5]
1706; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1707; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
1708; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1709; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1710; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1711; GCN-IR-NEXT:    v_cndmask_b32_e64 v2, v1, 0, s[4:5]
1712; GCN-IR-NEXT:    v_cndmask_b32_e64 v3, v0, 0, s[4:5]
1713; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1714; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1715; GCN-IR-NEXT:    s_cbranch_execz BB12_6
1716; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1717; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 1, v4
1718; GCN-IR-NEXT:    v_addc_u32_e32 v8, vcc, 0, v5, vcc
1719; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v4
1720; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[7:8], v[4:5]
1721; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1722; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[0:1], v2
1723; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1724; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1725; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1726; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
1727; GCN-IR-NEXT:    s_cbranch_execz BB12_5
1728; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1729; GCN-IR-NEXT:    v_lshr_b64 v[7:8], v[0:1], v7
1730; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, 0xffffffc4, v6
1731; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1732; GCN-IR-NEXT:    v_addc_u32_e64 v1, s[4:5], 0, -1, vcc
1733; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1734; GCN-IR-NEXT:  BB12_3: ; %udiv-do-while
1735; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1736; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
1737; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1738; GCN-IR-NEXT:    v_or_b32_e32 v6, v7, v4
1739; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1740; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, 23, v6
1741; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, 0, v8, vcc
1742; GCN-IR-NEXT:    v_or_b32_e32 v2, v9, v2
1743; GCN-IR-NEXT:    v_add_i32_e32 v9, vcc, 1, v0
1744; GCN-IR-NEXT:    v_ashrrev_i32_e32 v7, 31, v4
1745; GCN-IR-NEXT:    v_or_b32_e32 v3, v10, v3
1746; GCN-IR-NEXT:    v_addc_u32_e32 v10, vcc, 0, v1, vcc
1747; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[9:10], v[0:1]
1748; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v7
1749; GCN-IR-NEXT:    v_and_b32_e32 v7, 24, v7
1750; GCN-IR-NEXT:    v_mov_b32_e32 v0, v9
1751; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1752; GCN-IR-NEXT:    v_sub_i32_e64 v7, s[4:5], v6, v7
1753; GCN-IR-NEXT:    v_mov_b32_e32 v1, v10
1754; GCN-IR-NEXT:    v_mov_b32_e32 v10, v5
1755; GCN-IR-NEXT:    v_subbrev_u32_e64 v8, s[4:5], 0, v8, s[4:5]
1756; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
1757; GCN-IR-NEXT:    v_mov_b32_e32 v9, v4
1758; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
1759; GCN-IR-NEXT:    s_cbranch_execnz BB12_3
1760; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1761; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1762; GCN-IR-NEXT:  BB12_5: ; %Flow3
1763; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1764; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[2:3], 1
1765; GCN-IR-NEXT:    v_or_b32_e32 v2, v5, v1
1766; GCN-IR-NEXT:    v_or_b32_e32 v3, v4, v0
1767; GCN-IR-NEXT:  BB12_6: ; %Flow4
1768; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1769; GCN-IR-NEXT:    v_mov_b32_e32 v0, v3
1770; GCN-IR-NEXT:    v_mov_b32_e32 v1, v2
1771; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1772  %result = udiv i64 %x, 24
1773  ret i64 %result
1774}
1775
1776define amdgpu_kernel void @s_test_udiv24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1777; GCN-LABEL: s_test_udiv24_k_num_i64:
1778; GCN:       ; %bb.0:
1779; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1780; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
1781; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1782; GCN-NEXT:    s_lshr_b32 s2, s3, 8
1783; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
1784; GCN-NEXT:    s_mov_b32 s3, 0xf000
1785; GCN-NEXT:    s_mov_b32 s2, -1
1786; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1787; GCN-NEXT:    v_mul_f32_e32 v1, s4, v1
1788; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1789; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1790; GCN-NEXT:    v_mad_f32 v1, -v1, v0, s4
1791; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1792; GCN-NEXT:    v_mov_b32_e32 v1, 0
1793; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1794; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1795; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1796; GCN-NEXT:    s_endpgm
1797;
1798; GCN-IR-LABEL: s_test_udiv24_k_num_i64:
1799; GCN-IR:       ; %bb.0:
1800; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1801; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
1802; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1803; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 8
1804; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
1805; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1806; GCN-IR-NEXT:    s_mov_b32 s2, -1
1807; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1808; GCN-IR-NEXT:    v_mul_f32_e32 v1, s4, v1
1809; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1810; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1811; GCN-IR-NEXT:    v_mad_f32 v1, -v1, v0, s4
1812; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1813; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1814; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1815; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1816; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1817; GCN-IR-NEXT:    s_endpgm
1818  %x.shr = lshr i64 %x, 40
1819  %result = udiv i64 24, %x.shr
1820  store i64 %result, i64 addrspace(1)* %out
1821  ret void
1822}
1823
1824define amdgpu_kernel void @s_test_udiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
1825; GCN-LABEL: s_test_udiv24_k_den_i64:
1826; GCN:       ; %bb.0:
1827; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1828; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1829; GCN-NEXT:    s_mov_b32 s6, 0x46b6fe00
1830; GCN-NEXT:    s_mov_b32 s3, 0xf000
1831; GCN-NEXT:    s_mov_b32 s2, -1
1832; GCN-NEXT:    s_lshr_b32 s0, s7, 8
1833; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
1834; GCN-NEXT:    s_mov_b32 s0, s4
1835; GCN-NEXT:    s_mov_b32 s1, s5
1836; GCN-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1837; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1838; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1839; GCN-NEXT:    v_mad_f32 v0, -v1, s6, v0
1840; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s6
1841; GCN-NEXT:    v_mov_b32_e32 v1, 0
1842; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1843; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1844; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1845; GCN-NEXT:    s_endpgm
1846;
1847; GCN-IR-LABEL: s_test_udiv24_k_den_i64:
1848; GCN-IR:       ; %bb.0:
1849; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1850; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1851; GCN-IR-NEXT:    s_mov_b32 s6, 0x46b6fe00
1852; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1853; GCN-IR-NEXT:    s_mov_b32 s2, -1
1854; GCN-IR-NEXT:    s_lshr_b32 s0, s7, 8
1855; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
1856; GCN-IR-NEXT:    s_mov_b32 s0, s4
1857; GCN-IR-NEXT:    s_mov_b32 s1, s5
1858; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1859; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1860; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1861; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s6, v0
1862; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s6
1863; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1864; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1865; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1866; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1867; GCN-IR-NEXT:    s_endpgm
1868  %x.shr = lshr i64 %x, 40
1869  %result = udiv i64 %x.shr, 23423
1870  store i64 %result, i64 addrspace(1)* %out
1871  ret void
1872}
1873
1874define i64 @v_test_udiv24_k_num_i64(i64 %x) {
1875; GCN-LABEL: v_test_udiv24_k_num_i64:
1876; GCN:       ; %bb.0:
1877; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1878; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1879; GCN-NEXT:    v_cvt_f32_u32_e32 v0, v0
1880; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
1881; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1882; GCN-NEXT:    v_mul_f32_e32 v1, s4, v1
1883; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1884; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1885; GCN-NEXT:    v_mad_f32 v1, -v1, v0, s4
1886; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1887; GCN-NEXT:    v_mov_b32_e32 v1, 0
1888; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1889; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1890; GCN-NEXT:    s_setpc_b64 s[30:31]
1891;
1892; GCN-IR-LABEL: v_test_udiv24_k_num_i64:
1893; GCN-IR:       ; %bb.0:
1894; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1895; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1896; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, v0
1897; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
1898; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1899; GCN-IR-NEXT:    v_mul_f32_e32 v1, s4, v1
1900; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1901; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1902; GCN-IR-NEXT:    v_mad_f32 v1, -v1, v0, s4
1903; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1904; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1905; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1906; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1907; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1908  %x.shr = lshr i64 %x, 40
1909  %result = udiv i64 24, %x.shr
1910  ret i64 %result
1911}
1912
1913define i64 @v_test_udiv24_pow2_k_num_i64(i64 %x) {
1914; GCN-LABEL: v_test_udiv24_pow2_k_num_i64:
1915; GCN:       ; %bb.0:
1916; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1917; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1918; GCN-NEXT:    v_cvt_f32_u32_e32 v0, v0
1919; GCN-NEXT:    s_mov_b32 s4, 0x47000000
1920; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1921; GCN-NEXT:    v_mul_f32_e32 v1, s4, v1
1922; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1923; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1924; GCN-NEXT:    v_mad_f32 v1, -v1, v0, s4
1925; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1926; GCN-NEXT:    v_mov_b32_e32 v1, 0
1927; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1928; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1929; GCN-NEXT:    s_setpc_b64 s[30:31]
1930;
1931; GCN-IR-LABEL: v_test_udiv24_pow2_k_num_i64:
1932; GCN-IR:       ; %bb.0:
1933; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1934; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1935; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, v0
1936; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
1937; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1938; GCN-IR-NEXT:    v_mul_f32_e32 v1, s4, v1
1939; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1940; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1941; GCN-IR-NEXT:    v_mad_f32 v1, -v1, v0, s4
1942; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1943; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1944; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1945; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1946; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1947  %x.shr = lshr i64 %x, 40
1948  %result = udiv i64 32768, %x.shr
1949  ret i64 %result
1950}
1951
1952define i64 @v_test_udiv24_pow2_k_den_i64(i64 %x) {
1953; GCN-LABEL: v_test_udiv24_pow2_k_den_i64:
1954; GCN:       ; %bb.0:
1955; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1956; GCN-NEXT:    v_lshrrev_b32_e32 v0, 23, v1
1957; GCN-NEXT:    v_mov_b32_e32 v1, 0
1958; GCN-NEXT:    s_setpc_b64 s[30:31]
1959;
1960; GCN-IR-LABEL: v_test_udiv24_pow2_k_den_i64:
1961; GCN-IR:       ; %bb.0:
1962; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1963; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1964; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, v0
1965; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
1966; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38000000, v0
1967; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1968; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1969; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s4, v0
1970; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
1971; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1972; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1973; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1974; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1975  %x.shr = lshr i64 %x, 40
1976  %result = udiv i64 %x.shr, 32768
1977  ret i64 %result
1978}
1979