1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_udiv_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_udiv_i64:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xd
9; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
10; GCN-NEXT:    s_mov_b32 s7, 0xf000
11; GCN-NEXT:    s_mov_b32 s6, -1
12; GCN-NEXT:    s_waitcnt lgkmcnt(0)
13; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
14; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s9
15; GCN-NEXT:    s_sub_u32 s4, 0, s8
16; GCN-NEXT:    s_subb_u32 s5, 0, s9
17; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
18; GCN-NEXT:    v_rcp_f32_e32 v0, v0
19; GCN-NEXT:    v_mov_b32_e32 v1, 0
20; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
21; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
22; GCN-NEXT:    v_trunc_f32_e32 v2, v2
23; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
24; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
25; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
26; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
27; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
28; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
29; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
30; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
31; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
32; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
33; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
34; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
35; GCN-NEXT:    v_mul_lo_u32 v7, v2, v5
36; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
37; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
38; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
39; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
40; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
41; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
42; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
43; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
44; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
45; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
46; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
47; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
48; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
49; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
50; GCN-NEXT:    v_mul_lo_u32 v5, s5, v0
51; GCN-NEXT:    s_mov_b32 s5, s1
52; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
53; GCN-NEXT:    v_mul_lo_u32 v4, s4, v0
54; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
55; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
56; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
57; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
58; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
59; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
60; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
61; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
62; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
63; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
64; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
65; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
66; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v1, vcc
67; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
68; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
69; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
70; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
71; GCN-NEXT:    v_mul_lo_u32 v3, s2, v2
72; GCN-NEXT:    v_mul_hi_u32 v4, s2, v0
73; GCN-NEXT:    v_mul_hi_u32 v5, s2, v2
74; GCN-NEXT:    v_mul_hi_u32 v6, s3, v2
75; GCN-NEXT:    v_mul_lo_u32 v2, s3, v2
76; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
77; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
78; GCN-NEXT:    v_mul_lo_u32 v5, s3, v0
79; GCN-NEXT:    v_mul_hi_u32 v0, s3, v0
80; GCN-NEXT:    s_mov_b32 s4, s0
81; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
82; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
83; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
84; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
85; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
86; GCN-NEXT:    v_mul_lo_u32 v2, s8, v1
87; GCN-NEXT:    v_mul_hi_u32 v3, s8, v0
88; GCN-NEXT:    v_mul_lo_u32 v4, s9, v0
89; GCN-NEXT:    v_mov_b32_e32 v5, s9
90; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
91; GCN-NEXT:    v_mul_lo_u32 v3, s8, v0
92; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
93; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s3, v2
94; GCN-NEXT:    v_sub_i32_e32 v3, vcc, s2, v3
95; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
96; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s8, v3
97; GCN-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
98; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v4
99; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
100; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v5
101; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
102; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v4
103; GCN-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
104; GCN-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
105; GCN-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
106; GCN-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
107; GCN-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
108; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
109; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
110; GCN-NEXT:    v_mov_b32_e32 v6, s3
111; GCN-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
112; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
113; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
114; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
115; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
116; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v2
117; GCN-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
118; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
119; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
120; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
121; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
122; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
123; GCN-NEXT:    s_endpgm
124;
125; GCN-IR-LABEL: s_test_udiv_i64:
126; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
127; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
128; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
129; GCN-IR-NEXT:    s_mov_b64 s[6:7], 0
130; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
131; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[4:5], 0
132; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
133; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s4
134; GCN-IR-NEXT:    s_add_i32 s14, s12, 32
135; GCN-IR-NEXT:    s_or_b64 s[12:13], s[8:9], s[10:11]
136; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s5
137; GCN-IR-NEXT:    s_min_u32 s10, s14, s8
138; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s2
139; GCN-IR-NEXT:    s_add_i32 s8, s8, 32
140; GCN-IR-NEXT:    s_flbit_i32_b32 s9, s3
141; GCN-IR-NEXT:    s_min_u32 s14, s8, s9
142; GCN-IR-NEXT:    s_sub_u32 s8, s10, s14
143; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
144; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[16:17], s[8:9], 63
145; GCN-IR-NEXT:    s_mov_b32 s11, 0
146; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[16:17]
147; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[16:17], s[8:9], 63
148; GCN-IR-NEXT:    s_xor_b64 s[18:19], s[12:13], -1
149; GCN-IR-NEXT:    s_and_b64 s[16:17], s[18:19], s[16:17]
150; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[16:17]
151; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_5
152; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
153; GCN-IR-NEXT:    s_add_u32 s12, s8, 1
154; GCN-IR-NEXT:    s_addc_u32 s13, s9, 0
155; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[16:17], s[12:13], 0
156; GCN-IR-NEXT:    s_sub_i32 s8, 63, s8
157; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[16:17]
158; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[2:3], s8
159; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_4
160; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
161; GCN-IR-NEXT:    s_lshr_b64 s[12:13], s[2:3], s12
162; GCN-IR-NEXT:    s_add_u32 s16, s4, -1
163; GCN-IR-NEXT:    s_addc_u32 s17, s5, -1
164; GCN-IR-NEXT:    s_not_b64 s[2:3], s[10:11]
165; GCN-IR-NEXT:    s_add_u32 s2, s2, s14
166; GCN-IR-NEXT:    s_mov_b32 s15, s11
167; GCN-IR-NEXT:    s_addc_u32 s3, s3, s11
168; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
169; GCN-IR-NEXT:    s_mov_b32 s7, 0
170; GCN-IR-NEXT:  .LBB0_3: ; %udiv-do-while
171; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
172; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
173; GCN-IR-NEXT:    s_lshr_b32 s6, s9, 31
174; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
175; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[6:7]
176; GCN-IR-NEXT:    s_or_b64 s[8:9], s[10:11], s[8:9]
177; GCN-IR-NEXT:    s_sub_u32 s6, s16, s12
178; GCN-IR-NEXT:    s_subb_u32 s6, s17, s13
179; GCN-IR-NEXT:    s_ashr_i32 s10, s6, 31
180; GCN-IR-NEXT:    s_mov_b32 s11, s10
181; GCN-IR-NEXT:    s_and_b32 s6, s10, 1
182; GCN-IR-NEXT:    s_and_b64 s[10:11], s[10:11], s[4:5]
183; GCN-IR-NEXT:    s_sub_u32 s12, s12, s10
184; GCN-IR-NEXT:    s_subb_u32 s13, s13, s11
185; GCN-IR-NEXT:    s_add_u32 s2, s2, 1
186; GCN-IR-NEXT:    s_addc_u32 s3, s3, 0
187; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[14:15], s[2:3], 0
188; GCN-IR-NEXT:    s_mov_b64 s[10:11], s[6:7]
189; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[14:15]
190; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_3
191; GCN-IR-NEXT:  .LBB0_4: ; %Flow6
192; GCN-IR-NEXT:    s_lshl_b64 s[2:3], s[8:9], 1
193; GCN-IR-NEXT:    s_or_b64 s[2:3], s[6:7], s[2:3]
194; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
195; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
196; GCN-IR-NEXT:    s_branch .LBB0_6
197; GCN-IR-NEXT:  .LBB0_5:
198; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
199; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[12:13]
200; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
201; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[12:13]
202; GCN-IR-NEXT:  .LBB0_6: ; %udiv-end
203; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
204; GCN-IR-NEXT:    s_mov_b32 s2, -1
205; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
206; GCN-IR-NEXT:    s_endpgm
207  %result = udiv i64 %x, %y
208  store i64 %result, i64 addrspace(1)* %out
209  ret void
210}
211
212define i64 @v_test_udiv_i64(i64 %x, i64 %y) {
213; GCN-LABEL: v_test_udiv_i64:
214; GCN:       ; %bb.0:
215; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
216; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v2
217; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v3
218; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v2
219; GCN-NEXT:    v_subb_u32_e32 v7, vcc, 0, v3, vcc
220; GCN-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
221; GCN-NEXT:    v_rcp_f32_e32 v4, v4
222; GCN-NEXT:    v_mov_b32_e32 v13, 0
223; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
224; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
225; GCN-NEXT:    v_trunc_f32_e32 v5, v5
226; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
227; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
228; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
229; GCN-NEXT:    v_mul_lo_u32 v8, v6, v5
230; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
231; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
232; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
233; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
234; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
235; GCN-NEXT:    v_mul_lo_u32 v10, v4, v8
236; GCN-NEXT:    v_mul_hi_u32 v11, v4, v9
237; GCN-NEXT:    v_mul_hi_u32 v12, v4, v8
238; GCN-NEXT:    v_mul_hi_u32 v14, v5, v8
239; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
240; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
241; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
242; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
243; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
244; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
245; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v11, v9, vcc
246; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v13, vcc
247; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
248; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
249; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
250; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v9, vcc
251; GCN-NEXT:    v_mul_lo_u32 v8, v6, v5
252; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
253; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
254; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
255; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
256; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
257; GCN-NEXT:    v_mul_lo_u32 v10, v4, v7
258; GCN-NEXT:    v_mul_hi_u32 v11, v4, v6
259; GCN-NEXT:    v_mul_hi_u32 v12, v4, v7
260; GCN-NEXT:    v_mul_hi_u32 v9, v5, v6
261; GCN-NEXT:    v_mul_lo_u32 v6, v5, v6
262; GCN-NEXT:    v_mul_hi_u32 v8, v5, v7
263; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
264; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
265; GCN-NEXT:    v_mul_lo_u32 v7, v5, v7
266; GCN-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
267; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
268; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v8, v13, vcc
269; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
270; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
271; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
272; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
273; GCN-NEXT:    v_mul_lo_u32 v6, v0, v5
274; GCN-NEXT:    v_mul_hi_u32 v7, v0, v4
275; GCN-NEXT:    v_mul_hi_u32 v8, v0, v5
276; GCN-NEXT:    v_mul_hi_u32 v9, v1, v5
277; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
278; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
279; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
280; GCN-NEXT:    v_mul_lo_u32 v8, v1, v4
281; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
282; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
283; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v4, vcc
284; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v13, vcc
285; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
286; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
287; GCN-NEXT:    v_mul_lo_u32 v6, v2, v5
288; GCN-NEXT:    v_mul_hi_u32 v7, v2, v4
289; GCN-NEXT:    v_mul_lo_u32 v8, v3, v4
290; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
291; GCN-NEXT:    v_mul_lo_u32 v7, v2, v4
292; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
293; GCN-NEXT:    v_sub_i32_e32 v8, vcc, v1, v6
294; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v7
295; GCN-NEXT:    v_subb_u32_e64 v7, s[4:5], v8, v3, vcc
296; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v0, v2
297; GCN-NEXT:    v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5]
298; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v3
299; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
300; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v2
301; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
302; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v3
303; GCN-NEXT:    v_cndmask_b32_e64 v7, v9, v8, s[4:5]
304; GCN-NEXT:    v_add_i32_e64 v8, s[4:5], 2, v4
305; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
306; GCN-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, v5, s[4:5]
307; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
308; GCN-NEXT:    v_add_i32_e64 v10, s[4:5], 1, v4
309; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
310; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
311; GCN-NEXT:    v_addc_u32_e64 v11, s[4:5], 0, v5, s[4:5]
312; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
313; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
314; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
315; GCN-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
316; GCN-NEXT:    v_cndmask_b32_e64 v7, v10, v8, s[4:5]
317; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
318; GCN-NEXT:    v_cndmask_b32_e64 v1, v11, v9, s[4:5]
319; GCN-NEXT:    v_cndmask_b32_e32 v0, v4, v7, vcc
320; GCN-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
321; GCN-NEXT:    s_setpc_b64 s[30:31]
322;
323; GCN-IR-LABEL: v_test_udiv_i64:
324; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
325; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
326; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[2:3]
327; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
328; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v2
329; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
330; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
331; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v3
332; GCN-IR-NEXT:    v_min_u32_e32 v8, v4, v5
333; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
334; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
335; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
336; GCN-IR-NEXT:    v_min_u32_e32 v10, v4, v5
337; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v8, v10
338; GCN-IR-NEXT:    v_subb_u32_e64 v7, s[6:7], 0, 0, vcc
339; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[6:7]
340; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
341; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
342; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[6:7]
343; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
344; GCN-IR-NEXT:    v_mov_b32_e32 v11, v9
345; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v1, 0, s[4:5]
346; GCN-IR-NEXT:    v_cndmask_b32_e64 v5, v0, 0, s[4:5]
347; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
348; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
349; GCN-IR-NEXT:    s_cbranch_execz .LBB1_6
350; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
351; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v6
352; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v7, vcc
353; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v6
354; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[12:13]
355; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[0:1], v4
356; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
357; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
358; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
359; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
360; GCN-IR-NEXT:    s_cbranch_execz .LBB1_5
361; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
362; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, -1, v2
363; GCN-IR-NEXT:    v_lshr_b64 v[12:13], v[0:1], v12
364; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, -1, v3, vcc
365; GCN-IR-NEXT:    v_not_b32_e32 v0, v8
366; GCN-IR-NEXT:    v_not_b32_e32 v1, v9
367; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v10
368; GCN-IR-NEXT:    v_mov_b32_e32 v8, 0
369; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, v1, v11, vcc
370; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
371; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
372; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
373; GCN-IR-NEXT:  .LBB1_3: ; %udiv-do-while
374; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
375; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[12:13], 1
376; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
377; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v6
378; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
379; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v14, v10
380; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v15, v11, vcc
381; GCN-IR-NEXT:    v_or_b32_e32 v4, v8, v4
382; GCN-IR-NEXT:    v_ashrrev_i32_e32 v8, 31, v6
383; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, 1, v0
384; GCN-IR-NEXT:    v_or_b32_e32 v5, v9, v5
385; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v8
386; GCN-IR-NEXT:    v_and_b32_e32 v9, v8, v3
387; GCN-IR-NEXT:    v_and_b32_e32 v8, v8, v2
388; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
389; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
390; GCN-IR-NEXT:    v_sub_i32_e64 v12, s[4:5], v10, v8
391; GCN-IR-NEXT:    v_subb_u32_e64 v13, s[4:5], v11, v9, s[4:5]
392; GCN-IR-NEXT:    v_mov_b32_e32 v9, v7
393; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
394; GCN-IR-NEXT:    v_mov_b32_e32 v8, v6
395; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
396; GCN-IR-NEXT:    s_cbranch_execnz .LBB1_3
397; GCN-IR-NEXT:  ; %bb.4: ; %Flow
398; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
399; GCN-IR-NEXT:  .LBB1_5: ; %Flow3
400; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
401; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[4:5], 1
402; GCN-IR-NEXT:    v_or_b32_e32 v4, v7, v1
403; GCN-IR-NEXT:    v_or_b32_e32 v5, v6, v0
404; GCN-IR-NEXT:  .LBB1_6: ; %Flow4
405; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
406; GCN-IR-NEXT:    v_mov_b32_e32 v0, v5
407; GCN-IR-NEXT:    v_mov_b32_e32 v1, v4
408; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
409  %result = udiv i64 %x, %y
410  ret i64 %result
411}
412
413define amdgpu_kernel void @s_test_udiv24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
414; GCN-LABEL: s_test_udiv24_64:
415; GCN:       ; %bb.0:
416; GCN-NEXT:    s_load_dword s4, s[0:1], 0xe
417; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
418; GCN-NEXT:    s_mov_b32 s7, 0xf000
419; GCN-NEXT:    s_mov_b32 s6, -1
420; GCN-NEXT:    s_waitcnt lgkmcnt(0)
421; GCN-NEXT:    s_lshr_b32 s2, s4, 8
422; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
423; GCN-NEXT:    s_lshr_b32 s2, s3, 8
424; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s2
425; GCN-NEXT:    s_mov_b32 s4, s0
426; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
427; GCN-NEXT:    s_mov_b32 s5, s1
428; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
429; GCN-NEXT:    v_trunc_f32_e32 v2, v2
430; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
431; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
432; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
433; GCN-NEXT:    v_mov_b32_e32 v1, 0
434; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
435; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
436; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
437; GCN-NEXT:    s_endpgm
438;
439; GCN-IR-LABEL: s_test_udiv24_64:
440; GCN-IR:       ; %bb.0:
441; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xe
442; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
443; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
444; GCN-IR-NEXT:    s_mov_b32 s6, -1
445; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
446; GCN-IR-NEXT:    s_lshr_b32 s2, s4, 8
447; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
448; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 8
449; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s2
450; GCN-IR-NEXT:    s_mov_b32 s4, s0
451; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
452; GCN-IR-NEXT:    s_mov_b32 s5, s1
453; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
454; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
455; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
456; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
457; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
458; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
459; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
460; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
461; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
462; GCN-IR-NEXT:    s_endpgm
463  %1 = lshr i64 %x, 40
464  %2 = lshr i64 %y, 40
465  %result = udiv i64 %1, %2
466  store i64 %result, i64 addrspace(1)* %out
467  ret void
468}
469
470define i64 @v_test_udiv24_i64(i64 %x, i64 %y) {
471; GCN-LABEL: v_test_udiv24_i64:
472; GCN:       ; %bb.0:
473; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
474; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v3
475; GCN-NEXT:    v_cvt_f32_u32_e32 v0, v0
476; GCN-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
477; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v1
478; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
479; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
480; GCN-NEXT:    v_trunc_f32_e32 v2, v2
481; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
482; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
483; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
484; GCN-NEXT:    v_mov_b32_e32 v1, 0
485; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
486; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
487; GCN-NEXT:    s_setpc_b64 s[30:31]
488;
489; GCN-IR-LABEL: v_test_udiv24_i64:
490; GCN-IR:       ; %bb.0:
491; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
492; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v3
493; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, v0
494; GCN-IR-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
495; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, v1
496; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
497; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
498; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
499; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
500; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
501; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
502; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
503; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
504; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
505; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
506  %1 = lshr i64 %x, 40
507  %2 = lshr i64 %y, 40
508  %result = udiv i64 %1, %2
509  ret i64 %result
510}
511
512define amdgpu_kernel void @s_test_udiv32_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
513; GCN-LABEL: s_test_udiv32_i64:
514; GCN:       ; %bb.0:
515; GCN-NEXT:    s_load_dword s4, s[0:1], 0xe
516; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
517; GCN-NEXT:    s_mov_b32 s7, 0xf000
518; GCN-NEXT:    s_mov_b32 s6, -1
519; GCN-NEXT:    s_waitcnt lgkmcnt(0)
520; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
521; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s3
522; GCN-NEXT:    s_mov_b32 s4, s0
523; GCN-NEXT:    s_mov_b32 s5, s1
524; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
525; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
526; GCN-NEXT:    v_trunc_f32_e32 v2, v2
527; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
528; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
529; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
530; GCN-NEXT:    v_mov_b32_e32 v1, 0
531; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
532; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
533; GCN-NEXT:    s_endpgm
534;
535; GCN-IR-LABEL: s_test_udiv32_i64:
536; GCN-IR:       ; %bb.0:
537; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xe
538; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
539; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
540; GCN-IR-NEXT:    s_mov_b32 s6, -1
541; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
542; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
543; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s3
544; GCN-IR-NEXT:    s_mov_b32 s4, s0
545; GCN-IR-NEXT:    s_mov_b32 s5, s1
546; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
547; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
548; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
549; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
550; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
551; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
552; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
553; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
554; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
555; GCN-IR-NEXT:    s_endpgm
556  %1 = lshr i64 %x, 32
557  %2 = lshr i64 %y, 32
558  %result = udiv i64 %1, %2
559  store i64 %result, i64 addrspace(1)* %out
560  ret void
561}
562
563define amdgpu_kernel void @s_test_udiv31_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
564; GCN-LABEL: s_test_udiv31_i64:
565; GCN:       ; %bb.0:
566; GCN-NEXT:    s_load_dword s4, s[0:1], 0xe
567; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
568; GCN-NEXT:    s_mov_b32 s7, 0xf000
569; GCN-NEXT:    s_mov_b32 s6, -1
570; GCN-NEXT:    s_waitcnt lgkmcnt(0)
571; GCN-NEXT:    s_lshr_b32 s2, s4, 1
572; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
573; GCN-NEXT:    s_lshr_b32 s2, s3, 1
574; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s2
575; GCN-NEXT:    s_mov_b32 s4, s0
576; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
577; GCN-NEXT:    s_mov_b32 s5, s1
578; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
579; GCN-NEXT:    v_trunc_f32_e32 v2, v2
580; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
581; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
582; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
583; GCN-NEXT:    v_mov_b32_e32 v1, 0
584; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
585; GCN-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
586; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
587; GCN-NEXT:    s_endpgm
588;
589; GCN-IR-LABEL: s_test_udiv31_i64:
590; GCN-IR:       ; %bb.0:
591; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xe
592; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
593; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
594; GCN-IR-NEXT:    s_mov_b32 s6, -1
595; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
596; GCN-IR-NEXT:    s_lshr_b32 s2, s4, 1
597; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
598; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 1
599; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s2
600; GCN-IR-NEXT:    s_mov_b32 s4, s0
601; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
602; GCN-IR-NEXT:    s_mov_b32 s5, s1
603; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
604; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
605; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
606; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
607; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
608; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
609; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
610; GCN-IR-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
611; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
612; GCN-IR-NEXT:    s_endpgm
613  %1 = lshr i64 %x, 33
614  %2 = lshr i64 %y, 33
615  %result = udiv i64 %1, %2
616  store i64 %result, i64 addrspace(1)* %out
617  ret void
618}
619
620define amdgpu_kernel void @s_test_udiv23_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
621; GCN-LABEL: s_test_udiv23_i64:
622; GCN:       ; %bb.0:
623; GCN-NEXT:    s_load_dword s4, s[0:1], 0xe
624; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
625; GCN-NEXT:    s_mov_b32 s7, 0xf000
626; GCN-NEXT:    s_mov_b32 s6, -1
627; GCN-NEXT:    s_waitcnt lgkmcnt(0)
628; GCN-NEXT:    s_lshr_b32 s2, s4, 9
629; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
630; GCN-NEXT:    s_lshr_b32 s2, s3, 9
631; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s2
632; GCN-NEXT:    s_mov_b32 s4, s0
633; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
634; GCN-NEXT:    s_mov_b32 s5, s1
635; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
636; GCN-NEXT:    v_trunc_f32_e32 v2, v2
637; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
638; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
639; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
640; GCN-NEXT:    v_mov_b32_e32 v1, 0
641; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
642; GCN-NEXT:    v_and_b32_e32 v0, 0x7fffff, v0
643; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
644; GCN-NEXT:    s_endpgm
645;
646; GCN-IR-LABEL: s_test_udiv23_i64:
647; GCN-IR:       ; %bb.0:
648; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xe
649; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
650; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
651; GCN-IR-NEXT:    s_mov_b32 s6, -1
652; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
653; GCN-IR-NEXT:    s_lshr_b32 s2, s4, 9
654; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
655; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 9
656; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s2
657; GCN-IR-NEXT:    s_mov_b32 s4, s0
658; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
659; GCN-IR-NEXT:    s_mov_b32 s5, s1
660; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
661; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
662; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
663; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
664; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
665; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
666; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
667; GCN-IR-NEXT:    v_and_b32_e32 v0, 0x7fffff, v0
668; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
669; GCN-IR-NEXT:    s_endpgm
670  %1 = lshr i64 %x, 41
671  %2 = lshr i64 %y, 41
672  %result = udiv i64 %1, %2
673  store i64 %result, i64 addrspace(1)* %out
674  ret void
675}
676
677define amdgpu_kernel void @s_test_udiv24_i48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
678; GCN-LABEL: s_test_udiv24_i48:
679; GCN:       ; %bb.0:
680; GCN-NEXT:    s_load_dword s2, s[0:1], 0xe
681; GCN-NEXT:    s_load_dword s4, s[0:1], 0xd
682; GCN-NEXT:    s_mov_b32 s6, 0xffff
683; GCN-NEXT:    s_mov_b32 s7, 0xff000000
684; GCN-NEXT:    v_cvt_f32_ubyte3_e32 v2, s6
685; GCN-NEXT:    s_waitcnt lgkmcnt(0)
686; GCN-NEXT:    s_and_b32 s3, s2, s6
687; GCN-NEXT:    s_and_b32 s2, s4, s7
688; GCN-NEXT:    v_mov_b32_e32 v0, s2
689; GCN-NEXT:    v_alignbit_b32 v0, s3, v0, 24
690; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v0
691; GCN-NEXT:    s_load_dword s8, s[0:1], 0xb
692; GCN-NEXT:    s_load_dword s9, s[0:1], 0xc
693; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
694; GCN-NEXT:    s_lshr_b64 s[0:1], s[2:3], 24
695; GCN-NEXT:    v_mac_f32_e32 v1, 0x4f800000, v2
696; GCN-NEXT:    v_rcp_f32_e32 v1, v1
697; GCN-NEXT:    s_waitcnt lgkmcnt(0)
698; GCN-NEXT:    s_and_b32 s6, s9, s6
699; GCN-NEXT:    s_and_b32 s8, s8, s7
700; GCN-NEXT:    s_sub_u32 s0, 0, s0
701; GCN-NEXT:    v_mul_f32_e32 v1, 0x5f7ffffc, v1
702; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v1
703; GCN-NEXT:    v_trunc_f32_e32 v2, v2
704; GCN-NEXT:    v_mac_f32_e32 v1, 0xcf800000, v2
705; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
706; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
707; GCN-NEXT:    s_subb_u32 s1, 0, s1
708; GCN-NEXT:    v_mov_b32_e32 v8, 0
709; GCN-NEXT:    v_mul_hi_u32 v3, s0, v1
710; GCN-NEXT:    v_mul_lo_u32 v4, s0, v2
711; GCN-NEXT:    v_mul_lo_u32 v5, s1, v1
712; GCN-NEXT:    s_mov_b32 s7, 0xf000
713; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
714; GCN-NEXT:    v_mul_lo_u32 v4, s0, v1
715; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
716; GCN-NEXT:    v_mul_lo_u32 v5, v1, v3
717; GCN-NEXT:    v_mul_hi_u32 v6, v1, v4
718; GCN-NEXT:    v_mul_hi_u32 v7, v1, v3
719; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
720; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
721; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
722; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
723; GCN-NEXT:    v_mul_lo_u32 v7, v2, v4
724; GCN-NEXT:    v_mul_hi_u32 v4, v2, v4
725; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
726; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v4, vcc
727; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v8, vcc
728; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
729; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
730; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
731; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
732; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
733; GCN-NEXT:    v_mul_hi_u32 v4, s0, v1
734; GCN-NEXT:    v_mul_lo_u32 v5, s1, v1
735; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
736; GCN-NEXT:    v_mul_lo_u32 v4, s0, v1
737; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
738; GCN-NEXT:    v_mul_lo_u32 v7, v1, v3
739; GCN-NEXT:    v_mul_hi_u32 v9, v1, v4
740; GCN-NEXT:    v_mul_hi_u32 v10, v1, v3
741; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
742; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
743; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
744; GCN-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
745; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
746; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
747; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
748; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v6, vcc
749; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
750; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
751; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
752; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
753; GCN-NEXT:    v_mov_b32_e32 v3, s8
754; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
755; GCN-NEXT:    v_alignbit_b32 v3, s6, v3, 24
756; GCN-NEXT:    v_mul_lo_u32 v4, v3, v2
757; GCN-NEXT:    v_mul_hi_u32 v1, v3, v1
758; GCN-NEXT:    v_mul_hi_u32 v2, v3, v2
759; GCN-NEXT:    s_mov_b32 s6, -1
760; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
761; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
762; GCN-NEXT:    v_add_i32_e32 v1, vcc, 0, v1
763; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
764; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v8, vcc
765; GCN-NEXT:    v_add_i32_e32 v1, vcc, 0, v1
766; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
767; GCN-NEXT:    v_mul_lo_u32 v6, v0, v2
768; GCN-NEXT:    v_mul_hi_u32 v7, v0, v1
769; GCN-NEXT:    v_add_i32_e32 v4, vcc, 2, v1
770; GCN-NEXT:    v_mul_lo_u32 v10, v0, v1
771; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v2, vcc
772; GCN-NEXT:    v_add_i32_e32 v8, vcc, 1, v1
773; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v2, vcc
774; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
775; GCN-NEXT:    v_sub_i32_e32 v3, vcc, v3, v10
776; GCN-NEXT:    v_subb_u32_e32 v6, vcc, 0, v6, vcc
777; GCN-NEXT:    v_sub_i32_e32 v7, vcc, v3, v0
778; GCN-NEXT:    v_subbrev_u32_e32 v10, vcc, 0, v6, vcc
779; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v7, v0
780; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
781; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v10
782; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], v3, v0
783; GCN-NEXT:    v_cndmask_b32_e32 v7, -1, v7, vcc
784; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, s[0:1]
785; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v6
786; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
787; GCN-NEXT:    v_cndmask_b32_e64 v0, -1, v0, s[0:1]
788; GCN-NEXT:    v_cndmask_b32_e32 v4, v8, v4, vcc
789; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v0
790; GCN-NEXT:    v_cndmask_b32_e64 v0, v1, v4, s[0:1]
791; GCN-NEXT:    v_cndmask_b32_e32 v1, v9, v5, vcc
792; GCN-NEXT:    v_cndmask_b32_e64 v1, v2, v1, s[0:1]
793; GCN-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
794; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
795; GCN-NEXT:    s_endpgm
796;
797; GCN-IR-LABEL: s_test_udiv24_i48:
798; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
799; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xc
800; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
801; GCN-IR-NEXT:    s_load_dword s3, s[0:1], 0xb
802; GCN-IR-NEXT:    s_load_dword s6, s[0:1], 0xd
803; GCN-IR-NEXT:    s_load_dword s7, s[0:1], 0xe
804; GCN-IR-NEXT:    s_mov_b32 s8, 0xffff
805; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
806; GCN-IR-NEXT:    s_and_b32 s1, s2, s8
807; GCN-IR-NEXT:    s_mov_b32 s2, 0xff000000
808; GCN-IR-NEXT:    s_and_b32 s0, s3, s2
809; GCN-IR-NEXT:    s_and_b32 s3, s7, s8
810; GCN-IR-NEXT:    s_and_b32 s2, s6, s2
811; GCN-IR-NEXT:    s_lshr_b64 s[8:9], s[0:1], 24
812; GCN-IR-NEXT:    s_lshr_b64 s[2:3], s[2:3], 24
813; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[6:7], s[2:3], 0
814; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[8:9], 0
815; GCN-IR-NEXT:    s_mov_b64 s[0:1], 0
816; GCN-IR-NEXT:    s_or_b64 s[12:13], s[6:7], s[10:11]
817; GCN-IR-NEXT:    s_flbit_i32_b32 s6, s2
818; GCN-IR-NEXT:    s_add_i32 s6, s6, 32
819; GCN-IR-NEXT:    s_flbit_i32_b32 s7, s3
820; GCN-IR-NEXT:    s_min_u32 s10, s6, s7
821; GCN-IR-NEXT:    s_flbit_i32_b32 s6, s8
822; GCN-IR-NEXT:    s_add_i32 s6, s6, 32
823; GCN-IR-NEXT:    s_flbit_i32_b32 s7, s9
824; GCN-IR-NEXT:    s_min_u32 s14, s6, s7
825; GCN-IR-NEXT:    s_sub_u32 s6, s10, s14
826; GCN-IR-NEXT:    s_subb_u32 s7, 0, 0
827; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[16:17], s[6:7], 63
828; GCN-IR-NEXT:    s_mov_b32 s11, 0
829; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[16:17]
830; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[16:17], s[6:7], 63
831; GCN-IR-NEXT:    s_xor_b64 s[18:19], s[12:13], -1
832; GCN-IR-NEXT:    s_and_b64 s[16:17], s[18:19], s[16:17]
833; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[16:17]
834; GCN-IR-NEXT:    s_cbranch_vccz .LBB7_5
835; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
836; GCN-IR-NEXT:    s_add_u32 s12, s6, 1
837; GCN-IR-NEXT:    s_addc_u32 s13, s7, 0
838; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[16:17], s[12:13], 0
839; GCN-IR-NEXT:    s_sub_i32 s6, 63, s6
840; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[16:17]
841; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[8:9], s6
842; GCN-IR-NEXT:    s_cbranch_vccz .LBB7_4
843; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
844; GCN-IR-NEXT:    s_lshr_b64 s[12:13], s[8:9], s12
845; GCN-IR-NEXT:    s_add_u32 s16, s2, -1
846; GCN-IR-NEXT:    s_addc_u32 s17, s3, -1
847; GCN-IR-NEXT:    s_not_b64 s[0:1], s[10:11]
848; GCN-IR-NEXT:    s_add_u32 s8, s0, s14
849; GCN-IR-NEXT:    s_mov_b32 s15, s11
850; GCN-IR-NEXT:    s_addc_u32 s9, s1, s11
851; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
852; GCN-IR-NEXT:    s_mov_b32 s1, 0
853; GCN-IR-NEXT:  .LBB7_3: ; %udiv-do-while
854; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
855; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
856; GCN-IR-NEXT:    s_lshr_b32 s0, s7, 31
857; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[6:7], 1
858; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[0:1]
859; GCN-IR-NEXT:    s_or_b64 s[6:7], s[10:11], s[6:7]
860; GCN-IR-NEXT:    s_sub_u32 s0, s16, s12
861; GCN-IR-NEXT:    s_subb_u32 s0, s17, s13
862; GCN-IR-NEXT:    s_ashr_i32 s10, s0, 31
863; GCN-IR-NEXT:    s_mov_b32 s11, s10
864; GCN-IR-NEXT:    s_and_b32 s0, s10, 1
865; GCN-IR-NEXT:    s_and_b64 s[10:11], s[10:11], s[2:3]
866; GCN-IR-NEXT:    s_sub_u32 s12, s12, s10
867; GCN-IR-NEXT:    s_subb_u32 s13, s13, s11
868; GCN-IR-NEXT:    s_add_u32 s8, s8, 1
869; GCN-IR-NEXT:    s_addc_u32 s9, s9, 0
870; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[14:15], s[8:9], 0
871; GCN-IR-NEXT:    s_mov_b64 s[10:11], s[0:1]
872; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[14:15]
873; GCN-IR-NEXT:    s_cbranch_vccz .LBB7_3
874; GCN-IR-NEXT:  .LBB7_4: ; %Flow3
875; GCN-IR-NEXT:    s_lshl_b64 s[2:3], s[6:7], 1
876; GCN-IR-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
877; GCN-IR-NEXT:    v_mov_b32_e32 v0, s0
878; GCN-IR-NEXT:    v_mov_b32_e32 v1, s1
879; GCN-IR-NEXT:    s_branch .LBB7_6
880; GCN-IR-NEXT:  .LBB7_5:
881; GCN-IR-NEXT:    v_mov_b32_e32 v0, s9
882; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[12:13]
883; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
884; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[12:13]
885; GCN-IR-NEXT:  .LBB7_6: ; %udiv-end
886; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
887; GCN-IR-NEXT:    s_mov_b32 s6, -1
888; GCN-IR-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
889; GCN-IR-NEXT:    buffer_store_dword v0, off, s[4:7], 0
890; GCN-IR-NEXT:    s_endpgm
891  %1 = lshr i48 %x, 24
892  %2 = lshr i48 %y, 24
893  %result = udiv i48 %1, %2
894  store i48 %result, i48 addrspace(1)* %out
895  ret void
896}
897
898define amdgpu_kernel void @s_test_udiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
899; GCN-LABEL: s_test_udiv_k_num_i64:
900; GCN:       ; %bb.0:
901; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
902; GCN-NEXT:    s_mov_b32 s7, 0xf000
903; GCN-NEXT:    s_mov_b32 s6, -1
904; GCN-NEXT:    s_waitcnt lgkmcnt(0)
905; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
906; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s3
907; GCN-NEXT:    s_sub_u32 s4, 0, s2
908; GCN-NEXT:    s_subb_u32 s5, 0, s3
909; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
910; GCN-NEXT:    v_rcp_f32_e32 v0, v0
911; GCN-NEXT:    v_mov_b32_e32 v1, 0
912; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
913; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
914; GCN-NEXT:    v_trunc_f32_e32 v2, v2
915; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
916; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
917; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
918; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
919; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
920; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
921; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
922; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
923; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
924; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
925; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
926; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
927; GCN-NEXT:    v_mul_hi_u32 v7, v2, v5
928; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
929; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
930; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
931; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
932; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
933; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
934; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v7, vcc
935; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
936; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
937; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
938; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
939; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
940; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
941; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
942; GCN-NEXT:    v_mul_lo_u32 v5, s5, v0
943; GCN-NEXT:    s_mov_b32 s5, s1
944; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
945; GCN-NEXT:    v_mul_lo_u32 v4, s4, v0
946; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
947; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
948; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
949; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
950; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
951; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
952; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
953; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
954; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
955; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
956; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
957; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
958; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v5, v1, vcc
959; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
960; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
961; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
962; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
963; GCN-NEXT:    v_mul_lo_u32 v2, v1, 24
964; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
965; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
966; GCN-NEXT:    v_mov_b32_e32 v4, s3
967; GCN-NEXT:    s_mov_b32 s4, s0
968; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
969; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v1, vcc
970; GCN-NEXT:    v_mul_lo_u32 v1, s3, v0
971; GCN-NEXT:    v_mul_hi_u32 v2, s2, v0
972; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
973; GCN-NEXT:    v_mul_lo_u32 v2, s2, v0
974; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 0, v1
975; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 24, v2
976; GCN-NEXT:    v_subb_u32_e64 v3, s[0:1], v3, v4, vcc
977; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s2, v2
978; GCN-NEXT:    v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1]
979; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v3
980; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
981; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v4
982; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]
983; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s3, v3
984; GCN-NEXT:    v_cndmask_b32_e64 v3, v5, v4, s[0:1]
985; GCN-NEXT:    v_add_i32_e64 v4, s[0:1], 2, v0
986; GCN-NEXT:    v_addc_u32_e64 v5, s[0:1], 0, 0, s[0:1]
987; GCN-NEXT:    v_add_i32_e64 v6, s[0:1], 1, v0
988; GCN-NEXT:    v_addc_u32_e64 v7, s[0:1], 0, 0, s[0:1]
989; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
990; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v3
991; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
992; GCN-NEXT:    v_cndmask_b32_e64 v3, v7, v5, s[0:1]
993; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
994; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v2
995; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
996; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v1
997; GCN-NEXT:    v_cndmask_b32_e32 v1, v5, v2, vcc
998; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
999; GCN-NEXT:    v_cndmask_b32_e64 v2, v6, v4, s[0:1]
1000; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
1001; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1002; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1003; GCN-NEXT:    s_endpgm
1004;
1005; GCN-IR-LABEL: s_test_udiv_k_num_i64:
1006; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1007; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1008; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1009; GCN-IR-NEXT:    s_flbit_i32_b32 s4, s2
1010; GCN-IR-NEXT:    s_flbit_i32_b32 s5, s3
1011; GCN-IR-NEXT:    s_add_i32 s4, s4, 32
1012; GCN-IR-NEXT:    s_min_u32 s8, s4, s5
1013; GCN-IR-NEXT:    s_add_u32 s6, s8, 0xffffffc5
1014; GCN-IR-NEXT:    s_addc_u32 s7, 0, -1
1015; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
1016; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[12:13], s[6:7], 63
1017; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0
1018; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
1019; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[12:13], s[6:7], 63
1020; GCN-IR-NEXT:    s_xor_b64 s[14:15], s[10:11], -1
1021; GCN-IR-NEXT:    s_and_b64 s[12:13], s[14:15], s[12:13]
1022; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
1023; GCN-IR-NEXT:    s_cbranch_vccz .LBB8_5
1024; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1025; GCN-IR-NEXT:    s_add_u32 s10, s6, 1
1026; GCN-IR-NEXT:    s_addc_u32 s11, s7, 0
1027; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[10:11], 0
1028; GCN-IR-NEXT:    s_sub_i32 s6, 63, s6
1029; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[12:13]
1030; GCN-IR-NEXT:    s_lshl_b64 s[6:7], 24, s6
1031; GCN-IR-NEXT:    s_cbranch_vccz .LBB8_4
1032; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1033; GCN-IR-NEXT:    s_lshr_b64 s[10:11], 24, s10
1034; GCN-IR-NEXT:    s_add_u32 s14, s2, -1
1035; GCN-IR-NEXT:    s_addc_u32 s15, s3, -1
1036; GCN-IR-NEXT:    s_sub_u32 s8, 58, s8
1037; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
1038; GCN-IR-NEXT:    s_mov_b64 s[12:13], 0
1039; GCN-IR-NEXT:    s_mov_b32 s5, 0
1040; GCN-IR-NEXT:  .LBB8_3: ; %udiv-do-while
1041; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1042; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
1043; GCN-IR-NEXT:    s_lshr_b32 s4, s7, 31
1044; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[6:7], 1
1045; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[4:5]
1046; GCN-IR-NEXT:    s_or_b64 s[6:7], s[12:13], s[6:7]
1047; GCN-IR-NEXT:    s_sub_u32 s4, s14, s10
1048; GCN-IR-NEXT:    s_subb_u32 s4, s15, s11
1049; GCN-IR-NEXT:    s_ashr_i32 s12, s4, 31
1050; GCN-IR-NEXT:    s_mov_b32 s13, s12
1051; GCN-IR-NEXT:    s_and_b32 s4, s12, 1
1052; GCN-IR-NEXT:    s_and_b64 s[12:13], s[12:13], s[2:3]
1053; GCN-IR-NEXT:    s_sub_u32 s10, s10, s12
1054; GCN-IR-NEXT:    s_subb_u32 s11, s11, s13
1055; GCN-IR-NEXT:    s_add_u32 s8, s8, 1
1056; GCN-IR-NEXT:    s_addc_u32 s9, s9, 0
1057; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[16:17], s[8:9], 0
1058; GCN-IR-NEXT:    s_mov_b64 s[12:13], s[4:5]
1059; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[16:17]
1060; GCN-IR-NEXT:    s_cbranch_vccz .LBB8_3
1061; GCN-IR-NEXT:  .LBB8_4: ; %Flow5
1062; GCN-IR-NEXT:    s_lshl_b64 s[2:3], s[6:7], 1
1063; GCN-IR-NEXT:    s_or_b64 s[2:3], s[4:5], s[2:3]
1064; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1065; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
1066; GCN-IR-NEXT:    s_branch .LBB8_6
1067; GCN-IR-NEXT:  .LBB8_5:
1068; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1069; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, 24, 0, s[10:11]
1070; GCN-IR-NEXT:  .LBB8_6: ; %udiv-end
1071; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1072; GCN-IR-NEXT:    s_mov_b32 s2, -1
1073; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1074; GCN-IR-NEXT:    s_endpgm
1075  %result = udiv i64 24, %x
1076  store i64 %result, i64 addrspace(1)* %out
1077  ret void
1078}
1079
1080; define i64 @v_test_udiv_k_num_i64(i64 %x) {
1081;   %result = udiv i64 24, %x
1082;   ret i64 %result
1083; }
1084
1085define i64 @v_test_udiv_pow2_k_num_i64(i64 %x) {
1086; GCN-LABEL: v_test_udiv_pow2_k_num_i64:
1087; GCN:       ; %bb.0:
1088; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1089; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1090; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1091; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1092; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1093; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
1094; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1095; GCN-NEXT:    v_mov_b32_e32 v11, 0
1096; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1097; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1098; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1099; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1100; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1101; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1102; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1103; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1104; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1105; GCN-NEXT:    v_mul_lo_u32 v9, v4, v2
1106; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1107; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1108; GCN-NEXT:    v_mul_lo_u32 v7, v2, v6
1109; GCN-NEXT:    v_mul_hi_u32 v8, v2, v9
1110; GCN-NEXT:    v_mul_hi_u32 v10, v2, v6
1111; GCN-NEXT:    v_mul_hi_u32 v12, v3, v6
1112; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1113; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1114; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v10, vcc
1115; GCN-NEXT:    v_mul_lo_u32 v10, v3, v9
1116; GCN-NEXT:    v_mul_hi_u32 v9, v3, v9
1117; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
1118; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v9, vcc
1119; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v11, vcc
1120; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1121; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
1122; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
1123; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v7, vcc
1124; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1125; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1126; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1127; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1128; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1129; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
1130; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
1131; GCN-NEXT:    v_mul_hi_u32 v9, v2, v4
1132; GCN-NEXT:    v_mul_hi_u32 v10, v2, v5
1133; GCN-NEXT:    v_mul_hi_u32 v7, v3, v4
1134; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1135; GCN-NEXT:    v_mul_hi_u32 v6, v3, v5
1136; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1137; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
1138; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
1139; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
1140; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
1141; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v11, vcc
1142; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1143; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
1144; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1145; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v3, v5, vcc
1146; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1147; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
1148; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1149; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1150; GCN-NEXT:    v_mul_lo_u32 v4, v0, v2
1151; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v3
1152; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0x8000, v4
1153; GCN-NEXT:    v_subb_u32_e64 v5, s[4:5], v5, v1, vcc
1154; GCN-NEXT:    v_sub_i32_e64 v6, s[4:5], v4, v0
1155; GCN-NEXT:    v_subbrev_u32_e64 v5, s[4:5], 0, v5, s[4:5]
1156; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v5, v1
1157; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
1158; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v0
1159; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
1160; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v5, v1
1161; GCN-NEXT:    v_cndmask_b32_e64 v5, v7, v6, s[4:5]
1162; GCN-NEXT:    v_add_i32_e64 v6, s[4:5], 2, v2
1163; GCN-NEXT:    v_addc_u32_e64 v7, s[4:5], 0, 0, s[4:5]
1164; GCN-NEXT:    v_add_i32_e64 v8, s[4:5], 1, v2
1165; GCN-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, 0, s[4:5]
1166; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1167; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v5
1168; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1169; GCN-NEXT:    v_cndmask_b32_e64 v5, v8, v6, s[4:5]
1170; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1171; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v0
1172; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1173; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1174; GCN-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
1175; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1176; GCN-NEXT:    v_cndmask_b32_e64 v1, v9, v7, s[4:5]
1177; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1178; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
1179; GCN-NEXT:    s_setpc_b64 s[30:31]
1180;
1181; GCN-IR-LABEL: v_test_udiv_pow2_k_num_i64:
1182; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1183; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1184; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1185; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1186; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1187; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1188; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 0xffffffd0, v6
1189; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[6:7], 0, -1, vcc
1190; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1191; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[4:5]
1192; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0x8000
1193; GCN-IR-NEXT:    v_mov_b32_e32 v2, s8
1194; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1195; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1196; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1197; GCN-IR-NEXT:    v_cndmask_b32_e64 v2, v2, 0, s[4:5]
1198; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1199; GCN-IR-NEXT:    v_mov_b32_e32 v3, v7
1200; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1201; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1202; GCN-IR-NEXT:    s_cbranch_execz .LBB9_6
1203; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1204; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
1205; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
1206; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v4
1207; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[8:9]
1208; GCN-IR-NEXT:    v_lshl_b64 v[2:3], s[8:9], v2
1209; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1210; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1211; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1212; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1213; GCN-IR-NEXT:    s_cbranch_execz .LBB9_5
1214; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1215; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, -1, v0
1216; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0x8000
1217; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, -1, v1, vcc
1218; GCN-IR-NEXT:    v_lshr_b64 v[8:9], s[4:5], v8
1219; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, 47, v6
1220; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1221; GCN-IR-NEXT:    v_subb_u32_e32 v7, vcc, 0, v7, vcc
1222; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1223; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1224; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1225; GCN-IR-NEXT:  .LBB9_3: ; %udiv-do-while
1226; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1227; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1228; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1229; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1230; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1231; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, v12, v8
1232; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, v13, v9, vcc
1233; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1234; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1235; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 1, v6
1236; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1237; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1238; GCN-IR-NEXT:    v_and_b32_e32 v11, v10, v1
1239; GCN-IR-NEXT:    v_and_b32_e32 v10, v10, v0
1240; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
1241; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[6:7]
1242; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v10
1243; GCN-IR-NEXT:    v_subb_u32_e64 v9, s[4:5], v9, v11, s[4:5]
1244; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1245; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1246; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1247; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1248; GCN-IR-NEXT:    s_cbranch_execnz .LBB9_3
1249; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1250; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1251; GCN-IR-NEXT:  .LBB9_5: ; %Flow3
1252; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1253; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[2:3], 1
1254; GCN-IR-NEXT:    v_or_b32_e32 v3, v5, v1
1255; GCN-IR-NEXT:    v_or_b32_e32 v2, v4, v0
1256; GCN-IR-NEXT:  .LBB9_6: ; %Flow4
1257; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1258; GCN-IR-NEXT:    v_mov_b32_e32 v0, v2
1259; GCN-IR-NEXT:    v_mov_b32_e32 v1, v3
1260; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1261  %result = udiv i64 32768, %x
1262  ret i64 %result
1263}
1264
1265define i64 @v_test_udiv_pow2_k_den_i64(i64 %x) {
1266; GCN-LABEL: v_test_udiv_pow2_k_den_i64:
1267; GCN:       ; %bb.0:
1268; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1269; GCN-NEXT:    v_alignbit_b32 v0, v1, v0, 15
1270; GCN-NEXT:    v_lshrrev_b32_e32 v1, 15, v1
1271; GCN-NEXT:    s_setpc_b64 s[30:31]
1272;
1273; GCN-IR-LABEL: v_test_udiv_pow2_k_den_i64:
1274; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1275; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1276; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1277; GCN-IR-NEXT:    v_add_i32_e64 v2, s[4:5], 32, v2
1278; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1279; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1280; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 48, v6
1281; GCN-IR-NEXT:    v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5]
1282; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1283; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
1284; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1285; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1286; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1287; GCN-IR-NEXT:    v_cndmask_b32_e64 v2, v1, 0, s[4:5]
1288; GCN-IR-NEXT:    v_cndmask_b32_e64 v3, v0, 0, s[4:5]
1289; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1290; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1291; GCN-IR-NEXT:    s_cbranch_execz .LBB10_6
1292; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1293; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 1, v4
1294; GCN-IR-NEXT:    v_addc_u32_e32 v8, vcc, 0, v5, vcc
1295; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v4
1296; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[7:8]
1297; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[0:1], v2
1298; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1299; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1300; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1301; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1302; GCN-IR-NEXT:    s_cbranch_execz .LBB10_5
1303; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1304; GCN-IR-NEXT:    v_lshr_b64 v[7:8], v[0:1], v7
1305; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, 0xffffffcf, v6
1306; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1307; GCN-IR-NEXT:    v_addc_u32_e64 v1, s[4:5], 0, -1, vcc
1308; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1309; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1310; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1311; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
1312; GCN-IR-NEXT:  .LBB10_3: ; %udiv-do-while
1313; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1314; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
1315; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1316; GCN-IR-NEXT:    v_or_b32_e32 v6, v7, v4
1317; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, s12, v6
1318; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, 0, v8, vcc
1319; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, 1, v0
1320; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1321; GCN-IR-NEXT:    v_ashrrev_i32_e32 v7, 31, v4
1322; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1323; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v7
1324; GCN-IR-NEXT:    v_and_b32_e32 v7, 0x8000, v7
1325; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1326; GCN-IR-NEXT:    v_or_b32_e32 v3, v10, v3
1327; GCN-IR-NEXT:    v_or_b32_e32 v2, v9, v2
1328; GCN-IR-NEXT:    v_sub_i32_e64 v7, s[4:5], v6, v7
1329; GCN-IR-NEXT:    v_mov_b32_e32 v10, v5
1330; GCN-IR-NEXT:    v_subbrev_u32_e64 v8, s[4:5], 0, v8, s[4:5]
1331; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1332; GCN-IR-NEXT:    v_mov_b32_e32 v9, v4
1333; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1334; GCN-IR-NEXT:    s_cbranch_execnz .LBB10_3
1335; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1336; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1337; GCN-IR-NEXT:  .LBB10_5: ; %Flow3
1338; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1339; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[2:3], 1
1340; GCN-IR-NEXT:    v_or_b32_e32 v2, v5, v1
1341; GCN-IR-NEXT:    v_or_b32_e32 v3, v4, v0
1342; GCN-IR-NEXT:  .LBB10_6: ; %Flow4
1343; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1344; GCN-IR-NEXT:    v_mov_b32_e32 v0, v3
1345; GCN-IR-NEXT:    v_mov_b32_e32 v1, v2
1346; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1347  %result = udiv i64 %x, 32768
1348  ret i64 %result
1349}
1350
1351define amdgpu_kernel void @s_test_udiv_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
1352; GCN-LABEL: s_test_udiv_k_den_i64:
1353; GCN:       ; %bb.0:
1354; GCN-NEXT:    v_mov_b32_e32 v0, 0x4f800000
1355; GCN-NEXT:    v_madak_f32 v0, 0, v0, 0x41c00000
1356; GCN-NEXT:    v_rcp_f32_e32 v0, v0
1357; GCN-NEXT:    s_movk_i32 s4, 0xffe8
1358; GCN-NEXT:    v_mov_b32_e32 v7, 0
1359; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1360; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
1361; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
1362; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1363; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
1364; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
1365; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
1366; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1367; GCN-NEXT:    s_mov_b32 s5, s1
1368; GCN-NEXT:    s_mov_b32 s7, 0xf000
1369; GCN-NEXT:    v_mul_hi_u32 v2, v0, s4
1370; GCN-NEXT:    v_mul_lo_u32 v3, v1, s4
1371; GCN-NEXT:    v_mul_lo_u32 v4, v0, s4
1372; GCN-NEXT:    s_mov_b32 s6, -1
1373; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
1374; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1375; GCN-NEXT:    v_mul_lo_u32 v3, v0, v2
1376; GCN-NEXT:    v_mul_hi_u32 v5, v0, v4
1377; GCN-NEXT:    v_mul_hi_u32 v6, v0, v2
1378; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
1379; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
1380; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
1381; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
1382; GCN-NEXT:    v_mul_lo_u32 v6, v1, v4
1383; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
1384; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
1385; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
1386; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
1387; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1388; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
1389; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1390; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
1391; GCN-NEXT:    v_mul_hi_u32 v2, v0, s4
1392; GCN-NEXT:    v_mul_lo_u32 v3, v1, s4
1393; GCN-NEXT:    v_mul_lo_u32 v4, v0, s4
1394; GCN-NEXT:    s_mov_b32 s4, s0
1395; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
1396; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
1397; GCN-NEXT:    v_mul_lo_u32 v3, v0, v2
1398; GCN-NEXT:    v_mul_hi_u32 v5, v0, v4
1399; GCN-NEXT:    v_mul_hi_u32 v6, v0, v2
1400; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
1401; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
1402; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
1403; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
1404; GCN-NEXT:    v_mul_lo_u32 v6, v1, v4
1405; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
1406; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
1407; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
1408; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v7, vcc
1409; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1410; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
1411; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1412; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
1413; GCN-NEXT:    v_mul_lo_u32 v2, s2, v1
1414; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
1415; GCN-NEXT:    v_mul_hi_u32 v4, s2, v1
1416; GCN-NEXT:    v_mul_hi_u32 v5, s3, v1
1417; GCN-NEXT:    v_mul_lo_u32 v1, s3, v1
1418; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1419; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
1420; GCN-NEXT:    v_mul_lo_u32 v4, s3, v0
1421; GCN-NEXT:    v_mul_hi_u32 v0, s3, v0
1422; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1423; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
1424; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
1425; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1426; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
1427; GCN-NEXT:    v_mul_lo_u32 v4, v1, 24
1428; GCN-NEXT:    v_mul_hi_u32 v5, v0, 24
1429; GCN-NEXT:    v_add_i32_e32 v2, vcc, 2, v0
1430; GCN-NEXT:    v_mul_lo_u32 v8, v0, 24
1431; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
1432; GCN-NEXT:    v_add_i32_e32 v6, vcc, 1, v0
1433; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v1, vcc
1434; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1435; GCN-NEXT:    v_mov_b32_e32 v5, s3
1436; GCN-NEXT:    v_sub_i32_e32 v8, vcc, s2, v8
1437; GCN-NEXT:    v_subb_u32_e32 v4, vcc, v5, v4, vcc
1438; GCN-NEXT:    v_subrev_i32_e32 v5, vcc, 24, v8
1439; GCN-NEXT:    v_subbrev_u32_e32 v9, vcc, 0, v4, vcc
1440; GCN-NEXT:    v_cmp_lt_u32_e32 vcc, 23, v5
1441; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
1442; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v9
1443; GCN-NEXT:    v_cndmask_b32_e32 v5, -1, v5, vcc
1444; GCN-NEXT:    v_cmp_lt_u32_e64 s[0:1], 23, v8
1445; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
1446; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
1447; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v4
1448; GCN-NEXT:    v_cndmask_b32_e64 v4, -1, v5, s[0:1]
1449; GCN-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
1450; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
1451; GCN-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
1452; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
1453; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
1454; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1455; GCN-NEXT:    s_endpgm
1456;
1457; GCN-IR-LABEL: s_test_udiv_k_den_i64:
1458; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1459; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1460; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1461; GCN-IR-NEXT:    s_flbit_i32_b32 s4, s2
1462; GCN-IR-NEXT:    s_flbit_i32_b32 s5, s3
1463; GCN-IR-NEXT:    s_add_i32 s4, s4, 32
1464; GCN-IR-NEXT:    s_min_u32 s10, s4, s5
1465; GCN-IR-NEXT:    s_sub_u32 s6, 59, s10
1466; GCN-IR-NEXT:    s_subb_u32 s7, 0, 0
1467; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[2:3], 0
1468; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[12:13], s[6:7], 63
1469; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0
1470; GCN-IR-NEXT:    s_or_b64 s[8:9], s[8:9], s[12:13]
1471; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[12:13], s[6:7], 63
1472; GCN-IR-NEXT:    s_xor_b64 s[14:15], s[8:9], -1
1473; GCN-IR-NEXT:    s_and_b64 s[12:13], s[14:15], s[12:13]
1474; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
1475; GCN-IR-NEXT:    s_cbranch_vccz .LBB11_5
1476; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1477; GCN-IR-NEXT:    s_add_u32 s8, s6, 1
1478; GCN-IR-NEXT:    s_addc_u32 s9, s7, 0
1479; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[8:9], 0
1480; GCN-IR-NEXT:    s_sub_i32 s6, 63, s6
1481; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[12:13]
1482; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[2:3], s6
1483; GCN-IR-NEXT:    s_cbranch_vccz .LBB11_4
1484; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1485; GCN-IR-NEXT:    s_lshr_b64 s[8:9], s[2:3], s8
1486; GCN-IR-NEXT:    s_add_u32 s2, s10, 0xffffffc4
1487; GCN-IR-NEXT:    s_addc_u32 s3, 0, -1
1488; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1489; GCN-IR-NEXT:    s_mov_b32 s5, 0
1490; GCN-IR-NEXT:  .LBB11_3: ; %udiv-do-while
1491; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1492; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
1493; GCN-IR-NEXT:    s_lshr_b32 s4, s7, 31
1494; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[6:7], 1
1495; GCN-IR-NEXT:    s_or_b64 s[8:9], s[8:9], s[4:5]
1496; GCN-IR-NEXT:    s_or_b64 s[6:7], s[10:11], s[6:7]
1497; GCN-IR-NEXT:    s_sub_u32 s4, 23, s8
1498; GCN-IR-NEXT:    s_subb_u32 s4, 0, s9
1499; GCN-IR-NEXT:    s_ashr_i32 s10, s4, 31
1500; GCN-IR-NEXT:    s_and_b32 s4, s10, 1
1501; GCN-IR-NEXT:    s_and_b32 s10, s10, 24
1502; GCN-IR-NEXT:    s_sub_u32 s8, s8, s10
1503; GCN-IR-NEXT:    s_subb_u32 s9, s9, 0
1504; GCN-IR-NEXT:    s_add_u32 s2, s2, 1
1505; GCN-IR-NEXT:    s_addc_u32 s3, s3, 0
1506; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[2:3], 0
1507; GCN-IR-NEXT:    s_mov_b64 s[10:11], s[4:5]
1508; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
1509; GCN-IR-NEXT:    s_cbranch_vccz .LBB11_3
1510; GCN-IR-NEXT:  .LBB11_4: ; %Flow5
1511; GCN-IR-NEXT:    s_lshl_b64 s[2:3], s[6:7], 1
1512; GCN-IR-NEXT:    s_or_b64 s[2:3], s[4:5], s[2:3]
1513; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1514; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
1515; GCN-IR-NEXT:    s_branch .LBB11_6
1516; GCN-IR-NEXT:  .LBB11_5:
1517; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
1518; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[8:9]
1519; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1520; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[8:9]
1521; GCN-IR-NEXT:  .LBB11_6: ; %udiv-end
1522; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1523; GCN-IR-NEXT:    s_mov_b32 s2, -1
1524; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1525; GCN-IR-NEXT:    s_endpgm
1526  %result = udiv i64 %x, 24
1527  store i64 %result, i64 addrspace(1)* %out
1528  ret void
1529}
1530
1531define i64 @v_test_udiv_k_den_i64(i64 %x) {
1532; GCN-LABEL: v_test_udiv_k_den_i64:
1533; GCN:       ; %bb.0:
1534; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1535; GCN-NEXT:    v_mov_b32_e32 v2, 0x4f800000
1536; GCN-NEXT:    v_madak_f32 v2, 0, v2, 0x41c00000
1537; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1538; GCN-NEXT:    s_movk_i32 s4, 0xffe8
1539; GCN-NEXT:    v_mov_b32_e32 v8, 0
1540; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1541; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1542; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1543; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1544; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1545; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1546; GCN-NEXT:    v_mul_hi_u32 v4, v2, s4
1547; GCN-NEXT:    v_mul_lo_u32 v6, v3, s4
1548; GCN-NEXT:    v_mul_lo_u32 v5, v2, s4
1549; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, v2, v4
1550; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
1551; GCN-NEXT:    v_mul_hi_u32 v7, v2, v5
1552; GCN-NEXT:    v_mul_lo_u32 v6, v2, v4
1553; GCN-NEXT:    v_mul_hi_u32 v9, v2, v4
1554; GCN-NEXT:    v_mul_hi_u32 v10, v3, v4
1555; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1556; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1557; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v9, vcc
1558; GCN-NEXT:    v_mul_lo_u32 v9, v3, v5
1559; GCN-NEXT:    v_mul_hi_u32 v5, v3, v5
1560; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
1561; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v5, vcc
1562; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v8, vcc
1563; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1564; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
1565; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1566; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
1567; GCN-NEXT:    v_mul_hi_u32 v4, v2, s4
1568; GCN-NEXT:    v_mul_lo_u32 v5, v3, s4
1569; GCN-NEXT:    v_mul_lo_u32 v6, v2, s4
1570; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, v2, v4
1571; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1572; GCN-NEXT:    v_mul_lo_u32 v5, v2, v4
1573; GCN-NEXT:    v_mul_hi_u32 v7, v2, v6
1574; GCN-NEXT:    v_mul_hi_u32 v9, v2, v4
1575; GCN-NEXT:    v_mul_hi_u32 v10, v3, v4
1576; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1577; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
1578; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v9, vcc
1579; GCN-NEXT:    v_mul_lo_u32 v9, v3, v6
1580; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
1581; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
1582; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
1583; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v8, vcc
1584; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1585; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
1586; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1587; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
1588; GCN-NEXT:    v_mul_lo_u32 v4, v0, v3
1589; GCN-NEXT:    v_mul_hi_u32 v5, v0, v2
1590; GCN-NEXT:    v_mul_hi_u32 v6, v0, v3
1591; GCN-NEXT:    v_mul_hi_u32 v7, v1, v3
1592; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
1593; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1594; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
1595; GCN-NEXT:    v_mul_lo_u32 v6, v1, v2
1596; GCN-NEXT:    v_mul_hi_u32 v2, v1, v2
1597; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
1598; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v2, vcc
1599; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v8, vcc
1600; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
1601; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
1602; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
1603; GCN-NEXT:    v_mul_hi_u32 v5, v2, 24
1604; GCN-NEXT:    v_mul_lo_u32 v6, v2, 24
1605; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1606; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
1607; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc
1608; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, 24, v0
1609; GCN-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v1, vcc
1610; GCN-NEXT:    v_cmp_lt_u32_e32 vcc, 23, v4
1611; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
1612; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v5
1613; GCN-NEXT:    v_cndmask_b32_e32 v4, -1, v4, vcc
1614; GCN-NEXT:    v_add_i32_e32 v5, vcc, 2, v2
1615; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v3, vcc
1616; GCN-NEXT:    v_add_i32_e32 v7, vcc, 1, v2
1617; GCN-NEXT:    v_cmp_lt_u32_e64 s[4:5], 23, v0
1618; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v3, vcc
1619; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, s[4:5]
1620; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v1
1621; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
1622; GCN-NEXT:    v_cndmask_b32_e64 v0, -1, v0, s[4:5]
1623; GCN-NEXT:    v_cndmask_b32_e32 v4, v7, v5, vcc
1624; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v0
1625; GCN-NEXT:    v_cndmask_b32_e32 v1, v8, v6, vcc
1626; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, v4, s[4:5]
1627; GCN-NEXT:    v_cndmask_b32_e64 v1, v3, v1, s[4:5]
1628; GCN-NEXT:    s_setpc_b64 s[30:31]
1629;
1630; GCN-IR-LABEL: v_test_udiv_k_den_i64:
1631; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1632; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1633; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1634; GCN-IR-NEXT:    v_add_i32_e64 v2, s[4:5], 32, v2
1635; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1636; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1637; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 59, v6
1638; GCN-IR-NEXT:    v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5]
1639; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1640; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
1641; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1642; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1643; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1644; GCN-IR-NEXT:    v_cndmask_b32_e64 v2, v1, 0, s[4:5]
1645; GCN-IR-NEXT:    v_cndmask_b32_e64 v3, v0, 0, s[4:5]
1646; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1647; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1648; GCN-IR-NEXT:    s_cbranch_execz .LBB12_6
1649; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1650; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 1, v4
1651; GCN-IR-NEXT:    v_addc_u32_e32 v8, vcc, 0, v5, vcc
1652; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v4
1653; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[7:8]
1654; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[0:1], v2
1655; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1656; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1657; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1658; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1659; GCN-IR-NEXT:    s_cbranch_execz .LBB12_5
1660; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1661; GCN-IR-NEXT:    v_lshr_b64 v[7:8], v[0:1], v7
1662; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, 0xffffffc4, v6
1663; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1664; GCN-IR-NEXT:    v_addc_u32_e64 v1, s[4:5], 0, -1, vcc
1665; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1666; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1667; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1668; GCN-IR-NEXT:  .LBB12_3: ; %udiv-do-while
1669; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1670; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
1671; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1672; GCN-IR-NEXT:    v_or_b32_e32 v6, v7, v4
1673; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, 23, v6
1674; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, 0, v8, vcc
1675; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, 1, v0
1676; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1677; GCN-IR-NEXT:    v_ashrrev_i32_e32 v7, 31, v4
1678; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1679; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v7
1680; GCN-IR-NEXT:    v_and_b32_e32 v7, 24, v7
1681; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1682; GCN-IR-NEXT:    v_or_b32_e32 v3, v10, v3
1683; GCN-IR-NEXT:    v_or_b32_e32 v2, v9, v2
1684; GCN-IR-NEXT:    v_sub_i32_e64 v7, s[4:5], v6, v7
1685; GCN-IR-NEXT:    v_mov_b32_e32 v10, v5
1686; GCN-IR-NEXT:    v_subbrev_u32_e64 v8, s[4:5], 0, v8, s[4:5]
1687; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1688; GCN-IR-NEXT:    v_mov_b32_e32 v9, v4
1689; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1690; GCN-IR-NEXT:    s_cbranch_execnz .LBB12_3
1691; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1692; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1693; GCN-IR-NEXT:  .LBB12_5: ; %Flow3
1694; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1695; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[2:3], 1
1696; GCN-IR-NEXT:    v_or_b32_e32 v2, v5, v1
1697; GCN-IR-NEXT:    v_or_b32_e32 v3, v4, v0
1698; GCN-IR-NEXT:  .LBB12_6: ; %Flow4
1699; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1700; GCN-IR-NEXT:    v_mov_b32_e32 v0, v3
1701; GCN-IR-NEXT:    v_mov_b32_e32 v1, v2
1702; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1703  %result = udiv i64 %x, 24
1704  ret i64 %result
1705}
1706
1707define amdgpu_kernel void @s_test_udiv24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1708; GCN-LABEL: s_test_udiv24_k_num_i64:
1709; GCN:       ; %bb.0:
1710; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1711; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
1712; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1713; GCN-NEXT:    s_lshr_b32 s2, s3, 8
1714; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
1715; GCN-NEXT:    s_mov_b32 s3, 0xf000
1716; GCN-NEXT:    s_mov_b32 s2, -1
1717; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1718; GCN-NEXT:    v_mul_f32_e32 v1, s4, v1
1719; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1720; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1721; GCN-NEXT:    v_mad_f32 v1, -v1, v0, s4
1722; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1723; GCN-NEXT:    v_mov_b32_e32 v1, 0
1724; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1725; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1726; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1727; GCN-NEXT:    s_endpgm
1728;
1729; GCN-IR-LABEL: s_test_udiv24_k_num_i64:
1730; GCN-IR:       ; %bb.0:
1731; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1732; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
1733; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1734; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 8
1735; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
1736; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1737; GCN-IR-NEXT:    s_mov_b32 s2, -1
1738; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1739; GCN-IR-NEXT:    v_mul_f32_e32 v1, s4, v1
1740; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1741; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1742; GCN-IR-NEXT:    v_mad_f32 v1, -v1, v0, s4
1743; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1744; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1745; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1746; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1747; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1748; GCN-IR-NEXT:    s_endpgm
1749  %x.shr = lshr i64 %x, 40
1750  %result = udiv i64 24, %x.shr
1751  store i64 %result, i64 addrspace(1)* %out
1752  ret void
1753}
1754
1755define amdgpu_kernel void @s_test_udiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
1756; GCN-LABEL: s_test_udiv24_k_den_i64:
1757; GCN:       ; %bb.0:
1758; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1759; GCN-NEXT:    s_mov_b32 s7, 0xf000
1760; GCN-NEXT:    s_mov_b32 s6, -1
1761; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1762; GCN-NEXT:    s_lshr_b32 s2, s3, 8
1763; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
1764; GCN-NEXT:    s_mov_b32 s2, 0x46b6fe00
1765; GCN-NEXT:    s_mov_b32 s4, s0
1766; GCN-NEXT:    s_mov_b32 s5, s1
1767; GCN-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1768; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1769; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1770; GCN-NEXT:    v_mad_f32 v0, -v1, s2, v0
1771; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s2
1772; GCN-NEXT:    v_mov_b32_e32 v1, 0
1773; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1774; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1775; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1776; GCN-NEXT:    s_endpgm
1777;
1778; GCN-IR-LABEL: s_test_udiv24_k_den_i64:
1779; GCN-IR:       ; %bb.0:
1780; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1781; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1782; GCN-IR-NEXT:    s_mov_b32 s6, -1
1783; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1784; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 8
1785; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
1786; GCN-IR-NEXT:    s_mov_b32 s2, 0x46b6fe00
1787; GCN-IR-NEXT:    s_mov_b32 s4, s0
1788; GCN-IR-NEXT:    s_mov_b32 s5, s1
1789; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1790; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1791; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1792; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s2, v0
1793; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s2
1794; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1795; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1796; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1797; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1798; GCN-IR-NEXT:    s_endpgm
1799  %x.shr = lshr i64 %x, 40
1800  %result = udiv i64 %x.shr, 23423
1801  store i64 %result, i64 addrspace(1)* %out
1802  ret void
1803}
1804
1805define i64 @v_test_udiv24_k_num_i64(i64 %x) {
1806; GCN-LABEL: v_test_udiv24_k_num_i64:
1807; GCN:       ; %bb.0:
1808; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1809; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1810; GCN-NEXT:    v_cvt_f32_u32_e32 v0, v0
1811; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
1812; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1813; GCN-NEXT:    v_mul_f32_e32 v1, s4, v1
1814; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1815; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1816; GCN-NEXT:    v_mad_f32 v1, -v1, v0, s4
1817; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1818; GCN-NEXT:    v_mov_b32_e32 v1, 0
1819; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1820; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1821; GCN-NEXT:    s_setpc_b64 s[30:31]
1822;
1823; GCN-IR-LABEL: v_test_udiv24_k_num_i64:
1824; GCN-IR:       ; %bb.0:
1825; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1826; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1827; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, v0
1828; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
1829; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1830; GCN-IR-NEXT:    v_mul_f32_e32 v1, s4, v1
1831; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1832; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1833; GCN-IR-NEXT:    v_mad_f32 v1, -v1, v0, s4
1834; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1835; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1836; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1837; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1838; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1839  %x.shr = lshr i64 %x, 40
1840  %result = udiv i64 24, %x.shr
1841  ret i64 %result
1842}
1843
1844define i64 @v_test_udiv24_pow2_k_num_i64(i64 %x) {
1845; GCN-LABEL: v_test_udiv24_pow2_k_num_i64:
1846; GCN:       ; %bb.0:
1847; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1848; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1849; GCN-NEXT:    v_cvt_f32_u32_e32 v0, v0
1850; GCN-NEXT:    s_mov_b32 s4, 0x47000000
1851; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1852; GCN-NEXT:    v_mul_f32_e32 v1, s4, v1
1853; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1854; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1855; GCN-NEXT:    v_mad_f32 v1, -v1, v0, s4
1856; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1857; GCN-NEXT:    v_mov_b32_e32 v1, 0
1858; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1859; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1860; GCN-NEXT:    s_setpc_b64 s[30:31]
1861;
1862; GCN-IR-LABEL: v_test_udiv24_pow2_k_num_i64:
1863; GCN-IR:       ; %bb.0:
1864; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1865; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1866; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, v0
1867; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
1868; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1869; GCN-IR-NEXT:    v_mul_f32_e32 v1, s4, v1
1870; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1871; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1872; GCN-IR-NEXT:    v_mad_f32 v1, -v1, v0, s4
1873; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1874; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1875; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1876; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1877; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1878  %x.shr = lshr i64 %x, 40
1879  %result = udiv i64 32768, %x.shr
1880  ret i64 %result
1881}
1882
1883define i64 @v_test_udiv24_pow2_k_den_i64(i64 %x) {
1884; GCN-LABEL: v_test_udiv24_pow2_k_den_i64:
1885; GCN:       ; %bb.0:
1886; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1887; GCN-NEXT:    v_lshrrev_b32_e32 v0, 23, v1
1888; GCN-NEXT:    v_mov_b32_e32 v1, 0
1889; GCN-NEXT:    s_setpc_b64 s[30:31]
1890;
1891; GCN-IR-LABEL: v_test_udiv24_pow2_k_den_i64:
1892; GCN-IR:       ; %bb.0:
1893; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1894; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1895; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, v0
1896; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
1897; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38000000, v0
1898; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1899; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1900; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s4, v0
1901; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
1902; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1903; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1904; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1905; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1906  %x.shr = lshr i64 %x, 40
1907  %result = udiv i64 %x.shr, 32768
1908  ret i64 %result
1909}
1910