1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s -check-prefixes=SI 3; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -denormal-fp-math-f32=preserve-sign < %s | FileCheck %s -check-prefixes=VI 4; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=fiji -denormal-fp-math-f32=ieee < %s | FileCheck %s -check-prefixes=GCN 5; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=gfx1030 -denormal-fp-math-f32=ieee < %s | FileCheck %s -check-prefixes=GFX1030 6; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefixes=EG 7 8define amdgpu_kernel void @udiv_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { 9; SI-LABEL: udiv_i32: 10; SI: ; %bb.0: 11; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 12; SI-NEXT: s_mov_b32 s7, 0xf000 13; SI-NEXT: s_mov_b32 s6, -1 14; SI-NEXT: s_mov_b32 s10, s6 15; SI-NEXT: s_mov_b32 s11, s7 16; SI-NEXT: s_waitcnt lgkmcnt(0) 17; SI-NEXT: s_mov_b32 s8, s2 18; SI-NEXT: s_mov_b32 s9, s3 19; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0 20; SI-NEXT: s_mov_b32 s4, s0 21; SI-NEXT: s_mov_b32 s5, s1 22; SI-NEXT: s_waitcnt vmcnt(0) 23; SI-NEXT: v_cvt_f32_u32_e32 v2, v1 24; SI-NEXT: v_sub_i32_e32 v3, vcc, 0, v1 25; SI-NEXT: v_rcp_iflag_f32_e32 v2, v2 26; SI-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 27; SI-NEXT: v_cvt_u32_f32_e32 v2, v2 28; SI-NEXT: v_mul_lo_u32 v3, v3, v2 29; SI-NEXT: v_mul_hi_u32 v3, v2, v3 30; SI-NEXT: v_add_i32_e32 v2, vcc, v3, v2 31; SI-NEXT: v_mul_hi_u32 v2, v0, v2 32; SI-NEXT: v_mul_lo_u32 v3, v2, v1 33; SI-NEXT: v_add_i32_e32 v4, vcc, 1, v2 34; SI-NEXT: v_subrev_i32_e32 v0, vcc, v3, v0 35; SI-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v1 36; SI-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1] 37; SI-NEXT: v_subrev_i32_e32 v3, vcc, v1, v0 38; SI-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1] 39; SI-NEXT: v_add_i32_e32 v3, vcc, 1, v2 40; SI-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1 41; SI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc 42; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 43; SI-NEXT: s_endpgm 44; 45; VI-LABEL: udiv_i32: 46; VI: ; %bb.0: 47; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 48; VI-NEXT: s_mov_b32 s7, 0xf000 49; VI-NEXT: s_mov_b32 s6, -1 50; VI-NEXT: s_mov_b32 s10, s6 51; VI-NEXT: s_mov_b32 s11, s7 52; VI-NEXT: s_waitcnt lgkmcnt(0) 53; VI-NEXT: s_mov_b32 s8, s2 54; VI-NEXT: s_mov_b32 s9, s3 55; VI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0 56; VI-NEXT: s_mov_b32 s4, s0 57; VI-NEXT: s_mov_b32 s5, s1 58; VI-NEXT: s_waitcnt vmcnt(0) 59; VI-NEXT: v_cvt_f32_u32_e32 v2, v1 60; VI-NEXT: v_sub_u32_e32 v3, vcc, 0, v1 61; VI-NEXT: v_rcp_iflag_f32_e32 v2, v2 62; VI-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 63; VI-NEXT: v_cvt_u32_f32_e32 v2, v2 64; VI-NEXT: v_mul_lo_u32 v3, v3, v2 65; VI-NEXT: v_mul_hi_u32 v3, v2, v3 66; VI-NEXT: v_add_u32_e32 v2, vcc, v3, v2 67; VI-NEXT: v_mul_hi_u32 v2, v0, v2 68; VI-NEXT: v_mul_lo_u32 v3, v2, v1 69; VI-NEXT: v_add_u32_e32 v4, vcc, 1, v2 70; VI-NEXT: v_subrev_u32_e32 v0, vcc, v3, v0 71; VI-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v1 72; VI-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1] 73; VI-NEXT: v_subrev_u32_e32 v3, vcc, v1, v0 74; VI-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1] 75; VI-NEXT: v_add_u32_e32 v3, vcc, 1, v2 76; VI-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1 77; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc 78; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 79; VI-NEXT: s_endpgm 80; 81; GCN-LABEL: udiv_i32: 82; GCN: ; %bb.0: 83; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 84; GCN-NEXT: s_waitcnt lgkmcnt(0) 85; GCN-NEXT: v_mov_b32_e32 v0, s2 86; GCN-NEXT: v_mov_b32_e32 v1, s3 87; GCN-NEXT: flat_load_dwordx2 v[0:1], v[0:1] 88; GCN-NEXT: s_waitcnt vmcnt(0) 89; GCN-NEXT: v_cvt_f32_u32_e32 v2, v1 90; GCN-NEXT: v_sub_u32_e32 v3, vcc, 0, v1 91; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2 92; GCN-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 93; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 94; GCN-NEXT: v_mul_lo_u32 v3, v3, v2 95; GCN-NEXT: v_mul_hi_u32 v3, v2, v3 96; GCN-NEXT: v_add_u32_e32 v2, vcc, v3, v2 97; GCN-NEXT: v_mul_hi_u32 v4, v0, v2 98; GCN-NEXT: v_mov_b32_e32 v2, s0 99; GCN-NEXT: v_mov_b32_e32 v3, s1 100; GCN-NEXT: v_mul_lo_u32 v5, v4, v1 101; GCN-NEXT: v_add_u32_e32 v6, vcc, 1, v4 102; GCN-NEXT: v_subrev_u32_e32 v0, vcc, v5, v0 103; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v1 104; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[0:1] 105; GCN-NEXT: v_subrev_u32_e32 v5, vcc, v1, v0 106; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v5, s[0:1] 107; GCN-NEXT: v_add_u32_e32 v5, vcc, 1, v4 108; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1 109; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc 110; GCN-NEXT: flat_store_dword v[2:3], v0 111; GCN-NEXT: s_endpgm 112; 113; GFX1030-LABEL: udiv_i32: 114; GFX1030: ; %bb.0: 115; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 116; GFX1030-NEXT: v_mov_b32_e32 v2, 0 117; GFX1030-NEXT: s_waitcnt lgkmcnt(0) 118; GFX1030-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3] 119; GFX1030-NEXT: s_waitcnt vmcnt(0) 120; GFX1030-NEXT: v_cvt_f32_u32_e32 v3, v1 121; GFX1030-NEXT: v_sub_nc_u32_e32 v4, 0, v1 122; GFX1030-NEXT: v_rcp_iflag_f32_e32 v3, v3 123; GFX1030-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3 124; GFX1030-NEXT: v_cvt_u32_f32_e32 v3, v3 125; GFX1030-NEXT: v_mul_lo_u32 v4, v4, v3 126; GFX1030-NEXT: v_mul_hi_u32 v4, v3, v4 127; GFX1030-NEXT: v_add_nc_u32_e32 v3, v3, v4 128; GFX1030-NEXT: v_mul_hi_u32 v3, v0, v3 129; GFX1030-NEXT: v_mul_lo_u32 v4, v3, v1 130; GFX1030-NEXT: v_sub_nc_u32_e32 v0, v0, v4 131; GFX1030-NEXT: v_add_nc_u32_e32 v4, 1, v3 132; GFX1030-NEXT: v_sub_nc_u32_e32 v5, v0, v1 133; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v1 134; GFX1030-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo 135; GFX1030-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo 136; GFX1030-NEXT: v_add_nc_u32_e32 v4, 1, v3 137; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v1 138; GFX1030-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc_lo 139; GFX1030-NEXT: global_store_dword v2, v0, s[0:1] 140; GFX1030-NEXT: s_endpgm 141; 142; EG-LABEL: udiv_i32: 143; EG: ; %bb.0: 144; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] 145; EG-NEXT: TEX 0 @6 146; EG-NEXT: ALU 17, @9, KC0[CB0:0-32], KC1[] 147; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 148; EG-NEXT: CF_END 149; EG-NEXT: PAD 150; EG-NEXT: Fetch clause starting at 6: 151; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1 152; EG-NEXT: ALU clause starting at 8: 153; EG-NEXT: MOV * T0.X, KC0[2].Z, 154; EG-NEXT: ALU clause starting at 9: 155; EG-NEXT: SUB_INT T0.W, 0.0, T0.Y, 156; EG-NEXT: RECIP_UINT * T0.Z, T0.Y, 157; EG-NEXT: MULLO_INT * T0.W, PV.W, PS, 158; EG-NEXT: MULHI * T0.W, T0.Z, PS, 159; EG-NEXT: ADD_INT * T0.W, T0.Z, PS, 160; EG-NEXT: MULHI * T0.Z, T0.X, PV.W, 161; EG-NEXT: MULLO_INT * T0.W, PS, T0.Y, 162; EG-NEXT: SUB_INT * T0.W, T0.X, PS, 163; EG-NEXT: ADD_INT T1.Z, T0.Z, 1, 164; EG-NEXT: SETGE_UINT T1.W, PV.W, T0.Y, 165; EG-NEXT: SUB_INT * T2.W, PV.W, T0.Y, 166; EG-NEXT: CNDE_INT T0.W, PV.W, T0.W, PS, 167; EG-NEXT: CNDE_INT * T1.W, PV.W, T0.Z, PV.Z, 168; EG-NEXT: ADD_INT T2.W, PS, 1, 169; EG-NEXT: SETGE_UINT * T0.W, PV.W, T0.Y, 170; EG-NEXT: CNDE_INT T0.X, PS, T1.W, PV.W, 171; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 172; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 173 %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 174 %a = load i32, i32 addrspace(1)* %in 175 %b = load i32, i32 addrspace(1)* %b_ptr 176 %result = udiv i32 %a, %b 177 store i32 %result, i32 addrspace(1)* %out 178 ret void 179} 180 181define amdgpu_kernel void @s_udiv_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) { 182; SI-LABEL: s_udiv_i32: 183; SI: ; %bb.0: 184; SI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb 185; SI-NEXT: s_mov_b32 s7, 0xf000 186; SI-NEXT: s_mov_b32 s6, -1 187; SI-NEXT: s_waitcnt lgkmcnt(0) 188; SI-NEXT: v_cvt_f32_u32_e32 v0, s3 189; SI-NEXT: s_sub_i32 s4, 0, s3 190; SI-NEXT: v_rcp_iflag_f32_e32 v0, v0 191; SI-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 192; SI-NEXT: v_cvt_u32_f32_e32 v0, v0 193; SI-NEXT: v_mul_lo_u32 v1, s4, v0 194; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 195; SI-NEXT: v_mul_hi_u32 v1, v0, v1 196; SI-NEXT: v_add_i32_e32 v0, vcc, v1, v0 197; SI-NEXT: v_mul_hi_u32 v0, s2, v0 198; SI-NEXT: v_mul_lo_u32 v1, v0, s3 199; SI-NEXT: v_add_i32_e32 v2, vcc, 1, v0 200; SI-NEXT: v_sub_i32_e32 v1, vcc, s2, v1 201; SI-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1 202; SI-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] 203; SI-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1 204; SI-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1] 205; SI-NEXT: v_add_i32_e32 v2, vcc, 1, v0 206; SI-NEXT: v_cmp_le_u32_e32 vcc, s3, v1 207; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 208; SI-NEXT: s_waitcnt lgkmcnt(0) 209; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 210; SI-NEXT: s_endpgm 211; 212; VI-LABEL: s_udiv_i32: 213; VI: ; %bb.0: 214; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c 215; VI-NEXT: s_mov_b32 s7, 0xf000 216; VI-NEXT: s_mov_b32 s6, -1 217; VI-NEXT: s_waitcnt lgkmcnt(0) 218; VI-NEXT: v_cvt_f32_u32_e32 v0, s3 219; VI-NEXT: s_sub_i32 s4, 0, s3 220; VI-NEXT: v_rcp_iflag_f32_e32 v0, v0 221; VI-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 222; VI-NEXT: v_cvt_u32_f32_e32 v0, v0 223; VI-NEXT: v_mul_lo_u32 v1, s4, v0 224; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 225; VI-NEXT: v_mul_hi_u32 v1, v0, v1 226; VI-NEXT: v_add_u32_e32 v0, vcc, v1, v0 227; VI-NEXT: v_mul_hi_u32 v0, s2, v0 228; VI-NEXT: v_mul_lo_u32 v1, v0, s3 229; VI-NEXT: v_add_u32_e32 v2, vcc, 1, v0 230; VI-NEXT: v_sub_u32_e32 v1, vcc, s2, v1 231; VI-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1 232; VI-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] 233; VI-NEXT: v_subrev_u32_e32 v2, vcc, s3, v1 234; VI-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1] 235; VI-NEXT: v_add_u32_e32 v2, vcc, 1, v0 236; VI-NEXT: v_cmp_le_u32_e32 vcc, s3, v1 237; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 238; VI-NEXT: s_waitcnt lgkmcnt(0) 239; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 240; VI-NEXT: s_endpgm 241; 242; GCN-LABEL: s_udiv_i32: 243; GCN: ; %bb.0: 244; GCN-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x8 245; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 246; GCN-NEXT: s_waitcnt lgkmcnt(0) 247; GCN-NEXT: v_cvt_f32_u32_e32 v0, s3 248; GCN-NEXT: s_sub_i32 s0, 0, s3 249; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 250; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 251; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 252; GCN-NEXT: v_mul_lo_u32 v1, s0, v0 253; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 254; GCN-NEXT: v_add_u32_e32 v0, vcc, v1, v0 255; GCN-NEXT: v_mul_hi_u32 v0, s2, v0 256; GCN-NEXT: v_mul_lo_u32 v1, v0, s3 257; GCN-NEXT: v_add_u32_e32 v2, vcc, 1, v0 258; GCN-NEXT: v_sub_u32_e32 v1, vcc, s2, v1 259; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1 260; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] 261; GCN-NEXT: v_subrev_u32_e32 v2, vcc, s3, v1 262; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1] 263; GCN-NEXT: v_add_u32_e32 v2, vcc, 1, v0 264; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v1 265; GCN-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc 266; GCN-NEXT: v_mov_b32_e32 v0, s4 267; GCN-NEXT: v_mov_b32_e32 v1, s5 268; GCN-NEXT: flat_store_dword v[0:1], v2 269; GCN-NEXT: s_endpgm 270; 271; GFX1030-LABEL: s_udiv_i32: 272; GFX1030: ; %bb.0: 273; GFX1030-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8 274; GFX1030-NEXT: s_waitcnt lgkmcnt(0) 275; GFX1030-NEXT: v_cvt_f32_u32_e32 v0, s1 276; GFX1030-NEXT: s_sub_i32 s2, 0, s1 277; GFX1030-NEXT: v_rcp_iflag_f32_e32 v0, v0 278; GFX1030-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 279; GFX1030-NEXT: v_cvt_u32_f32_e32 v0, v0 280; GFX1030-NEXT: v_mul_lo_u32 v1, s2, v0 281; GFX1030-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x0 282; GFX1030-NEXT: v_mul_hi_u32 v1, v0, v1 283; GFX1030-NEXT: v_add_nc_u32_e32 v0, v0, v1 284; GFX1030-NEXT: v_mul_hi_u32 v0, s0, v0 285; GFX1030-NEXT: v_mul_lo_u32 v1, v0, s1 286; GFX1030-NEXT: v_add_nc_u32_e32 v2, 1, v0 287; GFX1030-NEXT: v_sub_nc_u32_e32 v1, s0, v1 288; GFX1030-NEXT: v_subrev_nc_u32_e32 v3, s1, v1 289; GFX1030-NEXT: v_cmp_le_u32_e32 vcc_lo, s1, v1 290; GFX1030-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo 291; GFX1030-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo 292; GFX1030-NEXT: v_mov_b32_e32 v3, 0 293; GFX1030-NEXT: v_add_nc_u32_e32 v2, 1, v0 294; GFX1030-NEXT: v_cmp_le_u32_e32 vcc_lo, s1, v1 295; GFX1030-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo 296; GFX1030-NEXT: s_waitcnt lgkmcnt(0) 297; GFX1030-NEXT: global_store_dword v3, v0, s[2:3] 298; GFX1030-NEXT: s_endpgm 299; 300; EG-LABEL: s_udiv_i32: 301; EG: ; %bb.0: 302; EG-NEXT: ALU 17, @4, KC0[CB0:0-32], KC1[] 303; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 304; EG-NEXT: CF_END 305; EG-NEXT: PAD 306; EG-NEXT: ALU clause starting at 4: 307; EG-NEXT: SUB_INT T0.W, 0.0, KC0[2].W, 308; EG-NEXT: RECIP_UINT * T0.X, KC0[2].W, 309; EG-NEXT: MULLO_INT * T0.Y, PV.W, PS, 310; EG-NEXT: MULHI * T0.Y, T0.X, PS, 311; EG-NEXT: ADD_INT * T0.W, T0.X, PS, 312; EG-NEXT: MULHI * T0.X, KC0[2].Z, PV.W, 313; EG-NEXT: MULLO_INT * T0.Y, PS, KC0[2].W, 314; EG-NEXT: SUB_INT * T0.W, KC0[2].Z, PS, 315; EG-NEXT: SUB_INT T0.Z, PV.W, KC0[2].W, 316; EG-NEXT: SETGE_UINT T1.W, PV.W, KC0[2].W, 317; EG-NEXT: ADD_INT * T2.W, T0.X, 1, 318; EG-NEXT: CNDE_INT T2.W, PV.W, T0.X, PS, 319; EG-NEXT: CNDE_INT * T0.W, PV.W, T0.W, PV.Z, 320; EG-NEXT: SETGE_UINT T0.W, PS, KC0[2].W, 321; EG-NEXT: ADD_INT * T1.W, PV.W, 1, 322; EG-NEXT: CNDE_INT T0.X, PV.W, T2.W, PS, 323; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 324; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 325 %result = udiv i32 %a, %b 326 store i32 %result, i32 addrspace(1)* %out 327 ret void 328} 329 330 331; The code generated by udiv is long and complex and may frequently 332; change. The goal of this test is to make sure the ISel doesn't fail 333; when it gets a v4i32 udiv 334define amdgpu_kernel void @udiv_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { 335; SI-LABEL: udiv_v2i32: 336; SI: ; %bb.0: 337; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 338; SI-NEXT: s_mov_b32 s7, 0xf000 339; SI-NEXT: s_mov_b32 s6, -1 340; SI-NEXT: s_mov_b32 s10, s6 341; SI-NEXT: s_mov_b32 s11, s7 342; SI-NEXT: s_waitcnt lgkmcnt(0) 343; SI-NEXT: s_mov_b32 s8, s2 344; SI-NEXT: s_mov_b32 s9, s3 345; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 346; SI-NEXT: s_mov_b32 s2, 0x4f7ffffe 347; SI-NEXT: s_mov_b32 s4, s0 348; SI-NEXT: s_mov_b32 s5, s1 349; SI-NEXT: s_waitcnt vmcnt(0) 350; SI-NEXT: v_cvt_f32_u32_e32 v4, v2 351; SI-NEXT: v_cvt_f32_u32_e32 v5, v3 352; SI-NEXT: v_sub_i32_e32 v6, vcc, 0, v2 353; SI-NEXT: v_rcp_iflag_f32_e32 v4, v4 354; SI-NEXT: v_rcp_iflag_f32_e32 v5, v5 355; SI-NEXT: v_sub_i32_e32 v7, vcc, 0, v3 356; SI-NEXT: v_mul_f32_e32 v4, s2, v4 357; SI-NEXT: v_mul_f32_e32 v5, s2, v5 358; SI-NEXT: v_cvt_u32_f32_e32 v4, v4 359; SI-NEXT: v_cvt_u32_f32_e32 v5, v5 360; SI-NEXT: v_mul_lo_u32 v6, v6, v4 361; SI-NEXT: v_mul_lo_u32 v7, v7, v5 362; SI-NEXT: v_mul_hi_u32 v6, v4, v6 363; SI-NEXT: v_mul_hi_u32 v7, v5, v7 364; SI-NEXT: v_add_i32_e32 v4, vcc, v6, v4 365; SI-NEXT: v_add_i32_e32 v5, vcc, v7, v5 366; SI-NEXT: v_mul_hi_u32 v4, v0, v4 367; SI-NEXT: v_mul_hi_u32 v5, v1, v5 368; SI-NEXT: v_mul_lo_u32 v6, v4, v2 369; SI-NEXT: v_mul_lo_u32 v8, v5, v3 370; SI-NEXT: v_add_i32_e32 v7, vcc, 1, v4 371; SI-NEXT: v_subrev_i32_e32 v0, vcc, v6, v0 372; SI-NEXT: v_subrev_i32_e32 v1, vcc, v8, v1 373; SI-NEXT: v_add_i32_e32 v9, vcc, 1, v5 374; SI-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2 375; SI-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v3 376; SI-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[0:1] 377; SI-NEXT: v_subrev_i32_e32 v6, vcc, v2, v0 378; SI-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[2:3] 379; SI-NEXT: v_subrev_i32_e32 v7, vcc, v3, v1 380; SI-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1] 381; SI-NEXT: v_add_i32_e32 v6, vcc, 1, v4 382; SI-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[2:3] 383; SI-NEXT: v_add_i32_e32 v7, vcc, 1, v5 384; SI-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 385; SI-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc 386; SI-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 387; SI-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc 388; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 389; SI-NEXT: s_endpgm 390; 391; VI-LABEL: udiv_v2i32: 392; VI: ; %bb.0: 393; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 394; VI-NEXT: s_mov_b32 s7, 0xf000 395; VI-NEXT: s_mov_b32 s6, -1 396; VI-NEXT: s_mov_b32 s10, s6 397; VI-NEXT: s_mov_b32 s11, s7 398; VI-NEXT: s_waitcnt lgkmcnt(0) 399; VI-NEXT: s_mov_b32 s8, s2 400; VI-NEXT: s_mov_b32 s9, s3 401; VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 402; VI-NEXT: s_mov_b32 s2, 0x4f7ffffe 403; VI-NEXT: s_mov_b32 s4, s0 404; VI-NEXT: s_mov_b32 s5, s1 405; VI-NEXT: s_waitcnt vmcnt(0) 406; VI-NEXT: v_cvt_f32_u32_e32 v4, v2 407; VI-NEXT: v_cvt_f32_u32_e32 v5, v3 408; VI-NEXT: v_sub_u32_e32 v6, vcc, 0, v2 409; VI-NEXT: v_rcp_iflag_f32_e32 v4, v4 410; VI-NEXT: v_rcp_iflag_f32_e32 v5, v5 411; VI-NEXT: v_sub_u32_e32 v7, vcc, 0, v3 412; VI-NEXT: v_mul_f32_e32 v4, s2, v4 413; VI-NEXT: v_mul_f32_e32 v5, s2, v5 414; VI-NEXT: v_cvt_u32_f32_e32 v4, v4 415; VI-NEXT: v_cvt_u32_f32_e32 v5, v5 416; VI-NEXT: v_mul_lo_u32 v6, v6, v4 417; VI-NEXT: v_mul_lo_u32 v7, v7, v5 418; VI-NEXT: v_mul_hi_u32 v6, v4, v6 419; VI-NEXT: v_mul_hi_u32 v7, v5, v7 420; VI-NEXT: v_add_u32_e32 v4, vcc, v6, v4 421; VI-NEXT: v_add_u32_e32 v5, vcc, v7, v5 422; VI-NEXT: v_mul_hi_u32 v4, v0, v4 423; VI-NEXT: v_mul_hi_u32 v5, v1, v5 424; VI-NEXT: v_mul_lo_u32 v6, v4, v2 425; VI-NEXT: v_mul_lo_u32 v8, v5, v3 426; VI-NEXT: v_add_u32_e32 v7, vcc, 1, v4 427; VI-NEXT: v_subrev_u32_e32 v0, vcc, v6, v0 428; VI-NEXT: v_subrev_u32_e32 v1, vcc, v8, v1 429; VI-NEXT: v_add_u32_e32 v9, vcc, 1, v5 430; VI-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2 431; VI-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v3 432; VI-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[0:1] 433; VI-NEXT: v_subrev_u32_e32 v6, vcc, v2, v0 434; VI-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[2:3] 435; VI-NEXT: v_subrev_u32_e32 v7, vcc, v3, v1 436; VI-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1] 437; VI-NEXT: v_add_u32_e32 v6, vcc, 1, v4 438; VI-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[2:3] 439; VI-NEXT: v_add_u32_e32 v7, vcc, 1, v5 440; VI-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 441; VI-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc 442; VI-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 443; VI-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc 444; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 445; VI-NEXT: s_endpgm 446; 447; GCN-LABEL: udiv_v2i32: 448; GCN: ; %bb.0: 449; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 450; GCN-NEXT: s_waitcnt lgkmcnt(0) 451; GCN-NEXT: v_mov_b32_e32 v0, s2 452; GCN-NEXT: v_mov_b32_e32 v1, s3 453; GCN-NEXT: flat_load_dwordx4 v[0:3], v[0:1] 454; GCN-NEXT: s_mov_b32 s2, 0x4f7ffffe 455; GCN-NEXT: s_waitcnt vmcnt(0) 456; GCN-NEXT: v_cvt_f32_u32_e32 v4, v2 457; GCN-NEXT: v_cvt_f32_u32_e32 v5, v3 458; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v4 459; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v5 460; GCN-NEXT: v_mul_f32_e32 v4, s2, v4 461; GCN-NEXT: v_cvt_u32_f32_e32 v6, v4 462; GCN-NEXT: v_mul_f32_e32 v5, s2, v5 463; GCN-NEXT: v_cvt_u32_f32_e32 v7, v5 464; GCN-NEXT: v_sub_u32_e32 v4, vcc, 0, v2 465; GCN-NEXT: v_mul_lo_u32 v5, v4, v6 466; GCN-NEXT: v_sub_u32_e32 v4, vcc, 0, v3 467; GCN-NEXT: v_mul_lo_u32 v8, v4, v7 468; GCN-NEXT: v_mul_hi_u32 v9, v6, v5 469; GCN-NEXT: v_mov_b32_e32 v4, s0 470; GCN-NEXT: v_mov_b32_e32 v5, s1 471; GCN-NEXT: v_mul_hi_u32 v8, v7, v8 472; GCN-NEXT: v_add_u32_e32 v6, vcc, v9, v6 473; GCN-NEXT: v_mul_hi_u32 v6, v0, v6 474; GCN-NEXT: v_add_u32_e32 v7, vcc, v8, v7 475; GCN-NEXT: v_mul_hi_u32 v7, v1, v7 476; GCN-NEXT: v_mul_lo_u32 v8, v6, v2 477; GCN-NEXT: v_add_u32_e32 v9, vcc, 1, v6 478; GCN-NEXT: v_mul_lo_u32 v10, v7, v3 479; GCN-NEXT: v_subrev_u32_e32 v0, vcc, v8, v0 480; GCN-NEXT: v_add_u32_e32 v11, vcc, 1, v7 481; GCN-NEXT: v_subrev_u32_e32 v1, vcc, v10, v1 482; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v2 483; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v3 484; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v9, s[0:1] 485; GCN-NEXT: v_subrev_u32_e32 v8, vcc, v2, v0 486; GCN-NEXT: v_cndmask_b32_e64 v7, v7, v11, s[2:3] 487; GCN-NEXT: v_subrev_u32_e32 v9, vcc, v3, v1 488; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v8, s[0:1] 489; GCN-NEXT: v_add_u32_e32 v8, vcc, 1, v6 490; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v9, s[2:3] 491; GCN-NEXT: v_add_u32_e32 v9, vcc, 1, v7 492; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 493; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc 494; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 495; GCN-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc 496; GCN-NEXT: flat_store_dwordx2 v[4:5], v[0:1] 497; GCN-NEXT: s_endpgm 498; 499; GFX1030-LABEL: udiv_v2i32: 500; GFX1030: ; %bb.0: 501; GFX1030-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 502; GFX1030-NEXT: v_mov_b32_e32 v4, 0 503; GFX1030-NEXT: s_mov_b32 s0, 0x4f7ffffe 504; GFX1030-NEXT: s_waitcnt lgkmcnt(0) 505; GFX1030-NEXT: global_load_dwordx4 v[0:3], v4, s[6:7] 506; GFX1030-NEXT: s_waitcnt vmcnt(0) 507; GFX1030-NEXT: v_cvt_f32_u32_e32 v5, v2 508; GFX1030-NEXT: v_cvt_f32_u32_e32 v6, v3 509; GFX1030-NEXT: v_sub_nc_u32_e32 v7, 0, v2 510; GFX1030-NEXT: v_sub_nc_u32_e32 v8, 0, v3 511; GFX1030-NEXT: v_rcp_iflag_f32_e32 v5, v5 512; GFX1030-NEXT: v_rcp_iflag_f32_e32 v6, v6 513; GFX1030-NEXT: v_mul_f32_e32 v5, s0, v5 514; GFX1030-NEXT: v_mul_f32_e32 v6, s0, v6 515; GFX1030-NEXT: v_cvt_u32_f32_e32 v5, v5 516; GFX1030-NEXT: v_cvt_u32_f32_e32 v6, v6 517; GFX1030-NEXT: v_mul_lo_u32 v7, v7, v5 518; GFX1030-NEXT: v_mul_lo_u32 v8, v8, v6 519; GFX1030-NEXT: v_mul_hi_u32 v7, v5, v7 520; GFX1030-NEXT: v_mul_hi_u32 v8, v6, v8 521; GFX1030-NEXT: v_add_nc_u32_e32 v5, v5, v7 522; GFX1030-NEXT: v_add_nc_u32_e32 v6, v6, v8 523; GFX1030-NEXT: v_mul_hi_u32 v5, v0, v5 524; GFX1030-NEXT: v_mul_hi_u32 v6, v1, v6 525; GFX1030-NEXT: v_mul_lo_u32 v7, v5, v2 526; GFX1030-NEXT: v_mul_lo_u32 v8, v6, v3 527; GFX1030-NEXT: v_sub_nc_u32_e32 v0, v0, v7 528; GFX1030-NEXT: v_add_nc_u32_e32 v7, 1, v5 529; GFX1030-NEXT: v_sub_nc_u32_e32 v1, v1, v8 530; GFX1030-NEXT: v_add_nc_u32_e32 v8, 1, v6 531; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v2 532; GFX1030-NEXT: v_sub_nc_u32_e32 v9, v1, v3 533; GFX1030-NEXT: v_cmp_ge_u32_e64 s0, v1, v3 534; GFX1030-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo 535; GFX1030-NEXT: v_sub_nc_u32_e32 v7, v0, v2 536; GFX1030-NEXT: v_cndmask_b32_e64 v6, v6, v8, s0 537; GFX1030-NEXT: v_cndmask_b32_e64 v1, v1, v9, s0 538; GFX1030-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc_lo 539; GFX1030-NEXT: v_add_nc_u32_e32 v7, 1, v5 540; GFX1030-NEXT: v_add_nc_u32_e32 v8, 1, v6 541; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v0, v2 542; GFX1030-NEXT: v_cndmask_b32_e32 v0, v5, v7, vcc_lo 543; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v1, v3 544; GFX1030-NEXT: v_cndmask_b32_e32 v1, v6, v8, vcc_lo 545; GFX1030-NEXT: global_store_dwordx2 v4, v[0:1], s[4:5] 546; GFX1030-NEXT: s_endpgm 547; 548; EG-LABEL: udiv_v2i32: 549; EG: ; %bb.0: 550; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] 551; EG-NEXT: TEX 1 @6 552; EG-NEXT: ALU 33, @11, KC0[CB0:0-32], KC1[] 553; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XY, T0.X, 1 554; EG-NEXT: CF_END 555; EG-NEXT: PAD 556; EG-NEXT: Fetch clause starting at 6: 557; EG-NEXT: VTX_READ_64 T1.XY, T0.X, 8, #1 558; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1 559; EG-NEXT: ALU clause starting at 10: 560; EG-NEXT: MOV * T0.X, KC0[2].Z, 561; EG-NEXT: ALU clause starting at 11: 562; EG-NEXT: SUB_INT T0.W, 0.0, T1.Y, 563; EG-NEXT: RECIP_UINT * T0.Z, T1.Y, 564; EG-NEXT: MULLO_INT * T0.W, PV.W, PS, 565; EG-NEXT: SUB_INT T1.W, 0.0, T1.X, 566; EG-NEXT: RECIP_UINT * T1.Z, T1.X, 567; EG-NEXT: MULLO_INT * T1.W, PV.W, PS, 568; EG-NEXT: MULHI * T1.W, T1.Z, PS, 569; EG-NEXT: ADD_INT T1.W, T1.Z, PS, 570; EG-NEXT: MULHI * T0.W, T0.Z, T0.W, 571; EG-NEXT: ADD_INT T0.W, T0.Z, PS, 572; EG-NEXT: MULHI * T0.Z, T0.X, PV.W, 573; EG-NEXT: MULHI * T0.W, T0.Y, PV.W, 574; EG-NEXT: MULLO_INT * T1.Z, PS, T1.Y, 575; EG-NEXT: SUB_INT T1.W, T0.Y, PS, 576; EG-NEXT: MULLO_INT * T0.Y, T0.Z, T1.X, 577; EG-NEXT: SUB_INT T0.Y, T0.X, PS, 578; EG-NEXT: ADD_INT T1.Z, T0.W, 1, 579; EG-NEXT: SETGE_UINT T2.W, PV.W, T1.Y, 580; EG-NEXT: SUB_INT * T3.W, PV.W, T1.Y, 581; EG-NEXT: CNDE_INT T0.X, PV.W, T1.W, PS, 582; EG-NEXT: CNDE_INT T2.Y, PV.W, T0.W, PV.Z, BS:VEC_021/SCL_122 583; EG-NEXT: ADD_INT T1.Z, T0.Z, 1, 584; EG-NEXT: SETGE_UINT T0.W, PV.Y, T1.X, 585; EG-NEXT: SUB_INT * T1.W, PV.Y, T1.X, 586; EG-NEXT: CNDE_INT T0.Y, PV.W, T0.Y, PS, BS:VEC_021/SCL_122 587; EG-NEXT: CNDE_INT T0.Z, PV.W, T0.Z, PV.Z, 588; EG-NEXT: ADD_INT T0.W, PV.Y, 1, 589; EG-NEXT: SETGE_UINT * T1.W, PV.X, T1.Y, 590; EG-NEXT: CNDE_INT T1.Y, PS, T2.Y, PV.W, 591; EG-NEXT: ADD_INT T0.W, PV.Z, 1, 592; EG-NEXT: SETGE_UINT * T1.W, PV.Y, T1.X, 593; EG-NEXT: CNDE_INT T1.X, PS, T0.Z, PV.W, 594; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x, 595; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 596 %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1 597 %a = load <2 x i32>, <2 x i32> addrspace(1) * %in 598 %b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr 599 %result = udiv <2 x i32> %a, %b 600 store <2 x i32> %result, <2 x i32> addrspace(1)* %out 601 ret void 602} 603 604define amdgpu_kernel void @udiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { 605; SI-LABEL: udiv_v4i32: 606; SI: ; %bb.0: 607; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 608; SI-NEXT: s_mov_b32 s11, 0xf000 609; SI-NEXT: s_mov_b32 s10, -1 610; SI-NEXT: s_mov_b32 s6, s10 611; SI-NEXT: s_mov_b32 s7, s11 612; SI-NEXT: s_waitcnt lgkmcnt(0) 613; SI-NEXT: s_mov_b32 s4, s2 614; SI-NEXT: s_mov_b32 s5, s3 615; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0 616; SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:16 617; SI-NEXT: s_mov_b32 s2, 0x4f7ffffe 618; SI-NEXT: s_mov_b32 s8, s0 619; SI-NEXT: s_mov_b32 s9, s1 620; SI-NEXT: s_waitcnt vmcnt(0) 621; SI-NEXT: v_cvt_f32_u32_e32 v8, v4 622; SI-NEXT: v_cvt_f32_u32_e32 v10, v5 623; SI-NEXT: v_cvt_f32_u32_e32 v12, v6 624; SI-NEXT: v_cvt_f32_u32_e32 v14, v7 625; SI-NEXT: v_rcp_iflag_f32_e32 v8, v8 626; SI-NEXT: v_rcp_iflag_f32_e32 v10, v10 627; SI-NEXT: v_rcp_iflag_f32_e32 v12, v12 628; SI-NEXT: v_rcp_iflag_f32_e32 v14, v14 629; SI-NEXT: v_mul_f32_e32 v8, s2, v8 630; SI-NEXT: v_mul_f32_e32 v10, s2, v10 631; SI-NEXT: v_mul_f32_e32 v12, s2, v12 632; SI-NEXT: v_mul_f32_e32 v14, s2, v14 633; SI-NEXT: v_cvt_u32_f32_e32 v8, v8 634; SI-NEXT: v_cvt_u32_f32_e32 v10, v10 635; SI-NEXT: v_cvt_u32_f32_e32 v12, v12 636; SI-NEXT: v_cvt_u32_f32_e32 v14, v14 637; SI-NEXT: v_sub_i32_e32 v9, vcc, 0, v4 638; SI-NEXT: v_sub_i32_e32 v11, vcc, 0, v5 639; SI-NEXT: v_sub_i32_e32 v13, vcc, 0, v6 640; SI-NEXT: v_sub_i32_e32 v15, vcc, 0, v7 641; SI-NEXT: v_mul_lo_u32 v9, v9, v8 642; SI-NEXT: v_mul_lo_u32 v11, v11, v10 643; SI-NEXT: v_mul_lo_u32 v13, v13, v12 644; SI-NEXT: v_mul_lo_u32 v15, v15, v14 645; SI-NEXT: v_mul_hi_u32 v9, v8, v9 646; SI-NEXT: v_mul_hi_u32 v11, v10, v11 647; SI-NEXT: v_mul_hi_u32 v13, v12, v13 648; SI-NEXT: v_mul_hi_u32 v15, v14, v15 649; SI-NEXT: v_add_i32_e32 v8, vcc, v9, v8 650; SI-NEXT: v_add_i32_e32 v9, vcc, v11, v10 651; SI-NEXT: v_add_i32_e32 v10, vcc, v13, v12 652; SI-NEXT: v_add_i32_e32 v11, vcc, v15, v14 653; SI-NEXT: v_mul_hi_u32 v8, v0, v8 654; SI-NEXT: v_mul_hi_u32 v9, v1, v9 655; SI-NEXT: v_mul_hi_u32 v10, v2, v10 656; SI-NEXT: v_mul_hi_u32 v11, v3, v11 657; SI-NEXT: v_mul_lo_u32 v12, v8, v4 658; SI-NEXT: v_mul_lo_u32 v14, v9, v5 659; SI-NEXT: v_mul_lo_u32 v16, v10, v6 660; SI-NEXT: v_mul_lo_u32 v18, v11, v7 661; SI-NEXT: v_subrev_i32_e32 v0, vcc, v12, v0 662; SI-NEXT: v_subrev_i32_e32 v1, vcc, v14, v1 663; SI-NEXT: v_subrev_i32_e32 v2, vcc, v16, v2 664; SI-NEXT: v_subrev_i32_e32 v3, vcc, v18, v3 665; SI-NEXT: v_add_i32_e32 v13, vcc, 1, v8 666; SI-NEXT: v_add_i32_e32 v15, vcc, 1, v9 667; SI-NEXT: v_add_i32_e32 v17, vcc, 1, v10 668; SI-NEXT: v_add_i32_e32 v19, vcc, 1, v11 669; SI-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v4 670; SI-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v5 671; SI-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v6 672; SI-NEXT: v_cmp_ge_u32_e64 s[6:7], v3, v7 673; SI-NEXT: v_cndmask_b32_e64 v8, v8, v13, s[0:1] 674; SI-NEXT: v_subrev_i32_e32 v12, vcc, v4, v0 675; SI-NEXT: v_cndmask_b32_e64 v9, v9, v15, s[2:3] 676; SI-NEXT: v_subrev_i32_e32 v13, vcc, v5, v1 677; SI-NEXT: v_cndmask_b32_e64 v10, v10, v17, s[4:5] 678; SI-NEXT: v_subrev_i32_e32 v14, vcc, v6, v2 679; SI-NEXT: v_cndmask_b32_e64 v11, v11, v19, s[6:7] 680; SI-NEXT: v_subrev_i32_e32 v15, vcc, v7, v3 681; SI-NEXT: v_cndmask_b32_e64 v0, v0, v12, s[0:1] 682; SI-NEXT: v_add_i32_e32 v12, vcc, 1, v8 683; SI-NEXT: v_cndmask_b32_e64 v1, v1, v13, s[2:3] 684; SI-NEXT: v_add_i32_e32 v13, vcc, 1, v9 685; SI-NEXT: v_cndmask_b32_e64 v2, v2, v14, s[4:5] 686; SI-NEXT: v_add_i32_e32 v14, vcc, 1, v10 687; SI-NEXT: v_cndmask_b32_e64 v3, v3, v15, s[6:7] 688; SI-NEXT: v_add_i32_e32 v15, vcc, 1, v11 689; SI-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4 690; SI-NEXT: v_cndmask_b32_e32 v0, v8, v12, vcc 691; SI-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5 692; SI-NEXT: v_cndmask_b32_e32 v1, v9, v13, vcc 693; SI-NEXT: v_cmp_ge_u32_e32 vcc, v2, v6 694; SI-NEXT: v_cndmask_b32_e32 v2, v10, v14, vcc 695; SI-NEXT: v_cmp_ge_u32_e32 vcc, v3, v7 696; SI-NEXT: v_cndmask_b32_e32 v3, v11, v15, vcc 697; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 698; SI-NEXT: s_endpgm 699; 700; VI-LABEL: udiv_v4i32: 701; VI: ; %bb.0: 702; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 703; VI-NEXT: s_mov_b32 s11, 0xf000 704; VI-NEXT: s_mov_b32 s10, -1 705; VI-NEXT: s_mov_b32 s6, s10 706; VI-NEXT: s_mov_b32 s7, s11 707; VI-NEXT: s_waitcnt lgkmcnt(0) 708; VI-NEXT: s_mov_b32 s4, s2 709; VI-NEXT: s_mov_b32 s5, s3 710; VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0 711; VI-NEXT: buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:16 712; VI-NEXT: s_mov_b32 s2, 0x4f7ffffe 713; VI-NEXT: s_mov_b32 s8, s0 714; VI-NEXT: s_mov_b32 s9, s1 715; VI-NEXT: s_waitcnt vmcnt(0) 716; VI-NEXT: v_cvt_f32_u32_e32 v8, v4 717; VI-NEXT: v_cvt_f32_u32_e32 v10, v5 718; VI-NEXT: v_cvt_f32_u32_e32 v12, v6 719; VI-NEXT: v_cvt_f32_u32_e32 v14, v7 720; VI-NEXT: v_rcp_iflag_f32_e32 v8, v8 721; VI-NEXT: v_rcp_iflag_f32_e32 v10, v10 722; VI-NEXT: v_rcp_iflag_f32_e32 v12, v12 723; VI-NEXT: v_rcp_iflag_f32_e32 v14, v14 724; VI-NEXT: v_mul_f32_e32 v8, s2, v8 725; VI-NEXT: v_mul_f32_e32 v10, s2, v10 726; VI-NEXT: v_mul_f32_e32 v12, s2, v12 727; VI-NEXT: v_mul_f32_e32 v14, s2, v14 728; VI-NEXT: v_cvt_u32_f32_e32 v8, v8 729; VI-NEXT: v_cvt_u32_f32_e32 v10, v10 730; VI-NEXT: v_cvt_u32_f32_e32 v12, v12 731; VI-NEXT: v_cvt_u32_f32_e32 v14, v14 732; VI-NEXT: v_sub_u32_e32 v9, vcc, 0, v4 733; VI-NEXT: v_sub_u32_e32 v11, vcc, 0, v5 734; VI-NEXT: v_sub_u32_e32 v13, vcc, 0, v6 735; VI-NEXT: v_sub_u32_e32 v15, vcc, 0, v7 736; VI-NEXT: v_mul_lo_u32 v9, v9, v8 737; VI-NEXT: v_mul_lo_u32 v11, v11, v10 738; VI-NEXT: v_mul_lo_u32 v13, v13, v12 739; VI-NEXT: v_mul_lo_u32 v15, v15, v14 740; VI-NEXT: v_mul_hi_u32 v9, v8, v9 741; VI-NEXT: v_mul_hi_u32 v11, v10, v11 742; VI-NEXT: v_mul_hi_u32 v13, v12, v13 743; VI-NEXT: v_mul_hi_u32 v15, v14, v15 744; VI-NEXT: v_add_u32_e32 v8, vcc, v9, v8 745; VI-NEXT: v_add_u32_e32 v9, vcc, v11, v10 746; VI-NEXT: v_add_u32_e32 v10, vcc, v13, v12 747; VI-NEXT: v_add_u32_e32 v11, vcc, v15, v14 748; VI-NEXT: v_mul_hi_u32 v8, v0, v8 749; VI-NEXT: v_mul_hi_u32 v9, v1, v9 750; VI-NEXT: v_mul_hi_u32 v10, v2, v10 751; VI-NEXT: v_mul_hi_u32 v11, v3, v11 752; VI-NEXT: v_mul_lo_u32 v12, v8, v4 753; VI-NEXT: v_mul_lo_u32 v14, v9, v5 754; VI-NEXT: v_mul_lo_u32 v16, v10, v6 755; VI-NEXT: v_mul_lo_u32 v18, v11, v7 756; VI-NEXT: v_subrev_u32_e32 v0, vcc, v12, v0 757; VI-NEXT: v_subrev_u32_e32 v1, vcc, v14, v1 758; VI-NEXT: v_subrev_u32_e32 v2, vcc, v16, v2 759; VI-NEXT: v_subrev_u32_e32 v3, vcc, v18, v3 760; VI-NEXT: v_add_u32_e32 v13, vcc, 1, v8 761; VI-NEXT: v_add_u32_e32 v15, vcc, 1, v9 762; VI-NEXT: v_add_u32_e32 v17, vcc, 1, v10 763; VI-NEXT: v_add_u32_e32 v19, vcc, 1, v11 764; VI-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v4 765; VI-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v5 766; VI-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v6 767; VI-NEXT: v_cmp_ge_u32_e64 s[6:7], v3, v7 768; VI-NEXT: v_cndmask_b32_e64 v8, v8, v13, s[0:1] 769; VI-NEXT: v_subrev_u32_e32 v12, vcc, v4, v0 770; VI-NEXT: v_cndmask_b32_e64 v9, v9, v15, s[2:3] 771; VI-NEXT: v_subrev_u32_e32 v13, vcc, v5, v1 772; VI-NEXT: v_cndmask_b32_e64 v10, v10, v17, s[4:5] 773; VI-NEXT: v_subrev_u32_e32 v14, vcc, v6, v2 774; VI-NEXT: v_cndmask_b32_e64 v11, v11, v19, s[6:7] 775; VI-NEXT: v_subrev_u32_e32 v15, vcc, v7, v3 776; VI-NEXT: v_cndmask_b32_e64 v0, v0, v12, s[0:1] 777; VI-NEXT: v_add_u32_e32 v12, vcc, 1, v8 778; VI-NEXT: v_cndmask_b32_e64 v1, v1, v13, s[2:3] 779; VI-NEXT: v_add_u32_e32 v13, vcc, 1, v9 780; VI-NEXT: v_cndmask_b32_e64 v2, v2, v14, s[4:5] 781; VI-NEXT: v_add_u32_e32 v14, vcc, 1, v10 782; VI-NEXT: v_cndmask_b32_e64 v3, v3, v15, s[6:7] 783; VI-NEXT: v_add_u32_e32 v15, vcc, 1, v11 784; VI-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4 785; VI-NEXT: v_cndmask_b32_e32 v0, v8, v12, vcc 786; VI-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5 787; VI-NEXT: v_cndmask_b32_e32 v1, v9, v13, vcc 788; VI-NEXT: v_cmp_ge_u32_e32 vcc, v2, v6 789; VI-NEXT: v_cndmask_b32_e32 v2, v10, v14, vcc 790; VI-NEXT: v_cmp_ge_u32_e32 vcc, v3, v7 791; VI-NEXT: v_cndmask_b32_e32 v3, v11, v15, vcc 792; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 793; VI-NEXT: s_endpgm 794; 795; GCN-LABEL: udiv_v4i32: 796; GCN: ; %bb.0: 797; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 798; GCN-NEXT: s_waitcnt lgkmcnt(0) 799; GCN-NEXT: v_mov_b32_e32 v0, s2 800; GCN-NEXT: v_mov_b32_e32 v1, s3 801; GCN-NEXT: s_add_u32 s2, s2, 16 802; GCN-NEXT: s_addc_u32 s3, s3, 0 803; GCN-NEXT: v_mov_b32_e32 v5, s3 804; GCN-NEXT: v_mov_b32_e32 v4, s2 805; GCN-NEXT: flat_load_dwordx4 v[0:3], v[0:1] 806; GCN-NEXT: flat_load_dwordx4 v[4:7], v[4:5] 807; GCN-NEXT: s_mov_b32 s2, 0x4f7ffffe 808; GCN-NEXT: v_mov_b32_e32 v8, s0 809; GCN-NEXT: v_mov_b32_e32 v9, s1 810; GCN-NEXT: s_waitcnt vmcnt(0) 811; GCN-NEXT: v_cvt_f32_u32_e32 v10, v4 812; GCN-NEXT: v_cvt_f32_u32_e32 v12, v5 813; GCN-NEXT: v_cvt_f32_u32_e32 v14, v6 814; GCN-NEXT: v_cvt_f32_u32_e32 v16, v7 815; GCN-NEXT: v_rcp_iflag_f32_e32 v10, v10 816; GCN-NEXT: v_rcp_iflag_f32_e32 v12, v12 817; GCN-NEXT: v_rcp_iflag_f32_e32 v14, v14 818; GCN-NEXT: v_rcp_iflag_f32_e32 v16, v16 819; GCN-NEXT: v_mul_f32_e32 v10, s2, v10 820; GCN-NEXT: v_mul_f32_e32 v12, s2, v12 821; GCN-NEXT: v_mul_f32_e32 v14, s2, v14 822; GCN-NEXT: v_mul_f32_e32 v16, s2, v16 823; GCN-NEXT: v_cvt_u32_f32_e32 v10, v10 824; GCN-NEXT: v_cvt_u32_f32_e32 v12, v12 825; GCN-NEXT: v_cvt_u32_f32_e32 v14, v14 826; GCN-NEXT: v_cvt_u32_f32_e32 v16, v16 827; GCN-NEXT: v_sub_u32_e32 v11, vcc, 0, v4 828; GCN-NEXT: v_sub_u32_e32 v13, vcc, 0, v5 829; GCN-NEXT: v_sub_u32_e32 v15, vcc, 0, v6 830; GCN-NEXT: v_sub_u32_e32 v17, vcc, 0, v7 831; GCN-NEXT: v_mul_lo_u32 v11, v11, v10 832; GCN-NEXT: v_mul_lo_u32 v13, v13, v12 833; GCN-NEXT: v_mul_lo_u32 v15, v15, v14 834; GCN-NEXT: v_mul_lo_u32 v17, v17, v16 835; GCN-NEXT: v_mul_hi_u32 v11, v10, v11 836; GCN-NEXT: v_mul_hi_u32 v13, v12, v13 837; GCN-NEXT: v_mul_hi_u32 v15, v14, v15 838; GCN-NEXT: v_mul_hi_u32 v17, v16, v17 839; GCN-NEXT: v_add_u32_e32 v10, vcc, v11, v10 840; GCN-NEXT: v_add_u32_e32 v11, vcc, v13, v12 841; GCN-NEXT: v_add_u32_e32 v12, vcc, v15, v14 842; GCN-NEXT: v_add_u32_e32 v13, vcc, v17, v16 843; GCN-NEXT: v_mul_hi_u32 v10, v0, v10 844; GCN-NEXT: v_mul_hi_u32 v11, v1, v11 845; GCN-NEXT: v_mul_hi_u32 v12, v2, v12 846; GCN-NEXT: v_mul_hi_u32 v13, v3, v13 847; GCN-NEXT: v_mul_lo_u32 v14, v10, v4 848; GCN-NEXT: v_mul_lo_u32 v16, v11, v5 849; GCN-NEXT: v_mul_lo_u32 v18, v12, v6 850; GCN-NEXT: v_mul_lo_u32 v19, v13, v7 851; GCN-NEXT: v_subrev_u32_e32 v0, vcc, v14, v0 852; GCN-NEXT: v_subrev_u32_e32 v1, vcc, v16, v1 853; GCN-NEXT: v_subrev_u32_e32 v2, vcc, v18, v2 854; GCN-NEXT: v_subrev_u32_e32 v3, vcc, v19, v3 855; GCN-NEXT: v_add_u32_e32 v15, vcc, 1, v10 856; GCN-NEXT: v_add_u32_e32 v17, vcc, 1, v11 857; GCN-NEXT: v_add_u32_e32 v14, vcc, 1, v12 858; GCN-NEXT: v_add_u32_e32 v16, vcc, 1, v13 859; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v4 860; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v1, v5 861; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v6 862; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v3, v7 863; GCN-NEXT: v_cndmask_b32_e64 v10, v10, v15, s[0:1] 864; GCN-NEXT: v_subrev_u32_e32 v15, vcc, v4, v0 865; GCN-NEXT: v_cndmask_b32_e64 v11, v11, v17, s[2:3] 866; GCN-NEXT: v_subrev_u32_e32 v17, vcc, v5, v1 867; GCN-NEXT: v_cndmask_b32_e64 v12, v12, v14, s[4:5] 868; GCN-NEXT: v_subrev_u32_e32 v14, vcc, v6, v2 869; GCN-NEXT: v_cndmask_b32_e64 v13, v13, v16, s[6:7] 870; GCN-NEXT: v_subrev_u32_e32 v16, vcc, v7, v3 871; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v15, s[0:1] 872; GCN-NEXT: v_add_u32_e32 v15, vcc, 1, v10 873; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[2:3] 874; GCN-NEXT: v_add_u32_e32 v17, vcc, 1, v11 875; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v14, s[4:5] 876; GCN-NEXT: v_add_u32_e32 v14, vcc, 1, v12 877; GCN-NEXT: v_cndmask_b32_e64 v3, v3, v16, s[6:7] 878; GCN-NEXT: v_add_u32_e32 v16, vcc, 1, v13 879; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4 880; GCN-NEXT: v_cndmask_b32_e32 v0, v10, v15, vcc 881; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v5 882; GCN-NEXT: v_cndmask_b32_e32 v1, v11, v17, vcc 883; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v2, v6 884; GCN-NEXT: v_cndmask_b32_e32 v2, v12, v14, vcc 885; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v7 886; GCN-NEXT: v_cndmask_b32_e32 v3, v13, v16, vcc 887; GCN-NEXT: flat_store_dwordx4 v[8:9], v[0:3] 888; GCN-NEXT: s_endpgm 889; 890; GFX1030-LABEL: udiv_v4i32: 891; GFX1030: ; %bb.0: 892; GFX1030-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 893; GFX1030-NEXT: v_mov_b32_e32 v8, 0 894; GFX1030-NEXT: s_mov_b32 s0, 0x4f7ffffe 895; GFX1030-NEXT: s_waitcnt lgkmcnt(0) 896; GFX1030-NEXT: s_clause 0x1 897; GFX1030-NEXT: global_load_dwordx4 v[0:3], v8, s[6:7] offset:16 898; GFX1030-NEXT: global_load_dwordx4 v[4:7], v8, s[6:7] 899; GFX1030-NEXT: s_waitcnt vmcnt(1) 900; GFX1030-NEXT: v_cvt_f32_u32_e32 v9, v0 901; GFX1030-NEXT: v_cvt_f32_u32_e32 v10, v1 902; GFX1030-NEXT: v_cvt_f32_u32_e32 v11, v2 903; GFX1030-NEXT: v_cvt_f32_u32_e32 v12, v3 904; GFX1030-NEXT: v_sub_nc_u32_e32 v13, 0, v0 905; GFX1030-NEXT: v_rcp_iflag_f32_e32 v9, v9 906; GFX1030-NEXT: v_rcp_iflag_f32_e32 v10, v10 907; GFX1030-NEXT: v_rcp_iflag_f32_e32 v11, v11 908; GFX1030-NEXT: v_rcp_iflag_f32_e32 v12, v12 909; GFX1030-NEXT: v_sub_nc_u32_e32 v14, 0, v1 910; GFX1030-NEXT: v_sub_nc_u32_e32 v15, 0, v2 911; GFX1030-NEXT: v_sub_nc_u32_e32 v16, 0, v3 912; GFX1030-NEXT: v_mul_f32_e32 v9, s0, v9 913; GFX1030-NEXT: v_mul_f32_e32 v10, s0, v10 914; GFX1030-NEXT: v_mul_f32_e32 v11, s0, v11 915; GFX1030-NEXT: v_mul_f32_e32 v12, s0, v12 916; GFX1030-NEXT: v_cvt_u32_f32_e32 v9, v9 917; GFX1030-NEXT: v_cvt_u32_f32_e32 v10, v10 918; GFX1030-NEXT: v_cvt_u32_f32_e32 v11, v11 919; GFX1030-NEXT: v_cvt_u32_f32_e32 v12, v12 920; GFX1030-NEXT: v_mul_lo_u32 v13, v13, v9 921; GFX1030-NEXT: v_mul_lo_u32 v14, v14, v10 922; GFX1030-NEXT: v_mul_lo_u32 v15, v15, v11 923; GFX1030-NEXT: v_mul_lo_u32 v16, v16, v12 924; GFX1030-NEXT: v_mul_hi_u32 v13, v9, v13 925; GFX1030-NEXT: v_mul_hi_u32 v14, v10, v14 926; GFX1030-NEXT: v_mul_hi_u32 v15, v11, v15 927; GFX1030-NEXT: v_mul_hi_u32 v16, v12, v16 928; GFX1030-NEXT: v_add_nc_u32_e32 v9, v9, v13 929; GFX1030-NEXT: v_add_nc_u32_e32 v10, v10, v14 930; GFX1030-NEXT: v_add_nc_u32_e32 v11, v11, v15 931; GFX1030-NEXT: v_add_nc_u32_e32 v12, v12, v16 932; GFX1030-NEXT: s_waitcnt vmcnt(0) 933; GFX1030-NEXT: v_mul_hi_u32 v9, v4, v9 934; GFX1030-NEXT: v_mul_hi_u32 v10, v5, v10 935; GFX1030-NEXT: v_mul_hi_u32 v11, v6, v11 936; GFX1030-NEXT: v_mul_hi_u32 v12, v7, v12 937; GFX1030-NEXT: v_mul_lo_u32 v13, v9, v0 938; GFX1030-NEXT: v_mul_lo_u32 v14, v10, v1 939; GFX1030-NEXT: v_mul_lo_u32 v15, v11, v2 940; GFX1030-NEXT: v_mul_lo_u32 v16, v12, v3 941; GFX1030-NEXT: v_add_nc_u32_e32 v17, 1, v9 942; GFX1030-NEXT: v_add_nc_u32_e32 v18, 1, v10 943; GFX1030-NEXT: v_add_nc_u32_e32 v19, 1, v11 944; GFX1030-NEXT: v_sub_nc_u32_e32 v4, v4, v13 945; GFX1030-NEXT: v_sub_nc_u32_e32 v5, v5, v14 946; GFX1030-NEXT: v_sub_nc_u32_e32 v6, v6, v15 947; GFX1030-NEXT: v_sub_nc_u32_e32 v7, v7, v16 948; GFX1030-NEXT: v_add_nc_u32_e32 v13, 1, v12 949; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v4, v0 950; GFX1030-NEXT: v_sub_nc_u32_e32 v14, v4, v0 951; GFX1030-NEXT: v_cmp_ge_u32_e64 s0, v5, v1 952; GFX1030-NEXT: v_sub_nc_u32_e32 v15, v5, v1 953; GFX1030-NEXT: v_cmp_ge_u32_e64 s1, v6, v2 954; GFX1030-NEXT: v_cndmask_b32_e32 v9, v9, v17, vcc_lo 955; GFX1030-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc_lo 956; GFX1030-NEXT: v_cndmask_b32_e64 v10, v10, v18, s0 957; GFX1030-NEXT: v_sub_nc_u32_e32 v16, v6, v2 958; GFX1030-NEXT: v_cmp_ge_u32_e64 s2, v7, v3 959; GFX1030-NEXT: v_add_nc_u32_e32 v14, 1, v9 960; GFX1030-NEXT: v_cndmask_b32_e64 v5, v5, v15, s0 961; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v4, v0 962; GFX1030-NEXT: v_cndmask_b32_e64 v11, v11, v19, s1 963; GFX1030-NEXT: v_cndmask_b32_e64 v12, v12, v13, s2 964; GFX1030-NEXT: v_sub_nc_u32_e32 v13, v7, v3 965; GFX1030-NEXT: v_add_nc_u32_e32 v15, 1, v10 966; GFX1030-NEXT: v_cndmask_b32_e64 v6, v6, v16, s1 967; GFX1030-NEXT: v_cndmask_b32_e32 v0, v9, v14, vcc_lo 968; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v5, v1 969; GFX1030-NEXT: v_add_nc_u32_e32 v16, 1, v11 970; GFX1030-NEXT: v_cndmask_b32_e64 v7, v7, v13, s2 971; GFX1030-NEXT: v_add_nc_u32_e32 v13, 1, v12 972; GFX1030-NEXT: v_cndmask_b32_e32 v1, v10, v15, vcc_lo 973; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v6, v2 974; GFX1030-NEXT: v_cndmask_b32_e32 v2, v11, v16, vcc_lo 975; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v7, v3 976; GFX1030-NEXT: v_cndmask_b32_e32 v3, v12, v13, vcc_lo 977; GFX1030-NEXT: global_store_dwordx4 v8, v[0:3], s[4:5] 978; GFX1030-NEXT: s_endpgm 979; 980; EG-LABEL: udiv_v4i32: 981; EG: ; %bb.0: 982; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] 983; EG-NEXT: TEX 1 @6 984; EG-NEXT: ALU 65, @11, KC0[CB0:0-32], KC1[] 985; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 1 986; EG-NEXT: CF_END 987; EG-NEXT: PAD 988; EG-NEXT: Fetch clause starting at 6: 989; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1 990; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1 991; EG-NEXT: ALU clause starting at 10: 992; EG-NEXT: MOV * T0.X, KC0[2].Z, 993; EG-NEXT: ALU clause starting at 11: 994; EG-NEXT: SUB_INT T2.W, 0.0, T1.W, 995; EG-NEXT: RECIP_UINT * T2.X, T1.W, 996; EG-NEXT: MULLO_INT * T2.Y, PV.W, PS, 997; EG-NEXT: MULHI * T2.Y, T2.X, PS, 998; EG-NEXT: ADD_INT * T2.W, T2.X, PS, 999; EG-NEXT: MULHI * T2.X, T0.W, PV.W, 1000; EG-NEXT: MULLO_INT * T2.Y, PS, T1.W, 1001; EG-NEXT: SUB_INT T2.W, 0.0, T1.X, 1002; EG-NEXT: RECIP_UINT * T2.Z, T1.X, 1003; EG-NEXT: MULLO_INT * T2.W, PV.W, PS, 1004; EG-NEXT: SUB_INT T3.W, 0.0, T1.Y, 1005; EG-NEXT: RECIP_UINT * T3.X, T1.Y, 1006; EG-NEXT: MULLO_INT * T3.Y, PV.W, PS, 1007; EG-NEXT: SUB_INT T3.W, 0.0, T1.Z, 1008; EG-NEXT: RECIP_UINT * T3.Z, T1.Z, 1009; EG-NEXT: MULLO_INT * T3.W, PV.W, PS, 1010; EG-NEXT: MULHI * T3.W, T3.Z, PS, 1011; EG-NEXT: ADD_INT T3.W, T3.Z, PS, 1012; EG-NEXT: MULHI * T3.Y, T3.X, T3.Y, 1013; EG-NEXT: ADD_INT T4.W, T3.X, PS, 1014; EG-NEXT: MULHI * T3.X, T0.Z, PV.W, 1015; EG-NEXT: MULHI * T3.Y, T0.Y, PV.W, 1016; EG-NEXT: MULLO_INT * T3.Z, PS, T1.Y, 1017; EG-NEXT: SUB_INT T3.W, T0.Y, PS, 1018; EG-NEXT: MULLO_INT * T0.Y, T3.X, T1.Z, 1019; EG-NEXT: SUB_INT T4.X, T0.Z, PS, 1020; EG-NEXT: ADD_INT T0.Y, T3.Y, 1, 1021; EG-NEXT: SETGE_UINT T0.Z, PV.W, T1.Y, 1022; EG-NEXT: SUB_INT T4.W, PV.W, T1.Y, 1023; EG-NEXT: MULHI * T2.W, T2.Z, T2.W, 1024; EG-NEXT: CNDE_INT T5.X, PV.Z, T3.W, PV.W, 1025; EG-NEXT: CNDE_INT T0.Y, PV.Z, T3.Y, PV.Y, BS:VEC_021/SCL_122 1026; EG-NEXT: SETGE_UINT T0.Z, PV.X, T1.Z, 1027; EG-NEXT: ADD_INT T2.W, T2.Z, PS, 1028; EG-NEXT: SUB_INT * T0.W, T0.W, T2.Y, 1029; EG-NEXT: ADD_INT T6.X, T3.X, 1, 1030; EG-NEXT: ADD_INT T2.Y, T2.X, 1, BS:VEC_120/SCL_212 1031; EG-NEXT: SETGE_UINT T2.Z, PS, T1.W, 1032; EG-NEXT: SUB_INT T3.W, PS, T1.W, 1033; EG-NEXT: MULHI * T2.W, T0.X, PV.W, 1034; EG-NEXT: SUB_INT T7.X, T4.X, T1.Z, 1035; EG-NEXT: CNDE_INT T3.Y, PV.Z, T0.W, PV.W, 1036; EG-NEXT: CNDE_INT T2.Z, PV.Z, T2.X, PV.Y, 1037; EG-NEXT: CNDE_INT * T0.W, T0.Z, T3.X, PV.X, BS:VEC_021/SCL_122 1038; EG-NEXT: MULLO_INT * T2.X, T2.W, T1.X, 1039; EG-NEXT: ADD_INT T3.X, T0.W, 1, 1040; EG-NEXT: ADD_INT T2.Y, T2.Z, 1, 1041; EG-NEXT: SETGE_UINT T3.Z, T3.Y, T1.W, 1042; EG-NEXT: SUB_INT T1.W, T0.X, PS, BS:VEC_201 1043; EG-NEXT: CNDE_INT * T3.W, T0.Z, T4.X, T7.X, 1044; EG-NEXT: SETGE_UINT T0.X, PS, T1.Z, BS:VEC_021/SCL_122 1045; EG-NEXT: ADD_INT T3.Y, T2.W, 1, 1046; EG-NEXT: SETGE_UINT T0.Z, PV.W, T1.X, 1047; EG-NEXT: SUB_INT T3.W, PV.W, T1.X, 1048; EG-NEXT: CNDE_INT * T4.W, PV.Z, T2.Z, PV.Y, 1049; EG-NEXT: CNDE_INT T2.X, PV.Z, T1.W, PV.W, 1050; EG-NEXT: CNDE_INT T2.Y, PV.Z, T2.W, PV.Y, BS:VEC_021/SCL_122 1051; EG-NEXT: CNDE_INT T4.Z, PV.X, T0.W, T3.X, BS:VEC_201 1052; EG-NEXT: ADD_INT T0.W, T0.Y, 1, 1053; EG-NEXT: SETGE_UINT * T1.W, T5.X, T1.Y, 1054; EG-NEXT: CNDE_INT T4.Y, PS, T0.Y, PV.W, 1055; EG-NEXT: ADD_INT T0.W, PV.Y, 1, 1056; EG-NEXT: SETGE_UINT * T1.W, PV.X, T1.X, 1057; EG-NEXT: CNDE_INT T4.X, PS, T2.Y, PV.W, 1058; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x, 1059; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1060 %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1 1061 %a = load <4 x i32>, <4 x i32> addrspace(1) * %in 1062 %b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr 1063 %result = udiv <4 x i32> %a, %b 1064 store <4 x i32> %result, <4 x i32> addrspace(1)* %out 1065 ret void 1066} 1067 1068define amdgpu_kernel void @udiv_i32_div_pow2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { 1069; SI-LABEL: udiv_i32_div_pow2: 1070; SI: ; %bb.0: 1071; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 1072; SI-NEXT: s_mov_b32 s3, 0xf000 1073; SI-NEXT: s_mov_b32 s2, -1 1074; SI-NEXT: s_waitcnt lgkmcnt(0) 1075; SI-NEXT: s_mov_b32 s0, s4 1076; SI-NEXT: s_mov_b32 s1, s5 1077; SI-NEXT: s_mov_b32 s4, s6 1078; SI-NEXT: s_mov_b32 s5, s7 1079; SI-NEXT: s_mov_b32 s6, s2 1080; SI-NEXT: s_mov_b32 s7, s3 1081; SI-NEXT: buffer_load_dword v0, off, s[4:7], 0 1082; SI-NEXT: s_waitcnt vmcnt(0) 1083; SI-NEXT: v_lshrrev_b32_e32 v0, 4, v0 1084; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 1085; SI-NEXT: s_endpgm 1086; 1087; VI-LABEL: udiv_i32_div_pow2: 1088; VI: ; %bb.0: 1089; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 1090; VI-NEXT: s_mov_b32 s3, 0xf000 1091; VI-NEXT: s_mov_b32 s2, -1 1092; VI-NEXT: s_waitcnt lgkmcnt(0) 1093; VI-NEXT: s_mov_b32 s0, s4 1094; VI-NEXT: s_mov_b32 s1, s5 1095; VI-NEXT: s_mov_b32 s4, s6 1096; VI-NEXT: s_mov_b32 s5, s7 1097; VI-NEXT: s_mov_b32 s6, s2 1098; VI-NEXT: s_mov_b32 s7, s3 1099; VI-NEXT: buffer_load_dword v0, off, s[4:7], 0 1100; VI-NEXT: s_waitcnt vmcnt(0) 1101; VI-NEXT: v_lshrrev_b32_e32 v0, 4, v0 1102; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 1103; VI-NEXT: s_endpgm 1104; 1105; GCN-LABEL: udiv_i32_div_pow2: 1106; GCN: ; %bb.0: 1107; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 1108; GCN-NEXT: s_waitcnt lgkmcnt(0) 1109; GCN-NEXT: v_mov_b32_e32 v2, s2 1110; GCN-NEXT: v_mov_b32_e32 v3, s3 1111; GCN-NEXT: flat_load_dword v2, v[2:3] 1112; GCN-NEXT: v_mov_b32_e32 v0, s0 1113; GCN-NEXT: v_mov_b32_e32 v1, s1 1114; GCN-NEXT: s_waitcnt vmcnt(0) 1115; GCN-NEXT: v_lshrrev_b32_e32 v2, 4, v2 1116; GCN-NEXT: flat_store_dword v[0:1], v2 1117; GCN-NEXT: s_endpgm 1118; 1119; GFX1030-LABEL: udiv_i32_div_pow2: 1120; GFX1030: ; %bb.0: 1121; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 1122; GFX1030-NEXT: v_mov_b32_e32 v0, 0 1123; GFX1030-NEXT: s_waitcnt lgkmcnt(0) 1124; GFX1030-NEXT: global_load_dword v1, v0, s[2:3] 1125; GFX1030-NEXT: s_waitcnt vmcnt(0) 1126; GFX1030-NEXT: v_lshrrev_b32_e32 v1, 4, v1 1127; GFX1030-NEXT: global_store_dword v0, v1, s[0:1] 1128; GFX1030-NEXT: s_endpgm 1129; 1130; EG-LABEL: udiv_i32_div_pow2: 1131; EG: ; %bb.0: 1132; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] 1133; EG-NEXT: TEX 0 @6 1134; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[] 1135; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 1136; EG-NEXT: CF_END 1137; EG-NEXT: PAD 1138; EG-NEXT: Fetch clause starting at 6: 1139; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 1140; EG-NEXT: ALU clause starting at 8: 1141; EG-NEXT: MOV * T0.X, KC0[2].Z, 1142; EG-NEXT: ALU clause starting at 9: 1143; EG-NEXT: LSHR T0.X, T0.X, literal.x, 1144; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, 1145; EG-NEXT: 4(5.605194e-45), 2(2.802597e-45) 1146 %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 1147 %a = load i32, i32 addrspace(1)* %in 1148 %result = udiv i32 %a, 16 1149 store i32 %result, i32 addrspace(1)* %out 1150 ret void 1151} 1152 1153define amdgpu_kernel void @udiv_i32_div_k_even(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { 1154; SI-LABEL: udiv_i32_div_k_even: 1155; SI: ; %bb.0: 1156; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 1157; SI-NEXT: s_mov_b32 s3, 0xf000 1158; SI-NEXT: s_mov_b32 s2, -1 1159; SI-NEXT: s_mov_b32 s10, s2 1160; SI-NEXT: s_mov_b32 s11, s3 1161; SI-NEXT: s_waitcnt lgkmcnt(0) 1162; SI-NEXT: s_mov_b32 s8, s6 1163; SI-NEXT: s_mov_b32 s9, s7 1164; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0 1165; SI-NEXT: s_mov_b32 s0, 0xfabbd9c1 1166; SI-NEXT: s_mov_b32 s1, s5 1167; SI-NEXT: s_waitcnt vmcnt(0) 1168; SI-NEXT: v_mul_hi_u32 v0, v0, s0 1169; SI-NEXT: s_mov_b32 s0, s4 1170; SI-NEXT: v_lshrrev_b32_e32 v0, 25, v0 1171; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 1172; SI-NEXT: s_endpgm 1173; 1174; VI-LABEL: udiv_i32_div_k_even: 1175; VI: ; %bb.0: 1176; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 1177; VI-NEXT: s_mov_b32 s3, 0xf000 1178; VI-NEXT: s_mov_b32 s2, -1 1179; VI-NEXT: s_mov_b32 s10, s2 1180; VI-NEXT: s_mov_b32 s11, s3 1181; VI-NEXT: s_waitcnt lgkmcnt(0) 1182; VI-NEXT: s_mov_b32 s8, s6 1183; VI-NEXT: s_mov_b32 s9, s7 1184; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0 1185; VI-NEXT: s_mov_b32 s0, 0xfabbd9c1 1186; VI-NEXT: s_mov_b32 s1, s5 1187; VI-NEXT: s_waitcnt vmcnt(0) 1188; VI-NEXT: v_mul_hi_u32 v0, v0, s0 1189; VI-NEXT: s_mov_b32 s0, s4 1190; VI-NEXT: v_lshrrev_b32_e32 v0, 25, v0 1191; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 1192; VI-NEXT: s_endpgm 1193; 1194; GCN-LABEL: udiv_i32_div_k_even: 1195; GCN: ; %bb.0: 1196; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 1197; GCN-NEXT: s_waitcnt lgkmcnt(0) 1198; GCN-NEXT: v_mov_b32_e32 v0, s2 1199; GCN-NEXT: v_mov_b32_e32 v1, s3 1200; GCN-NEXT: flat_load_dword v0, v[0:1] 1201; GCN-NEXT: s_mov_b32 s2, 0xfabbd9c1 1202; GCN-NEXT: v_mov_b32_e32 v1, s1 1203; GCN-NEXT: s_waitcnt vmcnt(0) 1204; GCN-NEXT: v_mul_hi_u32 v2, v0, s2 1205; GCN-NEXT: v_mov_b32_e32 v0, s0 1206; GCN-NEXT: v_lshrrev_b32_e32 v2, 25, v2 1207; GCN-NEXT: flat_store_dword v[0:1], v2 1208; GCN-NEXT: s_endpgm 1209; 1210; GFX1030-LABEL: udiv_i32_div_k_even: 1211; GFX1030: ; %bb.0: 1212; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 1213; GFX1030-NEXT: v_mov_b32_e32 v0, 0 1214; GFX1030-NEXT: s_waitcnt lgkmcnt(0) 1215; GFX1030-NEXT: global_load_dword v1, v0, s[2:3] 1216; GFX1030-NEXT: s_waitcnt vmcnt(0) 1217; GFX1030-NEXT: v_mul_hi_u32 v1, 0xfabbd9c1, v1 1218; GFX1030-NEXT: v_lshrrev_b32_e32 v1, 25, v1 1219; GFX1030-NEXT: global_store_dword v0, v1, s[0:1] 1220; GFX1030-NEXT: s_endpgm 1221; 1222; EG-LABEL: udiv_i32_div_k_even: 1223; EG: ; %bb.0: 1224; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] 1225; EG-NEXT: TEX 0 @6 1226; EG-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[] 1227; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 1228; EG-NEXT: CF_END 1229; EG-NEXT: PAD 1230; EG-NEXT: Fetch clause starting at 6: 1231; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 1232; EG-NEXT: ALU clause starting at 8: 1233; EG-NEXT: MOV * T0.X, KC0[2].Z, 1234; EG-NEXT: ALU clause starting at 9: 1235; EG-NEXT: MULHI * T0.X, T0.X, literal.x, 1236; EG-NEXT: -88352319(-4.876880e+35), 0(0.000000e+00) 1237; EG-NEXT: LSHR T0.X, PS, literal.x, 1238; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, 1239; EG-NEXT: 25(3.503246e-44), 2(2.802597e-45) 1240 %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 1241 %a = load i32, i32 addrspace(1)* %in 1242 %result = udiv i32 %a, 34259182 1243 store i32 %result, i32 addrspace(1)* %out 1244 ret void 1245} 1246 1247define amdgpu_kernel void @udiv_i32_div_k_odd(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { 1248; SI-LABEL: udiv_i32_div_k_odd: 1249; SI: ; %bb.0: 1250; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 1251; SI-NEXT: s_mov_b32 s3, 0xf000 1252; SI-NEXT: s_mov_b32 s2, -1 1253; SI-NEXT: s_mov_b32 s10, s2 1254; SI-NEXT: s_mov_b32 s11, s3 1255; SI-NEXT: s_waitcnt lgkmcnt(0) 1256; SI-NEXT: s_mov_b32 s8, s6 1257; SI-NEXT: s_mov_b32 s9, s7 1258; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0 1259; SI-NEXT: s_mov_b32 s0, 0x7d5deca3 1260; SI-NEXT: s_mov_b32 s1, s5 1261; SI-NEXT: s_waitcnt vmcnt(0) 1262; SI-NEXT: v_mul_hi_u32 v0, v0, s0 1263; SI-NEXT: s_mov_b32 s0, s4 1264; SI-NEXT: v_lshrrev_b32_e32 v0, 24, v0 1265; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 1266; SI-NEXT: s_endpgm 1267; 1268; VI-LABEL: udiv_i32_div_k_odd: 1269; VI: ; %bb.0: 1270; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 1271; VI-NEXT: s_mov_b32 s3, 0xf000 1272; VI-NEXT: s_mov_b32 s2, -1 1273; VI-NEXT: s_mov_b32 s10, s2 1274; VI-NEXT: s_mov_b32 s11, s3 1275; VI-NEXT: s_waitcnt lgkmcnt(0) 1276; VI-NEXT: s_mov_b32 s8, s6 1277; VI-NEXT: s_mov_b32 s9, s7 1278; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0 1279; VI-NEXT: s_mov_b32 s0, 0x7d5deca3 1280; VI-NEXT: s_mov_b32 s1, s5 1281; VI-NEXT: s_waitcnt vmcnt(0) 1282; VI-NEXT: v_mul_hi_u32 v0, v0, s0 1283; VI-NEXT: s_mov_b32 s0, s4 1284; VI-NEXT: v_lshrrev_b32_e32 v0, 24, v0 1285; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 1286; VI-NEXT: s_endpgm 1287; 1288; GCN-LABEL: udiv_i32_div_k_odd: 1289; GCN: ; %bb.0: 1290; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 1291; GCN-NEXT: s_waitcnt lgkmcnt(0) 1292; GCN-NEXT: v_mov_b32_e32 v0, s2 1293; GCN-NEXT: v_mov_b32_e32 v1, s3 1294; GCN-NEXT: flat_load_dword v0, v[0:1] 1295; GCN-NEXT: s_mov_b32 s2, 0x7d5deca3 1296; GCN-NEXT: v_mov_b32_e32 v1, s1 1297; GCN-NEXT: s_waitcnt vmcnt(0) 1298; GCN-NEXT: v_mul_hi_u32 v2, v0, s2 1299; GCN-NEXT: v_mov_b32_e32 v0, s0 1300; GCN-NEXT: v_lshrrev_b32_e32 v2, 24, v2 1301; GCN-NEXT: flat_store_dword v[0:1], v2 1302; GCN-NEXT: s_endpgm 1303; 1304; GFX1030-LABEL: udiv_i32_div_k_odd: 1305; GFX1030: ; %bb.0: 1306; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 1307; GFX1030-NEXT: v_mov_b32_e32 v0, 0 1308; GFX1030-NEXT: s_waitcnt lgkmcnt(0) 1309; GFX1030-NEXT: global_load_dword v1, v0, s[2:3] 1310; GFX1030-NEXT: s_waitcnt vmcnt(0) 1311; GFX1030-NEXT: v_mul_hi_u32 v1, 0x7d5deca3, v1 1312; GFX1030-NEXT: v_lshrrev_b32_e32 v1, 24, v1 1313; GFX1030-NEXT: global_store_dword v0, v1, s[0:1] 1314; GFX1030-NEXT: s_endpgm 1315; 1316; EG-LABEL: udiv_i32_div_k_odd: 1317; EG: ; %bb.0: 1318; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] 1319; EG-NEXT: TEX 0 @6 1320; EG-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[] 1321; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 1322; EG-NEXT: CF_END 1323; EG-NEXT: PAD 1324; EG-NEXT: Fetch clause starting at 6: 1325; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 1326; EG-NEXT: ALU clause starting at 8: 1327; EG-NEXT: MOV * T0.X, KC0[2].Z, 1328; EG-NEXT: ALU clause starting at 9: 1329; EG-NEXT: MULHI * T0.X, T0.X, literal.x, 1330; EG-NEXT: 2103307427(1.843675e+37), 0(0.000000e+00) 1331; EG-NEXT: LSHR T0.X, PS, literal.x, 1332; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, 1333; EG-NEXT: 24(3.363116e-44), 2(2.802597e-45) 1334 %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 1335 %a = load i32, i32 addrspace(1)* %in 1336 %result = udiv i32 %a, 34259183 1337 store i32 %result, i32 addrspace(1)* %out 1338 ret void 1339} 1340 1341define amdgpu_kernel void @v_udiv_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { 1342; SI-LABEL: v_udiv_i8: 1343; SI: ; %bb.0: 1344; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 1345; SI-NEXT: s_mov_b32 s3, 0xf000 1346; SI-NEXT: s_mov_b32 s2, -1 1347; SI-NEXT: s_mov_b32 s10, s2 1348; SI-NEXT: s_mov_b32 s11, s3 1349; SI-NEXT: s_waitcnt lgkmcnt(0) 1350; SI-NEXT: s_mov_b32 s8, s6 1351; SI-NEXT: s_mov_b32 s9, s7 1352; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 1353; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:1 1354; SI-NEXT: s_mov_b32 s0, s4 1355; SI-NEXT: s_mov_b32 s1, s5 1356; SI-NEXT: s_waitcnt vmcnt(1) 1357; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0 1358; SI-NEXT: s_waitcnt vmcnt(0) 1359; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1 1360; SI-NEXT: v_rcp_iflag_f32_e32 v2, v1 1361; SI-NEXT: v_mul_f32_e32 v2, v0, v2 1362; SI-NEXT: v_trunc_f32_e32 v2, v2 1363; SI-NEXT: v_cvt_u32_f32_e32 v3, v2 1364; SI-NEXT: v_mad_f32 v0, -v2, v1, v0 1365; SI-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1 1366; SI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc 1367; SI-NEXT: v_and_b32_e32 v0, 0xff, v0 1368; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 1369; SI-NEXT: s_endpgm 1370; 1371; VI-LABEL: v_udiv_i8: 1372; VI: ; %bb.0: 1373; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 1374; VI-NEXT: s_mov_b32 s3, 0xf000 1375; VI-NEXT: s_mov_b32 s2, -1 1376; VI-NEXT: s_mov_b32 s10, s2 1377; VI-NEXT: s_mov_b32 s11, s3 1378; VI-NEXT: s_waitcnt lgkmcnt(0) 1379; VI-NEXT: s_mov_b32 s8, s6 1380; VI-NEXT: s_mov_b32 s9, s7 1381; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 1382; VI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:1 1383; VI-NEXT: s_mov_b32 s0, s4 1384; VI-NEXT: s_mov_b32 s1, s5 1385; VI-NEXT: s_waitcnt vmcnt(1) 1386; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0 1387; VI-NEXT: s_waitcnt vmcnt(0) 1388; VI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1 1389; VI-NEXT: v_rcp_iflag_f32_e32 v2, v1 1390; VI-NEXT: v_mul_f32_e32 v2, v0, v2 1391; VI-NEXT: v_trunc_f32_e32 v2, v2 1392; VI-NEXT: v_cvt_u32_f32_e32 v3, v2 1393; VI-NEXT: v_mad_f32 v0, -v2, v1, v0 1394; VI-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1 1395; VI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc 1396; VI-NEXT: v_and_b32_e32 v0, 0xff, v0 1397; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 1398; VI-NEXT: s_endpgm 1399; 1400; GCN-LABEL: v_udiv_i8: 1401; GCN: ; %bb.0: 1402; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 1403; GCN-NEXT: s_waitcnt lgkmcnt(0) 1404; GCN-NEXT: v_mov_b32_e32 v0, s2 1405; GCN-NEXT: v_mov_b32_e32 v1, s3 1406; GCN-NEXT: flat_load_ushort v2, v[0:1] 1407; GCN-NEXT: v_mov_b32_e32 v0, s0 1408; GCN-NEXT: v_mov_b32_e32 v1, s1 1409; GCN-NEXT: s_waitcnt vmcnt(0) 1410; GCN-NEXT: v_cvt_f32_ubyte1_e32 v3, v2 1411; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v3 1412; GCN-NEXT: v_cvt_f32_ubyte0_e32 v2, v2 1413; GCN-NEXT: v_mul_f32_e32 v4, v2, v4 1414; GCN-NEXT: v_trunc_f32_e32 v4, v4 1415; GCN-NEXT: v_cvt_u32_f32_e32 v5, v4 1416; GCN-NEXT: v_mad_f32 v2, -v4, v3, v2 1417; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v3 1418; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc 1419; GCN-NEXT: v_and_b32_e32 v2, 0xff, v2 1420; GCN-NEXT: flat_store_dword v[0:1], v2 1421; GCN-NEXT: s_endpgm 1422; 1423; GFX1030-LABEL: v_udiv_i8: 1424; GFX1030: ; %bb.0: 1425; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 1426; GFX1030-NEXT: v_mov_b32_e32 v0, 0 1427; GFX1030-NEXT: s_waitcnt lgkmcnt(0) 1428; GFX1030-NEXT: global_load_ushort v1, v0, s[2:3] 1429; GFX1030-NEXT: s_waitcnt vmcnt(0) 1430; GFX1030-NEXT: v_cvt_f32_ubyte1_e32 v2, v1 1431; GFX1030-NEXT: v_cvt_f32_ubyte0_e32 v1, v1 1432; GFX1030-NEXT: v_rcp_iflag_f32_e32 v3, v2 1433; GFX1030-NEXT: v_mul_f32_e32 v3, v1, v3 1434; GFX1030-NEXT: v_trunc_f32_e32 v3, v3 1435; GFX1030-NEXT: v_fma_f32 v1, -v3, v2, v1 1436; GFX1030-NEXT: v_cvt_u32_f32_e32 v3, v3 1437; GFX1030-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v1|, v2 1438; GFX1030-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v3, vcc_lo 1439; GFX1030-NEXT: v_and_b32_e32 v1, 0xff, v1 1440; GFX1030-NEXT: global_store_dword v0, v1, s[0:1] 1441; GFX1030-NEXT: s_endpgm 1442; 1443; EG-LABEL: v_udiv_i8: 1444; EG: ; %bb.0: 1445; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] 1446; EG-NEXT: TEX 1 @6 1447; EG-NEXT: ALU 14, @11, KC0[CB0:0-32], KC1[] 1448; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 1449; EG-NEXT: CF_END 1450; EG-NEXT: PAD 1451; EG-NEXT: Fetch clause starting at 6: 1452; EG-NEXT: VTX_READ_8 T1.X, T0.X, 1, #1 1453; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1 1454; EG-NEXT: ALU clause starting at 10: 1455; EG-NEXT: MOV * T0.X, KC0[2].Z, 1456; EG-NEXT: ALU clause starting at 11: 1457; EG-NEXT: UINT_TO_FLT * T0.Y, T1.X, 1458; EG-NEXT: RECIP_IEEE * T0.Z, PS, 1459; EG-NEXT: UINT_TO_FLT * T0.X, T0.X, 1460; EG-NEXT: MUL_IEEE * T0.W, PS, T0.Z, 1461; EG-NEXT: TRUNC * T0.W, PV.W, 1462; EG-NEXT: MULADD_IEEE T1.W, -PV.W, T0.Y, T0.X, 1463; EG-NEXT: TRUNC * T0.W, PV.W, 1464; EG-NEXT: SETGE * T1.W, |PV.W|, |T0.Y|, 1465; EG-NEXT: CNDE T1.W, PV.W, 0.0, literal.x, 1466; EG-NEXT: FLT_TO_UINT * T0.X, T0.W, 1467; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00) 1468; EG-NEXT: ADD_INT * T0.W, PS, PV.W, 1469; EG-NEXT: AND_INT T0.X, PV.W, literal.x, 1470; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, 1471; EG-NEXT: 255(3.573311e-43), 2(2.802597e-45) 1472 %den_ptr = getelementptr i8, i8 addrspace(1)* %in, i8 1 1473 %num = load i8, i8 addrspace(1) * %in 1474 %den = load i8, i8 addrspace(1) * %den_ptr 1475 %result = udiv i8 %num, %den 1476 %result.ext = zext i8 %result to i32 1477 store i32 %result.ext, i32 addrspace(1)* %out 1478 ret void 1479} 1480 1481define amdgpu_kernel void @v_udiv_i16(i32 addrspace(1)* %out, i16 addrspace(1)* %in) { 1482; SI-LABEL: v_udiv_i16: 1483; SI: ; %bb.0: 1484; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 1485; SI-NEXT: s_mov_b32 s3, 0xf000 1486; SI-NEXT: s_mov_b32 s2, -1 1487; SI-NEXT: s_mov_b32 s10, s2 1488; SI-NEXT: s_mov_b32 s11, s3 1489; SI-NEXT: s_waitcnt lgkmcnt(0) 1490; SI-NEXT: s_mov_b32 s8, s6 1491; SI-NEXT: s_mov_b32 s9, s7 1492; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0 offset:2 1493; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 1494; SI-NEXT: s_mov_b32 s0, s4 1495; SI-NEXT: s_mov_b32 s1, s5 1496; SI-NEXT: s_waitcnt vmcnt(1) 1497; SI-NEXT: v_cvt_f32_u32_e32 v0, v0 1498; SI-NEXT: s_waitcnt vmcnt(0) 1499; SI-NEXT: v_cvt_f32_u32_e32 v1, v1 1500; SI-NEXT: v_rcp_iflag_f32_e32 v2, v0 1501; SI-NEXT: v_mul_f32_e32 v2, v1, v2 1502; SI-NEXT: v_trunc_f32_e32 v2, v2 1503; SI-NEXT: v_cvt_u32_f32_e32 v3, v2 1504; SI-NEXT: v_mad_f32 v1, -v2, v0, v1 1505; SI-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 1506; SI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc 1507; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0 1508; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 1509; SI-NEXT: s_endpgm 1510; 1511; VI-LABEL: v_udiv_i16: 1512; VI: ; %bb.0: 1513; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 1514; VI-NEXT: s_mov_b32 s3, 0xf000 1515; VI-NEXT: s_mov_b32 s2, -1 1516; VI-NEXT: s_mov_b32 s10, s2 1517; VI-NEXT: s_mov_b32 s11, s3 1518; VI-NEXT: s_waitcnt lgkmcnt(0) 1519; VI-NEXT: s_mov_b32 s8, s6 1520; VI-NEXT: s_mov_b32 s9, s7 1521; VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0 offset:2 1522; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 1523; VI-NEXT: s_mov_b32 s0, s4 1524; VI-NEXT: s_mov_b32 s1, s5 1525; VI-NEXT: s_waitcnt vmcnt(1) 1526; VI-NEXT: v_cvt_f32_u32_e32 v0, v0 1527; VI-NEXT: s_waitcnt vmcnt(0) 1528; VI-NEXT: v_cvt_f32_u32_e32 v1, v1 1529; VI-NEXT: v_rcp_iflag_f32_e32 v2, v0 1530; VI-NEXT: v_mul_f32_e32 v2, v1, v2 1531; VI-NEXT: v_trunc_f32_e32 v2, v2 1532; VI-NEXT: v_cvt_u32_f32_e32 v3, v2 1533; VI-NEXT: v_mad_f32 v1, -v2, v0, v1 1534; VI-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 1535; VI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc 1536; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0 1537; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 1538; VI-NEXT: s_endpgm 1539; 1540; GCN-LABEL: v_udiv_i16: 1541; GCN: ; %bb.0: 1542; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 1543; GCN-NEXT: s_waitcnt lgkmcnt(0) 1544; GCN-NEXT: s_add_u32 s4, s2, 2 1545; GCN-NEXT: s_addc_u32 s5, s3, 0 1546; GCN-NEXT: v_mov_b32_e32 v2, s4 1547; GCN-NEXT: v_mov_b32_e32 v3, s5 1548; GCN-NEXT: flat_load_ushort v2, v[2:3] 1549; GCN-NEXT: v_mov_b32_e32 v0, s2 1550; GCN-NEXT: v_mov_b32_e32 v1, s3 1551; GCN-NEXT: flat_load_ushort v0, v[0:1] 1552; GCN-NEXT: v_mov_b32_e32 v1, s1 1553; GCN-NEXT: s_waitcnt vmcnt(1) 1554; GCN-NEXT: v_cvt_f32_u32_e32 v2, v2 1555; GCN-NEXT: s_waitcnt vmcnt(0) 1556; GCN-NEXT: v_cvt_f32_u32_e32 v3, v0 1557; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2 1558; GCN-NEXT: v_mov_b32_e32 v0, s0 1559; GCN-NEXT: v_mul_f32_e32 v4, v3, v4 1560; GCN-NEXT: v_trunc_f32_e32 v4, v4 1561; GCN-NEXT: v_cvt_u32_f32_e32 v5, v4 1562; GCN-NEXT: v_mad_f32 v3, -v4, v2, v3 1563; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v2 1564; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc 1565; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2 1566; GCN-NEXT: flat_store_dword v[0:1], v2 1567; GCN-NEXT: s_endpgm 1568; 1569; GFX1030-LABEL: v_udiv_i16: 1570; GFX1030: ; %bb.0: 1571; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 1572; GFX1030-NEXT: v_mov_b32_e32 v0, 0 1573; GFX1030-NEXT: s_waitcnt lgkmcnt(0) 1574; GFX1030-NEXT: s_clause 0x1 1575; GFX1030-NEXT: global_load_ushort v1, v0, s[2:3] offset:2 1576; GFX1030-NEXT: global_load_ushort v2, v0, s[2:3] 1577; GFX1030-NEXT: s_waitcnt vmcnt(1) 1578; GFX1030-NEXT: v_cvt_f32_u32_e32 v1, v1 1579; GFX1030-NEXT: s_waitcnt vmcnt(0) 1580; GFX1030-NEXT: v_cvt_f32_u32_e32 v2, v2 1581; GFX1030-NEXT: v_rcp_iflag_f32_e32 v3, v1 1582; GFX1030-NEXT: v_mul_f32_e32 v3, v2, v3 1583; GFX1030-NEXT: v_trunc_f32_e32 v3, v3 1584; GFX1030-NEXT: v_fma_f32 v2, -v3, v1, v2 1585; GFX1030-NEXT: v_cvt_u32_f32_e32 v3, v3 1586; GFX1030-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v2|, v1 1587; GFX1030-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v3, vcc_lo 1588; GFX1030-NEXT: v_and_b32_e32 v1, 0xffff, v1 1589; GFX1030-NEXT: global_store_dword v0, v1, s[0:1] 1590; GFX1030-NEXT: s_endpgm 1591; 1592; EG-LABEL: v_udiv_i16: 1593; EG: ; %bb.0: 1594; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] 1595; EG-NEXT: TEX 1 @6 1596; EG-NEXT: ALU 14, @11, KC0[CB0:0-32], KC1[] 1597; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 1598; EG-NEXT: CF_END 1599; EG-NEXT: PAD 1600; EG-NEXT: Fetch clause starting at 6: 1601; EG-NEXT: VTX_READ_16 T1.X, T0.X, 2, #1 1602; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #1 1603; EG-NEXT: ALU clause starting at 10: 1604; EG-NEXT: MOV * T0.X, KC0[2].Z, 1605; EG-NEXT: ALU clause starting at 11: 1606; EG-NEXT: UINT_TO_FLT * T0.Y, T1.X, 1607; EG-NEXT: RECIP_IEEE * T0.Z, PS, 1608; EG-NEXT: UINT_TO_FLT * T0.X, T0.X, 1609; EG-NEXT: MUL_IEEE * T0.W, PS, T0.Z, 1610; EG-NEXT: TRUNC * T0.W, PV.W, 1611; EG-NEXT: MULADD_IEEE T1.W, -PV.W, T0.Y, T0.X, 1612; EG-NEXT: TRUNC * T0.W, PV.W, 1613; EG-NEXT: SETGE * T1.W, |PV.W|, |T0.Y|, 1614; EG-NEXT: CNDE T1.W, PV.W, 0.0, literal.x, 1615; EG-NEXT: FLT_TO_UINT * T0.X, T0.W, 1616; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00) 1617; EG-NEXT: ADD_INT * T0.W, PS, PV.W, 1618; EG-NEXT: AND_INT T0.X, PV.W, literal.x, 1619; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, 1620; EG-NEXT: 65535(9.183409e-41), 2(2.802597e-45) 1621 %den_ptr = getelementptr i16, i16 addrspace(1)* %in, i16 1 1622 %num = load i16, i16 addrspace(1) * %in 1623 %den = load i16, i16 addrspace(1) * %den_ptr 1624 %result = udiv i16 %num, %den 1625 %result.ext = zext i16 %result to i32 1626 store i32 %result.ext, i32 addrspace(1)* %out 1627 ret void 1628} 1629 1630define amdgpu_kernel void @v_udiv_i23(i32 addrspace(1)* %out, i23 addrspace(1)* %in) { 1631; SI-LABEL: v_udiv_i23: 1632; SI: ; %bb.0: 1633; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 1634; SI-NEXT: s_mov_b32 s3, 0xf000 1635; SI-NEXT: s_mov_b32 s2, -1 1636; SI-NEXT: s_mov_b32 s10, s2 1637; SI-NEXT: s_mov_b32 s11, s3 1638; SI-NEXT: s_waitcnt lgkmcnt(0) 1639; SI-NEXT: s_mov_b32 s8, s6 1640; SI-NEXT: s_mov_b32 s9, s7 1641; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0 1642; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:2 1643; SI-NEXT: buffer_load_ushort v2, off, s[8:11], 0 offset:4 1644; SI-NEXT: buffer_load_ubyte v3, off, s[8:11], 0 offset:6 1645; SI-NEXT: s_mov_b32 s0, s4 1646; SI-NEXT: s_mov_b32 s1, s5 1647; SI-NEXT: s_waitcnt vmcnt(2) 1648; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1649; SI-NEXT: v_or_b32_e32 v0, v0, v1 1650; SI-NEXT: s_waitcnt vmcnt(0) 1651; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 1652; SI-NEXT: v_or_b32_e32 v2, v2, v3 1653; SI-NEXT: v_cvt_f32_u32_e32 v2, v2 1654; SI-NEXT: v_cvt_f32_u32_e32 v0, v0 1655; SI-NEXT: v_rcp_iflag_f32_e32 v1, v2 1656; SI-NEXT: v_mul_f32_e32 v1, v0, v1 1657; SI-NEXT: v_trunc_f32_e32 v1, v1 1658; SI-NEXT: v_cvt_u32_f32_e32 v3, v1 1659; SI-NEXT: v_mad_f32 v0, -v1, v2, v0 1660; SI-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v2 1661; SI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc 1662; SI-NEXT: v_and_b32_e32 v0, 0x7fffff, v0 1663; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 1664; SI-NEXT: s_endpgm 1665; 1666; VI-LABEL: v_udiv_i23: 1667; VI: ; %bb.0: 1668; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 1669; VI-NEXT: s_mov_b32 s3, 0xf000 1670; VI-NEXT: s_mov_b32 s2, -1 1671; VI-NEXT: s_mov_b32 s10, s2 1672; VI-NEXT: s_mov_b32 s11, s3 1673; VI-NEXT: s_waitcnt lgkmcnt(0) 1674; VI-NEXT: s_mov_b32 s8, s6 1675; VI-NEXT: s_mov_b32 s9, s7 1676; VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0 1677; VI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:2 1678; VI-NEXT: buffer_load_ushort v2, off, s[8:11], 0 offset:4 1679; VI-NEXT: buffer_load_ubyte v3, off, s[8:11], 0 offset:6 1680; VI-NEXT: s_mov_b32 s0, s4 1681; VI-NEXT: s_mov_b32 s1, s5 1682; VI-NEXT: s_waitcnt vmcnt(2) 1683; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1684; VI-NEXT: v_or_b32_e32 v0, v0, v1 1685; VI-NEXT: s_waitcnt vmcnt(0) 1686; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 1687; VI-NEXT: v_or_b32_e32 v2, v2, v3 1688; VI-NEXT: v_cvt_f32_u32_e32 v2, v2 1689; VI-NEXT: v_cvt_f32_u32_e32 v0, v0 1690; VI-NEXT: v_rcp_iflag_f32_e32 v1, v2 1691; VI-NEXT: v_mul_f32_e32 v1, v0, v1 1692; VI-NEXT: v_trunc_f32_e32 v1, v1 1693; VI-NEXT: v_cvt_u32_f32_e32 v3, v1 1694; VI-NEXT: v_mad_f32 v0, -v1, v2, v0 1695; VI-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v2 1696; VI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc 1697; VI-NEXT: v_and_b32_e32 v0, 0x7fffff, v0 1698; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 1699; VI-NEXT: s_endpgm 1700; 1701; GCN-LABEL: v_udiv_i23: 1702; GCN: ; %bb.0: 1703; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 1704; GCN-NEXT: s_waitcnt lgkmcnt(0) 1705; GCN-NEXT: s_add_u32 s4, s2, 4 1706; GCN-NEXT: s_addc_u32 s5, s3, 0 1707; GCN-NEXT: s_add_u32 s6, s2, 2 1708; GCN-NEXT: v_mov_b32_e32 v0, s2 1709; GCN-NEXT: s_addc_u32 s7, s3, 0 1710; GCN-NEXT: v_mov_b32_e32 v1, s3 1711; GCN-NEXT: s_add_u32 s2, s2, 6 1712; GCN-NEXT: v_mov_b32_e32 v4, s6 1713; GCN-NEXT: s_addc_u32 s3, s3, 0 1714; GCN-NEXT: v_mov_b32_e32 v2, s4 1715; GCN-NEXT: v_mov_b32_e32 v5, s7 1716; GCN-NEXT: v_mov_b32_e32 v7, s3 1717; GCN-NEXT: v_mov_b32_e32 v3, s5 1718; GCN-NEXT: v_mov_b32_e32 v6, s2 1719; GCN-NEXT: flat_load_ubyte v4, v[4:5] 1720; GCN-NEXT: flat_load_ushort v0, v[0:1] 1721; GCN-NEXT: flat_load_ubyte v1, v[6:7] 1722; GCN-NEXT: flat_load_ushort v2, v[2:3] 1723; GCN-NEXT: s_waitcnt vmcnt(1) 1724; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1725; GCN-NEXT: s_waitcnt vmcnt(0) 1726; GCN-NEXT: v_or_b32_e32 v1, v2, v1 1727; GCN-NEXT: v_cvt_f32_u32_e32 v2, v1 1728; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v4 1729; GCN-NEXT: v_or_b32_e32 v0, v0, v1 1730; GCN-NEXT: v_cvt_f32_u32_e32 v3, v0 1731; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2 1732; GCN-NEXT: v_mov_b32_e32 v0, s0 1733; GCN-NEXT: v_mov_b32_e32 v1, s1 1734; GCN-NEXT: v_mul_f32_e32 v4, v3, v4 1735; GCN-NEXT: v_trunc_f32_e32 v4, v4 1736; GCN-NEXT: v_cvt_u32_f32_e32 v5, v4 1737; GCN-NEXT: v_mad_f32 v3, -v4, v2, v3 1738; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v2 1739; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc 1740; GCN-NEXT: v_and_b32_e32 v2, 0x7fffff, v2 1741; GCN-NEXT: flat_store_dword v[0:1], v2 1742; GCN-NEXT: s_endpgm 1743; 1744; GFX1030-LABEL: v_udiv_i23: 1745; GFX1030: ; %bb.0: 1746; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 1747; GFX1030-NEXT: v_mov_b32_e32 v0, 0 1748; GFX1030-NEXT: s_waitcnt lgkmcnt(0) 1749; GFX1030-NEXT: s_clause 0x3 1750; GFX1030-NEXT: global_load_ubyte v1, v0, s[2:3] offset:6 1751; GFX1030-NEXT: global_load_ushort v2, v0, s[2:3] offset:4 1752; GFX1030-NEXT: global_load_ubyte v3, v0, s[2:3] offset:2 1753; GFX1030-NEXT: global_load_ushort v4, v0, s[2:3] 1754; GFX1030-NEXT: s_waitcnt vmcnt(3) 1755; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1756; GFX1030-NEXT: s_waitcnt vmcnt(2) 1757; GFX1030-NEXT: v_or_b32_e32 v1, v2, v1 1758; GFX1030-NEXT: s_waitcnt vmcnt(1) 1759; GFX1030-NEXT: v_lshlrev_b32_e32 v2, 16, v3 1760; GFX1030-NEXT: v_cvt_f32_u32_e32 v1, v1 1761; GFX1030-NEXT: s_waitcnt vmcnt(0) 1762; GFX1030-NEXT: v_or_b32_e32 v2, v4, v2 1763; GFX1030-NEXT: v_rcp_iflag_f32_e32 v3, v1 1764; GFX1030-NEXT: v_cvt_f32_u32_e32 v2, v2 1765; GFX1030-NEXT: v_mul_f32_e32 v3, v2, v3 1766; GFX1030-NEXT: v_trunc_f32_e32 v3, v3 1767; GFX1030-NEXT: v_fma_f32 v2, -v3, v1, v2 1768; GFX1030-NEXT: v_cvt_u32_f32_e32 v3, v3 1769; GFX1030-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v2|, v1 1770; GFX1030-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v3, vcc_lo 1771; GFX1030-NEXT: v_and_b32_e32 v1, 0x7fffff, v1 1772; GFX1030-NEXT: global_store_dword v0, v1, s[0:1] 1773; GFX1030-NEXT: s_endpgm 1774; 1775; EG-LABEL: v_udiv_i23: 1776; EG: ; %bb.0: 1777; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[] 1778; EG-NEXT: TEX 3 @6 1779; EG-NEXT: ALU 20, @15, KC0[CB0:0-32], KC1[] 1780; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 1781; EG-NEXT: CF_END 1782; EG-NEXT: PAD 1783; EG-NEXT: Fetch clause starting at 6: 1784; EG-NEXT: VTX_READ_8 T1.X, T0.X, 6, #1 1785; EG-NEXT: VTX_READ_16 T2.X, T0.X, 0, #1 1786; EG-NEXT: VTX_READ_8 T3.X, T0.X, 2, #1 1787; EG-NEXT: VTX_READ_16 T0.X, T0.X, 4, #1 1788; EG-NEXT: ALU clause starting at 14: 1789; EG-NEXT: MOV * T0.X, KC0[2].Z, 1790; EG-NEXT: ALU clause starting at 15: 1791; EG-NEXT: LSHL * T0.W, T1.X, literal.x, 1792; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) 1793; EG-NEXT: OR_INT T0.W, T0.X, PV.W, 1794; EG-NEXT: LSHL * T1.W, T3.X, literal.x, 1795; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) 1796; EG-NEXT: UINT_TO_FLT * T0.X, PV.W, 1797; EG-NEXT: OR_INT T0.W, T2.X, T1.W, 1798; EG-NEXT: RECIP_IEEE * T0.Y, PS, 1799; EG-NEXT: UINT_TO_FLT * T0.Z, PV.W, 1800; EG-NEXT: MUL_IEEE * T0.W, PS, T0.Y, 1801; EG-NEXT: TRUNC * T0.W, PV.W, 1802; EG-NEXT: MULADD_IEEE T1.W, -PV.W, T0.X, T0.Z, 1803; EG-NEXT: TRUNC * T0.W, PV.W, 1804; EG-NEXT: SETGE * T1.W, |PV.W|, |T0.X|, 1805; EG-NEXT: CNDE T1.W, PV.W, 0.0, literal.x, 1806; EG-NEXT: FLT_TO_UINT * T0.X, T0.W, 1807; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00) 1808; EG-NEXT: ADD_INT * T0.W, PS, PV.W, 1809; EG-NEXT: AND_INT T0.X, PV.W, literal.x, 1810; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, 1811; EG-NEXT: 8388607(1.175494e-38), 2(2.802597e-45) 1812 %den_ptr = getelementptr i23, i23 addrspace(1)* %in, i23 1 1813 %num = load i23, i23 addrspace(1) * %in 1814 %den = load i23, i23 addrspace(1) * %den_ptr 1815 %result = udiv i23 %num, %den 1816 %result.ext = zext i23 %result to i32 1817 store i32 %result.ext, i32 addrspace(1)* %out 1818 ret void 1819} 1820 1821define amdgpu_kernel void @v_udiv_i24(i32 addrspace(1)* %out, i24 addrspace(1)* %in) { 1822; SI-LABEL: v_udiv_i24: 1823; SI: ; %bb.0: 1824; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1825; SI-NEXT: s_mov_b32 s7, 0xf000 1826; SI-NEXT: s_mov_b32 s6, -1 1827; SI-NEXT: s_mov_b32 s10, s6 1828; SI-NEXT: s_mov_b32 s11, s7 1829; SI-NEXT: s_waitcnt lgkmcnt(0) 1830; SI-NEXT: s_mov_b32 s8, s2 1831; SI-NEXT: s_mov_b32 s9, s3 1832; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0 offset:4 1833; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:6 1834; SI-NEXT: buffer_load_ushort v3, off, s[8:11], 0 1835; SI-NEXT: buffer_load_ubyte v4, off, s[8:11], 0 offset:2 1836; SI-NEXT: s_mov_b32 s4, s0 1837; SI-NEXT: s_mov_b32 s5, s1 1838; SI-NEXT: s_waitcnt vmcnt(2) 1839; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1840; SI-NEXT: v_or_b32_e32 v0, v0, v1 1841; SI-NEXT: v_cvt_f32_u32_e32 v1, v0 1842; SI-NEXT: v_sub_i32_e32 v2, vcc, 0, v0 1843; SI-NEXT: s_waitcnt vmcnt(0) 1844; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 1845; SI-NEXT: v_rcp_iflag_f32_e32 v1, v1 1846; SI-NEXT: v_or_b32_e32 v3, v3, v4 1847; SI-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 1848; SI-NEXT: v_cvt_u32_f32_e32 v1, v1 1849; SI-NEXT: v_mul_lo_u32 v2, v2, v1 1850; SI-NEXT: v_mul_hi_u32 v2, v1, v2 1851; SI-NEXT: v_add_i32_e32 v1, vcc, v2, v1 1852; SI-NEXT: v_mul_hi_u32 v1, v3, v1 1853; SI-NEXT: v_mul_lo_u32 v2, v1, v0 1854; SI-NEXT: v_add_i32_e32 v4, vcc, 1, v1 1855; SI-NEXT: v_subrev_i32_e32 v2, vcc, v2, v3 1856; SI-NEXT: v_cmp_ge_u32_e64 s[0:1], v2, v0 1857; SI-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1] 1858; SI-NEXT: v_subrev_i32_e32 v3, vcc, v0, v2 1859; SI-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] 1860; SI-NEXT: v_add_i32_e32 v3, vcc, 1, v1 1861; SI-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0 1862; SI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 1863; SI-NEXT: v_and_b32_e32 v0, 0xffffff, v0 1864; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 1865; SI-NEXT: s_endpgm 1866; 1867; VI-LABEL: v_udiv_i24: 1868; VI: ; %bb.0: 1869; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1870; VI-NEXT: s_mov_b32 s7, 0xf000 1871; VI-NEXT: s_mov_b32 s6, -1 1872; VI-NEXT: s_mov_b32 s10, s6 1873; VI-NEXT: s_mov_b32 s11, s7 1874; VI-NEXT: s_waitcnt lgkmcnt(0) 1875; VI-NEXT: s_mov_b32 s8, s2 1876; VI-NEXT: s_mov_b32 s9, s3 1877; VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0 offset:4 1878; VI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:6 1879; VI-NEXT: buffer_load_ushort v3, off, s[8:11], 0 1880; VI-NEXT: buffer_load_ubyte v4, off, s[8:11], 0 offset:2 1881; VI-NEXT: s_mov_b32 s4, s0 1882; VI-NEXT: s_mov_b32 s5, s1 1883; VI-NEXT: s_waitcnt vmcnt(2) 1884; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1885; VI-NEXT: v_or_b32_e32 v0, v0, v1 1886; VI-NEXT: v_cvt_f32_u32_e32 v1, v0 1887; VI-NEXT: v_sub_u32_e32 v2, vcc, 0, v0 1888; VI-NEXT: s_waitcnt vmcnt(0) 1889; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 1890; VI-NEXT: v_rcp_iflag_f32_e32 v1, v1 1891; VI-NEXT: v_or_b32_e32 v3, v3, v4 1892; VI-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 1893; VI-NEXT: v_cvt_u32_f32_e32 v1, v1 1894; VI-NEXT: v_mul_lo_u32 v2, v2, v1 1895; VI-NEXT: v_mul_hi_u32 v2, v1, v2 1896; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1 1897; VI-NEXT: v_mul_hi_u32 v1, v3, v1 1898; VI-NEXT: v_mul_lo_u32 v2, v1, v0 1899; VI-NEXT: v_add_u32_e32 v4, vcc, 1, v1 1900; VI-NEXT: v_subrev_u32_e32 v2, vcc, v2, v3 1901; VI-NEXT: v_cmp_ge_u32_e64 s[0:1], v2, v0 1902; VI-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1] 1903; VI-NEXT: v_subrev_u32_e32 v3, vcc, v0, v2 1904; VI-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] 1905; VI-NEXT: v_add_u32_e32 v3, vcc, 1, v1 1906; VI-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0 1907; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc 1908; VI-NEXT: v_and_b32_e32 v0, 0xffffff, v0 1909; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 1910; VI-NEXT: s_endpgm 1911; 1912; GCN-LABEL: v_udiv_i24: 1913; GCN: ; %bb.0: 1914; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 1915; GCN-NEXT: s_waitcnt lgkmcnt(0) 1916; GCN-NEXT: s_add_u32 s4, s2, 4 1917; GCN-NEXT: s_addc_u32 s5, s3, 0 1918; GCN-NEXT: s_add_u32 s6, s2, 2 1919; GCN-NEXT: v_mov_b32_e32 v0, s4 1920; GCN-NEXT: s_addc_u32 s7, s3, 0 1921; GCN-NEXT: v_mov_b32_e32 v1, s5 1922; GCN-NEXT: s_add_u32 s4, s2, 6 1923; GCN-NEXT: s_addc_u32 s5, s3, 0 1924; GCN-NEXT: v_mov_b32_e32 v2, s4 1925; GCN-NEXT: v_mov_b32_e32 v3, s5 1926; GCN-NEXT: flat_load_ubyte v2, v[2:3] 1927; GCN-NEXT: flat_load_ushort v0, v[0:1] 1928; GCN-NEXT: s_waitcnt vmcnt(1) 1929; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v2 1930; GCN-NEXT: s_waitcnt vmcnt(0) 1931; GCN-NEXT: v_or_b32_e32 v4, v0, v1 1932; GCN-NEXT: v_cvt_f32_u32_e32 v0, v4 1933; GCN-NEXT: v_sub_u32_e32 v6, vcc, 0, v4 1934; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 1935; GCN-NEXT: v_mov_b32_e32 v0, s2 1936; GCN-NEXT: v_mov_b32_e32 v1, s3 1937; GCN-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 1938; GCN-NEXT: v_cvt_u32_f32_e32 v5, v2 1939; GCN-NEXT: v_mov_b32_e32 v2, s6 1940; GCN-NEXT: v_mov_b32_e32 v3, s7 1941; GCN-NEXT: flat_load_ubyte v2, v[2:3] 1942; GCN-NEXT: flat_load_ushort v0, v[0:1] 1943; GCN-NEXT: v_mul_lo_u32 v6, v6, v5 1944; GCN-NEXT: v_mul_hi_u32 v1, v5, v6 1945; GCN-NEXT: s_waitcnt vmcnt(1) 1946; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 1947; GCN-NEXT: s_waitcnt vmcnt(0) 1948; GCN-NEXT: v_or_b32_e32 v2, v0, v2 1949; GCN-NEXT: v_add_u32_e32 v0, vcc, v1, v5 1950; GCN-NEXT: v_mul_hi_u32 v3, v2, v0 1951; GCN-NEXT: v_mov_b32_e32 v0, s0 1952; GCN-NEXT: v_mov_b32_e32 v1, s1 1953; GCN-NEXT: v_mul_lo_u32 v5, v3, v4 1954; GCN-NEXT: v_add_u32_e32 v6, vcc, 1, v3 1955; GCN-NEXT: v_subrev_u32_e32 v2, vcc, v5, v2 1956; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v2, v4 1957; GCN-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[0:1] 1958; GCN-NEXT: v_subrev_u32_e32 v5, vcc, v4, v2 1959; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1] 1960; GCN-NEXT: v_add_u32_e32 v5, vcc, 1, v3 1961; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4 1962; GCN-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc 1963; GCN-NEXT: v_and_b32_e32 v2, 0xffffff, v2 1964; GCN-NEXT: flat_store_dword v[0:1], v2 1965; GCN-NEXT: s_endpgm 1966; 1967; GFX1030-LABEL: v_udiv_i24: 1968; GFX1030: ; %bb.0: 1969; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 1970; GFX1030-NEXT: v_mov_b32_e32 v0, 0 1971; GFX1030-NEXT: s_waitcnt lgkmcnt(0) 1972; GFX1030-NEXT: s_clause 0x3 1973; GFX1030-NEXT: global_load_ubyte v1, v0, s[2:3] offset:6 1974; GFX1030-NEXT: global_load_ushort v2, v0, s[2:3] offset:4 1975; GFX1030-NEXT: global_load_ubyte v3, v0, s[2:3] offset:2 1976; GFX1030-NEXT: global_load_ushort v4, v0, s[2:3] 1977; GFX1030-NEXT: s_waitcnt vmcnt(3) 1978; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1 1979; GFX1030-NEXT: s_waitcnt vmcnt(1) 1980; GFX1030-NEXT: v_lshlrev_b32_e32 v3, 16, v3 1981; GFX1030-NEXT: v_or_b32_e32 v1, v2, v1 1982; GFX1030-NEXT: s_waitcnt vmcnt(0) 1983; GFX1030-NEXT: v_or_b32_e32 v3, v4, v3 1984; GFX1030-NEXT: v_cvt_f32_u32_e32 v2, v1 1985; GFX1030-NEXT: v_sub_nc_u32_e32 v5, 0, v1 1986; GFX1030-NEXT: v_rcp_iflag_f32_e32 v2, v2 1987; GFX1030-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 1988; GFX1030-NEXT: v_cvt_u32_f32_e32 v2, v2 1989; GFX1030-NEXT: v_mul_lo_u32 v5, v5, v2 1990; GFX1030-NEXT: v_mul_hi_u32 v5, v2, v5 1991; GFX1030-NEXT: v_add_nc_u32_e32 v2, v2, v5 1992; GFX1030-NEXT: v_mul_hi_u32 v2, v3, v2 1993; GFX1030-NEXT: v_mul_lo_u32 v4, v2, v1 1994; GFX1030-NEXT: v_sub_nc_u32_e32 v3, v3, v4 1995; GFX1030-NEXT: v_add_nc_u32_e32 v4, 1, v2 1996; GFX1030-NEXT: v_sub_nc_u32_e32 v5, v3, v1 1997; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v3, v1 1998; GFX1030-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo 1999; GFX1030-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo 2000; GFX1030-NEXT: v_add_nc_u32_e32 v4, 1, v2 2001; GFX1030-NEXT: v_cmp_ge_u32_e32 vcc_lo, v3, v1 2002; GFX1030-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo 2003; GFX1030-NEXT: v_and_b32_e32 v1, 0xffffff, v1 2004; GFX1030-NEXT: global_store_dword v0, v1, s[0:1] 2005; GFX1030-NEXT: s_endpgm 2006; 2007; EG-LABEL: v_udiv_i24: 2008; EG: ; %bb.0: 2009; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[] 2010; EG-NEXT: TEX 3 @6 2011; EG-NEXT: ALU 23, @15, KC0[CB0:0-32], KC1[] 2012; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 2013; EG-NEXT: CF_END 2014; EG-NEXT: PAD 2015; EG-NEXT: Fetch clause starting at 6: 2016; EG-NEXT: VTX_READ_8 T1.X, T0.X, 6, #1 2017; EG-NEXT: VTX_READ_16 T2.X, T0.X, 0, #1 2018; EG-NEXT: VTX_READ_8 T3.X, T0.X, 2, #1 2019; EG-NEXT: VTX_READ_16 T0.X, T0.X, 4, #1 2020; EG-NEXT: ALU clause starting at 14: 2021; EG-NEXT: MOV * T0.X, KC0[2].Z, 2022; EG-NEXT: ALU clause starting at 15: 2023; EG-NEXT: LSHL * T0.W, T1.X, literal.x, 2024; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) 2025; EG-NEXT: OR_INT * T0.W, T0.X, PV.W, 2026; EG-NEXT: SUB_INT T1.W, 0.0, PV.W, 2027; EG-NEXT: RECIP_UINT * T0.X, PV.W, 2028; EG-NEXT: MULLO_INT * T0.Y, PV.W, PS, 2029; EG-NEXT: LSHL T1.W, T3.X, literal.x, 2030; EG-NEXT: MULHI * T0.Y, T0.X, PS, 2031; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) 2032; EG-NEXT: ADD_INT T2.W, T0.X, PS, 2033; EG-NEXT: OR_INT * T1.W, T2.X, PV.W, 2034; EG-NEXT: MULHI * T0.X, PS, PV.W, 2035; EG-NEXT: MULLO_INT * T0.Y, PS, T0.W, 2036; EG-NEXT: SUB_INT * T1.W, T1.W, PS, 2037; EG-NEXT: ADD_INT T0.Z, T0.X, 1, 2038; EG-NEXT: SETGE_UINT T2.W, PV.W, T0.W, 2039; EG-NEXT: SUB_INT * T3.W, PV.W, T0.W, 2040; EG-NEXT: CNDE_INT T1.W, PV.W, T1.W, PS, 2041; EG-NEXT: CNDE_INT * T2.W, PV.W, T0.X, PV.Z, 2042; EG-NEXT: ADD_INT T3.W, PS, 1, 2043; EG-NEXT: SETGE_UINT * T0.W, PV.W, T0.W, 2044; EG-NEXT: CNDE_INT T0.X, PS, T2.W, PV.W, 2045; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 2046; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 2047 %den_ptr = getelementptr i24, i24 addrspace(1)* %in, i24 1 2048 %num = load i24, i24 addrspace(1) * %in 2049 %den = load i24, i24 addrspace(1) * %den_ptr 2050 %result = udiv i24 %num, %den 2051 %result.ext = zext i24 %result to i32 2052 store i32 %result.ext, i32 addrspace(1)* %out 2053 ret void 2054} 2055 2056define amdgpu_kernel void @scalarize_mulhu_4xi32(<4 x i32> addrspace(1)* nocapture readonly %in, <4 x i32> addrspace(1)* nocapture %out) { 2057; SI-LABEL: scalarize_mulhu_4xi32: 2058; SI: ; %bb.0: 2059; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 2060; SI-NEXT: s_mov_b32 s3, 0xf000 2061; SI-NEXT: s_mov_b32 s2, -1 2062; SI-NEXT: s_waitcnt lgkmcnt(0) 2063; SI-NEXT: s_mov_b32 s0, s4 2064; SI-NEXT: s_mov_b32 s1, s5 2065; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 2066; SI-NEXT: s_mov_b32 s4, 0x1389c755 2067; SI-NEXT: s_mov_b32 s0, s6 2068; SI-NEXT: s_mov_b32 s1, s7 2069; SI-NEXT: s_waitcnt vmcnt(0) 2070; SI-NEXT: v_lshrrev_b32_e32 v0, 2, v0 2071; SI-NEXT: v_lshrrev_b32_e32 v1, 2, v1 2072; SI-NEXT: v_lshrrev_b32_e32 v2, 2, v2 2073; SI-NEXT: v_lshrrev_b32_e32 v3, 2, v3 2074; SI-NEXT: v_mul_hi_u32 v0, v0, s4 2075; SI-NEXT: v_mul_hi_u32 v1, v1, s4 2076; SI-NEXT: v_mul_hi_u32 v2, v2, s4 2077; SI-NEXT: v_mul_hi_u32 v3, v3, s4 2078; SI-NEXT: v_lshrrev_b32_e32 v0, 10, v0 2079; SI-NEXT: v_lshrrev_b32_e32 v1, 10, v1 2080; SI-NEXT: v_lshrrev_b32_e32 v2, 10, v2 2081; SI-NEXT: v_lshrrev_b32_e32 v3, 10, v3 2082; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 2083; SI-NEXT: s_endpgm 2084; 2085; VI-LABEL: scalarize_mulhu_4xi32: 2086; VI: ; %bb.0: 2087; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 2088; VI-NEXT: s_mov_b32 s3, 0xf000 2089; VI-NEXT: s_mov_b32 s2, -1 2090; VI-NEXT: s_waitcnt lgkmcnt(0) 2091; VI-NEXT: s_mov_b32 s0, s4 2092; VI-NEXT: s_mov_b32 s1, s5 2093; VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 2094; VI-NEXT: s_mov_b32 s4, 0x1389c755 2095; VI-NEXT: s_mov_b32 s0, s6 2096; VI-NEXT: s_mov_b32 s1, s7 2097; VI-NEXT: s_waitcnt vmcnt(0) 2098; VI-NEXT: v_lshrrev_b32_e32 v0, 2, v0 2099; VI-NEXT: v_lshrrev_b32_e32 v1, 2, v1 2100; VI-NEXT: v_lshrrev_b32_e32 v2, 2, v2 2101; VI-NEXT: v_lshrrev_b32_e32 v3, 2, v3 2102; VI-NEXT: v_mul_hi_u32 v0, v0, s4 2103; VI-NEXT: v_mul_hi_u32 v1, v1, s4 2104; VI-NEXT: v_mul_hi_u32 v2, v2, s4 2105; VI-NEXT: v_mul_hi_u32 v3, v3, s4 2106; VI-NEXT: v_lshrrev_b32_e32 v0, 10, v0 2107; VI-NEXT: v_lshrrev_b32_e32 v1, 10, v1 2108; VI-NEXT: v_lshrrev_b32_e32 v2, 10, v2 2109; VI-NEXT: v_lshrrev_b32_e32 v3, 10, v3 2110; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 2111; VI-NEXT: s_endpgm 2112; 2113; GCN-LABEL: scalarize_mulhu_4xi32: 2114; GCN: ; %bb.0: 2115; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 2116; GCN-NEXT: s_waitcnt lgkmcnt(0) 2117; GCN-NEXT: v_mov_b32_e32 v0, s0 2118; GCN-NEXT: v_mov_b32_e32 v1, s1 2119; GCN-NEXT: flat_load_dwordx4 v[0:3], v[0:1] 2120; GCN-NEXT: s_mov_b32 s0, 0x1389c755 2121; GCN-NEXT: v_mov_b32_e32 v4, s2 2122; GCN-NEXT: v_mov_b32_e32 v5, s3 2123; GCN-NEXT: s_waitcnt vmcnt(0) 2124; GCN-NEXT: v_lshrrev_b32_e32 v0, 2, v0 2125; GCN-NEXT: v_lshrrev_b32_e32 v1, 2, v1 2126; GCN-NEXT: v_lshrrev_b32_e32 v2, 2, v2 2127; GCN-NEXT: v_lshrrev_b32_e32 v3, 2, v3 2128; GCN-NEXT: v_mul_hi_u32 v0, v0, s0 2129; GCN-NEXT: v_mul_hi_u32 v1, v1, s0 2130; GCN-NEXT: v_mul_hi_u32 v2, v2, s0 2131; GCN-NEXT: v_mul_hi_u32 v3, v3, s0 2132; GCN-NEXT: v_lshrrev_b32_e32 v0, 10, v0 2133; GCN-NEXT: v_lshrrev_b32_e32 v1, 10, v1 2134; GCN-NEXT: v_lshrrev_b32_e32 v2, 10, v2 2135; GCN-NEXT: v_lshrrev_b32_e32 v3, 10, v3 2136; GCN-NEXT: flat_store_dwordx4 v[4:5], v[0:3] 2137; GCN-NEXT: s_endpgm 2138; 2139; GFX1030-LABEL: scalarize_mulhu_4xi32: 2140; GFX1030: ; %bb.0: 2141; GFX1030-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 2142; GFX1030-NEXT: v_mov_b32_e32 v4, 0 2143; GFX1030-NEXT: s_waitcnt lgkmcnt(0) 2144; GFX1030-NEXT: global_load_dwordx4 v[0:3], v4, s[0:1] 2145; GFX1030-NEXT: s_mov_b32 s0, 0x1389c755 2146; GFX1030-NEXT: s_waitcnt vmcnt(0) 2147; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 2, v0 2148; GFX1030-NEXT: v_lshrrev_b32_e32 v1, 2, v1 2149; GFX1030-NEXT: v_lshrrev_b32_e32 v2, 2, v2 2150; GFX1030-NEXT: v_lshrrev_b32_e32 v3, 2, v3 2151; GFX1030-NEXT: v_mul_hi_u32 v0, v0, s0 2152; GFX1030-NEXT: v_mul_hi_u32 v1, v1, s0 2153; GFX1030-NEXT: v_mul_hi_u32 v2, v2, s0 2154; GFX1030-NEXT: v_mul_hi_u32 v3, v3, s0 2155; GFX1030-NEXT: v_lshrrev_b32_e32 v0, 10, v0 2156; GFX1030-NEXT: v_lshrrev_b32_e32 v1, 10, v1 2157; GFX1030-NEXT: v_lshrrev_b32_e32 v2, 10, v2 2158; GFX1030-NEXT: v_lshrrev_b32_e32 v3, 10, v3 2159; GFX1030-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] 2160; GFX1030-NEXT: s_endpgm 2161; 2162; EG-LABEL: scalarize_mulhu_4xi32: 2163; EG: ; %bb.0: 2164; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] 2165; EG-NEXT: TEX 0 @6 2166; EG-NEXT: ALU 20, @9, KC0[CB0:0-32], KC1[] 2167; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1 2168; EG-NEXT: CF_END 2169; EG-NEXT: PAD 2170; EG-NEXT: Fetch clause starting at 6: 2171; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1 2172; EG-NEXT: ALU clause starting at 8: 2173; EG-NEXT: MOV * T0.X, KC0[2].Y, 2174; EG-NEXT: ALU clause starting at 9: 2175; EG-NEXT: LSHR T0.W, T0.W, literal.x, 2176; EG-NEXT: LSHR * T1.W, T0.Z, literal.x, 2177; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 2178; EG-NEXT: MULHI * T0.Z, PV.W, literal.x, 2179; EG-NEXT: 327796565(3.478022e-27), 0(0.000000e+00) 2180; EG-NEXT: LSHR T1.Z, T0.Y, literal.x, 2181; EG-NEXT: LSHR T0.W, PS, literal.y, 2182; EG-NEXT: MULHI * T0.Y, T1.W, literal.z, 2183; EG-NEXT: 2(2.802597e-45), 10(1.401298e-44) 2184; EG-NEXT: 327796565(3.478022e-27), 0(0.000000e+00) 2185; EG-NEXT: LSHR T0.Z, PS, literal.x, 2186; EG-NEXT: LSHR T1.W, T0.X, literal.y, 2187; EG-NEXT: MULHI * T0.X, PV.Z, literal.z, 2188; EG-NEXT: 10(1.401298e-44), 2(2.802597e-45) 2189; EG-NEXT: 327796565(3.478022e-27), 0(0.000000e+00) 2190; EG-NEXT: LSHR T0.Y, PS, literal.x, 2191; EG-NEXT: MULHI * T0.X, PV.W, literal.y, 2192; EG-NEXT: 10(1.401298e-44), 327796565(3.478022e-27) 2193; EG-NEXT: LSHR T0.X, PS, literal.x, 2194; EG-NEXT: LSHR * T1.X, KC0[2].Z, literal.y, 2195; EG-NEXT: 10(1.401298e-44), 2(2.802597e-45) 2196 %1 = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16 2197 %2 = udiv <4 x i32> %1, <i32 53668, i32 53668, i32 53668, i32 53668> 2198 store <4 x i32> %2, <4 x i32> addrspace(1)* %out, align 16 2199 ret void 2200} 2201 2202define amdgpu_kernel void @test_udiv2(i32 %p) { 2203; SI-LABEL: test_udiv2: 2204; SI: ; %bb.0: 2205; SI-NEXT: s_load_dword s0, s[0:1], 0x9 2206; SI-NEXT: s_mov_b32 s3, 0xf000 2207; SI-NEXT: s_mov_b32 s2, -1 2208; SI-NEXT: s_waitcnt lgkmcnt(0) 2209; SI-NEXT: s_lshr_b32 s0, s0, 1 2210; SI-NEXT: v_mov_b32_e32 v0, s0 2211; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 2212; SI-NEXT: s_waitcnt vmcnt(0) 2213; SI-NEXT: s_endpgm 2214; 2215; VI-LABEL: test_udiv2: 2216; VI: ; %bb.0: 2217; VI-NEXT: s_load_dword s0, s[0:1], 0x24 2218; VI-NEXT: s_mov_b32 s3, 0xf000 2219; VI-NEXT: s_mov_b32 s2, -1 2220; VI-NEXT: s_waitcnt lgkmcnt(0) 2221; VI-NEXT: s_lshr_b32 s0, s0, 1 2222; VI-NEXT: v_mov_b32_e32 v0, s0 2223; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 2224; VI-NEXT: s_waitcnt vmcnt(0) 2225; VI-NEXT: s_endpgm 2226; 2227; GCN-LABEL: test_udiv2: 2228; GCN: ; %bb.0: 2229; GCN-NEXT: s_load_dword s0, s[4:5], 0x0 2230; GCN-NEXT: s_waitcnt lgkmcnt(0) 2231; GCN-NEXT: s_lshr_b32 s0, s0, 1 2232; GCN-NEXT: v_mov_b32_e32 v0, s0 2233; GCN-NEXT: flat_store_dword v[0:1], v0 2234; GCN-NEXT: s_waitcnt vmcnt(0) 2235; GCN-NEXT: s_endpgm 2236; 2237; GFX1030-LABEL: test_udiv2: 2238; GFX1030: ; %bb.0: 2239; GFX1030-NEXT: s_load_dword s0, s[4:5], 0x0 2240; GFX1030-NEXT: s_waitcnt lgkmcnt(0) 2241; GFX1030-NEXT: s_lshr_b32 s0, s0, 1 2242; GFX1030-NEXT: v_mov_b32_e32 v0, s0 2243; GFX1030-NEXT: global_store_dword v[0:1], v0, off 2244; GFX1030-NEXT: s_waitcnt_vscnt null, 0x0 2245; GFX1030-NEXT: s_endpgm 2246; 2247; EG-LABEL: test_udiv2: 2248; EG: ; %bb.0: 2249; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] 2250; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1 2251; EG-NEXT: CF_END 2252; EG-NEXT: PAD 2253; EG-NEXT: ALU clause starting at 4: 2254; EG-NEXT: MOV T0.X, literal.x, 2255; EG-NEXT: LSHR * T1.X, KC0[2].Y, 1, 2256; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00) 2257 %i = udiv i32 %p, 2 2258 store volatile i32 %i, i32 addrspace(1)* undef 2259 ret void 2260} 2261 2262define amdgpu_kernel void @test_udiv_3_mulhu(i32 %p) { 2263; SI-LABEL: test_udiv_3_mulhu: 2264; SI: ; %bb.0: 2265; SI-NEXT: s_load_dword s0, s[0:1], 0x9 2266; SI-NEXT: v_mov_b32_e32 v0, 0xaaaaaaab 2267; SI-NEXT: s_mov_b32 s3, 0xf000 2268; SI-NEXT: s_mov_b32 s2, -1 2269; SI-NEXT: s_waitcnt lgkmcnt(0) 2270; SI-NEXT: v_mul_hi_u32 v0, s0, v0 2271; SI-NEXT: v_lshrrev_b32_e32 v0, 1, v0 2272; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 2273; SI-NEXT: s_waitcnt vmcnt(0) 2274; SI-NEXT: s_endpgm 2275; 2276; VI-LABEL: test_udiv_3_mulhu: 2277; VI: ; %bb.0: 2278; VI-NEXT: s_load_dword s0, s[0:1], 0x24 2279; VI-NEXT: v_mov_b32_e32 v0, 0xaaaaaaab 2280; VI-NEXT: s_mov_b32 s3, 0xf000 2281; VI-NEXT: s_mov_b32 s2, -1 2282; VI-NEXT: s_waitcnt lgkmcnt(0) 2283; VI-NEXT: v_mul_hi_u32 v0, s0, v0 2284; VI-NEXT: v_lshrrev_b32_e32 v0, 1, v0 2285; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 2286; VI-NEXT: s_waitcnt vmcnt(0) 2287; VI-NEXT: s_endpgm 2288; 2289; GCN-LABEL: test_udiv_3_mulhu: 2290; GCN: ; %bb.0: 2291; GCN-NEXT: s_load_dword s0, s[4:5], 0x0 2292; GCN-NEXT: v_mov_b32_e32 v0, 0xaaaaaaab 2293; GCN-NEXT: s_waitcnt lgkmcnt(0) 2294; GCN-NEXT: v_mul_hi_u32 v0, s0, v0 2295; GCN-NEXT: v_lshrrev_b32_e32 v0, 1, v0 2296; GCN-NEXT: flat_store_dword v[0:1], v0 2297; GCN-NEXT: s_waitcnt vmcnt(0) 2298; GCN-NEXT: s_endpgm 2299; 2300; GFX1030-LABEL: test_udiv_3_mulhu: 2301; GFX1030: ; %bb.0: 2302; GFX1030-NEXT: s_load_dword s0, s[4:5], 0x0 2303; GFX1030-NEXT: s_waitcnt lgkmcnt(0) 2304; GFX1030-NEXT: s_mul_hi_u32 s0, s0, 0xaaaaaaab 2305; GFX1030-NEXT: s_lshr_b32 s0, s0, 1 2306; GFX1030-NEXT: v_mov_b32_e32 v0, s0 2307; GFX1030-NEXT: global_store_dword v[0:1], v0, off 2308; GFX1030-NEXT: s_waitcnt_vscnt null, 0x0 2309; GFX1030-NEXT: s_endpgm 2310; 2311; EG-LABEL: test_udiv_3_mulhu: 2312; EG: ; %bb.0: 2313; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[] 2314; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 2315; EG-NEXT: CF_END 2316; EG-NEXT: PAD 2317; EG-NEXT: ALU clause starting at 4: 2318; EG-NEXT: MULHI * T0.X, KC0[2].Y, literal.x, 2319; EG-NEXT: -1431655765(-3.031649e-13), 0(0.000000e+00) 2320; EG-NEXT: LSHR T0.X, PS, 1, 2321; EG-NEXT: MOV * T1.X, literal.x, 2322; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00) 2323 %i = udiv i32 %p, 3 2324 store volatile i32 %i, i32 addrspace(1)* undef 2325 ret void 2326} 2327 2328define amdgpu_kernel void @fdiv_test_denormals(i8 addrspace(1)* nocapture readonly %arg) { 2329; SI-LABEL: fdiv_test_denormals: 2330; SI: ; %bb.0: ; %bb 2331; SI-NEXT: s_mov_b32 s0, 0 2332; SI-NEXT: s_mov_b32 s3, 0xf000 2333; SI-NEXT: s_mov_b32 s2, -1 2334; SI-NEXT: s_mov_b32 s1, s0 2335; SI-NEXT: buffer_load_sbyte v0, off, s[0:3], 0 2336; SI-NEXT: buffer_load_sbyte v2, off, s[0:3], 0 2337; SI-NEXT: s_waitcnt vmcnt(1) 2338; SI-NEXT: v_cvt_f32_i32_e32 v1, v0 2339; SI-NEXT: s_waitcnt vmcnt(0) 2340; SI-NEXT: v_cvt_f32_i32_e32 v3, v2 2341; SI-NEXT: v_xor_b32_e32 v0, v2, v0 2342; SI-NEXT: v_ashrrev_i32_e32 v0, 30, v0 2343; SI-NEXT: v_rcp_iflag_f32_e32 v4, v1 2344; SI-NEXT: v_or_b32_e32 v0, 1, v0 2345; SI-NEXT: v_mul_f32_e32 v2, v3, v4 2346; SI-NEXT: v_trunc_f32_e32 v2, v2 2347; SI-NEXT: v_mad_f32 v3, -v2, v1, v3 2348; SI-NEXT: v_cvt_i32_f32_e32 v2, v2 2349; SI-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1| 2350; SI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc 2351; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v2 2352; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0 2353; SI-NEXT: s_endpgm 2354; 2355; VI-LABEL: fdiv_test_denormals: 2356; VI: ; %bb.0: ; %bb 2357; VI-NEXT: s_mov_b32 s0, 0 2358; VI-NEXT: s_mov_b32 s3, 0xf000 2359; VI-NEXT: s_mov_b32 s2, -1 2360; VI-NEXT: s_mov_b32 s1, s0 2361; VI-NEXT: buffer_load_sbyte v0, off, s[0:3], 0 2362; VI-NEXT: buffer_load_sbyte v2, off, s[0:3], 0 2363; VI-NEXT: s_waitcnt vmcnt(1) 2364; VI-NEXT: v_cvt_f32_i32_e32 v1, v0 2365; VI-NEXT: s_waitcnt vmcnt(0) 2366; VI-NEXT: v_cvt_f32_i32_e32 v3, v2 2367; VI-NEXT: v_xor_b32_e32 v0, v2, v0 2368; VI-NEXT: v_ashrrev_i32_e32 v0, 30, v0 2369; VI-NEXT: v_rcp_iflag_f32_e32 v4, v1 2370; VI-NEXT: v_or_b32_e32 v0, 1, v0 2371; VI-NEXT: v_mul_f32_e32 v2, v3, v4 2372; VI-NEXT: v_trunc_f32_e32 v2, v2 2373; VI-NEXT: v_mad_f32 v3, -v2, v1, v3 2374; VI-NEXT: v_cvt_i32_f32_e32 v2, v2 2375; VI-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1| 2376; VI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc 2377; VI-NEXT: v_add_u32_e32 v0, vcc, v2, v0 2378; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0 2379; VI-NEXT: s_endpgm 2380; 2381; GCN-LABEL: fdiv_test_denormals: 2382; GCN: ; %bb.0: ; %bb 2383; GCN-NEXT: v_mov_b32_e32 v0, 0 2384; GCN-NEXT: v_mov_b32_e32 v1, 0 2385; GCN-NEXT: flat_load_sbyte v2, v[0:1] 2386; GCN-NEXT: flat_load_sbyte v4, v[0:1] 2387; GCN-NEXT: s_waitcnt vmcnt(1) 2388; GCN-NEXT: v_cvt_f32_i32_e32 v3, v2 2389; GCN-NEXT: s_waitcnt vmcnt(0) 2390; GCN-NEXT: v_cvt_f32_i32_e32 v5, v4 2391; GCN-NEXT: v_xor_b32_e32 v2, v4, v2 2392; GCN-NEXT: v_ashrrev_i32_e32 v2, 30, v2 2393; GCN-NEXT: v_rcp_iflag_f32_e32 v6, v3 2394; GCN-NEXT: v_or_b32_e32 v2, 1, v2 2395; GCN-NEXT: v_mul_f32_e32 v4, v5, v6 2396; GCN-NEXT: v_trunc_f32_e32 v4, v4 2397; GCN-NEXT: v_mad_f32 v5, -v4, v3, v5 2398; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4 2399; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v5|, |v3| 2400; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc 2401; GCN-NEXT: v_add_u32_e32 v2, vcc, v4, v2 2402; GCN-NEXT: flat_store_byte v[0:1], v2 2403; GCN-NEXT: s_endpgm 2404; 2405; GFX1030-LABEL: fdiv_test_denormals: 2406; GFX1030: ; %bb.0: ; %bb 2407; GFX1030-NEXT: global_load_sbyte v2, v[0:1], off 2408; GFX1030-NEXT: v_mov_b32_e32 v0, 0 2409; GFX1030-NEXT: v_mov_b32_e32 v1, 0 2410; GFX1030-NEXT: global_load_sbyte v3, v[0:1], off 2411; GFX1030-NEXT: s_waitcnt vmcnt(1) 2412; GFX1030-NEXT: v_cvt_f32_i32_e32 v4, v2 2413; GFX1030-NEXT: v_rcp_iflag_f32_e32 v5, v4 2414; GFX1030-NEXT: s_waitcnt vmcnt(0) 2415; GFX1030-NEXT: v_cvt_f32_i32_e32 v6, v3 2416; GFX1030-NEXT: v_xor_b32_e32 v2, v3, v2 2417; GFX1030-NEXT: v_ashrrev_i32_e32 v2, 30, v2 2418; GFX1030-NEXT: v_mul_f32_e32 v5, v6, v5 2419; GFX1030-NEXT: v_or_b32_e32 v2, 1, v2 2420; GFX1030-NEXT: v_trunc_f32_e32 v3, v5 2421; GFX1030-NEXT: v_fma_f32 v5, -v3, v4, v6 2422; GFX1030-NEXT: v_cvt_i32_f32_e32 v3, v3 2423; GFX1030-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v5|, |v4| 2424; GFX1030-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc_lo 2425; GFX1030-NEXT: v_add_nc_u32_e32 v2, v3, v2 2426; GFX1030-NEXT: global_store_byte v[0:1], v2, off 2427; GFX1030-NEXT: s_endpgm 2428; 2429; EG-LABEL: fdiv_test_denormals: 2430; EG: ; %bb.0: ; %bb 2431; EG-NEXT: TEX 0 @6 2432; EG-NEXT: ALU 0, @10, KC0[], KC1[] 2433; EG-NEXT: TEX 0 @8 2434; EG-NEXT: ALU 25, @11, KC0[], KC1[] 2435; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X 2436; EG-NEXT: CF_END 2437; EG-NEXT: Fetch clause starting at 6: 2438; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1 2439; EG-NEXT: Fetch clause starting at 8: 2440; EG-NEXT: VTX_READ_8 T1.X, T1.X, 0, #1 2441; EG-NEXT: ALU clause starting at 10: 2442; EG-NEXT: MOV * T1.X, 0.0, 2443; EG-NEXT: ALU clause starting at 11: 2444; EG-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x, 2445; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) 2446; EG-NEXT: INT_TO_FLT * T0.X, PV.W, 2447; EG-NEXT: BFE_INT T1.W, T1.X, 0.0, literal.x, 2448; EG-NEXT: RECIP_IEEE * T0.Y, PS, 2449; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00) 2450; EG-NEXT: INT_TO_FLT * T0.Z, PV.W, 2451; EG-NEXT: MUL_IEEE * T2.W, PS, T0.Y, 2452; EG-NEXT: TRUNC T2.W, PV.W, 2453; EG-NEXT: XOR_INT * T0.W, T1.W, T0.W, 2454; EG-NEXT: ASHR T0.W, PS, literal.x, 2455; EG-NEXT: MULADD_IEEE * T1.W, -PV.W, T0.X, T0.Z, 2456; EG-NEXT: 30(4.203895e-44), 0(0.000000e+00) 2457; EG-NEXT: TRUNC T0.Z, T2.W, 2458; EG-NEXT: SETGE T1.W, |PS|, |T0.X|, 2459; EG-NEXT: OR_INT * T0.W, PV.W, 1, 2460; EG-NEXT: CNDE T0.W, PV.W, 0.0, PS, 2461; EG-NEXT: FLT_TO_INT * T1.W, PV.Z, 2462; EG-NEXT: ADD_INT * T0.W, PS, PV.W, 2463; EG-NEXT: AND_INT T0.X, PV.W, literal.x, 2464; EG-NEXT: MOV * T0.W, literal.x, 2465; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00) 2466; EG-NEXT: MOV T0.Y, 0.0, 2467; EG-NEXT: MOV * T0.Z, 0.0, 2468; EG-NEXT: MOV * T1.X, literal.x, 2469; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00) 2470bb: 2471 %tmp = load i8, i8 addrspace(1)* null, align 1 2472 %tmp1 = sext i8 %tmp to i32 2473 %tmp2 = getelementptr inbounds i8, i8 addrspace(1)* %arg, i64 undef 2474 %tmp3 = load i8, i8 addrspace(1)* %tmp2, align 1 2475 %tmp4 = sext i8 %tmp3 to i32 2476 %tmp5 = sdiv i32 %tmp1, %tmp4 2477 %tmp6 = trunc i32 %tmp5 to i8 2478 store i8 %tmp6, i8 addrspace(1)* null, align 1 2479 ret void 2480} 2481 2482define i64 @v_test_udiv64_mulhi_fold(i64 %arg) { 2483; SI-LABEL: v_test_udiv64_mulhi_fold: 2484; SI: ; %bb.0: 2485; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2486; SI-NEXT: v_mov_b32_e32 v2, 0x4f800000 2487; SI-NEXT: v_madak_f32 v2, 0, v2, 0x47c35000 2488; SI-NEXT: v_rcp_f32_e32 v2, v2 2489; SI-NEXT: s_mov_b32 s4, 0xfffe7960 2490; SI-NEXT: v_mov_b32_e32 v9, 0 2491; SI-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 2492; SI-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 2493; SI-NEXT: v_trunc_f32_e32 v3, v3 2494; SI-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 2495; SI-NEXT: v_cvt_u32_f32_e32 v2, v2 2496; SI-NEXT: v_cvt_u32_f32_e32 v3, v3 2497; SI-NEXT: v_mul_hi_u32 v4, v2, s4 2498; SI-NEXT: v_mul_lo_u32 v5, v3, s4 2499; SI-NEXT: v_mul_lo_u32 v6, v2, s4 2500; SI-NEXT: v_subrev_i32_e32 v4, vcc, v2, v4 2501; SI-NEXT: v_add_i32_e32 v4, vcc, v5, v4 2502; SI-NEXT: v_mul_lo_u32 v5, v2, v4 2503; SI-NEXT: v_mul_hi_u32 v7, v2, v6 2504; SI-NEXT: v_mul_hi_u32 v8, v2, v4 2505; SI-NEXT: v_mul_hi_u32 v10, v3, v4 2506; SI-NEXT: v_mul_lo_u32 v4, v3, v4 2507; SI-NEXT: v_add_i32_e32 v5, vcc, v7, v5 2508; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc 2509; SI-NEXT: v_mul_lo_u32 v8, v3, v6 2510; SI-NEXT: v_mul_hi_u32 v6, v3, v6 2511; SI-NEXT: v_add_i32_e32 v5, vcc, v5, v8 2512; SI-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc 2513; SI-NEXT: v_addc_u32_e32 v6, vcc, v10, v9, vcc 2514; SI-NEXT: v_add_i32_e32 v4, vcc, v5, v4 2515; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc 2516; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v4 2517; SI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc 2518; SI-NEXT: v_mul_hi_u32 v4, v2, s4 2519; SI-NEXT: v_mul_lo_u32 v5, v3, s4 2520; SI-NEXT: v_mul_lo_u32 v6, v2, s4 2521; SI-NEXT: s_mov_b32 s4, 0x186a0 2522; SI-NEXT: v_subrev_i32_e32 v4, vcc, v2, v4 2523; SI-NEXT: v_add_i32_e32 v4, vcc, v4, v5 2524; SI-NEXT: v_mul_lo_u32 v5, v2, v4 2525; SI-NEXT: v_mul_hi_u32 v7, v2, v6 2526; SI-NEXT: v_mul_hi_u32 v8, v2, v4 2527; SI-NEXT: v_mul_hi_u32 v10, v3, v4 2528; SI-NEXT: v_mul_lo_u32 v4, v3, v4 2529; SI-NEXT: v_add_i32_e32 v5, vcc, v7, v5 2530; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc 2531; SI-NEXT: v_mul_lo_u32 v8, v3, v6 2532; SI-NEXT: v_mul_hi_u32 v6, v3, v6 2533; SI-NEXT: v_add_i32_e32 v5, vcc, v5, v8 2534; SI-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc 2535; SI-NEXT: v_addc_u32_e32 v6, vcc, v10, v9, vcc 2536; SI-NEXT: v_add_i32_e32 v4, vcc, v5, v4 2537; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc 2538; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v4 2539; SI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc 2540; SI-NEXT: v_mul_lo_u32 v4, v0, v3 2541; SI-NEXT: v_mul_hi_u32 v5, v0, v2 2542; SI-NEXT: v_mul_hi_u32 v6, v0, v3 2543; SI-NEXT: v_mul_hi_u32 v7, v1, v3 2544; SI-NEXT: v_mul_lo_u32 v3, v1, v3 2545; SI-NEXT: v_add_i32_e32 v4, vcc, v5, v4 2546; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc 2547; SI-NEXT: v_mul_lo_u32 v6, v1, v2 2548; SI-NEXT: v_mul_hi_u32 v2, v1, v2 2549; SI-NEXT: v_add_i32_e32 v4, vcc, v4, v6 2550; SI-NEXT: v_addc_u32_e32 v2, vcc, v5, v2, vcc 2551; SI-NEXT: v_addc_u32_e32 v4, vcc, v7, v9, vcc 2552; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v3 2553; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc 2554; SI-NEXT: v_mul_lo_u32 v4, v3, s4 2555; SI-NEXT: v_mul_hi_u32 v5, v2, s4 2556; SI-NEXT: v_mul_lo_u32 v6, v2, s4 2557; SI-NEXT: v_add_i32_e32 v4, vcc, v5, v4 2558; SI-NEXT: v_sub_i32_e32 v0, vcc, v0, v6 2559; SI-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc 2560; SI-NEXT: v_subrev_i32_e32 v4, vcc, s4, v0 2561; SI-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v1, vcc 2562; SI-NEXT: s_mov_b32 s4, 0x1869f 2563; SI-NEXT: v_cmp_lt_u32_e32 vcc, s4, v4 2564; SI-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc 2565; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5 2566; SI-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc 2567; SI-NEXT: v_add_i32_e32 v5, vcc, 2, v2 2568; SI-NEXT: v_addc_u32_e32 v6, vcc, 0, v3, vcc 2569; SI-NEXT: v_add_i32_e32 v7, vcc, 1, v2 2570; SI-NEXT: v_cmp_lt_u32_e64 s[4:5], s4, v0 2571; SI-NEXT: v_addc_u32_e32 v8, vcc, 0, v3, vcc 2572; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5] 2573; SI-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1 2574; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 2575; SI-NEXT: v_cndmask_b32_e64 v0, -1, v0, s[4:5] 2576; SI-NEXT: v_cndmask_b32_e32 v4, v7, v5, vcc 2577; SI-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0 2578; SI-NEXT: v_cndmask_b32_e32 v1, v8, v6, vcc 2579; SI-NEXT: v_cndmask_b32_e64 v0, v2, v4, s[4:5] 2580; SI-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[4:5] 2581; SI-NEXT: s_setpc_b64 s[30:31] 2582; 2583; VI-LABEL: v_test_udiv64_mulhi_fold: 2584; VI: ; %bb.0: 2585; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2586; VI-NEXT: v_mov_b32_e32 v2, 0x4f800000 2587; VI-NEXT: v_madak_f32 v2, 0, v2, 0x47c35000 2588; VI-NEXT: v_rcp_f32_e32 v2, v2 2589; VI-NEXT: s_mov_b32 s6, 0xfffe7960 2590; VI-NEXT: v_mov_b32_e32 v9, 0 2591; VI-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 2592; VI-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 2593; VI-NEXT: v_trunc_f32_e32 v3, v3 2594; VI-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 2595; VI-NEXT: v_cvt_u32_f32_e32 v6, v2 2596; VI-NEXT: v_cvt_u32_f32_e32 v7, v3 2597; VI-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, s6, 0 2598; VI-NEXT: v_mul_lo_u32 v4, v7, s6 2599; VI-NEXT: v_subrev_u32_e32 v3, vcc, v6, v3 2600; VI-NEXT: v_add_u32_e32 v5, vcc, v4, v3 2601; VI-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v6, v5, 0 2602; VI-NEXT: v_mul_hi_u32 v8, v6, v2 2603; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v3 2604; VI-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v7, v2, 0 2605; VI-NEXT: v_addc_u32_e32 v10, vcc, 0, v4, vcc 2606; VI-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v7, v5, 0 2607; VI-NEXT: v_add_u32_e32 v2, vcc, v8, v2 2608; VI-NEXT: v_addc_u32_e32 v2, vcc, v10, v3, vcc 2609; VI-NEXT: v_addc_u32_e32 v3, vcc, v5, v9, vcc 2610; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v4 2611; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc 2612; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v2 2613; VI-NEXT: v_addc_u32_e32 v7, vcc, v7, v3, vcc 2614; VI-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, s6, 0 2615; VI-NEXT: v_mul_lo_u32 v4, v7, s6 2616; VI-NEXT: s_mov_b32 s6, 0x186a0 2617; VI-NEXT: v_subrev_u32_e32 v3, vcc, v6, v3 2618; VI-NEXT: v_add_u32_e32 v5, vcc, v3, v4 2619; VI-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v6, v5, 0 2620; VI-NEXT: v_mul_hi_u32 v8, v6, v2 2621; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v3 2622; VI-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v7, v2, 0 2623; VI-NEXT: v_addc_u32_e32 v10, vcc, 0, v4, vcc 2624; VI-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v7, v5, 0 2625; VI-NEXT: v_add_u32_e32 v2, vcc, v8, v2 2626; VI-NEXT: v_addc_u32_e32 v2, vcc, v10, v3, vcc 2627; VI-NEXT: v_addc_u32_e32 v3, vcc, v5, v9, vcc 2628; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v4 2629; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc 2630; VI-NEXT: v_add_u32_e32 v4, vcc, v6, v2 2631; VI-NEXT: v_addc_u32_e32 v5, vcc, v7, v3, vcc 2632; VI-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, v5, 0 2633; VI-NEXT: v_mul_hi_u32 v6, v0, v4 2634; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v2 2635; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc 2636; VI-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, v4, 0 2637; VI-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, v5, 0 2638; VI-NEXT: v_add_u32_e32 v2, vcc, v6, v2 2639; VI-NEXT: v_addc_u32_e32 v2, vcc, v7, v3, vcc 2640; VI-NEXT: v_addc_u32_e32 v3, vcc, v5, v9, vcc 2641; VI-NEXT: v_add_u32_e32 v4, vcc, v2, v4 2642; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v3, vcc 2643; VI-NEXT: v_mul_lo_u32 v6, v5, s6 2644; VI-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, s6, 0 2645; VI-NEXT: s_mov_b32 s4, 0x1869f 2646; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v6 2647; VI-NEXT: v_sub_u32_e32 v0, vcc, v0, v2 2648; VI-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc 2649; VI-NEXT: v_subrev_u32_e32 v2, vcc, s6, v0 2650; VI-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v1, vcc 2651; VI-NEXT: v_cmp_lt_u32_e32 vcc, s4, v2 2652; VI-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc 2653; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 2654; VI-NEXT: v_cndmask_b32_e32 v2, -1, v2, vcc 2655; VI-NEXT: v_add_u32_e32 v3, vcc, 2, v4 2656; VI-NEXT: v_addc_u32_e32 v6, vcc, 0, v5, vcc 2657; VI-NEXT: v_add_u32_e32 v7, vcc, 1, v4 2658; VI-NEXT: v_cmp_lt_u32_e64 s[4:5], s4, v0 2659; VI-NEXT: v_addc_u32_e32 v8, vcc, 0, v5, vcc 2660; VI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5] 2661; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1 2662; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 2663; VI-NEXT: v_cndmask_b32_e64 v0, -1, v0, s[4:5] 2664; VI-NEXT: v_cndmask_b32_e32 v2, v7, v3, vcc 2665; VI-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0 2666; VI-NEXT: v_cndmask_b32_e32 v1, v8, v6, vcc 2667; VI-NEXT: v_cndmask_b32_e64 v0, v4, v2, s[4:5] 2668; VI-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[4:5] 2669; VI-NEXT: s_setpc_b64 s[30:31] 2670; 2671; GCN-LABEL: v_test_udiv64_mulhi_fold: 2672; GCN: ; %bb.0: 2673; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2674; GCN-NEXT: v_mov_b32_e32 v2, 0x4f800000 2675; GCN-NEXT: v_madak_f32 v2, 0, v2, 0x47c35000 2676; GCN-NEXT: v_rcp_f32_e32 v2, v2 2677; GCN-NEXT: s_mov_b32 s6, 0xfffe7960 2678; GCN-NEXT: v_mov_b32_e32 v9, 0 2679; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 2680; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 2681; GCN-NEXT: v_trunc_f32_e32 v3, v3 2682; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 2683; GCN-NEXT: v_cvt_u32_f32_e32 v6, v2 2684; GCN-NEXT: v_cvt_u32_f32_e32 v7, v3 2685; GCN-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, s6, 0 2686; GCN-NEXT: v_mul_lo_u32 v4, v7, s6 2687; GCN-NEXT: v_subrev_u32_e32 v3, vcc, v6, v3 2688; GCN-NEXT: v_add_u32_e32 v5, vcc, v4, v3 2689; GCN-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v6, v5, 0 2690; GCN-NEXT: v_mul_hi_u32 v8, v6, v2 2691; GCN-NEXT: v_add_u32_e32 v8, vcc, v8, v3 2692; GCN-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v7, v2, 0 2693; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v4, vcc 2694; GCN-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v7, v5, 0 2695; GCN-NEXT: v_add_u32_e32 v2, vcc, v8, v2 2696; GCN-NEXT: v_addc_u32_e32 v2, vcc, v10, v3, vcc 2697; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v9, vcc 2698; GCN-NEXT: v_add_u32_e32 v2, vcc, v2, v4 2699; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc 2700; GCN-NEXT: v_add_u32_e32 v6, vcc, v6, v2 2701; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v3, vcc 2702; GCN-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, s6, 0 2703; GCN-NEXT: v_mul_lo_u32 v4, v7, s6 2704; GCN-NEXT: s_mov_b32 s6, 0x186a0 2705; GCN-NEXT: v_subrev_u32_e32 v3, vcc, v6, v3 2706; GCN-NEXT: v_add_u32_e32 v5, vcc, v3, v4 2707; GCN-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v6, v5, 0 2708; GCN-NEXT: v_mul_hi_u32 v8, v6, v2 2709; GCN-NEXT: v_add_u32_e32 v8, vcc, v8, v3 2710; GCN-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v7, v2, 0 2711; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v4, vcc 2712; GCN-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v7, v5, 0 2713; GCN-NEXT: v_add_u32_e32 v2, vcc, v8, v2 2714; GCN-NEXT: v_addc_u32_e32 v2, vcc, v10, v3, vcc 2715; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v9, vcc 2716; GCN-NEXT: v_add_u32_e32 v2, vcc, v2, v4 2717; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc 2718; GCN-NEXT: v_add_u32_e32 v4, vcc, v6, v2 2719; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v3, vcc 2720; GCN-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v0, v5, 0 2721; GCN-NEXT: v_mul_hi_u32 v6, v0, v4 2722; GCN-NEXT: v_add_u32_e32 v6, vcc, v6, v2 2723; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc 2724; GCN-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, v4, 0 2725; GCN-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, v5, 0 2726; GCN-NEXT: v_add_u32_e32 v2, vcc, v6, v2 2727; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v3, vcc 2728; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v9, vcc 2729; GCN-NEXT: v_add_u32_e32 v4, vcc, v2, v4 2730; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v3, vcc 2731; GCN-NEXT: v_mul_lo_u32 v6, v5, s6 2732; GCN-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v4, s6, 0 2733; GCN-NEXT: s_mov_b32 s4, 0x1869f 2734; GCN-NEXT: v_add_u32_e32 v3, vcc, v3, v6 2735; GCN-NEXT: v_sub_u32_e32 v0, vcc, v0, v2 2736; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc 2737; GCN-NEXT: v_subrev_u32_e32 v2, vcc, s6, v0 2738; GCN-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v1, vcc 2739; GCN-NEXT: v_cmp_lt_u32_e32 vcc, s4, v2 2740; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc 2741; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 2742; GCN-NEXT: v_cndmask_b32_e32 v2, -1, v2, vcc 2743; GCN-NEXT: v_add_u32_e32 v3, vcc, 2, v4 2744; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v5, vcc 2745; GCN-NEXT: v_add_u32_e32 v7, vcc, 1, v4 2746; GCN-NEXT: v_cmp_lt_u32_e64 s[4:5], s4, v0 2747; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v5, vcc 2748; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5] 2749; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1 2750; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 2751; GCN-NEXT: v_cndmask_b32_e64 v0, -1, v0, s[4:5] 2752; GCN-NEXT: v_cndmask_b32_e32 v2, v7, v3, vcc 2753; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0 2754; GCN-NEXT: v_cndmask_b32_e32 v1, v8, v6, vcc 2755; GCN-NEXT: v_cndmask_b32_e64 v0, v4, v2, s[4:5] 2756; GCN-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[4:5] 2757; GCN-NEXT: s_setpc_b64 s[30:31] 2758; 2759; GFX1030-LABEL: v_test_udiv64_mulhi_fold: 2760; GFX1030: ; %bb.0: 2761; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2762; GFX1030-NEXT: s_waitcnt_vscnt null, 0x0 2763; GFX1030-NEXT: s_mov_b32 s4, 0x346d900 2764; GFX1030-NEXT: s_mov_b32 s5, 0xfffe7960 2765; GFX1030-NEXT: s_add_u32 s4, 0x4237, s4 2766; GFX1030-NEXT: s_addc_u32 s6, 0, 0 2767; GFX1030-NEXT: v_add_co_u32 v2, s4, 0xa9000000, s4 2768; GFX1030-NEXT: s_cmpk_lg_u32 s4, 0x0 2769; GFX1030-NEXT: s_addc_u32 s4, s6, 0xa7c5 2770; GFX1030-NEXT: v_mul_hi_u32 v3, v2, s5 2771; GFX1030-NEXT: v_mul_lo_u32 v4, v2, s5 2772; GFX1030-NEXT: s_mul_i32 s5, s4, s5 2773; GFX1030-NEXT: v_sub_nc_u32_e32 v3, v3, v2 2774; GFX1030-NEXT: v_mul_hi_u32 v5, v2, v4 2775; GFX1030-NEXT: v_mul_hi_u32 v8, s4, v4 2776; GFX1030-NEXT: v_mul_lo_u32 v4, s4, v4 2777; GFX1030-NEXT: v_add_nc_u32_e32 v3, s5, v3 2778; GFX1030-NEXT: v_mul_lo_u32 v6, v2, v3 2779; GFX1030-NEXT: v_mul_hi_u32 v7, v2, v3 2780; GFX1030-NEXT: v_mul_hi_u32 v9, s4, v3 2781; GFX1030-NEXT: v_mul_lo_u32 v3, s4, v3 2782; GFX1030-NEXT: v_add_co_u32 v5, vcc_lo, v5, v6 2783; GFX1030-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo 2784; GFX1030-NEXT: v_add_co_u32 v4, vcc_lo, v5, v4 2785; GFX1030-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v6, v8, vcc_lo 2786; GFX1030-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v9, vcc_lo 2787; GFX1030-NEXT: v_add_co_u32 v3, vcc_lo, v4, v3 2788; GFX1030-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo 2789; GFX1030-NEXT: v_add_co_u32 v5, vcc_lo, v2, v3 2790; GFX1030-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, s4, v4, vcc_lo 2791; GFX1030-NEXT: v_mul_hi_u32 v8, v0, v5 2792; GFX1030-NEXT: v_mad_u64_u32 v[4:5], s4, v1, v5, 0 2793; GFX1030-NEXT: v_mad_u64_u32 v[2:3], s4, v0, v6, 0 2794; GFX1030-NEXT: v_mad_u64_u32 v[6:7], s4, v1, v6, 0 2795; GFX1030-NEXT: s_mov_b32 s4, 0x186a0 2796; GFX1030-NEXT: v_add_co_u32 v2, vcc_lo, v8, v2 2797; GFX1030-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo 2798; GFX1030-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4 2799; GFX1030-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v3, v5, vcc_lo 2800; GFX1030-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v7, vcc_lo 2801; GFX1030-NEXT: v_add_co_u32 v4, vcc_lo, v2, v6 2802; GFX1030-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo 2803; GFX1030-NEXT: v_mad_u64_u32 v[2:3], s5, v4, s4, 0 2804; GFX1030-NEXT: v_mul_lo_u32 v6, v5, s4 2805; GFX1030-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v2 2806; GFX1030-NEXT: v_add_nc_u32_e32 v3, v3, v6 2807; GFX1030-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo 2808; GFX1030-NEXT: v_sub_co_u32 v2, vcc_lo, v0, s4 2809; GFX1030-NEXT: s_mov_b32 s4, 0x1869f 2810; GFX1030-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo 2811; GFX1030-NEXT: v_cmp_lt_u32_e32 vcc_lo, s4, v2 2812; GFX1030-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc_lo 2813; GFX1030-NEXT: v_add_co_u32 v6, vcc_lo, v4, 2 2814; GFX1030-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo 2815; GFX1030-NEXT: v_cmp_lt_u32_e32 vcc_lo, s4, v0 2816; GFX1030-NEXT: v_cmp_eq_u32_e64 s4, 0, v1 2817; GFX1030-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo 2818; GFX1030-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v3 2819; GFX1030-NEXT: v_cndmask_b32_e64 v0, -1, v0, s4 2820; GFX1030-NEXT: v_cndmask_b32_e32 v2, -1, v2, vcc_lo 2821; GFX1030-NEXT: v_add_co_u32 v3, vcc_lo, v4, 1 2822; GFX1030-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v5, vcc_lo 2823; GFX1030-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 2824; GFX1030-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc_lo 2825; GFX1030-NEXT: v_cndmask_b32_e32 v2, v8, v7, vcc_lo 2826; GFX1030-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 2827; GFX1030-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc_lo 2828; GFX1030-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo 2829; GFX1030-NEXT: s_setpc_b64 s[30:31] 2830; 2831; EG-LABEL: v_test_udiv64_mulhi_fold: 2832; EG: ; %bb.0: 2833; EG-NEXT: CF_END 2834; EG-NEXT: PAD 2835 %d = udiv i64 %arg, 100000 2836 ret i64 %d 2837} 2838