1; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
3; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
4; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s
5
6; FUNC-LABEL: {{^}}store_i1:
7; EG: MEM_RAT MSKOR
8; EG-NOT: MEM_RAT MSKOR
9
10; CM: MEM_RAT MSKOR
11; CM-NOT: MEM_RAT MSKOR
12
13; GCN: buffer_store_byte
14define void @store_i1(i1 addrspace(1)* %out) {
15entry:
16  store i1 true, i1 addrspace(1)* %out
17  ret void
18}
19
20; i8 store
21; FUNC-LABEL: {{^}}store_i8:
22; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
23; EG-NOT: MEM_RAT MSKOR
24
25; IG 0: Get the byte index and truncate the value
26; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x
27; EG: LSHL T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x
28; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y
29; EG-NEXT: 3(4.203895e-45), 255(3.573311e-43)
30
31
32; IG 1: Truncate the calculated the shift amount for the mask
33
34; IG 2: Shift the value and the mask
35; EG: LSHL T[[RW_GPR]].X, PS, PV.[[SHIFT_CHAN]]
36; EG: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]]
37; EG-NEXT: 255
38; IG 3: Initialize the Y and Z channels to zero
39;       XXX: An optimal scheduler should merge this into one of the prevous IGs.
40; EG: MOV T[[RW_GPR]].Y, 0.0
41; EG: MOV * T[[RW_GPR]].Z, 0.0
42
43; GCN: buffer_store_byte
44
45define void @store_i8(i8 addrspace(1)* %out, i8 %in) {
46entry:
47  store i8 %in, i8 addrspace(1)* %out
48  ret void
49}
50
51; i16 store
52; FUNC-LABEL: {{^}}store_i16:
53; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
54; EG-NOT: MEM_RAT MSKOR
55
56; IG 0: Get the byte index and truncate the value
57
58
59; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x
60; EG-NEXT: 3(4.203895e-45),
61
62; EG: LSHL T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x
63; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y
64
65; EG-NEXT: 3(4.203895e-45), 65535(9.183409e-41)
66; IG 1: Truncate the calculated the shift amount for the mask
67
68; IG 2: Shift the value and the mask
69; EG: LSHL T[[RW_GPR]].X, PS, PV.[[SHIFT_CHAN]]
70; EG: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]]
71; EG-NEXT: 65535
72; IG 3: Initialize the Y and Z channels to zero
73;       XXX: An optimal scheduler should merge this into one of the prevous IGs.
74; EG: MOV T[[RW_GPR]].Y, 0.0
75; EG: MOV * T[[RW_GPR]].Z, 0.0
76
77; GCN: buffer_store_short
78define void @store_i16(i16 addrspace(1)* %out, i16 %in) {
79entry:
80  store i16 %in, i16 addrspace(1)* %out
81  ret void
82}
83
84; FUNC-LABEL: {{^}}store_i24:
85; GCN: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 16
86; GCN-DAG: buffer_store_byte
87; GCN-DAG: buffer_store_short
88
89; EG: MEM_RAT MSKOR
90; EG: MEM_RAT MSKOR
91define void @store_i24(i24 addrspace(1)* %out, i24 %in) {
92entry:
93  store i24 %in, i24 addrspace(1)* %out
94  ret void
95}
96
97; FUNC-LABEL: {{^}}store_i25:
98; GCN: s_and_b32 [[AND:s[0-9]+]], s{{[0-9]+}}, 0x1ffffff{{$}}
99; GCN: v_mov_b32_e32 [[VAND:v[0-9]+]], [[AND]]
100; GCN: buffer_store_dword [[VAND]]
101
102; EG: MEM_RAT_CACHELESS STORE_RAW
103; EG-NOT: MEM_RAT
104
105; CM: MEM_RAT_CACHELESS STORE_DWORD
106; CM-NOT: MEM_RAT
107define void @store_i25(i25 addrspace(1)* %out, i25 %in) {
108entry:
109  store i25 %in, i25 addrspace(1)* %out
110  ret void
111}
112
113; FUNC-LABEL: {{^}}store_v2i8:
114; v2i8 is naturally 2B aligned
115; EG: MEM_RAT MSKOR
116; EG-NOT: MEM_RAT MSKOR
117
118; CM: MEM_RAT MSKOR
119; CM-NOT: MEM_RAT MSKOR
120
121; GCN: buffer_store_short
122define void @store_v2i8(<2 x i8> addrspace(1)* %out, <2 x i32> %in) {
123entry:
124  %0 = trunc <2 x i32> %in to <2 x i8>
125  store <2 x i8> %0, <2 x i8> addrspace(1)* %out
126  ret void
127}
128
129; FUNC-LABEL: {{^}}store_v2i8_unaligned:
130; EG: MEM_RAT MSKOR
131; EG: MEM_RAT MSKOR
132; EG-NOT: MEM_RAT MSKOR
133
134; CM: MEM_RAT MSKOR
135; CM: MEM_RAT MSKOR
136; CM-NOT: MEM_RAT MSKOR
137
138; SI: buffer_store_byte
139define void @store_v2i8_unaligned(<2 x i8> addrspace(1)* %out, <2 x i32> %in) {
140entry:
141  %0 = trunc <2 x i32> %in to <2 x i8>
142  store <2 x i8> %0, <2 x i8> addrspace(1)* %out, align 1
143  ret void
144}
145
146
147; FUNC-LABEL: {{^}}store_v2i16:
148; EG: MEM_RAT_CACHELESS STORE_RAW
149
150; CM: MEM_RAT_CACHELESS STORE_DWORD
151
152; GCN: buffer_store_dword
153define void @store_v2i16(<2 x i16> addrspace(1)* %out, <2 x i32> %in) {
154entry:
155  %0 = trunc <2 x i32> %in to <2 x i16>
156  store <2 x i16> %0, <2 x i16> addrspace(1)* %out
157  ret void
158}
159
160; FUNC-LABEL: {{^}}store_v2i16_unaligned:
161; EG: MEM_RAT MSKOR
162; EG: MEM_RAT MSKOR
163; EG-NOT: MEM_RAT MSKOR
164; EG-NOT: MEM_RAT_CACHELESS STORE_RAW
165
166; CM: MEM_RAT MSKOR
167; CM: MEM_RAT MSKOR
168; CM-NOT: MEM_RAT MSKOR
169; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD
170
171; SI: buffer_store_short
172; SI: buffer_store_short
173define void @store_v2i16_unaligned(<2 x i16> addrspace(1)* %out, <2 x i32> %in) {
174entry:
175  %0 = trunc <2 x i32> %in to <2 x i16>
176  store <2 x i16> %0, <2 x i16> addrspace(1)* %out, align 2
177  ret void
178}
179
180; FUNC-LABEL: {{^}}store_v4i8:
181; EG: MEM_RAT_CACHELESS STORE_RAW
182
183; CM: MEM_RAT_CACHELESS STORE_DWORD
184
185; GCN: buffer_store_dword
186define void @store_v4i8(<4 x i8> addrspace(1)* %out, <4 x i32> %in) {
187entry:
188  %0 = trunc <4 x i32> %in to <4 x i8>
189  store <4 x i8> %0, <4 x i8> addrspace(1)* %out
190  ret void
191}
192
193; FUNC-LABEL: {{^}}store_v4i8_unaligned:
194; EG: MEM_RAT MSKOR
195; EG: MEM_RAT MSKOR
196; EG: MEM_RAT MSKOR
197; EG: MEM_RAT MSKOR
198; EG-NOT: MEM_RAT MSKOR
199; EG-NOT: MEM_RAT_CACHELESS STORE_RAW
200
201; CM: MEM_RAT MSKOR
202; CM: MEM_RAT MSKOR
203; CM: MEM_RAT MSKOR
204; CM: MEM_RAT MSKOR
205; CM-NOT: MEM_RAT MSKOR
206; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD
207
208; SI: buffer_store_byte
209; SI: buffer_store_byte
210; SI: buffer_store_byte
211; SI: buffer_store_byte
212; SI-NOT: buffer_store_dword
213define void @store_v4i8_unaligned(<4 x i8> addrspace(1)* %out, <4 x i32> %in) {
214entry:
215  %0 = trunc <4 x i32> %in to <4 x i8>
216  store <4 x i8> %0, <4 x i8> addrspace(1)* %out, align 1
217  ret void
218}
219
220; FUNC-LABEL: {{^}}store_v4i8_halfaligned:
221; EG: MEM_RAT MSKOR
222; EG: MEM_RAT MSKOR
223; EG-NOT: MEM_RAT MSKOR
224; EG-NOT: MEM_RAT_CACHELESS STORE_RAW
225
226; CM: MEM_RAT MSKOR
227; CM: MEM_RAT MSKOR
228; CM-NOT: MEM_RAT MSKOR
229; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD
230
231; SI: buffer_store_short
232; SI: buffer_store_short
233; SI-NOT: buffer_store_dword
234define void @store_v4i8_halfaligned(<4 x i8> addrspace(1)* %out, <4 x i32> %in) {
235entry:
236  %0 = trunc <4 x i32> %in to <4 x i8>
237  store <4 x i8> %0, <4 x i8> addrspace(1)* %out, align 2
238  ret void
239}
240
241; floating-point store
242; FUNC-LABEL: {{^}}store_f32:
243; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.X, T[0-9]+\.X}}, 1
244
245; CM: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}}
246
247; GCN: buffer_store_dword
248
249define void @store_f32(float addrspace(1)* %out, float %in) {
250  store float %in, float addrspace(1)* %out
251  ret void
252}
253
254; FUNC-LABEL: {{^}}store_v4i16:
255; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY
256
257; CM: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+}}
258
259; GCN: buffer_store_dwordx2
260define void @store_v4i16(<4 x i16> addrspace(1)* %out, <4 x i32> %in) {
261entry:
262  %0 = trunc <4 x i32> %in to <4 x i16>
263  store <4 x i16> %0, <4 x i16> addrspace(1)* %out
264  ret void
265}
266
267; vec2 floating-point stores
268; FUNC-LABEL: {{^}}store_v2f32:
269; EG: MEM_RAT_CACHELESS STORE_RAW
270
271; CM: MEM_RAT_CACHELESS STORE_DWORD
272
273; GCN: buffer_store_dwordx2
274
275define void @store_v2f32(<2 x float> addrspace(1)* %out, float %a, float %b) {
276entry:
277  %0 = insertelement <2 x float> <float 0.0, float 0.0>, float %a, i32 0
278  %1 = insertelement <2 x float> %0, float %b, i32 1
279  store <2 x float> %1, <2 x float> addrspace(1)* %out
280  ret void
281}
282
283; FUNC-LABEL: {{^}}store_v3i32:
284; GCN-DAG: buffer_store_dwordx2
285; GCN-DAG: buffer_store_dword v
286
287; EG-DAG: MEM_RAT_CACHELESS STORE_RAW {{T[0-9]+\.[XYZW]}}, {{T[0-9]+\.[XYZW]}},
288; EG-DAG: MEM_RAT_CACHELESS STORE_RAW {{T[0-9]+\.XY}}, {{T[0-9]+\.[XYZW]}},
289define void @store_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> %a) nounwind {
290  store <3 x i32> %a, <3 x i32> addrspace(1)* %out, align 16
291  ret void
292}
293
294; FUNC-LABEL: {{^}}store_v4i32:
295; EG: MEM_RAT_CACHELESS STORE_RAW {{T[0-9]+\.XYZW}}
296; EG-NOT: MEM_RAT_CACHELESS STORE_RAW
297
298; CM: MEM_RAT_CACHELESS STORE_DWORD
299; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD
300
301; GCN: buffer_store_dwordx4
302define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %in) {
303entry:
304  store <4 x i32> %in, <4 x i32> addrspace(1)* %out
305  ret void
306}
307
308; FUNC-LABEL: {{^}}store_v4i32_unaligned:
309; EG: MEM_RAT_CACHELESS STORE_RAW {{T[0-9]+\.XYZW}}
310; EG-NOT: MEM_RAT_CACHELESS STORE_RAW
311
312; CM: MEM_RAT_CACHELESS STORE_DWORD
313; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD
314
315; SI: buffer_store_dwordx4
316define void @store_v4i32_unaligned(<4 x i32> addrspace(1)* %out, <4 x i32> %in) {
317entry:
318  store <4 x i32> %in, <4 x i32> addrspace(1)* %out, align 4
319  ret void
320}
321
322; v4f32 store
323; FUNC-LABEL: {{^}}store_v4f32:
324; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1
325; EG-NOT: MEM_RAT_CACHELESS STORE_RAW
326
327; CM: MEM_RAT_CACHELESS STORE_DWORD
328; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD
329
330; GCN: buffer_store_dwordx4
331define void @store_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
332  %1 = load <4 x float>, <4 x float> addrspace(1) * %in
333  store <4 x float> %1, <4 x float> addrspace(1)* %out
334  ret void
335}
336
337; FUNC-LABEL: {{^}}store_i64_i8:
338; EG: MEM_RAT MSKOR
339
340; CM: MEM_RAT MSKOR
341
342; GCN: buffer_store_byte
343define void @store_i64_i8(i8 addrspace(1)* %out, i64 %in) {
344entry:
345  %0 = trunc i64 %in to i8
346  store i8 %0, i8 addrspace(1)* %out
347  ret void
348}
349
350; FUNC-LABEL: {{^}}store_i64_i16:
351; EG: MEM_RAT MSKOR
352; GCN: buffer_store_short
353define void @store_i64_i16(i16 addrspace(1)* %out, i64 %in) {
354entry:
355  %0 = trunc i64 %in to i16
356  store i16 %0, i16 addrspace(1)* %out
357  ret void
358}
359
360; The stores in this function are combined by the optimizer to create a
361; 64-bit store with 32-bit alignment.  This is legal and the legalizer
362; should not try to split the 64-bit store back into 2 32-bit stores.
363
364; FUNC-LABEL: {{^}}vecload2:
365; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.XY, T[0-9]+\.X}}, 1
366; EG-NOT: MEM_RAT_CACHELESS STORE_RAW
367
368; CM: MEM_RAT_CACHELESS STORE_DWORD
369; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD
370
371; GCN: buffer_store_dwordx2
372define void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 {
373entry:
374  %0 = load i32, i32 addrspace(2)* %mem, align 4
375  %arrayidx1.i = getelementptr inbounds i32, i32 addrspace(2)* %mem, i64 1
376  %1 = load i32, i32 addrspace(2)* %arrayidx1.i, align 4
377  store i32 %0, i32 addrspace(1)* %out, align 4
378  %arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 1
379  store i32 %1, i32 addrspace(1)* %arrayidx1, align 4
380  ret void
381}
382
383; When i128 was a legal type this program generated cannot select errors:
384
385; FUNC-LABEL: {{^}}"i128-const-store":
386; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 1
387
388; CM: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+}}, T{{[0-9]+}}.X
389
390; GCN: buffer_store_dwordx4
391define void @i128-const-store(i32 addrspace(1)* %out) {
392entry:
393  store i32 1, i32 addrspace(1)* %out, align 4
394  %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 1
395  store i32 1, i32 addrspace(1)* %arrayidx2, align 4
396  %arrayidx4 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 2
397  store i32 2, i32 addrspace(1)* %arrayidx4, align 4
398  %arrayidx6 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 3
399  store i32 2, i32 addrspace(1)* %arrayidx6, align 4
400  ret void
401}
402
403attributes #0 = { nounwind }
404