1; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji --amdhsa-code-object-version=3 < %s | FileCheck -check-prefix=VI %s
2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=3 < %s | FileCheck -check-prefix=GFX9 %s
3
4; Make sure the stack is never realigned for entry functions.
5
6define amdgpu_kernel void @max_alignment_128() #0 {
7; VI-LABEL: max_alignment_128:
8; VI:       ; %bb.0:
9; VI-NEXT:    s_add_u32 s0, s0, s7
10; VI-NEXT:    s_addc_u32 s1, s1, 0
11; VI-NEXT:    v_mov_b32_e32 v0, 9
12; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:128
13; VI-NEXT:    s_waitcnt vmcnt(0)
14; VI-NEXT:    s_endpgm
15; VI-NEXT:    .section .rodata,#alloc
16; VI-NEXT:    .p2align 6
17; VI-NEXT:    .amdhsa_kernel max_alignment_128
18; VI-NEXT:     .amdhsa_group_segment_fixed_size 0
19; VI-NEXT:     .amdhsa_private_segment_fixed_size 256
20; VI-NEXT:     .amdhsa_kernarg_size 0
21; VI-NEXT:     .amdhsa_user_sgpr_count 6
22; VI-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
23; VI-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
24; VI-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
25; VI-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 0
26; VI-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
27; VI-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 1
28; VI-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
29; VI-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1
30; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
31; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
32; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
33; VI-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
34; VI-NEXT:     .amdhsa_system_vgpr_workitem_id 0
35; VI-NEXT:     .amdhsa_next_free_vgpr 1
36; VI-NEXT:     .amdhsa_next_free_sgpr 8
37; VI-NEXT:     .amdhsa_reserve_vcc 0
38; VI-NEXT:     .amdhsa_reserve_flat_scratch 0
39; VI-NEXT:     .amdhsa_float_round_mode_32 0
40; VI-NEXT:     .amdhsa_float_round_mode_16_64 0
41; VI-NEXT:     .amdhsa_float_denorm_mode_32 3
42; VI-NEXT:     .amdhsa_float_denorm_mode_16_64 3
43; VI-NEXT:     .amdhsa_dx10_clamp 1
44; VI-NEXT:     .amdhsa_ieee_mode 1
45; VI-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0
46; VI-NEXT:     .amdhsa_exception_fp_denorm_src 0
47; VI-NEXT:     .amdhsa_exception_fp_ieee_div_zero 0
48; VI-NEXT:     .amdhsa_exception_fp_ieee_overflow 0
49; VI-NEXT:     .amdhsa_exception_fp_ieee_underflow 0
50; VI-NEXT:     .amdhsa_exception_fp_ieee_inexact 0
51; VI-NEXT:     .amdhsa_exception_int_div_zero 0
52; VI-NEXT:    .end_amdhsa_kernel
53; VI-NEXT:    .text
54;
55; GFX9-LABEL: max_alignment_128:
56; GFX9:       ; %bb.0:
57; GFX9-NEXT:    s_add_u32 s0, s0, s7
58; GFX9-NEXT:    s_addc_u32 s1, s1, 0
59; GFX9-NEXT:    v_mov_b32_e32 v0, 9
60; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:128
61; GFX9-NEXT:    s_waitcnt vmcnt(0)
62; GFX9-NEXT:    s_endpgm
63; GFX9-NEXT:    .section .rodata,#alloc
64; GFX9-NEXT:    .p2align 6
65; GFX9-NEXT:    .amdhsa_kernel max_alignment_128
66; GFX9-NEXT:     .amdhsa_group_segment_fixed_size 0
67; GFX9-NEXT:     .amdhsa_private_segment_fixed_size 256
68; GFX9-NEXT:     .amdhsa_kernarg_size 0
69; GFX9-NEXT:     .amdhsa_user_sgpr_count 6
70; GFX9-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
71; GFX9-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
72; GFX9-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
73; GFX9-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 0
74; GFX9-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
75; GFX9-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 1
76; GFX9-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
77; GFX9-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1
78; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
79; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
80; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
81; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
82; GFX9-NEXT:     .amdhsa_system_vgpr_workitem_id 0
83; GFX9-NEXT:     .amdhsa_next_free_vgpr 1
84; GFX9-NEXT:     .amdhsa_next_free_sgpr 8
85; GFX9-NEXT:     .amdhsa_reserve_vcc 0
86; GFX9-NEXT:     .amdhsa_reserve_flat_scratch 0
87; GFX9-NEXT:     .amdhsa_reserve_xnack_mask 1
88; GFX9-NEXT:     .amdhsa_float_round_mode_32 0
89; GFX9-NEXT:     .amdhsa_float_round_mode_16_64 0
90; GFX9-NEXT:     .amdhsa_float_denorm_mode_32 3
91; GFX9-NEXT:     .amdhsa_float_denorm_mode_16_64 3
92; GFX9-NEXT:     .amdhsa_dx10_clamp 1
93; GFX9-NEXT:     .amdhsa_ieee_mode 1
94; GFX9-NEXT:     .amdhsa_fp16_overflow 0
95; GFX9-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0
96; GFX9-NEXT:     .amdhsa_exception_fp_denorm_src 0
97; GFX9-NEXT:     .amdhsa_exception_fp_ieee_div_zero 0
98; GFX9-NEXT:     .amdhsa_exception_fp_ieee_overflow 0
99; GFX9-NEXT:     .amdhsa_exception_fp_ieee_underflow 0
100; GFX9-NEXT:     .amdhsa_exception_fp_ieee_inexact 0
101; GFX9-NEXT:     .amdhsa_exception_int_div_zero 0
102; GFX9-NEXT:    .end_amdhsa_kernel
103; GFX9-NEXT:    .text
104  %alloca.align = alloca i32, align 128, addrspace(5)
105  store volatile i32 9, i32 addrspace(5)* %alloca.align, align 128
106  ret void
107}
108
109define amdgpu_kernel void @stackrealign_attr() #1 {
110; VI-LABEL: stackrealign_attr:
111; VI:       ; %bb.0:
112; VI-NEXT:    s_add_u32 s0, s0, s7
113; VI-NEXT:    s_addc_u32 s1, s1, 0
114; VI-NEXT:    v_mov_b32_e32 v0, 9
115; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:4
116; VI-NEXT:    s_waitcnt vmcnt(0)
117; VI-NEXT:    s_endpgm
118; VI-NEXT:    .section .rodata,#alloc
119; VI-NEXT:    .p2align 6
120; VI-NEXT:    .amdhsa_kernel stackrealign_attr
121; VI-NEXT:     .amdhsa_group_segment_fixed_size 0
122; VI-NEXT:     .amdhsa_private_segment_fixed_size 8
123; VI-NEXT:     .amdhsa_kernarg_size 0
124; VI-NEXT:     .amdhsa_user_sgpr_count 6
125; VI-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
126; VI-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
127; VI-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
128; VI-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 0
129; VI-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
130; VI-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 1
131; VI-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
132; VI-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1
133; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
134; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
135; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
136; VI-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
137; VI-NEXT:     .amdhsa_system_vgpr_workitem_id 0
138; VI-NEXT:     .amdhsa_next_free_vgpr 1
139; VI-NEXT:     .amdhsa_next_free_sgpr 8
140; VI-NEXT:     .amdhsa_reserve_vcc 0
141; VI-NEXT:     .amdhsa_reserve_flat_scratch 0
142; VI-NEXT:     .amdhsa_float_round_mode_32 0
143; VI-NEXT:     .amdhsa_float_round_mode_16_64 0
144; VI-NEXT:     .amdhsa_float_denorm_mode_32 3
145; VI-NEXT:     .amdhsa_float_denorm_mode_16_64 3
146; VI-NEXT:     .amdhsa_dx10_clamp 1
147; VI-NEXT:     .amdhsa_ieee_mode 1
148; VI-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0
149; VI-NEXT:     .amdhsa_exception_fp_denorm_src 0
150; VI-NEXT:     .amdhsa_exception_fp_ieee_div_zero 0
151; VI-NEXT:     .amdhsa_exception_fp_ieee_overflow 0
152; VI-NEXT:     .amdhsa_exception_fp_ieee_underflow 0
153; VI-NEXT:     .amdhsa_exception_fp_ieee_inexact 0
154; VI-NEXT:     .amdhsa_exception_int_div_zero 0
155; VI-NEXT:    .end_amdhsa_kernel
156; VI-NEXT:    .text
157;
158; GFX9-LABEL: stackrealign_attr:
159; GFX9:       ; %bb.0:
160; GFX9-NEXT:    s_add_u32 s0, s0, s7
161; GFX9-NEXT:    s_addc_u32 s1, s1, 0
162; GFX9-NEXT:    v_mov_b32_e32 v0, 9
163; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:4
164; GFX9-NEXT:    s_waitcnt vmcnt(0)
165; GFX9-NEXT:    s_endpgm
166; GFX9-NEXT:    .section .rodata,#alloc
167; GFX9-NEXT:    .p2align 6
168; GFX9-NEXT:    .amdhsa_kernel stackrealign_attr
169; GFX9-NEXT:     .amdhsa_group_segment_fixed_size 0
170; GFX9-NEXT:     .amdhsa_private_segment_fixed_size 8
171; GFX9-NEXT:     .amdhsa_kernarg_size 0
172; GFX9-NEXT:     .amdhsa_user_sgpr_count 6
173; GFX9-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
174; GFX9-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
175; GFX9-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
176; GFX9-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 0
177; GFX9-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
178; GFX9-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 1
179; GFX9-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
180; GFX9-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1
181; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
182; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
183; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
184; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
185; GFX9-NEXT:     .amdhsa_system_vgpr_workitem_id 0
186; GFX9-NEXT:     .amdhsa_next_free_vgpr 1
187; GFX9-NEXT:     .amdhsa_next_free_sgpr 8
188; GFX9-NEXT:     .amdhsa_reserve_vcc 0
189; GFX9-NEXT:     .amdhsa_reserve_flat_scratch 0
190; GFX9-NEXT:     .amdhsa_reserve_xnack_mask 1
191; GFX9-NEXT:     .amdhsa_float_round_mode_32 0
192; GFX9-NEXT:     .amdhsa_float_round_mode_16_64 0
193; GFX9-NEXT:     .amdhsa_float_denorm_mode_32 3
194; GFX9-NEXT:     .amdhsa_float_denorm_mode_16_64 3
195; GFX9-NEXT:     .amdhsa_dx10_clamp 1
196; GFX9-NEXT:     .amdhsa_ieee_mode 1
197; GFX9-NEXT:     .amdhsa_fp16_overflow 0
198; GFX9-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0
199; GFX9-NEXT:     .amdhsa_exception_fp_denorm_src 0
200; GFX9-NEXT:     .amdhsa_exception_fp_ieee_div_zero 0
201; GFX9-NEXT:     .amdhsa_exception_fp_ieee_overflow 0
202; GFX9-NEXT:     .amdhsa_exception_fp_ieee_underflow 0
203; GFX9-NEXT:     .amdhsa_exception_fp_ieee_inexact 0
204; GFX9-NEXT:     .amdhsa_exception_int_div_zero 0
205; GFX9-NEXT:    .end_amdhsa_kernel
206; GFX9-NEXT:    .text
207  %alloca.align = alloca i32, align 4, addrspace(5)
208  store volatile i32 9, i32 addrspace(5)* %alloca.align, align 4
209  ret void
210}
211
212define amdgpu_kernel void @alignstack_attr() #2 {
213; VI-LABEL: alignstack_attr:
214; VI:       ; %bb.0:
215; VI-NEXT:    s_add_u32 s0, s0, s7
216; VI-NEXT:    s_addc_u32 s1, s1, 0
217; VI-NEXT:    v_mov_b32_e32 v0, 9
218; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:4
219; VI-NEXT:    s_waitcnt vmcnt(0)
220; VI-NEXT:    s_endpgm
221; VI-NEXT:    .section .rodata,#alloc
222; VI-NEXT:    .p2align 6
223; VI-NEXT:    .amdhsa_kernel alignstack_attr
224; VI-NEXT:     .amdhsa_group_segment_fixed_size 0
225; VI-NEXT:     .amdhsa_private_segment_fixed_size 128
226; VI-NEXT:     .amdhsa_kernarg_size 0
227; VI-NEXT:     .amdhsa_user_sgpr_count 6
228; VI-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
229; VI-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
230; VI-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
231; VI-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 0
232; VI-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
233; VI-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 1
234; VI-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
235; VI-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1
236; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
237; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
238; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
239; VI-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
240; VI-NEXT:     .amdhsa_system_vgpr_workitem_id 0
241; VI-NEXT:     .amdhsa_next_free_vgpr 1
242; VI-NEXT:     .amdhsa_next_free_sgpr 8
243; VI-NEXT:     .amdhsa_reserve_vcc 0
244; VI-NEXT:     .amdhsa_reserve_flat_scratch 0
245; VI-NEXT:     .amdhsa_float_round_mode_32 0
246; VI-NEXT:     .amdhsa_float_round_mode_16_64 0
247; VI-NEXT:     .amdhsa_float_denorm_mode_32 3
248; VI-NEXT:     .amdhsa_float_denorm_mode_16_64 3
249; VI-NEXT:     .amdhsa_dx10_clamp 1
250; VI-NEXT:     .amdhsa_ieee_mode 1
251; VI-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0
252; VI-NEXT:     .amdhsa_exception_fp_denorm_src 0
253; VI-NEXT:     .amdhsa_exception_fp_ieee_div_zero 0
254; VI-NEXT:     .amdhsa_exception_fp_ieee_overflow 0
255; VI-NEXT:     .amdhsa_exception_fp_ieee_underflow 0
256; VI-NEXT:     .amdhsa_exception_fp_ieee_inexact 0
257; VI-NEXT:     .amdhsa_exception_int_div_zero 0
258; VI-NEXT:    .end_amdhsa_kernel
259; VI-NEXT:    .text
260;
261; GFX9-LABEL: alignstack_attr:
262; GFX9:       ; %bb.0:
263; GFX9-NEXT:    s_add_u32 s0, s0, s7
264; GFX9-NEXT:    s_addc_u32 s1, s1, 0
265; GFX9-NEXT:    v_mov_b32_e32 v0, 9
266; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:4
267; GFX9-NEXT:    s_waitcnt vmcnt(0)
268; GFX9-NEXT:    s_endpgm
269; GFX9-NEXT:    .section .rodata,#alloc
270; GFX9-NEXT:    .p2align 6
271; GFX9-NEXT:    .amdhsa_kernel alignstack_attr
272; GFX9-NEXT:     .amdhsa_group_segment_fixed_size 0
273; GFX9-NEXT:     .amdhsa_private_segment_fixed_size 128
274; GFX9-NEXT:     .amdhsa_kernarg_size 0
275; GFX9-NEXT:     .amdhsa_user_sgpr_count 6
276; GFX9-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
277; GFX9-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
278; GFX9-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
279; GFX9-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 0
280; GFX9-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
281; GFX9-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 1
282; GFX9-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
283; GFX9-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1
284; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
285; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
286; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
287; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
288; GFX9-NEXT:     .amdhsa_system_vgpr_workitem_id 0
289; GFX9-NEXT:     .amdhsa_next_free_vgpr 1
290; GFX9-NEXT:     .amdhsa_next_free_sgpr 8
291; GFX9-NEXT:     .amdhsa_reserve_vcc 0
292; GFX9-NEXT:     .amdhsa_reserve_flat_scratch 0
293; GFX9-NEXT:     .amdhsa_reserve_xnack_mask 1
294; GFX9-NEXT:     .amdhsa_float_round_mode_32 0
295; GFX9-NEXT:     .amdhsa_float_round_mode_16_64 0
296; GFX9-NEXT:     .amdhsa_float_denorm_mode_32 3
297; GFX9-NEXT:     .amdhsa_float_denorm_mode_16_64 3
298; GFX9-NEXT:     .amdhsa_dx10_clamp 1
299; GFX9-NEXT:     .amdhsa_ieee_mode 1
300; GFX9-NEXT:     .amdhsa_fp16_overflow 0
301; GFX9-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0
302; GFX9-NEXT:     .amdhsa_exception_fp_denorm_src 0
303; GFX9-NEXT:     .amdhsa_exception_fp_ieee_div_zero 0
304; GFX9-NEXT:     .amdhsa_exception_fp_ieee_overflow 0
305; GFX9-NEXT:     .amdhsa_exception_fp_ieee_underflow 0
306; GFX9-NEXT:     .amdhsa_exception_fp_ieee_inexact 0
307; GFX9-NEXT:     .amdhsa_exception_int_div_zero 0
308; GFX9-NEXT:    .end_amdhsa_kernel
309; GFX9-NEXT:    .text
310  %alloca.align = alloca i32, align 4, addrspace(5)
311  store volatile i32 9, i32 addrspace(5)* %alloca.align, align 4
312  ret void
313}
314
315attributes #0 = { nounwind }
316attributes #1 = { nounwind "stackrealign" }
317attributes #2 = { nounwind alignstack=128 }
318