1; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji --amdhsa-code-object-version=3 < %s | FileCheck -check-prefix=VI %s
2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=3 < %s | FileCheck -check-prefix=GFX9 %s
3
4; Make sure the stack is never realigned for entry functions.
5
6define amdgpu_kernel void @max_alignment_128() #0 {
7; VI-LABEL: max_alignment_128:
8; VI:       ; %bb.0:
9; VI-NEXT:    s_add_u32 s4, s4, s7
10; VI-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
11; VI-NEXT:    s_add_u32 s0, s0, s7
12; VI-NEXT:    s_addc_u32 s1, s1, 0
13; VI-NEXT:    v_mov_b32_e32 v0, 9
14; VI-NEXT:    s_mov_b32 flat_scratch_lo, s5
15; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:128
16; VI-NEXT:    s_waitcnt vmcnt(0)
17; VI-NEXT:    s_endpgm
18; VI-NEXT:    .section .rodata,#alloc
19; VI-NEXT:    .p2align 6
20; VI-NEXT:    .amdhsa_kernel max_alignment_128
21; VI-NEXT:     .amdhsa_group_segment_fixed_size 0
22; VI-NEXT:     .amdhsa_private_segment_fixed_size 256
23; VI-NEXT:     .amdhsa_kernarg_size 0
24; VI-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
25; VI-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
26; VI-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
27; VI-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 0
28; VI-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
29; VI-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 1
30; VI-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
31; VI-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1
32; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
33; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
34; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
35; VI-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
36; VI-NEXT:     .amdhsa_system_vgpr_workitem_id 0
37; VI-NEXT:     .amdhsa_next_free_vgpr 1
38; VI-NEXT:     .amdhsa_next_free_sgpr 8
39; VI-NEXT:     .amdhsa_reserve_vcc 0
40; VI-NEXT:     .amdhsa_float_round_mode_32 0
41; VI-NEXT:     .amdhsa_float_round_mode_16_64 0
42; VI-NEXT:     .amdhsa_float_denorm_mode_32 3
43; VI-NEXT:     .amdhsa_float_denorm_mode_16_64 3
44; VI-NEXT:     .amdhsa_dx10_clamp 1
45; VI-NEXT:     .amdhsa_ieee_mode 1
46; VI-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0
47; VI-NEXT:     .amdhsa_exception_fp_denorm_src 0
48; VI-NEXT:     .amdhsa_exception_fp_ieee_div_zero 0
49; VI-NEXT:     .amdhsa_exception_fp_ieee_overflow 0
50; VI-NEXT:     .amdhsa_exception_fp_ieee_underflow 0
51; VI-NEXT:     .amdhsa_exception_fp_ieee_inexact 0
52; VI-NEXT:     .amdhsa_exception_int_div_zero 0
53; VI-NEXT:    .end_amdhsa_kernel
54; VI-NEXT:    .text
55;
56; GFX9-LABEL: max_alignment_128:
57; GFX9:       ; %bb.0:
58; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s4, s7
59; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s5, 0
60; GFX9-NEXT:    s_add_u32 s0, s0, s7
61; GFX9-NEXT:    s_addc_u32 s1, s1, 0
62; GFX9-NEXT:    v_mov_b32_e32 v0, 9
63; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:128
64; GFX9-NEXT:    s_waitcnt vmcnt(0)
65; GFX9-NEXT:    s_endpgm
66; GFX9-NEXT:    .section .rodata,#alloc
67; GFX9-NEXT:    .p2align 6
68; GFX9-NEXT:    .amdhsa_kernel max_alignment_128
69; GFX9-NEXT:     .amdhsa_group_segment_fixed_size 0
70; GFX9-NEXT:     .amdhsa_private_segment_fixed_size 256
71; GFX9-NEXT:     .amdhsa_kernarg_size 0
72; GFX9-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
73; GFX9-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
74; GFX9-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
75; GFX9-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 0
76; GFX9-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
77; GFX9-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 1
78; GFX9-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
79; GFX9-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1
80; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
81; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
82; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
83; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
84; GFX9-NEXT:     .amdhsa_system_vgpr_workitem_id 0
85; GFX9-NEXT:     .amdhsa_next_free_vgpr 1
86; GFX9-NEXT:     .amdhsa_next_free_sgpr 8
87; GFX9-NEXT:     .amdhsa_reserve_vcc 0
88; GFX9-NEXT:     .amdhsa_reserve_xnack_mask 1
89; GFX9-NEXT:     .amdhsa_float_round_mode_32 0
90; GFX9-NEXT:     .amdhsa_float_round_mode_16_64 0
91; GFX9-NEXT:     .amdhsa_float_denorm_mode_32 3
92; GFX9-NEXT:     .amdhsa_float_denorm_mode_16_64 3
93; GFX9-NEXT:     .amdhsa_dx10_clamp 1
94; GFX9-NEXT:     .amdhsa_ieee_mode 1
95; GFX9-NEXT:     .amdhsa_fp16_overflow 0
96; GFX9-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0
97; GFX9-NEXT:     .amdhsa_exception_fp_denorm_src 0
98; GFX9-NEXT:     .amdhsa_exception_fp_ieee_div_zero 0
99; GFX9-NEXT:     .amdhsa_exception_fp_ieee_overflow 0
100; GFX9-NEXT:     .amdhsa_exception_fp_ieee_underflow 0
101; GFX9-NEXT:     .amdhsa_exception_fp_ieee_inexact 0
102; GFX9-NEXT:     .amdhsa_exception_int_div_zero 0
103; GFX9-NEXT:    .end_amdhsa_kernel
104; GFX9-NEXT:    .text
105  %alloca.align = alloca i32, align 128, addrspace(5)
106  store volatile i32 9, i32 addrspace(5)* %alloca.align, align 128
107  ret void
108}
109
110define amdgpu_kernel void @stackrealign_attr() #1 {
111; VI-LABEL: stackrealign_attr:
112; VI:       ; %bb.0:
113; VI-NEXT:    s_add_u32 s4, s4, s7
114; VI-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
115; VI-NEXT:    s_add_u32 s0, s0, s7
116; VI-NEXT:    s_addc_u32 s1, s1, 0
117; VI-NEXT:    v_mov_b32_e32 v0, 9
118; VI-NEXT:    s_mov_b32 flat_scratch_lo, s5
119; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:4
120; VI-NEXT:    s_waitcnt vmcnt(0)
121; VI-NEXT:    s_endpgm
122; VI-NEXT:    .section .rodata,#alloc
123; VI-NEXT:    .p2align 6
124; VI-NEXT:    .amdhsa_kernel stackrealign_attr
125; VI-NEXT:     .amdhsa_group_segment_fixed_size 0
126; VI-NEXT:     .amdhsa_private_segment_fixed_size 8
127; VI-NEXT:     .amdhsa_kernarg_size 0
128; VI-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
129; VI-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
130; VI-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
131; VI-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 0
132; VI-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
133; VI-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 1
134; VI-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
135; VI-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1
136; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
137; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
138; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
139; VI-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
140; VI-NEXT:     .amdhsa_system_vgpr_workitem_id 0
141; VI-NEXT:     .amdhsa_next_free_vgpr 1
142; VI-NEXT:     .amdhsa_next_free_sgpr 8
143; VI-NEXT:     .amdhsa_reserve_vcc 0
144; VI-NEXT:     .amdhsa_float_round_mode_32 0
145; VI-NEXT:     .amdhsa_float_round_mode_16_64 0
146; VI-NEXT:     .amdhsa_float_denorm_mode_32 3
147; VI-NEXT:     .amdhsa_float_denorm_mode_16_64 3
148; VI-NEXT:     .amdhsa_dx10_clamp 1
149; VI-NEXT:     .amdhsa_ieee_mode 1
150; VI-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0
151; VI-NEXT:     .amdhsa_exception_fp_denorm_src 0
152; VI-NEXT:     .amdhsa_exception_fp_ieee_div_zero 0
153; VI-NEXT:     .amdhsa_exception_fp_ieee_overflow 0
154; VI-NEXT:     .amdhsa_exception_fp_ieee_underflow 0
155; VI-NEXT:     .amdhsa_exception_fp_ieee_inexact 0
156; VI-NEXT:     .amdhsa_exception_int_div_zero 0
157; VI-NEXT:    .end_amdhsa_kernel
158; VI-NEXT:    .text
159;
160; GFX9-LABEL: stackrealign_attr:
161; GFX9:       ; %bb.0:
162; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s4, s7
163; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s5, 0
164; GFX9-NEXT:    s_add_u32 s0, s0, s7
165; GFX9-NEXT:    s_addc_u32 s1, s1, 0
166; GFX9-NEXT:    v_mov_b32_e32 v0, 9
167; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:4
168; GFX9-NEXT:    s_waitcnt vmcnt(0)
169; GFX9-NEXT:    s_endpgm
170; GFX9-NEXT:    .section .rodata,#alloc
171; GFX9-NEXT:    .p2align 6
172; GFX9-NEXT:    .amdhsa_kernel stackrealign_attr
173; GFX9-NEXT:     .amdhsa_group_segment_fixed_size 0
174; GFX9-NEXT:     .amdhsa_private_segment_fixed_size 8
175; GFX9-NEXT:     .amdhsa_kernarg_size 0
176; GFX9-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
177; GFX9-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
178; GFX9-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
179; GFX9-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 0
180; GFX9-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
181; GFX9-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 1
182; GFX9-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
183; GFX9-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1
184; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
185; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
186; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
187; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
188; GFX9-NEXT:     .amdhsa_system_vgpr_workitem_id 0
189; GFX9-NEXT:     .amdhsa_next_free_vgpr 1
190; GFX9-NEXT:     .amdhsa_next_free_sgpr 8
191; GFX9-NEXT:     .amdhsa_reserve_vcc 0
192; GFX9-NEXT:     .amdhsa_reserve_xnack_mask 1
193; GFX9-NEXT:     .amdhsa_float_round_mode_32 0
194; GFX9-NEXT:     .amdhsa_float_round_mode_16_64 0
195; GFX9-NEXT:     .amdhsa_float_denorm_mode_32 3
196; GFX9-NEXT:     .amdhsa_float_denorm_mode_16_64 3
197; GFX9-NEXT:     .amdhsa_dx10_clamp 1
198; GFX9-NEXT:     .amdhsa_ieee_mode 1
199; GFX9-NEXT:     .amdhsa_fp16_overflow 0
200; GFX9-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0
201; GFX9-NEXT:     .amdhsa_exception_fp_denorm_src 0
202; GFX9-NEXT:     .amdhsa_exception_fp_ieee_div_zero 0
203; GFX9-NEXT:     .amdhsa_exception_fp_ieee_overflow 0
204; GFX9-NEXT:     .amdhsa_exception_fp_ieee_underflow 0
205; GFX9-NEXT:     .amdhsa_exception_fp_ieee_inexact 0
206; GFX9-NEXT:     .amdhsa_exception_int_div_zero 0
207; GFX9-NEXT:    .end_amdhsa_kernel
208; GFX9-NEXT:    .text
209  %alloca.align = alloca i32, align 4, addrspace(5)
210  store volatile i32 9, i32 addrspace(5)* %alloca.align, align 4
211  ret void
212}
213
214define amdgpu_kernel void @alignstack_attr() #2 {
215; VI-LABEL: alignstack_attr:
216; VI:       ; %bb.0:
217; VI-NEXT:    s_add_u32 s4, s4, s7
218; VI-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
219; VI-NEXT:    s_add_u32 s0, s0, s7
220; VI-NEXT:    s_addc_u32 s1, s1, 0
221; VI-NEXT:    v_mov_b32_e32 v0, 9
222; VI-NEXT:    s_mov_b32 flat_scratch_lo, s5
223; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:4
224; VI-NEXT:    s_waitcnt vmcnt(0)
225; VI-NEXT:    s_endpgm
226; VI-NEXT:    .section .rodata,#alloc
227; VI-NEXT:    .p2align 6
228; VI-NEXT:    .amdhsa_kernel alignstack_attr
229; VI-NEXT:     .amdhsa_group_segment_fixed_size 0
230; VI-NEXT:     .amdhsa_private_segment_fixed_size 128
231; VI-NEXT:     .amdhsa_kernarg_size 0
232; VI-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
233; VI-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
234; VI-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
235; VI-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 0
236; VI-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
237; VI-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 1
238; VI-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
239; VI-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1
240; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
241; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
242; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
243; VI-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
244; VI-NEXT:     .amdhsa_system_vgpr_workitem_id 0
245; VI-NEXT:     .amdhsa_next_free_vgpr 1
246; VI-NEXT:     .amdhsa_next_free_sgpr 8
247; VI-NEXT:     .amdhsa_reserve_vcc 0
248; VI-NEXT:     .amdhsa_float_round_mode_32 0
249; VI-NEXT:     .amdhsa_float_round_mode_16_64 0
250; VI-NEXT:     .amdhsa_float_denorm_mode_32 3
251; VI-NEXT:     .amdhsa_float_denorm_mode_16_64 3
252; VI-NEXT:     .amdhsa_dx10_clamp 1
253; VI-NEXT:     .amdhsa_ieee_mode 1
254; VI-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0
255; VI-NEXT:     .amdhsa_exception_fp_denorm_src 0
256; VI-NEXT:     .amdhsa_exception_fp_ieee_div_zero 0
257; VI-NEXT:     .amdhsa_exception_fp_ieee_overflow 0
258; VI-NEXT:     .amdhsa_exception_fp_ieee_underflow 0
259; VI-NEXT:     .amdhsa_exception_fp_ieee_inexact 0
260; VI-NEXT:     .amdhsa_exception_int_div_zero 0
261; VI-NEXT:    .end_amdhsa_kernel
262; VI-NEXT:    .text
263;
264; GFX9-LABEL: alignstack_attr:
265; GFX9:       ; %bb.0:
266; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s4, s7
267; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s5, 0
268; GFX9-NEXT:    s_add_u32 s0, s0, s7
269; GFX9-NEXT:    s_addc_u32 s1, s1, 0
270; GFX9-NEXT:    v_mov_b32_e32 v0, 9
271; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:4
272; GFX9-NEXT:    s_waitcnt vmcnt(0)
273; GFX9-NEXT:    s_endpgm
274; GFX9-NEXT:    .section .rodata,#alloc
275; GFX9-NEXT:    .p2align 6
276; GFX9-NEXT:    .amdhsa_kernel alignstack_attr
277; GFX9-NEXT:     .amdhsa_group_segment_fixed_size 0
278; GFX9-NEXT:     .amdhsa_private_segment_fixed_size 128
279; GFX9-NEXT:     .amdhsa_kernarg_size 0
280; GFX9-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
281; GFX9-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
282; GFX9-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
283; GFX9-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 0
284; GFX9-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
285; GFX9-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 1
286; GFX9-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
287; GFX9-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1
288; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
289; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
290; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
291; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
292; GFX9-NEXT:     .amdhsa_system_vgpr_workitem_id 0
293; GFX9-NEXT:     .amdhsa_next_free_vgpr 1
294; GFX9-NEXT:     .amdhsa_next_free_sgpr 8
295; GFX9-NEXT:     .amdhsa_reserve_vcc 0
296; GFX9-NEXT:     .amdhsa_reserve_xnack_mask 1
297; GFX9-NEXT:     .amdhsa_float_round_mode_32 0
298; GFX9-NEXT:     .amdhsa_float_round_mode_16_64 0
299; GFX9-NEXT:     .amdhsa_float_denorm_mode_32 3
300; GFX9-NEXT:     .amdhsa_float_denorm_mode_16_64 3
301; GFX9-NEXT:     .amdhsa_dx10_clamp 1
302; GFX9-NEXT:     .amdhsa_ieee_mode 1
303; GFX9-NEXT:     .amdhsa_fp16_overflow 0
304; GFX9-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0
305; GFX9-NEXT:     .amdhsa_exception_fp_denorm_src 0
306; GFX9-NEXT:     .amdhsa_exception_fp_ieee_div_zero 0
307; GFX9-NEXT:     .amdhsa_exception_fp_ieee_overflow 0
308; GFX9-NEXT:     .amdhsa_exception_fp_ieee_underflow 0
309; GFX9-NEXT:     .amdhsa_exception_fp_ieee_inexact 0
310; GFX9-NEXT:     .amdhsa_exception_int_div_zero 0
311; GFX9-NEXT:    .end_amdhsa_kernel
312; GFX9-NEXT:    .text
313  %alloca.align = alloca i32, align 4, addrspace(5)
314  store volatile i32 9, i32 addrspace(5)* %alloca.align, align 4
315  ret void
316}
317
318attributes #0 = { nounwind }
319attributes #1 = { nounwind "stackrealign" }
320attributes #2 = { nounwind alignstack=128 }
321