1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck --check-prefix=GFX6 %s
3; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck --check-prefix=GFX8 %s
4; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s
5
6define i8 @v_ssubsat_i8(i8 %lhs, i8 %rhs) {
7; GFX6-LABEL: v_ssubsat_i8:
8; GFX6:       ; %bb.0:
9; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
10; GFX6-NEXT:    v_bfe_i32 v1, v1, 0, 8
11; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 8
12; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
13; GFX6-NEXT:    v_min_i32_e32 v0, 0x7f, v0
14; GFX6-NEXT:    v_max_i32_e32 v0, 0xffffff80, v0
15; GFX6-NEXT:    s_setpc_b64 s[30:31]
16;
17; GFX8-LABEL: v_ssubsat_i8:
18; GFX8:       ; %bb.0:
19; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
20; GFX8-NEXT:    v_sub_u16_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
21; GFX8-NEXT:    v_min_i16_e32 v0, 0x7f, v0
22; GFX8-NEXT:    v_max_i16_e32 v0, 0xff80, v0
23; GFX8-NEXT:    s_setpc_b64 s[30:31]
24;
25; GFX9-LABEL: v_ssubsat_i8:
26; GFX9:       ; %bb.0:
27; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
28; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v1
29; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 8, v0
30; GFX9-NEXT:    v_sub_i16 v0, v0, v1 clamp
31; GFX9-NEXT:    v_ashrrev_i16_e32 v0, 8, v0
32; GFX9-NEXT:    s_setpc_b64 s[30:31]
33  %result = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs)
34  ret i8 %result
35}
36
37define i16 @v_ssubsat_i16(i16 %lhs, i16 %rhs) {
38; GFX6-LABEL: v_ssubsat_i16:
39; GFX6:       ; %bb.0:
40; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
41; GFX6-NEXT:    v_bfe_i32 v1, v1, 0, 16
42; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 16
43; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
44; GFX6-NEXT:    v_min_i32_e32 v0, 0x7fff, v0
45; GFX6-NEXT:    v_max_i32_e32 v0, 0xffff8000, v0
46; GFX6-NEXT:    s_setpc_b64 s[30:31]
47;
48; GFX8-LABEL: v_ssubsat_i16:
49; GFX8:       ; %bb.0:
50; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
51; GFX8-NEXT:    v_cmp_lt_i16_e32 vcc, 0, v1
52; GFX8-NEXT:    v_sub_u16_e32 v1, v0, v1
53; GFX8-NEXT:    v_cmp_lt_i16_e64 s[4:5], v1, v0
54; GFX8-NEXT:    v_mov_b32_e32 v0, 0xffff8000
55; GFX8-NEXT:    v_mov_b32_e32 v2, 0x7fff
56; GFX8-NEXT:    v_cmp_gt_i16_e64 s[6:7], 0, v1
57; GFX8-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[6:7]
58; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
59; GFX8-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
60; GFX8-NEXT:    s_setpc_b64 s[30:31]
61;
62; GFX9-LABEL: v_ssubsat_i16:
63; GFX9:       ; %bb.0:
64; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
65; GFX9-NEXT:    v_sub_i16 v0, v0, v1 clamp
66; GFX9-NEXT:    s_setpc_b64 s[30:31]
67  %result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)
68  ret i16 %result
69}
70
71define i32 @v_ssubsat_i32(i32 %lhs, i32 %rhs) {
72; GFX6-LABEL: v_ssubsat_i32:
73; GFX6:       ; %bb.0:
74; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
75; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v1
76; GFX6-NEXT:    v_sub_i32_e64 v1, s[4:5], v0, v1
77; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v1, v0
78; GFX6-NEXT:    v_bfrev_b32_e32 v0, 1
79; GFX6-NEXT:    v_bfrev_b32_e32 v2, -2
80; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v1
81; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[6:7]
82; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
83; GFX6-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
84; GFX6-NEXT:    s_setpc_b64 s[30:31]
85;
86; GFX8-LABEL: v_ssubsat_i32:
87; GFX8:       ; %bb.0:
88; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
89; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v1
90; GFX8-NEXT:    v_sub_u32_e64 v1, s[4:5], v0, v1
91; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v1, v0
92; GFX8-NEXT:    v_bfrev_b32_e32 v0, 1
93; GFX8-NEXT:    v_bfrev_b32_e32 v2, -2
94; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v1
95; GFX8-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[6:7]
96; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
97; GFX8-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
98; GFX8-NEXT:    s_setpc_b64 s[30:31]
99;
100; GFX9-LABEL: v_ssubsat_i32:
101; GFX9:       ; %bb.0:
102; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
103; GFX9-NEXT:    v_sub_i32 v0, v0, v1 clamp
104; GFX9-NEXT:    s_setpc_b64 s[30:31]
105  %result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)
106  ret i32 %result
107}
108
109define <2 x i16> @v_ssubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
110; GFX6-LABEL: v_ssubsat_v2i16:
111; GFX6:       ; %bb.0:
112; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
113; GFX6-NEXT:    v_bfe_i32 v2, v2, 0, 16
114; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 16
115; GFX6-NEXT:    v_bfe_i32 v3, v3, 0, 16
116; GFX6-NEXT:    v_bfe_i32 v1, v1, 0, 16
117; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v3
118; GFX6-NEXT:    s_movk_i32 s4, 0x7fff
119; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
120; GFX6-NEXT:    v_min_i32_e32 v1, s4, v1
121; GFX6-NEXT:    s_movk_i32 s5, 0x8000
122; GFX6-NEXT:    v_min_i32_e32 v0, s4, v0
123; GFX6-NEXT:    v_max_i32_e32 v1, s5, v1
124; GFX6-NEXT:    v_max_i32_e32 v0, s5, v0
125; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
126; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v0
127; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
128; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
129; GFX6-NEXT:    s_setpc_b64 s[30:31]
130;
131; GFX8-LABEL: v_ssubsat_v2i16:
132; GFX8:       ; %bb.0:
133; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
134; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
135; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
136; GFX8-NEXT:    v_sub_u16_e32 v4, v3, v2
137; GFX8-NEXT:    v_mov_b32_e32 v5, 0xffff8000
138; GFX8-NEXT:    v_mov_b32_e32 v6, 0x7fff
139; GFX8-NEXT:    v_cmp_gt_i16_e32 vcc, 0, v4
140; GFX8-NEXT:    v_cndmask_b32_e32 v7, v5, v6, vcc
141; GFX8-NEXT:    v_cmp_lt_i16_e32 vcc, v4, v3
142; GFX8-NEXT:    v_cmp_lt_i16_e64 s[4:5], 0, v2
143; GFX8-NEXT:    s_xor_b64 vcc, s[4:5], vcc
144; GFX8-NEXT:    v_cndmask_b32_e32 v2, v4, v7, vcc
145; GFX8-NEXT:    v_cmp_lt_i16_e32 vcc, 0, v1
146; GFX8-NEXT:    v_sub_u16_e32 v1, v0, v1
147; GFX8-NEXT:    v_cmp_lt_i16_e64 s[4:5], v1, v0
148; GFX8-NEXT:    v_cmp_gt_i16_e64 s[6:7], 0, v1
149; GFX8-NEXT:    v_cndmask_b32_e64 v0, v5, v6, s[6:7]
150; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
151; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
152; GFX8-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
153; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
154; GFX8-NEXT:    s_setpc_b64 s[30:31]
155;
156; GFX9-LABEL: v_ssubsat_v2i16:
157; GFX9:       ; %bb.0:
158; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
159; GFX9-NEXT:    v_pk_sub_i16 v0, v0, v1 clamp
160; GFX9-NEXT:    s_setpc_b64 s[30:31]
161  %result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
162  ret <2 x i16> %result
163}
164
165define <3 x i16> @v_ssubsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) {
166; GFX6-LABEL: v_ssubsat_v3i16:
167; GFX6:       ; %bb.0:
168; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
169; GFX6-NEXT:    v_bfe_i32 v3, v3, 0, 16
170; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 16
171; GFX6-NEXT:    v_bfe_i32 v4, v4, 0, 16
172; GFX6-NEXT:    v_bfe_i32 v1, v1, 0, 16
173; GFX6-NEXT:    v_bfe_i32 v5, v5, 0, 16
174; GFX6-NEXT:    v_bfe_i32 v2, v2, 0, 16
175; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v4
176; GFX6-NEXT:    s_movk_i32 s4, 0x7fff
177; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v3
178; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v5
179; GFX6-NEXT:    v_min_i32_e32 v1, s4, v1
180; GFX6-NEXT:    s_movk_i32 s5, 0x8000
181; GFX6-NEXT:    v_min_i32_e32 v0, s4, v0
182; GFX6-NEXT:    v_max_i32_e32 v1, s5, v1
183; GFX6-NEXT:    v_min_i32_e32 v2, s4, v2
184; GFX6-NEXT:    v_max_i32_e32 v0, s5, v0
185; GFX6-NEXT:    s_mov_b32 s6, 0xffff
186; GFX6-NEXT:    v_max_i32_e32 v3, s5, v2
187; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
188; GFX6-NEXT:    v_and_b32_e32 v0, s6, v0
189; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
190; GFX6-NEXT:    v_and_b32_e32 v2, s6, v3
191; GFX6-NEXT:    v_alignbit_b32 v1, v3, v1, 16
192; GFX6-NEXT:    s_setpc_b64 s[30:31]
193;
194; GFX8-LABEL: v_ssubsat_v3i16:
195; GFX8:       ; %bb.0:
196; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
197; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
198; GFX8-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
199; GFX8-NEXT:    v_sub_u16_e32 v6, v5, v4
200; GFX8-NEXT:    v_mov_b32_e32 v7, 0xffff8000
201; GFX8-NEXT:    v_mov_b32_e32 v8, 0x7fff
202; GFX8-NEXT:    v_cmp_gt_i16_e32 vcc, 0, v6
203; GFX8-NEXT:    v_cndmask_b32_e32 v9, v7, v8, vcc
204; GFX8-NEXT:    v_cmp_lt_i16_e32 vcc, v6, v5
205; GFX8-NEXT:    v_cmp_lt_i16_e64 s[4:5], 0, v4
206; GFX8-NEXT:    s_xor_b64 vcc, s[4:5], vcc
207; GFX8-NEXT:    v_cndmask_b32_e32 v4, v6, v9, vcc
208; GFX8-NEXT:    v_cmp_lt_i16_e32 vcc, 0, v3
209; GFX8-NEXT:    v_sub_u16_e32 v3, v1, v3
210; GFX8-NEXT:    v_cmp_lt_i16_e64 s[4:5], v3, v1
211; GFX8-NEXT:    v_cmp_gt_i16_e64 s[6:7], 0, v3
212; GFX8-NEXT:    v_cndmask_b32_e64 v1, v7, v8, s[6:7]
213; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
214; GFX8-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
215; GFX8-NEXT:    v_cmp_lt_i16_e32 vcc, 0, v2
216; GFX8-NEXT:    v_sub_u16_e32 v2, v0, v2
217; GFX8-NEXT:    v_cmp_lt_i16_e64 s[4:5], v2, v0
218; GFX8-NEXT:    v_cmp_gt_i16_e64 s[6:7], 0, v2
219; GFX8-NEXT:    v_cndmask_b32_e64 v0, v7, v8, s[6:7]
220; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
221; GFX8-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
222; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v4
223; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
224; GFX8-NEXT:    s_setpc_b64 s[30:31]
225;
226; GFX9-LABEL: v_ssubsat_v3i16:
227; GFX9:       ; %bb.0:
228; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
229; GFX9-NEXT:    v_pk_sub_i16 v1, v1, v3 clamp
230; GFX9-NEXT:    v_pk_sub_i16 v0, v0, v2 clamp
231; GFX9-NEXT:    s_setpc_b64 s[30:31]
232  %result = call <3 x i16> @llvm.ssub.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)
233  ret <3 x i16> %result
234}
235
236define <2 x float> @v_ssubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
237; GFX6-LABEL: v_ssubsat_v4i16:
238; GFX6:       ; %bb.0:
239; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
240; GFX6-NEXT:    v_bfe_i32 v4, v4, 0, 16
241; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 16
242; GFX6-NEXT:    v_bfe_i32 v5, v5, 0, 16
243; GFX6-NEXT:    v_bfe_i32 v1, v1, 0, 16
244; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v5
245; GFX6-NEXT:    s_movk_i32 s4, 0x7fff
246; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
247; GFX6-NEXT:    v_min_i32_e32 v1, s4, v1
248; GFX6-NEXT:    s_movk_i32 s5, 0x8000
249; GFX6-NEXT:    v_min_i32_e32 v0, s4, v0
250; GFX6-NEXT:    v_max_i32_e32 v1, s5, v1
251; GFX6-NEXT:    v_max_i32_e32 v0, s5, v0
252; GFX6-NEXT:    s_mov_b32 s6, 0xffff
253; GFX6-NEXT:    v_bfe_i32 v6, v6, 0, 16
254; GFX6-NEXT:    v_bfe_i32 v2, v2, 0, 16
255; GFX6-NEXT:    v_bfe_i32 v7, v7, 0, 16
256; GFX6-NEXT:    v_bfe_i32 v3, v3, 0, 16
257; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
258; GFX6-NEXT:    v_and_b32_e32 v0, s6, v0
259; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
260; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
261; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v3, v7
262; GFX6-NEXT:    v_min_i32_e32 v1, s4, v1
263; GFX6-NEXT:    v_min_i32_e32 v2, s4, v2
264; GFX6-NEXT:    v_max_i32_e32 v1, s5, v1
265; GFX6-NEXT:    v_max_i32_e32 v2, s5, v2
266; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
267; GFX6-NEXT:    v_and_b32_e32 v2, s6, v2
268; GFX6-NEXT:    v_or_b32_e32 v1, v2, v1
269; GFX6-NEXT:    s_setpc_b64 s[30:31]
270;
271; GFX8-LABEL: v_ssubsat_v4i16:
272; GFX8:       ; %bb.0:
273; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
274; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
275; GFX8-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
276; GFX8-NEXT:    v_sub_u16_e32 v6, v5, v4
277; GFX8-NEXT:    v_mov_b32_e32 v7, 0xffff8000
278; GFX8-NEXT:    v_mov_b32_e32 v8, 0x7fff
279; GFX8-NEXT:    v_cmp_gt_i16_e32 vcc, 0, v6
280; GFX8-NEXT:    v_cndmask_b32_e32 v9, v7, v8, vcc
281; GFX8-NEXT:    v_cmp_lt_i16_e32 vcc, v6, v5
282; GFX8-NEXT:    v_cmp_lt_i16_e64 s[4:5], 0, v4
283; GFX8-NEXT:    s_xor_b64 vcc, s[4:5], vcc
284; GFX8-NEXT:    v_cndmask_b32_e32 v4, v6, v9, vcc
285; GFX8-NEXT:    v_cmp_lt_i16_e32 vcc, 0, v2
286; GFX8-NEXT:    v_sub_u16_e32 v2, v0, v2
287; GFX8-NEXT:    v_cmp_lt_i16_e64 s[4:5], v2, v0
288; GFX8-NEXT:    v_cmp_gt_i16_e64 s[6:7], 0, v2
289; GFX8-NEXT:    v_cndmask_b32_e64 v0, v7, v8, s[6:7]
290; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
291; GFX8-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
292; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
293; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
294; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
295; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
296; GFX8-NEXT:    v_sub_u16_e32 v5, v4, v2
297; GFX8-NEXT:    v_cmp_gt_i16_e32 vcc, 0, v5
298; GFX8-NEXT:    v_cndmask_b32_e32 v6, v7, v8, vcc
299; GFX8-NEXT:    v_cmp_lt_i16_e32 vcc, v5, v4
300; GFX8-NEXT:    v_cmp_lt_i16_e64 s[4:5], 0, v2
301; GFX8-NEXT:    s_xor_b64 vcc, s[4:5], vcc
302; GFX8-NEXT:    v_cndmask_b32_e32 v2, v5, v6, vcc
303; GFX8-NEXT:    v_cmp_lt_i16_e32 vcc, 0, v3
304; GFX8-NEXT:    v_sub_u16_e32 v3, v1, v3
305; GFX8-NEXT:    v_cmp_lt_i16_e64 s[4:5], v3, v1
306; GFX8-NEXT:    v_cmp_gt_i16_e64 s[6:7], 0, v3
307; GFX8-NEXT:    v_cndmask_b32_e64 v1, v7, v8, s[6:7]
308; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
309; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
310; GFX8-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
311; GFX8-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
312; GFX8-NEXT:    s_setpc_b64 s[30:31]
313;
314; GFX9-LABEL: v_ssubsat_v4i16:
315; GFX9:       ; %bb.0:
316; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
317; GFX9-NEXT:    v_pk_sub_i16 v0, v0, v2 clamp
318; GFX9-NEXT:    v_pk_sub_i16 v1, v1, v3 clamp
319; GFX9-NEXT:    s_setpc_b64 s[30:31]
320  %result = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
321  %cast = bitcast <4 x i16> %result to <2 x float>
322  ret <2 x float> %cast
323}
324
325define <2 x i32> @v_ssubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
326; GFX6-LABEL: v_ssubsat_v2i32:
327; GFX6:       ; %bb.0:
328; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
329; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v2
330; GFX6-NEXT:    v_sub_i32_e64 v2, s[4:5], v0, v2
331; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v2, v0
332; GFX6-NEXT:    v_bfrev_b32_e32 v4, 1
333; GFX6-NEXT:    v_bfrev_b32_e32 v5, -2
334; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v2
335; GFX6-NEXT:    v_cndmask_b32_e64 v0, v4, v5, s[6:7]
336; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
337; GFX6-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
338; GFX6-NEXT:    v_sub_i32_e64 v2, s[4:5], v1, v3
339; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v3
340; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v2, v1
341; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v2
342; GFX6-NEXT:    v_cndmask_b32_e64 v1, v4, v5, s[6:7]
343; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
344; GFX6-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
345; GFX6-NEXT:    s_setpc_b64 s[30:31]
346;
347; GFX8-LABEL: v_ssubsat_v2i32:
348; GFX8:       ; %bb.0:
349; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
350; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v2
351; GFX8-NEXT:    v_sub_u32_e64 v2, s[4:5], v0, v2
352; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v2, v0
353; GFX8-NEXT:    v_bfrev_b32_e32 v4, 1
354; GFX8-NEXT:    v_bfrev_b32_e32 v5, -2
355; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v2
356; GFX8-NEXT:    v_cndmask_b32_e64 v0, v4, v5, s[6:7]
357; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
358; GFX8-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
359; GFX8-NEXT:    v_sub_u32_e64 v2, s[4:5], v1, v3
360; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v3
361; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v2, v1
362; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v2
363; GFX8-NEXT:    v_cndmask_b32_e64 v1, v4, v5, s[6:7]
364; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
365; GFX8-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
366; GFX8-NEXT:    s_setpc_b64 s[30:31]
367;
368; GFX9-LABEL: v_ssubsat_v2i32:
369; GFX9:       ; %bb.0:
370; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
371; GFX9-NEXT:    v_sub_i32 v0, v0, v2 clamp
372; GFX9-NEXT:    v_sub_i32 v1, v1, v3 clamp
373; GFX9-NEXT:    s_setpc_b64 s[30:31]
374  %result = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
375  ret <2 x i32> %result
376}
377
378define <3 x i32> @v_ssubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
379; GFX6-LABEL: v_ssubsat_v3i32:
380; GFX6:       ; %bb.0:
381; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
382; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v3
383; GFX6-NEXT:    v_sub_i32_e64 v3, s[4:5], v0, v3
384; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v3, v0
385; GFX6-NEXT:    v_bfrev_b32_e32 v6, 1
386; GFX6-NEXT:    v_bfrev_b32_e32 v7, -2
387; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v3
388; GFX6-NEXT:    v_cndmask_b32_e64 v0, v6, v7, s[6:7]
389; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
390; GFX6-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc
391; GFX6-NEXT:    v_sub_i32_e64 v3, s[4:5], v1, v4
392; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v4
393; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v3, v1
394; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v3
395; GFX6-NEXT:    v_cndmask_b32_e64 v1, v6, v7, s[6:7]
396; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
397; GFX6-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
398; GFX6-NEXT:    v_sub_i32_e64 v3, s[4:5], v2, v5
399; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v5
400; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v3, v2
401; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v3
402; GFX6-NEXT:    v_cndmask_b32_e64 v2, v6, v7, s[6:7]
403; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
404; GFX6-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
405; GFX6-NEXT:    s_setpc_b64 s[30:31]
406;
407; GFX8-LABEL: v_ssubsat_v3i32:
408; GFX8:       ; %bb.0:
409; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
410; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v3
411; GFX8-NEXT:    v_sub_u32_e64 v3, s[4:5], v0, v3
412; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v3, v0
413; GFX8-NEXT:    v_bfrev_b32_e32 v6, 1
414; GFX8-NEXT:    v_bfrev_b32_e32 v7, -2
415; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v3
416; GFX8-NEXT:    v_cndmask_b32_e64 v0, v6, v7, s[6:7]
417; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
418; GFX8-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc
419; GFX8-NEXT:    v_sub_u32_e64 v3, s[4:5], v1, v4
420; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v4
421; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v3, v1
422; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v3
423; GFX8-NEXT:    v_cndmask_b32_e64 v1, v6, v7, s[6:7]
424; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
425; GFX8-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
426; GFX8-NEXT:    v_sub_u32_e64 v3, s[4:5], v2, v5
427; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v5
428; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v3, v2
429; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v3
430; GFX8-NEXT:    v_cndmask_b32_e64 v2, v6, v7, s[6:7]
431; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
432; GFX8-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
433; GFX8-NEXT:    s_setpc_b64 s[30:31]
434;
435; GFX9-LABEL: v_ssubsat_v3i32:
436; GFX9:       ; %bb.0:
437; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
438; GFX9-NEXT:    v_sub_i32 v0, v0, v3 clamp
439; GFX9-NEXT:    v_sub_i32 v1, v1, v4 clamp
440; GFX9-NEXT:    v_sub_i32 v2, v2, v5 clamp
441; GFX9-NEXT:    s_setpc_b64 s[30:31]
442  %result = call <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
443  ret <3 x i32> %result
444}
445
446define <4 x i32> @v_ssubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
447; GFX6-LABEL: v_ssubsat_v4i32:
448; GFX6:       ; %bb.0:
449; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
450; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v4
451; GFX6-NEXT:    v_sub_i32_e64 v4, s[4:5], v0, v4
452; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v4, v0
453; GFX6-NEXT:    v_bfrev_b32_e32 v8, 1
454; GFX6-NEXT:    v_bfrev_b32_e32 v9, -2
455; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v4
456; GFX6-NEXT:    v_cndmask_b32_e64 v0, v8, v9, s[6:7]
457; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
458; GFX6-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
459; GFX6-NEXT:    v_sub_i32_e64 v4, s[4:5], v1, v5
460; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v5
461; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v4, v1
462; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v4
463; GFX6-NEXT:    v_cndmask_b32_e64 v1, v8, v9, s[6:7]
464; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
465; GFX6-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
466; GFX6-NEXT:    v_sub_i32_e64 v4, s[4:5], v2, v6
467; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v6
468; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v4, v2
469; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v4
470; GFX6-NEXT:    v_cndmask_b32_e64 v2, v8, v9, s[6:7]
471; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
472; GFX6-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
473; GFX6-NEXT:    v_sub_i32_e64 v4, s[4:5], v3, v7
474; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v7
475; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v4, v3
476; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v4
477; GFX6-NEXT:    v_cndmask_b32_e64 v3, v8, v9, s[6:7]
478; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
479; GFX6-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
480; GFX6-NEXT:    s_setpc_b64 s[30:31]
481;
482; GFX8-LABEL: v_ssubsat_v4i32:
483; GFX8:       ; %bb.0:
484; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
485; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v4
486; GFX8-NEXT:    v_sub_u32_e64 v4, s[4:5], v0, v4
487; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v4, v0
488; GFX8-NEXT:    v_bfrev_b32_e32 v8, 1
489; GFX8-NEXT:    v_bfrev_b32_e32 v9, -2
490; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v4
491; GFX8-NEXT:    v_cndmask_b32_e64 v0, v8, v9, s[6:7]
492; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
493; GFX8-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
494; GFX8-NEXT:    v_sub_u32_e64 v4, s[4:5], v1, v5
495; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v5
496; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v4, v1
497; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v4
498; GFX8-NEXT:    v_cndmask_b32_e64 v1, v8, v9, s[6:7]
499; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
500; GFX8-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
501; GFX8-NEXT:    v_sub_u32_e64 v4, s[4:5], v2, v6
502; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v6
503; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v4, v2
504; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v4
505; GFX8-NEXT:    v_cndmask_b32_e64 v2, v8, v9, s[6:7]
506; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
507; GFX8-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
508; GFX8-NEXT:    v_sub_u32_e64 v4, s[4:5], v3, v7
509; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v7
510; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v4, v3
511; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v4
512; GFX8-NEXT:    v_cndmask_b32_e64 v3, v8, v9, s[6:7]
513; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
514; GFX8-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
515; GFX8-NEXT:    s_setpc_b64 s[30:31]
516;
517; GFX9-LABEL: v_ssubsat_v4i32:
518; GFX9:       ; %bb.0:
519; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
520; GFX9-NEXT:    v_sub_i32 v0, v0, v4 clamp
521; GFX9-NEXT:    v_sub_i32 v1, v1, v5 clamp
522; GFX9-NEXT:    v_sub_i32 v2, v2, v6 clamp
523; GFX9-NEXT:    v_sub_i32 v3, v3, v7 clamp
524; GFX9-NEXT:    s_setpc_b64 s[30:31]
525  %result = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
526  ret <4 x i32> %result
527}
528
529define <8 x i32> @v_ssubsat_v8i32(<8 x i32> %lhs, <8 x i32> %rhs) {
530; GFX6-LABEL: v_ssubsat_v8i32:
531; GFX6:       ; %bb.0:
532; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
533; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v8
534; GFX6-NEXT:    v_sub_i32_e64 v8, s[4:5], v0, v8
535; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v8, v0
536; GFX6-NEXT:    v_bfrev_b32_e32 v16, 1
537; GFX6-NEXT:    v_bfrev_b32_e32 v17, -2
538; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v8
539; GFX6-NEXT:    v_cndmask_b32_e64 v0, v16, v17, s[6:7]
540; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
541; GFX6-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
542; GFX6-NEXT:    v_sub_i32_e64 v8, s[4:5], v1, v9
543; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v9
544; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v8, v1
545; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v8
546; GFX6-NEXT:    v_cndmask_b32_e64 v1, v16, v17, s[6:7]
547; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
548; GFX6-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
549; GFX6-NEXT:    v_sub_i32_e64 v8, s[4:5], v2, v10
550; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v10
551; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v8, v2
552; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v8
553; GFX6-NEXT:    v_cndmask_b32_e64 v2, v16, v17, s[6:7]
554; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
555; GFX6-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc
556; GFX6-NEXT:    v_sub_i32_e64 v8, s[4:5], v3, v11
557; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v11
558; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v8, v3
559; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v8
560; GFX6-NEXT:    v_cndmask_b32_e64 v3, v16, v17, s[6:7]
561; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
562; GFX6-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
563; GFX6-NEXT:    v_sub_i32_e64 v8, s[4:5], v4, v12
564; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v12
565; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v8, v4
566; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v8
567; GFX6-NEXT:    v_cndmask_b32_e64 v4, v16, v17, s[6:7]
568; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
569; GFX6-NEXT:    v_cndmask_b32_e32 v4, v8, v4, vcc
570; GFX6-NEXT:    v_sub_i32_e64 v8, s[4:5], v5, v13
571; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v13
572; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v8, v5
573; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v8
574; GFX6-NEXT:    v_cndmask_b32_e64 v5, v16, v17, s[6:7]
575; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
576; GFX6-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc
577; GFX6-NEXT:    v_sub_i32_e64 v8, s[4:5], v6, v14
578; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v14
579; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v8, v6
580; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v8
581; GFX6-NEXT:    v_cndmask_b32_e64 v6, v16, v17, s[6:7]
582; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
583; GFX6-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc
584; GFX6-NEXT:    v_sub_i32_e64 v8, s[4:5], v7, v15
585; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v15
586; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v8, v7
587; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v8
588; GFX6-NEXT:    v_cndmask_b32_e64 v7, v16, v17, s[6:7]
589; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
590; GFX6-NEXT:    v_cndmask_b32_e32 v7, v8, v7, vcc
591; GFX6-NEXT:    s_setpc_b64 s[30:31]
592;
593; GFX8-LABEL: v_ssubsat_v8i32:
594; GFX8:       ; %bb.0:
595; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
596; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v8
597; GFX8-NEXT:    v_sub_u32_e64 v8, s[4:5], v0, v8
598; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v8, v0
599; GFX8-NEXT:    v_bfrev_b32_e32 v16, 1
600; GFX8-NEXT:    v_bfrev_b32_e32 v17, -2
601; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v8
602; GFX8-NEXT:    v_cndmask_b32_e64 v0, v16, v17, s[6:7]
603; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
604; GFX8-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
605; GFX8-NEXT:    v_sub_u32_e64 v8, s[4:5], v1, v9
606; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v9
607; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v8, v1
608; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v8
609; GFX8-NEXT:    v_cndmask_b32_e64 v1, v16, v17, s[6:7]
610; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
611; GFX8-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
612; GFX8-NEXT:    v_sub_u32_e64 v8, s[4:5], v2, v10
613; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v10
614; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v8, v2
615; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v8
616; GFX8-NEXT:    v_cndmask_b32_e64 v2, v16, v17, s[6:7]
617; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
618; GFX8-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc
619; GFX8-NEXT:    v_sub_u32_e64 v8, s[4:5], v3, v11
620; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v11
621; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v8, v3
622; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v8
623; GFX8-NEXT:    v_cndmask_b32_e64 v3, v16, v17, s[6:7]
624; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
625; GFX8-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
626; GFX8-NEXT:    v_sub_u32_e64 v8, s[4:5], v4, v12
627; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v12
628; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v8, v4
629; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v8
630; GFX8-NEXT:    v_cndmask_b32_e64 v4, v16, v17, s[6:7]
631; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
632; GFX8-NEXT:    v_cndmask_b32_e32 v4, v8, v4, vcc
633; GFX8-NEXT:    v_sub_u32_e64 v8, s[4:5], v5, v13
634; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v13
635; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v8, v5
636; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v8
637; GFX8-NEXT:    v_cndmask_b32_e64 v5, v16, v17, s[6:7]
638; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
639; GFX8-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc
640; GFX8-NEXT:    v_sub_u32_e64 v8, s[4:5], v6, v14
641; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v14
642; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v8, v6
643; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v8
644; GFX8-NEXT:    v_cndmask_b32_e64 v6, v16, v17, s[6:7]
645; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
646; GFX8-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc
647; GFX8-NEXT:    v_sub_u32_e64 v8, s[4:5], v7, v15
648; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v15
649; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v8, v7
650; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v8
651; GFX8-NEXT:    v_cndmask_b32_e64 v7, v16, v17, s[6:7]
652; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
653; GFX8-NEXT:    v_cndmask_b32_e32 v7, v8, v7, vcc
654; GFX8-NEXT:    s_setpc_b64 s[30:31]
655;
656; GFX9-LABEL: v_ssubsat_v8i32:
657; GFX9:       ; %bb.0:
658; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
659; GFX9-NEXT:    v_sub_i32 v0, v0, v8 clamp
660; GFX9-NEXT:    v_sub_i32 v1, v1, v9 clamp
661; GFX9-NEXT:    v_sub_i32 v2, v2, v10 clamp
662; GFX9-NEXT:    v_sub_i32 v3, v3, v11 clamp
663; GFX9-NEXT:    v_sub_i32 v4, v4, v12 clamp
664; GFX9-NEXT:    v_sub_i32 v5, v5, v13 clamp
665; GFX9-NEXT:    v_sub_i32 v6, v6, v14 clamp
666; GFX9-NEXT:    v_sub_i32 v7, v7, v15 clamp
667; GFX9-NEXT:    s_setpc_b64 s[30:31]
668  %result = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> %lhs, <8 x i32> %rhs)
669  ret <8 x i32> %result
670}
671
672define <16 x i32> @v_ssubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
673; GFX6-LABEL: v_ssubsat_v16i32:
674; GFX6:       ; %bb.0:
675; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
676; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v16
677; GFX6-NEXT:    v_sub_i32_e64 v16, s[4:5], v0, v16
678; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v0
679; GFX6-NEXT:    v_bfrev_b32_e32 v32, 1
680; GFX6-NEXT:    v_bfrev_b32_e32 v33, -2
681; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
682; GFX6-NEXT:    v_cndmask_b32_e64 v0, v32, v33, s[6:7]
683; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
684; GFX6-NEXT:    v_cndmask_b32_e32 v0, v16, v0, vcc
685; GFX6-NEXT:    v_sub_i32_e64 v16, s[4:5], v1, v17
686; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v17
687; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v1
688; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
689; GFX6-NEXT:    v_cndmask_b32_e64 v1, v32, v33, s[6:7]
690; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
691; GFX6-NEXT:    v_cndmask_b32_e32 v1, v16, v1, vcc
692; GFX6-NEXT:    v_sub_i32_e64 v16, s[4:5], v2, v18
693; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v18
694; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v2
695; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
696; GFX6-NEXT:    v_cndmask_b32_e64 v2, v32, v33, s[6:7]
697; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
698; GFX6-NEXT:    v_cndmask_b32_e32 v2, v16, v2, vcc
699; GFX6-NEXT:    v_sub_i32_e64 v16, s[4:5], v3, v19
700; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v19
701; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v3
702; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
703; GFX6-NEXT:    v_cndmask_b32_e64 v3, v32, v33, s[6:7]
704; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
705; GFX6-NEXT:    v_cndmask_b32_e32 v3, v16, v3, vcc
706; GFX6-NEXT:    v_sub_i32_e64 v16, s[4:5], v4, v20
707; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v20
708; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v4
709; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
710; GFX6-NEXT:    v_cndmask_b32_e64 v4, v32, v33, s[6:7]
711; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
712; GFX6-NEXT:    v_cndmask_b32_e32 v4, v16, v4, vcc
713; GFX6-NEXT:    v_sub_i32_e64 v16, s[4:5], v5, v21
714; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v21
715; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v5
716; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
717; GFX6-NEXT:    v_cndmask_b32_e64 v5, v32, v33, s[6:7]
718; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
719; GFX6-NEXT:    v_cndmask_b32_e32 v5, v16, v5, vcc
720; GFX6-NEXT:    v_sub_i32_e64 v16, s[4:5], v6, v22
721; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v22
722; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v6
723; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
724; GFX6-NEXT:    v_cndmask_b32_e64 v6, v32, v33, s[6:7]
725; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
726; GFX6-NEXT:    v_cndmask_b32_e32 v6, v16, v6, vcc
727; GFX6-NEXT:    v_sub_i32_e64 v16, s[4:5], v7, v23
728; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v23
729; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v7
730; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
731; GFX6-NEXT:    v_cndmask_b32_e64 v7, v32, v33, s[6:7]
732; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
733; GFX6-NEXT:    v_cndmask_b32_e32 v7, v16, v7, vcc
734; GFX6-NEXT:    v_sub_i32_e64 v16, s[4:5], v8, v24
735; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v24
736; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v8
737; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
738; GFX6-NEXT:    v_cndmask_b32_e64 v8, v32, v33, s[6:7]
739; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
740; GFX6-NEXT:    v_cndmask_b32_e32 v8, v16, v8, vcc
741; GFX6-NEXT:    v_sub_i32_e64 v16, s[4:5], v9, v25
742; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v25
743; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v9
744; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
745; GFX6-NEXT:    v_cndmask_b32_e64 v9, v32, v33, s[6:7]
746; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
747; GFX6-NEXT:    v_cndmask_b32_e32 v9, v16, v9, vcc
748; GFX6-NEXT:    v_sub_i32_e64 v16, s[4:5], v10, v26
749; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v26
750; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v10
751; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
752; GFX6-NEXT:    v_cndmask_b32_e64 v10, v32, v33, s[6:7]
753; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
754; GFX6-NEXT:    v_cndmask_b32_e32 v10, v16, v10, vcc
755; GFX6-NEXT:    v_sub_i32_e64 v16, s[4:5], v11, v27
756; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v27
757; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v11
758; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
759; GFX6-NEXT:    v_cndmask_b32_e64 v11, v32, v33, s[6:7]
760; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
761; GFX6-NEXT:    v_cndmask_b32_e32 v11, v16, v11, vcc
762; GFX6-NEXT:    v_sub_i32_e64 v16, s[4:5], v12, v28
763; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v28
764; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v12
765; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
766; GFX6-NEXT:    v_cndmask_b32_e64 v12, v32, v33, s[6:7]
767; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
768; GFX6-NEXT:    v_cndmask_b32_e32 v12, v16, v12, vcc
769; GFX6-NEXT:    v_sub_i32_e64 v16, s[4:5], v13, v29
770; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v29
771; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v13
772; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
773; GFX6-NEXT:    v_cndmask_b32_e64 v13, v32, v33, s[6:7]
774; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
775; GFX6-NEXT:    v_cndmask_b32_e32 v13, v16, v13, vcc
776; GFX6-NEXT:    v_sub_i32_e64 v16, s[4:5], v14, v30
777; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v30
778; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v14
779; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
780; GFX6-NEXT:    v_cndmask_b32_e64 v14, v32, v33, s[6:7]
781; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
782; GFX6-NEXT:    v_cndmask_b32_e32 v14, v16, v14, vcc
783; GFX6-NEXT:    v_sub_i32_e64 v16, s[4:5], v15, v31
784; GFX6-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v31
785; GFX6-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v15
786; GFX6-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
787; GFX6-NEXT:    v_cndmask_b32_e64 v15, v32, v33, s[6:7]
788; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
789; GFX6-NEXT:    v_cndmask_b32_e32 v15, v16, v15, vcc
790; GFX6-NEXT:    s_setpc_b64 s[30:31]
791;
792; GFX8-LABEL: v_ssubsat_v16i32:
793; GFX8:       ; %bb.0:
794; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
795; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v16
796; GFX8-NEXT:    v_sub_u32_e64 v16, s[4:5], v0, v16
797; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v0
798; GFX8-NEXT:    v_bfrev_b32_e32 v32, 1
799; GFX8-NEXT:    v_bfrev_b32_e32 v33, -2
800; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
801; GFX8-NEXT:    v_cndmask_b32_e64 v0, v32, v33, s[6:7]
802; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
803; GFX8-NEXT:    v_cndmask_b32_e32 v0, v16, v0, vcc
804; GFX8-NEXT:    v_sub_u32_e64 v16, s[4:5], v1, v17
805; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v17
806; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v1
807; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
808; GFX8-NEXT:    v_cndmask_b32_e64 v1, v32, v33, s[6:7]
809; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
810; GFX8-NEXT:    v_cndmask_b32_e32 v1, v16, v1, vcc
811; GFX8-NEXT:    v_sub_u32_e64 v16, s[4:5], v2, v18
812; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v18
813; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v2
814; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
815; GFX8-NEXT:    v_cndmask_b32_e64 v2, v32, v33, s[6:7]
816; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
817; GFX8-NEXT:    v_cndmask_b32_e32 v2, v16, v2, vcc
818; GFX8-NEXT:    v_sub_u32_e64 v16, s[4:5], v3, v19
819; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v19
820; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v3
821; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
822; GFX8-NEXT:    v_cndmask_b32_e64 v3, v32, v33, s[6:7]
823; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
824; GFX8-NEXT:    v_cndmask_b32_e32 v3, v16, v3, vcc
825; GFX8-NEXT:    v_sub_u32_e64 v16, s[4:5], v4, v20
826; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v20
827; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v4
828; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
829; GFX8-NEXT:    v_cndmask_b32_e64 v4, v32, v33, s[6:7]
830; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
831; GFX8-NEXT:    v_cndmask_b32_e32 v4, v16, v4, vcc
832; GFX8-NEXT:    v_sub_u32_e64 v16, s[4:5], v5, v21
833; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v21
834; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v5
835; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
836; GFX8-NEXT:    v_cndmask_b32_e64 v5, v32, v33, s[6:7]
837; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
838; GFX8-NEXT:    v_cndmask_b32_e32 v5, v16, v5, vcc
839; GFX8-NEXT:    v_sub_u32_e64 v16, s[4:5], v6, v22
840; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v22
841; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v6
842; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
843; GFX8-NEXT:    v_cndmask_b32_e64 v6, v32, v33, s[6:7]
844; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
845; GFX8-NEXT:    v_cndmask_b32_e32 v6, v16, v6, vcc
846; GFX8-NEXT:    v_sub_u32_e64 v16, s[4:5], v7, v23
847; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v23
848; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v7
849; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
850; GFX8-NEXT:    v_cndmask_b32_e64 v7, v32, v33, s[6:7]
851; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
852; GFX8-NEXT:    v_cndmask_b32_e32 v7, v16, v7, vcc
853; GFX8-NEXT:    v_sub_u32_e64 v16, s[4:5], v8, v24
854; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v24
855; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v8
856; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
857; GFX8-NEXT:    v_cndmask_b32_e64 v8, v32, v33, s[6:7]
858; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
859; GFX8-NEXT:    v_cndmask_b32_e32 v8, v16, v8, vcc
860; GFX8-NEXT:    v_sub_u32_e64 v16, s[4:5], v9, v25
861; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v25
862; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v9
863; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
864; GFX8-NEXT:    v_cndmask_b32_e64 v9, v32, v33, s[6:7]
865; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
866; GFX8-NEXT:    v_cndmask_b32_e32 v9, v16, v9, vcc
867; GFX8-NEXT:    v_sub_u32_e64 v16, s[4:5], v10, v26
868; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v26
869; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v10
870; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
871; GFX8-NEXT:    v_cndmask_b32_e64 v10, v32, v33, s[6:7]
872; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
873; GFX8-NEXT:    v_cndmask_b32_e32 v10, v16, v10, vcc
874; GFX8-NEXT:    v_sub_u32_e64 v16, s[4:5], v11, v27
875; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v27
876; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v11
877; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
878; GFX8-NEXT:    v_cndmask_b32_e64 v11, v32, v33, s[6:7]
879; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
880; GFX8-NEXT:    v_cndmask_b32_e32 v11, v16, v11, vcc
881; GFX8-NEXT:    v_sub_u32_e64 v16, s[4:5], v12, v28
882; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v28
883; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v12
884; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
885; GFX8-NEXT:    v_cndmask_b32_e64 v12, v32, v33, s[6:7]
886; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
887; GFX8-NEXT:    v_cndmask_b32_e32 v12, v16, v12, vcc
888; GFX8-NEXT:    v_sub_u32_e64 v16, s[4:5], v13, v29
889; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v29
890; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v13
891; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
892; GFX8-NEXT:    v_cndmask_b32_e64 v13, v32, v33, s[6:7]
893; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
894; GFX8-NEXT:    v_cndmask_b32_e32 v13, v16, v13, vcc
895; GFX8-NEXT:    v_sub_u32_e64 v16, s[4:5], v14, v30
896; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v30
897; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v14
898; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
899; GFX8-NEXT:    v_cndmask_b32_e64 v14, v32, v33, s[6:7]
900; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
901; GFX8-NEXT:    v_cndmask_b32_e32 v14, v16, v14, vcc
902; GFX8-NEXT:    v_sub_u32_e64 v16, s[4:5], v15, v31
903; GFX8-NEXT:    v_cmp_lt_i32_e32 vcc, 0, v31
904; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v16, v15
905; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v16
906; GFX8-NEXT:    v_cndmask_b32_e64 v15, v32, v33, s[6:7]
907; GFX8-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
908; GFX8-NEXT:    v_cndmask_b32_e32 v15, v16, v15, vcc
909; GFX8-NEXT:    s_setpc_b64 s[30:31]
910;
911; GFX9-LABEL: v_ssubsat_v16i32:
912; GFX9:       ; %bb.0:
913; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
914; GFX9-NEXT:    v_sub_i32 v0, v0, v16 clamp
915; GFX9-NEXT:    v_sub_i32 v1, v1, v17 clamp
916; GFX9-NEXT:    v_sub_i32 v2, v2, v18 clamp
917; GFX9-NEXT:    v_sub_i32 v3, v3, v19 clamp
918; GFX9-NEXT:    v_sub_i32 v4, v4, v20 clamp
919; GFX9-NEXT:    v_sub_i32 v5, v5, v21 clamp
920; GFX9-NEXT:    v_sub_i32 v6, v6, v22 clamp
921; GFX9-NEXT:    v_sub_i32 v7, v7, v23 clamp
922; GFX9-NEXT:    v_sub_i32 v8, v8, v24 clamp
923; GFX9-NEXT:    v_sub_i32 v9, v9, v25 clamp
924; GFX9-NEXT:    v_sub_i32 v10, v10, v26 clamp
925; GFX9-NEXT:    v_sub_i32 v11, v11, v27 clamp
926; GFX9-NEXT:    v_sub_i32 v12, v12, v28 clamp
927; GFX9-NEXT:    v_sub_i32 v13, v13, v29 clamp
928; GFX9-NEXT:    v_sub_i32 v14, v14, v30 clamp
929; GFX9-NEXT:    v_sub_i32 v15, v15, v31 clamp
930; GFX9-NEXT:    s_setpc_b64 s[30:31]
931  %result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
932  ret <16 x i32> %result
933}
934
935
936define i64 @v_ssubsat_i64(i64 %lhs, i64 %rhs) {
937; GFX6-LABEL: v_ssubsat_i64:
938; GFX6:       ; %bb.0:
939; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
940; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, v0, v2
941; GFX6-NEXT:    v_subb_u32_e32 v5, vcc, v1, v3, vcc
942; GFX6-NEXT:    v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]
943; GFX6-NEXT:    v_cmp_lt_i64_e64 s[4:5], 0, v[2:3]
944; GFX6-NEXT:    v_bfrev_b32_e32 v1, 1
945; GFX6-NEXT:    s_xor_b64 vcc, s[4:5], vcc
946; GFX6-NEXT:    v_cmp_gt_i64_e64 s[4:5], 0, v[4:5]
947; GFX6-NEXT:    v_bfrev_b32_e32 v2, -2
948; GFX6-NEXT:    v_ashrrev_i32_e32 v0, 31, v5
949; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v2, s[4:5]
950; GFX6-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
951; GFX6-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
952; GFX6-NEXT:    s_setpc_b64 s[30:31]
953;
954; GFX8-LABEL: v_ssubsat_i64:
955; GFX8:       ; %bb.0:
956; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
957; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, v0, v2
958; GFX8-NEXT:    v_subb_u32_e32 v5, vcc, v1, v3, vcc
959; GFX8-NEXT:    v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]
960; GFX8-NEXT:    v_cmp_lt_i64_e64 s[4:5], 0, v[2:3]
961; GFX8-NEXT:    v_bfrev_b32_e32 v1, 1
962; GFX8-NEXT:    s_xor_b64 vcc, s[4:5], vcc
963; GFX8-NEXT:    v_cmp_gt_i64_e64 s[4:5], 0, v[4:5]
964; GFX8-NEXT:    v_bfrev_b32_e32 v2, -2
965; GFX8-NEXT:    v_ashrrev_i32_e32 v0, 31, v5
966; GFX8-NEXT:    v_cndmask_b32_e64 v1, v1, v2, s[4:5]
967; GFX8-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
968; GFX8-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
969; GFX8-NEXT:    s_setpc_b64 s[30:31]
970;
971; GFX9-LABEL: v_ssubsat_i64:
972; GFX9:       ; %bb.0:
973; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
974; GFX9-NEXT:    v_sub_co_u32_e32 v4, vcc, v0, v2
975; GFX9-NEXT:    v_subb_co_u32_e32 v5, vcc, v1, v3, vcc
976; GFX9-NEXT:    v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]
977; GFX9-NEXT:    v_cmp_lt_i64_e64 s[4:5], 0, v[2:3]
978; GFX9-NEXT:    v_bfrev_b32_e32 v1, 1
979; GFX9-NEXT:    s_xor_b64 vcc, s[4:5], vcc
980; GFX9-NEXT:    v_cmp_gt_i64_e64 s[4:5], 0, v[4:5]
981; GFX9-NEXT:    v_bfrev_b32_e32 v2, -2
982; GFX9-NEXT:    v_ashrrev_i32_e32 v0, 31, v5
983; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, v2, s[4:5]
984; GFX9-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
985; GFX9-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
986; GFX9-NEXT:    s_setpc_b64 s[30:31]
987  %result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
988  ret i64 %result
989}
990
991declare i8 @llvm.ssub.sat.i8(i8, i8) #0
992declare i16 @llvm.ssub.sat.i16(i16, i16) #0
993declare <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16>, <2 x i16>) #0
994declare <3 x i16> @llvm.ssub.sat.v3i16(<3 x i16>, <3 x i16>) #0
995declare <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16>, <4 x i16>) #0
996declare i32 @llvm.ssub.sat.i32(i32, i32) #0
997declare <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32>, <2 x i32>) #0
998declare <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32>, <3 x i32>) #0
999declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>) #0
1000declare <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32>, <8 x i32>) #0
1001declare <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32>, <16 x i32>) #0
1002declare i64 @llvm.ssub.sat.i64(i64, i64) #0
1003
1004attributes #0 = { nounwind readnone speculatable willreturn }
1005