1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck --check-prefix=GFX6 %s 3; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck --check-prefix=GFX8 %s 4; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s 5; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s 6 7define i8 @v_ssubsat_i8(i8 %lhs, i8 %rhs) { 8; GFX6-LABEL: v_ssubsat_i8: 9; GFX6: ; %bb.0: 10; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 11; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 8 12; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8 13; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 14; GFX6-NEXT: v_min_i32_e32 v0, 0x7f, v0 15; GFX6-NEXT: v_max_i32_e32 v0, 0xffffff80, v0 16; GFX6-NEXT: s_setpc_b64 s[30:31] 17; 18; GFX8-LABEL: v_ssubsat_i8: 19; GFX8: ; %bb.0: 20; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 21; GFX8-NEXT: v_sub_u16_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 22; GFX8-NEXT: v_min_i16_e32 v0, 0x7f, v0 23; GFX8-NEXT: v_max_i16_e32 v0, 0xff80, v0 24; GFX8-NEXT: s_setpc_b64 s[30:31] 25; 26; GFX9-LABEL: v_ssubsat_i8: 27; GFX9: ; %bb.0: 28; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 29; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1 30; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 31; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp 32; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0 33; GFX9-NEXT: s_setpc_b64 s[30:31] 34; 35; GFX10-LABEL: v_ssubsat_i8: 36; GFX10: ; %bb.0: 37; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 38; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 39; GFX10-NEXT: v_lshlrev_b16 v1, 8, v1 40; GFX10-NEXT: v_lshlrev_b16 v0, 8, v0 41; GFX10-NEXT: v_sub_nc_i16 v0, v0, v1 clamp 42; GFX10-NEXT: v_ashrrev_i16 v0, 8, v0 43; GFX10-NEXT: s_setpc_b64 s[30:31] 44 %result = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs) 45 ret i8 %result 46} 47 48define i16 @v_ssubsat_i16(i16 %lhs, i16 %rhs) { 49; GFX6-LABEL: v_ssubsat_i16: 50; GFX6: ; %bb.0: 51; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 52; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 53; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 54; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 55; GFX6-NEXT: v_min_i32_e32 v0, 0x7fff, v0 56; GFX6-NEXT: v_max_i32_e32 v0, 0xffff8000, v0 57; GFX6-NEXT: s_setpc_b64 s[30:31] 58; 59; GFX8-LABEL: v_ssubsat_i16: 60; GFX8: ; %bb.0: 61; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 62; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v1 63; GFX8-NEXT: v_sub_u16_e32 v1, v0, v1 64; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v1, v0 65; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v1 66; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0 67; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 68; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 69; GFX8-NEXT: s_setpc_b64 s[30:31] 70; 71; GFX9-LABEL: v_ssubsat_i16: 72; GFX9: ; %bb.0: 73; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 74; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp 75; GFX9-NEXT: s_setpc_b64 s[30:31] 76; 77; GFX10-LABEL: v_ssubsat_i16: 78; GFX10: ; %bb.0: 79; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 80; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 81; GFX10-NEXT: v_sub_nc_i16 v0, v0, v1 clamp 82; GFX10-NEXT: s_setpc_b64 s[30:31] 83 %result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs) 84 ret i16 %result 85} 86 87define i32 @v_ssubsat_i32(i32 %lhs, i32 %rhs) { 88; GFX6-LABEL: v_ssubsat_i32: 89; GFX6: ; %bb.0: 90; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 91; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v1 92; GFX6-NEXT: v_sub_i32_e64 v1, s[4:5], v0, v1 93; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v1, v0 94; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v1 95; GFX6-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 96; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 97; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 98; GFX6-NEXT: s_setpc_b64 s[30:31] 99; 100; GFX8-LABEL: v_ssubsat_i32: 101; GFX8: ; %bb.0: 102; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 103; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v1 104; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v0, v1 105; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v1, v0 106; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v1 107; GFX8-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 108; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 109; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 110; GFX8-NEXT: s_setpc_b64 s[30:31] 111; 112; GFX9-LABEL: v_ssubsat_i32: 113; GFX9: ; %bb.0: 114; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 115; GFX9-NEXT: v_sub_i32 v0, v0, v1 clamp 116; GFX9-NEXT: s_setpc_b64 s[30:31] 117; 118; GFX10-LABEL: v_ssubsat_i32: 119; GFX10: ; %bb.0: 120; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 121; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 122; GFX10-NEXT: v_sub_nc_i32 v0, v0, v1 clamp 123; GFX10-NEXT: s_setpc_b64 s[30:31] 124 %result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs) 125 ret i32 %result 126} 127 128define <2 x i16> @v_ssubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) { 129; GFX6-LABEL: v_ssubsat_v2i16: 130; GFX6: ; %bb.0: 131; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 132; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16 133; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 134; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16 135; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 136; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v3 137; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 138; GFX6-NEXT: v_min_i32_e32 v1, 0x7fff, v1 139; GFX6-NEXT: v_min_i32_e32 v0, 0x7fff, v0 140; GFX6-NEXT: v_max_i32_e32 v1, 0xffff8000, v1 141; GFX6-NEXT: v_max_i32_e32 v0, 0xffff8000, v0 142; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 143; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 144; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 145; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0 146; GFX6-NEXT: s_setpc_b64 s[30:31] 147; 148; GFX8-LABEL: v_ssubsat_v2i16: 149; GFX8: ; %bb.0: 150; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 151; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v1 152; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0 153; GFX8-NEXT: v_sub_u16_e32 v4, v3, v2 154; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v4, v3 155; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], 0, v2 156; GFX8-NEXT: v_ashrrev_i16_e32 v2, 15, v4 157; GFX8-NEXT: v_xor_b32_e32 v2, 0xffff8000, v2 158; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc 159; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc 160; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v1 161; GFX8-NEXT: v_sub_u16_e32 v1, v0, v1 162; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v1, v0 163; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v1 164; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0 165; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 166; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2 167; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 168; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 169; GFX8-NEXT: s_setpc_b64 s[30:31] 170; 171; GFX9-LABEL: v_ssubsat_v2i16: 172; GFX9: ; %bb.0: 173; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 174; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 clamp 175; GFX9-NEXT: s_setpc_b64 s[30:31] 176; 177; GFX10-LABEL: v_ssubsat_v2i16: 178; GFX10: ; %bb.0: 179; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 180; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 181; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1 clamp 182; GFX10-NEXT: s_setpc_b64 s[30:31] 183 %result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) 184 ret <2 x i16> %result 185} 186 187define <3 x i16> @v_ssubsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) { 188; GFX6-LABEL: v_ssubsat_v3i16: 189; GFX6: ; %bb.0: 190; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 191; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16 192; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 193; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16 194; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 195; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16 196; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16 197; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v4 198; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v3 199; GFX6-NEXT: v_min_i32_e32 v1, 0x7fff, v1 200; GFX6-NEXT: v_min_i32_e32 v0, 0x7fff, v0 201; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v5 202; GFX6-NEXT: v_max_i32_e32 v1, 0xffff8000, v1 203; GFX6-NEXT: v_max_i32_e32 v0, 0xffff8000, v0 204; GFX6-NEXT: v_min_i32_e32 v2, 0x7fff, v2 205; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 206; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 207; GFX6-NEXT: v_max_i32_e32 v3, 0xffff8000, v2 208; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 209; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3 210; GFX6-NEXT: v_alignbit_b32 v1, v3, v1, 16 211; GFX6-NEXT: s_setpc_b64 s[30:31] 212; 213; GFX8-LABEL: v_ssubsat_v3i16: 214; GFX8: ; %bb.0: 215; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 216; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v2 217; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0 218; GFX8-NEXT: v_sub_u16_e32 v6, v5, v4 219; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v6, v5 220; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], 0, v4 221; GFX8-NEXT: v_ashrrev_i16_e32 v4, 15, v6 222; GFX8-NEXT: v_xor_b32_e32 v4, 0xffff8000, v4 223; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc 224; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc 225; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v3 226; GFX8-NEXT: v_sub_u16_e32 v3, v1, v3 227; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v3, v1 228; GFX8-NEXT: v_ashrrev_i16_e32 v1, 15, v3 229; GFX8-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1 230; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 231; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc 232; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v2 233; GFX8-NEXT: v_sub_u16_e32 v2, v0, v2 234; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v2, v0 235; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v2 236; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0 237; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 238; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc 239; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4 240; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 241; GFX8-NEXT: s_setpc_b64 s[30:31] 242; 243; GFX9-LABEL: v_ssubsat_v3i16: 244; GFX9: ; %bb.0: 245; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 246; GFX9-NEXT: v_pk_sub_i16 v1, v1, v3 clamp 247; GFX9-NEXT: v_pk_sub_i16 v0, v0, v2 clamp 248; GFX9-NEXT: s_setpc_b64 s[30:31] 249; 250; GFX10-LABEL: v_ssubsat_v3i16: 251; GFX10: ; %bb.0: 252; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 253; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 254; GFX10-NEXT: v_pk_sub_i16 v0, v0, v2 clamp 255; GFX10-NEXT: v_pk_sub_i16 v1, v1, v3 clamp 256; GFX10-NEXT: s_setpc_b64 s[30:31] 257 %result = call <3 x i16> @llvm.ssub.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs) 258 ret <3 x i16> %result 259} 260 261define <2 x float> @v_ssubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) { 262; GFX6-LABEL: v_ssubsat_v4i16: 263; GFX6: ; %bb.0: 264; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 265; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16 266; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 267; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16 268; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 269; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v5 270; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 271; GFX6-NEXT: v_min_i32_e32 v1, 0x7fff, v1 272; GFX6-NEXT: v_min_i32_e32 v0, 0x7fff, v0 273; GFX6-NEXT: v_max_i32_e32 v1, 0xffff8000, v1 274; GFX6-NEXT: v_max_i32_e32 v0, 0xffff8000, v0 275; GFX6-NEXT: v_bfe_i32 v6, v6, 0, 16 276; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16 277; GFX6-NEXT: v_bfe_i32 v7, v7, 0, 16 278; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16 279; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 280; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 281; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 282; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v3, v7 283; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v6 284; GFX6-NEXT: v_min_i32_e32 v1, 0x7fff, v1 285; GFX6-NEXT: v_min_i32_e32 v2, 0x7fff, v2 286; GFX6-NEXT: v_max_i32_e32 v1, 0xffff8000, v1 287; GFX6-NEXT: v_max_i32_e32 v2, 0xffff8000, v2 288; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 289; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2 290; GFX6-NEXT: v_or_b32_e32 v1, v2, v1 291; GFX6-NEXT: s_setpc_b64 s[30:31] 292; 293; GFX8-LABEL: v_ssubsat_v4i16: 294; GFX8: ; %bb.0: 295; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 296; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v2 297; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0 298; GFX8-NEXT: v_sub_u16_e32 v6, v5, v4 299; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v6, v5 300; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], 0, v4 301; GFX8-NEXT: v_ashrrev_i16_e32 v4, 15, v6 302; GFX8-NEXT: v_xor_b32_e32 v4, 0xffff8000, v4 303; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc 304; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc 305; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v2 306; GFX8-NEXT: v_sub_u16_e32 v2, v0, v2 307; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v2, v0 308; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v2 309; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0 310; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 311; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4 312; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc 313; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 314; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v3 315; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1 316; GFX8-NEXT: v_sub_u16_e32 v5, v4, v2 317; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v5, v4 318; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], 0, v2 319; GFX8-NEXT: v_ashrrev_i16_e32 v2, 15, v5 320; GFX8-NEXT: v_xor_b32_e32 v2, 0xffff8000, v2 321; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc 322; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc 323; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v3 324; GFX8-NEXT: v_sub_u16_e32 v3, v1, v3 325; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v3, v1 326; GFX8-NEXT: v_ashrrev_i16_e32 v1, 15, v3 327; GFX8-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1 328; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 329; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2 330; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc 331; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 332; GFX8-NEXT: s_setpc_b64 s[30:31] 333; 334; GFX9-LABEL: v_ssubsat_v4i16: 335; GFX9: ; %bb.0: 336; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 337; GFX9-NEXT: v_pk_sub_i16 v0, v0, v2 clamp 338; GFX9-NEXT: v_pk_sub_i16 v1, v1, v3 clamp 339; GFX9-NEXT: s_setpc_b64 s[30:31] 340; 341; GFX10-LABEL: v_ssubsat_v4i16: 342; GFX10: ; %bb.0: 343; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 344; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 345; GFX10-NEXT: v_pk_sub_i16 v0, v0, v2 clamp 346; GFX10-NEXT: v_pk_sub_i16 v1, v1, v3 clamp 347; GFX10-NEXT: s_setpc_b64 s[30:31] 348 %result = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) 349 %cast = bitcast <4 x i16> %result to <2 x float> 350 ret <2 x float> %cast 351} 352 353define <2 x i32> @v_ssubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 354; GFX6-LABEL: v_ssubsat_v2i32: 355; GFX6: ; %bb.0: 356; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 357; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v2 358; GFX6-NEXT: v_sub_i32_e64 v2, s[4:5], v0, v2 359; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0 360; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v2 361; GFX6-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 362; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 363; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc 364; GFX6-NEXT: v_sub_i32_e64 v2, s[4:5], v1, v3 365; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v3 366; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v1 367; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v2 368; GFX6-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 369; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 370; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc 371; GFX6-NEXT: s_setpc_b64 s[30:31] 372; 373; GFX8-LABEL: v_ssubsat_v2i32: 374; GFX8: ; %bb.0: 375; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 376; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v2 377; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v0, v2 378; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0 379; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v2 380; GFX8-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 381; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 382; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc 383; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v1, v3 384; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v3 385; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v1 386; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v2 387; GFX8-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 388; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 389; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc 390; GFX8-NEXT: s_setpc_b64 s[30:31] 391; 392; GFX9-LABEL: v_ssubsat_v2i32: 393; GFX9: ; %bb.0: 394; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 395; GFX9-NEXT: v_sub_i32 v0, v0, v2 clamp 396; GFX9-NEXT: v_sub_i32 v1, v1, v3 clamp 397; GFX9-NEXT: s_setpc_b64 s[30:31] 398; 399; GFX10-LABEL: v_ssubsat_v2i32: 400; GFX10: ; %bb.0: 401; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 402; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 403; GFX10-NEXT: v_sub_nc_i32 v0, v0, v2 clamp 404; GFX10-NEXT: v_sub_nc_i32 v1, v1, v3 clamp 405; GFX10-NEXT: s_setpc_b64 s[30:31] 406 %result = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) 407 ret <2 x i32> %result 408} 409 410define <3 x i32> @v_ssubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) { 411; GFX6-LABEL: v_ssubsat_v3i32: 412; GFX6: ; %bb.0: 413; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 414; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v3 415; GFX6-NEXT: v_sub_i32_e64 v3, s[4:5], v0, v3 416; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v0 417; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v3 418; GFX6-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 419; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 420; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc 421; GFX6-NEXT: v_sub_i32_e64 v3, s[4:5], v1, v4 422; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v4 423; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v1 424; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v3 425; GFX6-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 426; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 427; GFX6-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc 428; GFX6-NEXT: v_sub_i32_e64 v3, s[4:5], v2, v5 429; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v5 430; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v2 431; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v3 432; GFX6-NEXT: v_xor_b32_e32 v2, 0x80000000, v2 433; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 434; GFX6-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc 435; GFX6-NEXT: s_setpc_b64 s[30:31] 436; 437; GFX8-LABEL: v_ssubsat_v3i32: 438; GFX8: ; %bb.0: 439; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 440; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v3 441; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v0, v3 442; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v0 443; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v3 444; GFX8-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 445; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 446; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc 447; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v1, v4 448; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v4 449; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v1 450; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v3 451; GFX8-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 452; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 453; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc 454; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v2, v5 455; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v5 456; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v2 457; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v3 458; GFX8-NEXT: v_xor_b32_e32 v2, 0x80000000, v2 459; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 460; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc 461; GFX8-NEXT: s_setpc_b64 s[30:31] 462; 463; GFX9-LABEL: v_ssubsat_v3i32: 464; GFX9: ; %bb.0: 465; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 466; GFX9-NEXT: v_sub_i32 v0, v0, v3 clamp 467; GFX9-NEXT: v_sub_i32 v1, v1, v4 clamp 468; GFX9-NEXT: v_sub_i32 v2, v2, v5 clamp 469; GFX9-NEXT: s_setpc_b64 s[30:31] 470; 471; GFX10-LABEL: v_ssubsat_v3i32: 472; GFX10: ; %bb.0: 473; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 474; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 475; GFX10-NEXT: v_sub_nc_i32 v0, v0, v3 clamp 476; GFX10-NEXT: v_sub_nc_i32 v1, v1, v4 clamp 477; GFX10-NEXT: v_sub_nc_i32 v2, v2, v5 clamp 478; GFX10-NEXT: s_setpc_b64 s[30:31] 479 %result = call <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs) 480 ret <3 x i32> %result 481} 482 483define <4 x i32> @v_ssubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) { 484; GFX6-LABEL: v_ssubsat_v4i32: 485; GFX6: ; %bb.0: 486; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 487; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v4 488; GFX6-NEXT: v_sub_i32_e64 v4, s[4:5], v0, v4 489; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v0 490; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v4 491; GFX6-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 492; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 493; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc 494; GFX6-NEXT: v_sub_i32_e64 v4, s[4:5], v1, v5 495; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v5 496; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v1 497; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v4 498; GFX6-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 499; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 500; GFX6-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc 501; GFX6-NEXT: v_sub_i32_e64 v4, s[4:5], v2, v6 502; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v6 503; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v2 504; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v4 505; GFX6-NEXT: v_xor_b32_e32 v2, 0x80000000, v2 506; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 507; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc 508; GFX6-NEXT: v_sub_i32_e64 v4, s[4:5], v3, v7 509; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v7 510; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v3 511; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v4 512; GFX6-NEXT: v_xor_b32_e32 v3, 0x80000000, v3 513; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 514; GFX6-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc 515; GFX6-NEXT: s_setpc_b64 s[30:31] 516; 517; GFX8-LABEL: v_ssubsat_v4i32: 518; GFX8: ; %bb.0: 519; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 520; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v4 521; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v0, v4 522; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v0 523; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v4 524; GFX8-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 525; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 526; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc 527; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v1, v5 528; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v5 529; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v1 530; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v4 531; GFX8-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 532; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 533; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc 534; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v2, v6 535; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v6 536; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v2 537; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v4 538; GFX8-NEXT: v_xor_b32_e32 v2, 0x80000000, v2 539; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 540; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc 541; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v3, v7 542; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v7 543; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v3 544; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v4 545; GFX8-NEXT: v_xor_b32_e32 v3, 0x80000000, v3 546; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 547; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc 548; GFX8-NEXT: s_setpc_b64 s[30:31] 549; 550; GFX9-LABEL: v_ssubsat_v4i32: 551; GFX9: ; %bb.0: 552; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 553; GFX9-NEXT: v_sub_i32 v0, v0, v4 clamp 554; GFX9-NEXT: v_sub_i32 v1, v1, v5 clamp 555; GFX9-NEXT: v_sub_i32 v2, v2, v6 clamp 556; GFX9-NEXT: v_sub_i32 v3, v3, v7 clamp 557; GFX9-NEXT: s_setpc_b64 s[30:31] 558; 559; GFX10-LABEL: v_ssubsat_v4i32: 560; GFX10: ; %bb.0: 561; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 562; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 563; GFX10-NEXT: v_sub_nc_i32 v0, v0, v4 clamp 564; GFX10-NEXT: v_sub_nc_i32 v1, v1, v5 clamp 565; GFX10-NEXT: v_sub_nc_i32 v2, v2, v6 clamp 566; GFX10-NEXT: v_sub_nc_i32 v3, v3, v7 clamp 567; GFX10-NEXT: s_setpc_b64 s[30:31] 568 %result = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) 569 ret <4 x i32> %result 570} 571 572define <8 x i32> @v_ssubsat_v8i32(<8 x i32> %lhs, <8 x i32> %rhs) { 573; GFX6-LABEL: v_ssubsat_v8i32: 574; GFX6: ; %bb.0: 575; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 576; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v8 577; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v0, v8 578; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v0 579; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v8 580; GFX6-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 581; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 582; GFX6-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc 583; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v1, v9 584; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v9 585; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v1 586; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v8 587; GFX6-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 588; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 589; GFX6-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc 590; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v2, v10 591; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v10 592; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v2 593; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v8 594; GFX6-NEXT: v_xor_b32_e32 v2, 0x80000000, v2 595; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 596; GFX6-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc 597; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v3, v11 598; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v11 599; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v3 600; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v8 601; GFX6-NEXT: v_xor_b32_e32 v3, 0x80000000, v3 602; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 603; GFX6-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc 604; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v4, v12 605; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v12 606; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v4 607; GFX6-NEXT: v_ashrrev_i32_e32 v4, 31, v8 608; GFX6-NEXT: v_xor_b32_e32 v4, 0x80000000, v4 609; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 610; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc 611; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v5, v13 612; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v13 613; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v5 614; GFX6-NEXT: v_ashrrev_i32_e32 v5, 31, v8 615; GFX6-NEXT: v_xor_b32_e32 v5, 0x80000000, v5 616; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 617; GFX6-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc 618; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v6, v14 619; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v14 620; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v6 621; GFX6-NEXT: v_ashrrev_i32_e32 v6, 31, v8 622; GFX6-NEXT: v_xor_b32_e32 v6, 0x80000000, v6 623; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 624; GFX6-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc 625; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v7, v15 626; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v15 627; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v7 628; GFX6-NEXT: v_ashrrev_i32_e32 v7, 31, v8 629; GFX6-NEXT: v_xor_b32_e32 v7, 0x80000000, v7 630; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 631; GFX6-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc 632; GFX6-NEXT: s_setpc_b64 s[30:31] 633; 634; GFX8-LABEL: v_ssubsat_v8i32: 635; GFX8: ; %bb.0: 636; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 637; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v8 638; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v0, v8 639; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v0 640; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v8 641; GFX8-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 642; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 643; GFX8-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc 644; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v1, v9 645; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v9 646; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v1 647; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v8 648; GFX8-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 649; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 650; GFX8-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc 651; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v2, v10 652; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v10 653; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v2 654; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v8 655; GFX8-NEXT: v_xor_b32_e32 v2, 0x80000000, v2 656; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 657; GFX8-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc 658; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v3, v11 659; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v11 660; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v3 661; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v8 662; GFX8-NEXT: v_xor_b32_e32 v3, 0x80000000, v3 663; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 664; GFX8-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc 665; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v4, v12 666; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v12 667; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v4 668; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v8 669; GFX8-NEXT: v_xor_b32_e32 v4, 0x80000000, v4 670; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 671; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc 672; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v5, v13 673; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v13 674; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v5 675; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v8 676; GFX8-NEXT: v_xor_b32_e32 v5, 0x80000000, v5 677; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 678; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc 679; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v6, v14 680; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v14 681; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v6 682; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v8 683; GFX8-NEXT: v_xor_b32_e32 v6, 0x80000000, v6 684; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 685; GFX8-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc 686; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v7, v15 687; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v15 688; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v7 689; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v8 690; GFX8-NEXT: v_xor_b32_e32 v7, 0x80000000, v7 691; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 692; GFX8-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc 693; GFX8-NEXT: s_setpc_b64 s[30:31] 694; 695; GFX9-LABEL: v_ssubsat_v8i32: 696; GFX9: ; %bb.0: 697; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 698; GFX9-NEXT: v_sub_i32 v0, v0, v8 clamp 699; GFX9-NEXT: v_sub_i32 v1, v1, v9 clamp 700; GFX9-NEXT: v_sub_i32 v2, v2, v10 clamp 701; GFX9-NEXT: v_sub_i32 v3, v3, v11 clamp 702; GFX9-NEXT: v_sub_i32 v4, v4, v12 clamp 703; GFX9-NEXT: v_sub_i32 v5, v5, v13 clamp 704; GFX9-NEXT: v_sub_i32 v6, v6, v14 clamp 705; GFX9-NEXT: v_sub_i32 v7, v7, v15 clamp 706; GFX9-NEXT: s_setpc_b64 s[30:31] 707; 708; GFX10-LABEL: v_ssubsat_v8i32: 709; GFX10: ; %bb.0: 710; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 711; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 712; GFX10-NEXT: v_sub_nc_i32 v0, v0, v8 clamp 713; GFX10-NEXT: v_sub_nc_i32 v1, v1, v9 clamp 714; GFX10-NEXT: v_sub_nc_i32 v2, v2, v10 clamp 715; GFX10-NEXT: v_sub_nc_i32 v3, v3, v11 clamp 716; GFX10-NEXT: v_sub_nc_i32 v4, v4, v12 clamp 717; GFX10-NEXT: v_sub_nc_i32 v5, v5, v13 clamp 718; GFX10-NEXT: v_sub_nc_i32 v6, v6, v14 clamp 719; GFX10-NEXT: v_sub_nc_i32 v7, v7, v15 clamp 720; GFX10-NEXT: s_setpc_b64 s[30:31] 721 %result = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> %lhs, <8 x i32> %rhs) 722 ret <8 x i32> %result 723} 724 725define <16 x i32> @v_ssubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) { 726; GFX6-LABEL: v_ssubsat_v16i32: 727; GFX6: ; %bb.0: 728; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 729; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v16 730; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v0, v16 731; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v0 732; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v16 733; GFX6-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 734; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 735; GFX6-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc 736; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v1, v17 737; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v17 738; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v1 739; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v16 740; GFX6-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 741; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 742; GFX6-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc 743; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v2, v18 744; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v18 745; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v2 746; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v16 747; GFX6-NEXT: v_xor_b32_e32 v2, 0x80000000, v2 748; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 749; GFX6-NEXT: v_cndmask_b32_e32 v2, v16, v2, vcc 750; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v3, v19 751; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v19 752; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v3 753; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v16 754; GFX6-NEXT: v_xor_b32_e32 v3, 0x80000000, v3 755; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 756; GFX6-NEXT: v_cndmask_b32_e32 v3, v16, v3, vcc 757; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v4, v20 758; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v20 759; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v4 760; GFX6-NEXT: v_ashrrev_i32_e32 v4, 31, v16 761; GFX6-NEXT: v_xor_b32_e32 v4, 0x80000000, v4 762; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 763; GFX6-NEXT: v_cndmask_b32_e32 v4, v16, v4, vcc 764; GFX6-NEXT: buffer_load_dword v16, off, s[0:3], s32 765; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v5, v21 766; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v21 767; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v5 768; GFX6-NEXT: v_ashrrev_i32_e32 v5, 31, v17 769; GFX6-NEXT: v_xor_b32_e32 v5, 0x80000000, v5 770; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 771; GFX6-NEXT: v_cndmask_b32_e32 v5, v17, v5, vcc 772; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v6, v22 773; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v22 774; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v6 775; GFX6-NEXT: v_ashrrev_i32_e32 v6, 31, v17 776; GFX6-NEXT: v_xor_b32_e32 v6, 0x80000000, v6 777; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 778; GFX6-NEXT: v_cndmask_b32_e32 v6, v17, v6, vcc 779; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v7, v23 780; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v23 781; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v7 782; GFX6-NEXT: v_ashrrev_i32_e32 v7, 31, v17 783; GFX6-NEXT: v_xor_b32_e32 v7, 0x80000000, v7 784; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 785; GFX6-NEXT: v_cndmask_b32_e32 v7, v17, v7, vcc 786; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v8, v24 787; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v24 788; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v8 789; GFX6-NEXT: v_ashrrev_i32_e32 v8, 31, v17 790; GFX6-NEXT: v_xor_b32_e32 v8, 0x80000000, v8 791; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 792; GFX6-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc 793; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v9, v25 794; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v25 795; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v9 796; GFX6-NEXT: v_ashrrev_i32_e32 v9, 31, v17 797; GFX6-NEXT: v_xor_b32_e32 v9, 0x80000000, v9 798; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 799; GFX6-NEXT: v_cndmask_b32_e32 v9, v17, v9, vcc 800; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v10, v26 801; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v26 802; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v10 803; GFX6-NEXT: v_ashrrev_i32_e32 v10, 31, v17 804; GFX6-NEXT: v_xor_b32_e32 v10, 0x80000000, v10 805; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 806; GFX6-NEXT: v_cndmask_b32_e32 v10, v17, v10, vcc 807; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v11, v27 808; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v27 809; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v11 810; GFX6-NEXT: v_ashrrev_i32_e32 v11, 31, v17 811; GFX6-NEXT: v_xor_b32_e32 v11, 0x80000000, v11 812; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 813; GFX6-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc 814; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v12, v28 815; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v28 816; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v12 817; GFX6-NEXT: v_ashrrev_i32_e32 v12, 31, v17 818; GFX6-NEXT: v_xor_b32_e32 v12, 0x80000000, v12 819; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 820; GFX6-NEXT: v_cndmask_b32_e32 v12, v17, v12, vcc 821; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v13, v29 822; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v29 823; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v13 824; GFX6-NEXT: v_ashrrev_i32_e32 v13, 31, v17 825; GFX6-NEXT: v_xor_b32_e32 v13, 0x80000000, v13 826; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 827; GFX6-NEXT: v_cndmask_b32_e32 v13, v17, v13, vcc 828; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v14, v30 829; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v30 830; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v14 831; GFX6-NEXT: v_ashrrev_i32_e32 v14, 31, v17 832; GFX6-NEXT: v_xor_b32_e32 v14, 0x80000000, v14 833; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 834; GFX6-NEXT: v_cndmask_b32_e32 v14, v17, v14, vcc 835; GFX6-NEXT: s_waitcnt vmcnt(0) 836; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v16 837; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v15, v16 838; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v15 839; GFX6-NEXT: v_ashrrev_i32_e32 v15, 31, v16 840; GFX6-NEXT: v_xor_b32_e32 v15, 0x80000000, v15 841; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 842; GFX6-NEXT: v_cndmask_b32_e32 v15, v16, v15, vcc 843; GFX6-NEXT: s_setpc_b64 s[30:31] 844; 845; GFX8-LABEL: v_ssubsat_v16i32: 846; GFX8: ; %bb.0: 847; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 848; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v16 849; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v0, v16 850; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v0 851; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v16 852; GFX8-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 853; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 854; GFX8-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc 855; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v1, v17 856; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v17 857; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v1 858; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v16 859; GFX8-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 860; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 861; GFX8-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc 862; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v2, v18 863; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v18 864; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v2 865; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v16 866; GFX8-NEXT: v_xor_b32_e32 v2, 0x80000000, v2 867; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 868; GFX8-NEXT: v_cndmask_b32_e32 v2, v16, v2, vcc 869; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v3, v19 870; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v19 871; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v3 872; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v16 873; GFX8-NEXT: v_xor_b32_e32 v3, 0x80000000, v3 874; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 875; GFX8-NEXT: v_cndmask_b32_e32 v3, v16, v3, vcc 876; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v4, v20 877; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v20 878; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v4 879; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v16 880; GFX8-NEXT: v_xor_b32_e32 v4, 0x80000000, v4 881; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 882; GFX8-NEXT: v_cndmask_b32_e32 v4, v16, v4, vcc 883; GFX8-NEXT: buffer_load_dword v16, off, s[0:3], s32 884; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v5, v21 885; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v21 886; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v5 887; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v17 888; GFX8-NEXT: v_xor_b32_e32 v5, 0x80000000, v5 889; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 890; GFX8-NEXT: v_cndmask_b32_e32 v5, v17, v5, vcc 891; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v6, v22 892; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v22 893; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v6 894; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v17 895; GFX8-NEXT: v_xor_b32_e32 v6, 0x80000000, v6 896; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 897; GFX8-NEXT: v_cndmask_b32_e32 v6, v17, v6, vcc 898; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v7, v23 899; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v23 900; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v7 901; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v17 902; GFX8-NEXT: v_xor_b32_e32 v7, 0x80000000, v7 903; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 904; GFX8-NEXT: v_cndmask_b32_e32 v7, v17, v7, vcc 905; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v8, v24 906; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v24 907; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v8 908; GFX8-NEXT: v_ashrrev_i32_e32 v8, 31, v17 909; GFX8-NEXT: v_xor_b32_e32 v8, 0x80000000, v8 910; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 911; GFX8-NEXT: v_cndmask_b32_e32 v8, v17, v8, vcc 912; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v9, v25 913; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v25 914; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v9 915; GFX8-NEXT: v_ashrrev_i32_e32 v9, 31, v17 916; GFX8-NEXT: v_xor_b32_e32 v9, 0x80000000, v9 917; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 918; GFX8-NEXT: v_cndmask_b32_e32 v9, v17, v9, vcc 919; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v10, v26 920; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v26 921; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v10 922; GFX8-NEXT: v_ashrrev_i32_e32 v10, 31, v17 923; GFX8-NEXT: v_xor_b32_e32 v10, 0x80000000, v10 924; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 925; GFX8-NEXT: v_cndmask_b32_e32 v10, v17, v10, vcc 926; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v11, v27 927; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v27 928; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v11 929; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v17 930; GFX8-NEXT: v_xor_b32_e32 v11, 0x80000000, v11 931; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 932; GFX8-NEXT: v_cndmask_b32_e32 v11, v17, v11, vcc 933; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v12, v28 934; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v28 935; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v12 936; GFX8-NEXT: v_ashrrev_i32_e32 v12, 31, v17 937; GFX8-NEXT: v_xor_b32_e32 v12, 0x80000000, v12 938; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 939; GFX8-NEXT: v_cndmask_b32_e32 v12, v17, v12, vcc 940; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v13, v29 941; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v29 942; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v13 943; GFX8-NEXT: v_ashrrev_i32_e32 v13, 31, v17 944; GFX8-NEXT: v_xor_b32_e32 v13, 0x80000000, v13 945; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 946; GFX8-NEXT: v_cndmask_b32_e32 v13, v17, v13, vcc 947; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v14, v30 948; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v30 949; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v14 950; GFX8-NEXT: v_ashrrev_i32_e32 v14, 31, v17 951; GFX8-NEXT: v_xor_b32_e32 v14, 0x80000000, v14 952; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 953; GFX8-NEXT: v_cndmask_b32_e32 v14, v17, v14, vcc 954; GFX8-NEXT: s_waitcnt vmcnt(0) 955; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v16 956; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v15, v16 957; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v15 958; GFX8-NEXT: v_ashrrev_i32_e32 v15, 31, v16 959; GFX8-NEXT: v_xor_b32_e32 v15, 0x80000000, v15 960; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 961; GFX8-NEXT: v_cndmask_b32_e32 v15, v16, v15, vcc 962; GFX8-NEXT: s_setpc_b64 s[30:31] 963; 964; GFX9-LABEL: v_ssubsat_v16i32: 965; GFX9: ; %bb.0: 966; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 967; GFX9-NEXT: v_sub_i32 v0, v0, v16 clamp 968; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 969; GFX9-NEXT: v_sub_i32 v1, v1, v17 clamp 970; GFX9-NEXT: v_sub_i32 v2, v2, v18 clamp 971; GFX9-NEXT: v_sub_i32 v3, v3, v19 clamp 972; GFX9-NEXT: v_sub_i32 v4, v4, v20 clamp 973; GFX9-NEXT: v_sub_i32 v5, v5, v21 clamp 974; GFX9-NEXT: v_sub_i32 v6, v6, v22 clamp 975; GFX9-NEXT: v_sub_i32 v7, v7, v23 clamp 976; GFX9-NEXT: v_sub_i32 v8, v8, v24 clamp 977; GFX9-NEXT: v_sub_i32 v9, v9, v25 clamp 978; GFX9-NEXT: v_sub_i32 v10, v10, v26 clamp 979; GFX9-NEXT: v_sub_i32 v11, v11, v27 clamp 980; GFX9-NEXT: v_sub_i32 v12, v12, v28 clamp 981; GFX9-NEXT: v_sub_i32 v13, v13, v29 clamp 982; GFX9-NEXT: v_sub_i32 v14, v14, v30 clamp 983; GFX9-NEXT: s_waitcnt vmcnt(0) 984; GFX9-NEXT: v_sub_i32 v15, v15, v16 clamp 985; GFX9-NEXT: s_setpc_b64 s[30:31] 986; 987; GFX10-LABEL: v_ssubsat_v16i32: 988; GFX10: ; %bb.0: 989; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 990; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 991; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32 992; GFX10-NEXT: v_sub_nc_i32 v0, v0, v16 clamp 993; GFX10-NEXT: v_sub_nc_i32 v1, v1, v17 clamp 994; GFX10-NEXT: v_sub_nc_i32 v2, v2, v18 clamp 995; GFX10-NEXT: v_sub_nc_i32 v3, v3, v19 clamp 996; GFX10-NEXT: v_sub_nc_i32 v4, v4, v20 clamp 997; GFX10-NEXT: v_sub_nc_i32 v5, v5, v21 clamp 998; GFX10-NEXT: v_sub_nc_i32 v6, v6, v22 clamp 999; GFX10-NEXT: v_sub_nc_i32 v7, v7, v23 clamp 1000; GFX10-NEXT: v_sub_nc_i32 v8, v8, v24 clamp 1001; GFX10-NEXT: v_sub_nc_i32 v9, v9, v25 clamp 1002; GFX10-NEXT: v_sub_nc_i32 v10, v10, v26 clamp 1003; GFX10-NEXT: v_sub_nc_i32 v11, v11, v27 clamp 1004; GFX10-NEXT: v_sub_nc_i32 v12, v12, v28 clamp 1005; GFX10-NEXT: v_sub_nc_i32 v13, v13, v29 clamp 1006; GFX10-NEXT: v_sub_nc_i32 v14, v14, v30 clamp 1007; GFX10-NEXT: s_waitcnt vmcnt(0) 1008; GFX10-NEXT: v_sub_nc_i32 v15, v15, v31 clamp 1009; GFX10-NEXT: s_setpc_b64 s[30:31] 1010 %result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) 1011 ret <16 x i32> %result 1012} 1013 1014 1015define i64 @v_ssubsat_i64(i64 %lhs, i64 %rhs) { 1016; GFX6-LABEL: v_ssubsat_i64: 1017; GFX6: ; %bb.0: 1018; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1019; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v0, v2 1020; GFX6-NEXT: v_subb_u32_e32 v5, vcc, v1, v3, vcc 1021; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1] 1022; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3] 1023; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v5 1024; GFX6-NEXT: s_xor_b64 vcc, s[4:5], vcc 1025; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc 1026; GFX6-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 1027; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc 1028; GFX6-NEXT: s_setpc_b64 s[30:31] 1029; 1030; GFX8-LABEL: v_ssubsat_i64: 1031; GFX8: ; %bb.0: 1032; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1033; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v0, v2 1034; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v1, v3, vcc 1035; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1] 1036; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3] 1037; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v5 1038; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc 1039; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc 1040; GFX8-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 1041; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc 1042; GFX8-NEXT: s_setpc_b64 s[30:31] 1043; 1044; GFX9-LABEL: v_ssubsat_i64: 1045; GFX9: ; %bb.0: 1046; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1047; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v0, v2 1048; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v1, v3, vcc 1049; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1] 1050; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3] 1051; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v5 1052; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc 1053; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc 1054; GFX9-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 1055; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc 1056; GFX9-NEXT: s_setpc_b64 s[30:31] 1057; 1058; GFX10-LABEL: v_ssubsat_i64: 1059; GFX10: ; %bb.0: 1060; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1061; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1062; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v2 1063; GFX10-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo 1064; GFX10-NEXT: v_cmp_lt_i64_e64 s4, 0, v[2:3] 1065; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v5 1066; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1] 1067; GFX10-NEXT: v_xor_b32_e32 v1, 0x80000000, v6 1068; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo 1069; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo 1070; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo 1071; GFX10-NEXT: s_setpc_b64 s[30:31] 1072 %result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs) 1073 ret i64 %result 1074} 1075 1076declare i8 @llvm.ssub.sat.i8(i8, i8) #0 1077declare i16 @llvm.ssub.sat.i16(i16, i16) #0 1078declare <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16>, <2 x i16>) #0 1079declare <3 x i16> @llvm.ssub.sat.v3i16(<3 x i16>, <3 x i16>) #0 1080declare <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16>, <4 x i16>) #0 1081declare i32 @llvm.ssub.sat.i32(i32, i32) #0 1082declare <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32>, <2 x i32>) #0 1083declare <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32>, <3 x i32>) #0 1084declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>) #0 1085declare <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32>, <8 x i32>) #0 1086declare <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32>, <16 x i32>) #0 1087declare i64 @llvm.ssub.sat.i64(i64, i64) #0 1088 1089attributes #0 = { nounwind readnone speculatable willreturn } 1090