1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck --check-prefix=GFX6 %s 3; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck --check-prefix=GFX8 %s 4; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s 5; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s 6 7define i8 @v_ssubsat_i8(i8 %lhs, i8 %rhs) { 8; GFX6-LABEL: v_ssubsat_i8: 9; GFX6: ; %bb.0: 10; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 11; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 8 12; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8 13; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 14; GFX6-NEXT: v_min_i32_e32 v0, 0x7f, v0 15; GFX6-NEXT: v_max_i32_e32 v0, 0xffffff80, v0 16; GFX6-NEXT: s_setpc_b64 s[30:31] 17; 18; GFX8-LABEL: v_ssubsat_i8: 19; GFX8: ; %bb.0: 20; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 21; GFX8-NEXT: v_sub_u16_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 22; GFX8-NEXT: v_min_i16_e32 v0, 0x7f, v0 23; GFX8-NEXT: v_max_i16_e32 v0, 0xff80, v0 24; GFX8-NEXT: s_setpc_b64 s[30:31] 25; 26; GFX9-LABEL: v_ssubsat_i8: 27; GFX9: ; %bb.0: 28; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 29; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1 30; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 31; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp 32; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0 33; GFX9-NEXT: s_setpc_b64 s[30:31] 34; 35; GFX10-LABEL: v_ssubsat_i8: 36; GFX10: ; %bb.0: 37; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 38; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 39; GFX10-NEXT: v_lshlrev_b16 v1, 8, v1 40; GFX10-NEXT: v_lshlrev_b16 v0, 8, v0 41; GFX10-NEXT: v_sub_nc_i16 v0, v0, v1 clamp 42; GFX10-NEXT: v_ashrrev_i16 v0, 8, v0 43; GFX10-NEXT: s_setpc_b64 s[30:31] 44 %result = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs) 45 ret i8 %result 46} 47 48define i16 @v_ssubsat_i16(i16 %lhs, i16 %rhs) { 49; GFX6-LABEL: v_ssubsat_i16: 50; GFX6: ; %bb.0: 51; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 52; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 53; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 54; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 55; GFX6-NEXT: v_min_i32_e32 v0, 0x7fff, v0 56; GFX6-NEXT: v_max_i32_e32 v0, 0xffff8000, v0 57; GFX6-NEXT: s_setpc_b64 s[30:31] 58; 59; GFX8-LABEL: v_ssubsat_i16: 60; GFX8: ; %bb.0: 61; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 62; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v1 63; GFX8-NEXT: v_sub_u16_e32 v1, v0, v1 64; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v1, v0 65; GFX8-NEXT: v_mov_b32_e32 v0, 0xffff8000 66; GFX8-NEXT: v_mov_b32_e32 v2, 0x7fff 67; GFX8-NEXT: v_cmp_gt_i16_e64 s[6:7], 0, v1 68; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[6:7] 69; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 70; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 71; GFX8-NEXT: s_setpc_b64 s[30:31] 72; 73; GFX9-LABEL: v_ssubsat_i16: 74; GFX9: ; %bb.0: 75; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 76; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp 77; GFX9-NEXT: s_setpc_b64 s[30:31] 78; 79; GFX10-LABEL: v_ssubsat_i16: 80; GFX10: ; %bb.0: 81; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 82; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 83; GFX10-NEXT: v_sub_nc_i16 v0, v0, v1 clamp 84; GFX10-NEXT: s_setpc_b64 s[30:31] 85 %result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs) 86 ret i16 %result 87} 88 89define i32 @v_ssubsat_i32(i32 %lhs, i32 %rhs) { 90; GFX6-LABEL: v_ssubsat_i32: 91; GFX6: ; %bb.0: 92; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 93; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v1 94; GFX6-NEXT: v_sub_i32_e64 v1, s[4:5], v0, v1 95; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v1, v0 96; GFX6-NEXT: v_bfrev_b32_e32 v0, 1 97; GFX6-NEXT: v_bfrev_b32_e32 v2, -2 98; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v1 99; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[6:7] 100; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 101; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 102; GFX6-NEXT: s_setpc_b64 s[30:31] 103; 104; GFX8-LABEL: v_ssubsat_i32: 105; GFX8: ; %bb.0: 106; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 107; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v1 108; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v0, v1 109; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v1, v0 110; GFX8-NEXT: v_bfrev_b32_e32 v0, 1 111; GFX8-NEXT: v_bfrev_b32_e32 v2, -2 112; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v1 113; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[6:7] 114; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 115; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 116; GFX8-NEXT: s_setpc_b64 s[30:31] 117; 118; GFX9-LABEL: v_ssubsat_i32: 119; GFX9: ; %bb.0: 120; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 121; GFX9-NEXT: v_sub_i32 v0, v0, v1 clamp 122; GFX9-NEXT: s_setpc_b64 s[30:31] 123; 124; GFX10-LABEL: v_ssubsat_i32: 125; GFX10: ; %bb.0: 126; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 127; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 128; GFX10-NEXT: v_sub_nc_i32 v0, v0, v1 clamp 129; GFX10-NEXT: s_setpc_b64 s[30:31] 130 %result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs) 131 ret i32 %result 132} 133 134define <2 x i16> @v_ssubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) { 135; GFX6-LABEL: v_ssubsat_v2i16: 136; GFX6: ; %bb.0: 137; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 138; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16 139; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 140; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16 141; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 142; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v3 143; GFX6-NEXT: s_movk_i32 s4, 0x7fff 144; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 145; GFX6-NEXT: v_min_i32_e32 v1, s4, v1 146; GFX6-NEXT: s_movk_i32 s5, 0x8000 147; GFX6-NEXT: v_min_i32_e32 v0, s4, v0 148; GFX6-NEXT: v_max_i32_e32 v1, s5, v1 149; GFX6-NEXT: v_max_i32_e32 v0, s5, v0 150; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 151; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 152; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 153; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0 154; GFX6-NEXT: s_setpc_b64 s[30:31] 155; 156; GFX8-LABEL: v_ssubsat_v2i16: 157; GFX8: ; %bb.0: 158; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 159; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v1 160; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0 161; GFX8-NEXT: v_sub_u16_e32 v4, v3, v2 162; GFX8-NEXT: v_mov_b32_e32 v5, 0xffff8000 163; GFX8-NEXT: v_mov_b32_e32 v6, 0x7fff 164; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v4 165; GFX8-NEXT: v_cndmask_b32_e32 v7, v5, v6, vcc 166; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v4, v3 167; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], 0, v2 168; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc 169; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc 170; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v1 171; GFX8-NEXT: v_sub_u16_e32 v1, v0, v1 172; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v1, v0 173; GFX8-NEXT: v_cmp_gt_i16_e64 s[6:7], 0, v1 174; GFX8-NEXT: v_cndmask_b32_e64 v0, v5, v6, s[6:7] 175; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 176; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2 177; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 178; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 179; GFX8-NEXT: s_setpc_b64 s[30:31] 180; 181; GFX9-LABEL: v_ssubsat_v2i16: 182; GFX9: ; %bb.0: 183; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 184; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 clamp 185; GFX9-NEXT: s_setpc_b64 s[30:31] 186; 187; GFX10-LABEL: v_ssubsat_v2i16: 188; GFX10: ; %bb.0: 189; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 190; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 191; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1 clamp 192; GFX10-NEXT: s_setpc_b64 s[30:31] 193 %result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) 194 ret <2 x i16> %result 195} 196 197define <3 x i16> @v_ssubsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) { 198; GFX6-LABEL: v_ssubsat_v3i16: 199; GFX6: ; %bb.0: 200; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 201; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16 202; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 203; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16 204; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 205; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16 206; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16 207; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v4 208; GFX6-NEXT: s_movk_i32 s4, 0x7fff 209; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v3 210; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v5 211; GFX6-NEXT: v_min_i32_e32 v1, s4, v1 212; GFX6-NEXT: s_movk_i32 s5, 0x8000 213; GFX6-NEXT: v_min_i32_e32 v0, s4, v0 214; GFX6-NEXT: v_max_i32_e32 v1, s5, v1 215; GFX6-NEXT: v_min_i32_e32 v2, s4, v2 216; GFX6-NEXT: v_max_i32_e32 v0, s5, v0 217; GFX6-NEXT: s_mov_b32 s6, 0xffff 218; GFX6-NEXT: v_max_i32_e32 v3, s5, v2 219; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 220; GFX6-NEXT: v_and_b32_e32 v0, s6, v0 221; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 222; GFX6-NEXT: v_and_b32_e32 v2, s6, v3 223; GFX6-NEXT: v_alignbit_b32 v1, v3, v1, 16 224; GFX6-NEXT: s_setpc_b64 s[30:31] 225; 226; GFX8-LABEL: v_ssubsat_v3i16: 227; GFX8: ; %bb.0: 228; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 229; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v2 230; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0 231; GFX8-NEXT: v_sub_u16_e32 v6, v5, v4 232; GFX8-NEXT: v_mov_b32_e32 v7, 0xffff8000 233; GFX8-NEXT: v_mov_b32_e32 v8, 0x7fff 234; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v6 235; GFX8-NEXT: v_cndmask_b32_e32 v9, v7, v8, vcc 236; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v6, v5 237; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], 0, v4 238; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc 239; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v9, vcc 240; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v3 241; GFX8-NEXT: v_sub_u16_e32 v3, v1, v3 242; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v3, v1 243; GFX8-NEXT: v_cmp_gt_i16_e64 s[6:7], 0, v3 244; GFX8-NEXT: v_cndmask_b32_e64 v1, v7, v8, s[6:7] 245; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 246; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc 247; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v2 248; GFX8-NEXT: v_sub_u16_e32 v2, v0, v2 249; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v2, v0 250; GFX8-NEXT: v_cmp_gt_i16_e64 s[6:7], 0, v2 251; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[6:7] 252; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 253; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc 254; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4 255; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 256; GFX8-NEXT: s_setpc_b64 s[30:31] 257; 258; GFX9-LABEL: v_ssubsat_v3i16: 259; GFX9: ; %bb.0: 260; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 261; GFX9-NEXT: v_pk_sub_i16 v1, v1, v3 clamp 262; GFX9-NEXT: v_pk_sub_i16 v0, v0, v2 clamp 263; GFX9-NEXT: s_setpc_b64 s[30:31] 264; 265; GFX10-LABEL: v_ssubsat_v3i16: 266; GFX10: ; %bb.0: 267; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 268; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 269; GFX10-NEXT: v_pk_sub_i16 v0, v0, v2 clamp 270; GFX10-NEXT: v_pk_sub_i16 v1, v1, v3 clamp 271; GFX10-NEXT: s_setpc_b64 s[30:31] 272 %result = call <3 x i16> @llvm.ssub.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs) 273 ret <3 x i16> %result 274} 275 276define <2 x float> @v_ssubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) { 277; GFX6-LABEL: v_ssubsat_v4i16: 278; GFX6: ; %bb.0: 279; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 280; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16 281; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 282; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16 283; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 284; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v5 285; GFX6-NEXT: s_movk_i32 s4, 0x7fff 286; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 287; GFX6-NEXT: v_min_i32_e32 v1, s4, v1 288; GFX6-NEXT: s_movk_i32 s5, 0x8000 289; GFX6-NEXT: v_min_i32_e32 v0, s4, v0 290; GFX6-NEXT: v_max_i32_e32 v1, s5, v1 291; GFX6-NEXT: v_max_i32_e32 v0, s5, v0 292; GFX6-NEXT: s_mov_b32 s6, 0xffff 293; GFX6-NEXT: v_bfe_i32 v6, v6, 0, 16 294; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16 295; GFX6-NEXT: v_bfe_i32 v7, v7, 0, 16 296; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16 297; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 298; GFX6-NEXT: v_and_b32_e32 v0, s6, v0 299; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v6 300; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 301; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v3, v7 302; GFX6-NEXT: v_min_i32_e32 v1, s4, v1 303; GFX6-NEXT: v_min_i32_e32 v2, s4, v2 304; GFX6-NEXT: v_max_i32_e32 v1, s5, v1 305; GFX6-NEXT: v_max_i32_e32 v2, s5, v2 306; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 307; GFX6-NEXT: v_and_b32_e32 v2, s6, v2 308; GFX6-NEXT: v_or_b32_e32 v1, v2, v1 309; GFX6-NEXT: s_setpc_b64 s[30:31] 310; 311; GFX8-LABEL: v_ssubsat_v4i16: 312; GFX8: ; %bb.0: 313; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 314; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v2 315; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0 316; GFX8-NEXT: v_sub_u16_e32 v6, v5, v4 317; GFX8-NEXT: v_mov_b32_e32 v7, 0xffff8000 318; GFX8-NEXT: v_mov_b32_e32 v8, 0x7fff 319; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v6 320; GFX8-NEXT: v_cndmask_b32_e32 v9, v7, v8, vcc 321; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v6, v5 322; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], 0, v4 323; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc 324; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v9, vcc 325; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v2 326; GFX8-NEXT: v_sub_u16_e32 v2, v0, v2 327; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v2, v0 328; GFX8-NEXT: v_cmp_gt_i16_e64 s[6:7], 0, v2 329; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[6:7] 330; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 331; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc 332; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4 333; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 334; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v3 335; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1 336; GFX8-NEXT: v_sub_u16_e32 v5, v4, v2 337; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v5 338; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc 339; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v5, v4 340; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], 0, v2 341; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc 342; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc 343; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v3 344; GFX8-NEXT: v_sub_u16_e32 v3, v1, v3 345; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v3, v1 346; GFX8-NEXT: v_cmp_gt_i16_e64 s[6:7], 0, v3 347; GFX8-NEXT: v_cndmask_b32_e64 v1, v7, v8, s[6:7] 348; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 349; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2 350; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc 351; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 352; GFX8-NEXT: s_setpc_b64 s[30:31] 353; 354; GFX9-LABEL: v_ssubsat_v4i16: 355; GFX9: ; %bb.0: 356; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 357; GFX9-NEXT: v_pk_sub_i16 v0, v0, v2 clamp 358; GFX9-NEXT: v_pk_sub_i16 v1, v1, v3 clamp 359; GFX9-NEXT: s_setpc_b64 s[30:31] 360; 361; GFX10-LABEL: v_ssubsat_v4i16: 362; GFX10: ; %bb.0: 363; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 364; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 365; GFX10-NEXT: v_pk_sub_i16 v0, v0, v2 clamp 366; GFX10-NEXT: v_pk_sub_i16 v1, v1, v3 clamp 367; GFX10-NEXT: s_setpc_b64 s[30:31] 368 %result = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) 369 %cast = bitcast <4 x i16> %result to <2 x float> 370 ret <2 x float> %cast 371} 372 373define <2 x i32> @v_ssubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { 374; GFX6-LABEL: v_ssubsat_v2i32: 375; GFX6: ; %bb.0: 376; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 377; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v2 378; GFX6-NEXT: v_sub_i32_e64 v2, s[4:5], v0, v2 379; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0 380; GFX6-NEXT: v_bfrev_b32_e32 v4, 1 381; GFX6-NEXT: v_bfrev_b32_e32 v5, -2 382; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v2 383; GFX6-NEXT: v_cndmask_b32_e64 v0, v4, v5, s[6:7] 384; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 385; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc 386; GFX6-NEXT: v_sub_i32_e64 v2, s[4:5], v1, v3 387; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v3 388; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v1 389; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v2 390; GFX6-NEXT: v_cndmask_b32_e64 v1, v4, v5, s[6:7] 391; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 392; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc 393; GFX6-NEXT: s_setpc_b64 s[30:31] 394; 395; GFX8-LABEL: v_ssubsat_v2i32: 396; GFX8: ; %bb.0: 397; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 398; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v2 399; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v0, v2 400; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0 401; GFX8-NEXT: v_bfrev_b32_e32 v4, 1 402; GFX8-NEXT: v_bfrev_b32_e32 v5, -2 403; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v2 404; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, v5, s[6:7] 405; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 406; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc 407; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v1, v3 408; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v3 409; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v1 410; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v2 411; GFX8-NEXT: v_cndmask_b32_e64 v1, v4, v5, s[6:7] 412; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 413; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc 414; GFX8-NEXT: s_setpc_b64 s[30:31] 415; 416; GFX9-LABEL: v_ssubsat_v2i32: 417; GFX9: ; %bb.0: 418; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 419; GFX9-NEXT: v_sub_i32 v0, v0, v2 clamp 420; GFX9-NEXT: v_sub_i32 v1, v1, v3 clamp 421; GFX9-NEXT: s_setpc_b64 s[30:31] 422; 423; GFX10-LABEL: v_ssubsat_v2i32: 424; GFX10: ; %bb.0: 425; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 426; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 427; GFX10-NEXT: v_sub_nc_i32 v0, v0, v2 clamp 428; GFX10-NEXT: v_sub_nc_i32 v1, v1, v3 clamp 429; GFX10-NEXT: s_setpc_b64 s[30:31] 430 %result = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) 431 ret <2 x i32> %result 432} 433 434define <3 x i32> @v_ssubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) { 435; GFX6-LABEL: v_ssubsat_v3i32: 436; GFX6: ; %bb.0: 437; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 438; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v3 439; GFX6-NEXT: v_sub_i32_e64 v3, s[4:5], v0, v3 440; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v0 441; GFX6-NEXT: v_bfrev_b32_e32 v6, 1 442; GFX6-NEXT: v_bfrev_b32_e32 v7, -2 443; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v3 444; GFX6-NEXT: v_cndmask_b32_e64 v0, v6, v7, s[6:7] 445; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 446; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc 447; GFX6-NEXT: v_sub_i32_e64 v3, s[4:5], v1, v4 448; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v4 449; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v1 450; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v3 451; GFX6-NEXT: v_cndmask_b32_e64 v1, v6, v7, s[6:7] 452; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 453; GFX6-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc 454; GFX6-NEXT: v_sub_i32_e64 v3, s[4:5], v2, v5 455; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v5 456; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v2 457; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v3 458; GFX6-NEXT: v_cndmask_b32_e64 v2, v6, v7, s[6:7] 459; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 460; GFX6-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc 461; GFX6-NEXT: s_setpc_b64 s[30:31] 462; 463; GFX8-LABEL: v_ssubsat_v3i32: 464; GFX8: ; %bb.0: 465; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 466; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v3 467; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v0, v3 468; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v0 469; GFX8-NEXT: v_bfrev_b32_e32 v6, 1 470; GFX8-NEXT: v_bfrev_b32_e32 v7, -2 471; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v3 472; GFX8-NEXT: v_cndmask_b32_e64 v0, v6, v7, s[6:7] 473; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 474; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc 475; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v1, v4 476; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v4 477; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v1 478; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v3 479; GFX8-NEXT: v_cndmask_b32_e64 v1, v6, v7, s[6:7] 480; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 481; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc 482; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v2, v5 483; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v5 484; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v2 485; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v3 486; GFX8-NEXT: v_cndmask_b32_e64 v2, v6, v7, s[6:7] 487; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 488; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc 489; GFX8-NEXT: s_setpc_b64 s[30:31] 490; 491; GFX9-LABEL: v_ssubsat_v3i32: 492; GFX9: ; %bb.0: 493; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 494; GFX9-NEXT: v_sub_i32 v0, v0, v3 clamp 495; GFX9-NEXT: v_sub_i32 v1, v1, v4 clamp 496; GFX9-NEXT: v_sub_i32 v2, v2, v5 clamp 497; GFX9-NEXT: s_setpc_b64 s[30:31] 498; 499; GFX10-LABEL: v_ssubsat_v3i32: 500; GFX10: ; %bb.0: 501; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 502; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 503; GFX10-NEXT: v_sub_nc_i32 v0, v0, v3 clamp 504; GFX10-NEXT: v_sub_nc_i32 v1, v1, v4 clamp 505; GFX10-NEXT: v_sub_nc_i32 v2, v2, v5 clamp 506; GFX10-NEXT: s_setpc_b64 s[30:31] 507 %result = call <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs) 508 ret <3 x i32> %result 509} 510 511define <4 x i32> @v_ssubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) { 512; GFX6-LABEL: v_ssubsat_v4i32: 513; GFX6: ; %bb.0: 514; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 515; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v4 516; GFX6-NEXT: v_sub_i32_e64 v4, s[4:5], v0, v4 517; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v0 518; GFX6-NEXT: v_bfrev_b32_e32 v8, 1 519; GFX6-NEXT: v_bfrev_b32_e32 v9, -2 520; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v4 521; GFX6-NEXT: v_cndmask_b32_e64 v0, v8, v9, s[6:7] 522; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 523; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc 524; GFX6-NEXT: v_sub_i32_e64 v4, s[4:5], v1, v5 525; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v5 526; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v1 527; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v4 528; GFX6-NEXT: v_cndmask_b32_e64 v1, v8, v9, s[6:7] 529; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 530; GFX6-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc 531; GFX6-NEXT: v_sub_i32_e64 v4, s[4:5], v2, v6 532; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v6 533; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v2 534; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v4 535; GFX6-NEXT: v_cndmask_b32_e64 v2, v8, v9, s[6:7] 536; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 537; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc 538; GFX6-NEXT: v_sub_i32_e64 v4, s[4:5], v3, v7 539; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v7 540; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v3 541; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v4 542; GFX6-NEXT: v_cndmask_b32_e64 v3, v8, v9, s[6:7] 543; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 544; GFX6-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc 545; GFX6-NEXT: s_setpc_b64 s[30:31] 546; 547; GFX8-LABEL: v_ssubsat_v4i32: 548; GFX8: ; %bb.0: 549; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 550; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v4 551; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v0, v4 552; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v0 553; GFX8-NEXT: v_bfrev_b32_e32 v8, 1 554; GFX8-NEXT: v_bfrev_b32_e32 v9, -2 555; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v4 556; GFX8-NEXT: v_cndmask_b32_e64 v0, v8, v9, s[6:7] 557; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 558; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc 559; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v1, v5 560; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v5 561; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v1 562; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v4 563; GFX8-NEXT: v_cndmask_b32_e64 v1, v8, v9, s[6:7] 564; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 565; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc 566; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v2, v6 567; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v6 568; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v2 569; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v4 570; GFX8-NEXT: v_cndmask_b32_e64 v2, v8, v9, s[6:7] 571; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 572; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc 573; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v3, v7 574; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v7 575; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v3 576; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v4 577; GFX8-NEXT: v_cndmask_b32_e64 v3, v8, v9, s[6:7] 578; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 579; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc 580; GFX8-NEXT: s_setpc_b64 s[30:31] 581; 582; GFX9-LABEL: v_ssubsat_v4i32: 583; GFX9: ; %bb.0: 584; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 585; GFX9-NEXT: v_sub_i32 v0, v0, v4 clamp 586; GFX9-NEXT: v_sub_i32 v1, v1, v5 clamp 587; GFX9-NEXT: v_sub_i32 v2, v2, v6 clamp 588; GFX9-NEXT: v_sub_i32 v3, v3, v7 clamp 589; GFX9-NEXT: s_setpc_b64 s[30:31] 590; 591; GFX10-LABEL: v_ssubsat_v4i32: 592; GFX10: ; %bb.0: 593; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 594; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 595; GFX10-NEXT: v_sub_nc_i32 v0, v0, v4 clamp 596; GFX10-NEXT: v_sub_nc_i32 v1, v1, v5 clamp 597; GFX10-NEXT: v_sub_nc_i32 v2, v2, v6 clamp 598; GFX10-NEXT: v_sub_nc_i32 v3, v3, v7 clamp 599; GFX10-NEXT: s_setpc_b64 s[30:31] 600 %result = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) 601 ret <4 x i32> %result 602} 603 604define <8 x i32> @v_ssubsat_v8i32(<8 x i32> %lhs, <8 x i32> %rhs) { 605; GFX6-LABEL: v_ssubsat_v8i32: 606; GFX6: ; %bb.0: 607; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 608; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v8 609; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v0, v8 610; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v0 611; GFX6-NEXT: v_bfrev_b32_e32 v16, 1 612; GFX6-NEXT: v_bfrev_b32_e32 v17, -2 613; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 614; GFX6-NEXT: v_cndmask_b32_e64 v0, v16, v17, s[6:7] 615; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 616; GFX6-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc 617; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v1, v9 618; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v9 619; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v1 620; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 621; GFX6-NEXT: v_cndmask_b32_e64 v1, v16, v17, s[6:7] 622; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 623; GFX6-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc 624; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v2, v10 625; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v10 626; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v2 627; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 628; GFX6-NEXT: v_cndmask_b32_e64 v2, v16, v17, s[6:7] 629; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 630; GFX6-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc 631; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v3, v11 632; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v11 633; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v3 634; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 635; GFX6-NEXT: v_cndmask_b32_e64 v3, v16, v17, s[6:7] 636; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 637; GFX6-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc 638; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v4, v12 639; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v12 640; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v4 641; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 642; GFX6-NEXT: v_cndmask_b32_e64 v4, v16, v17, s[6:7] 643; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 644; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc 645; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v5, v13 646; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v13 647; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v5 648; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 649; GFX6-NEXT: v_cndmask_b32_e64 v5, v16, v17, s[6:7] 650; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 651; GFX6-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc 652; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v6, v14 653; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v14 654; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v6 655; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 656; GFX6-NEXT: v_cndmask_b32_e64 v6, v16, v17, s[6:7] 657; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 658; GFX6-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc 659; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v7, v15 660; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v15 661; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v7 662; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 663; GFX6-NEXT: v_cndmask_b32_e64 v7, v16, v17, s[6:7] 664; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 665; GFX6-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc 666; GFX6-NEXT: s_setpc_b64 s[30:31] 667; 668; GFX8-LABEL: v_ssubsat_v8i32: 669; GFX8: ; %bb.0: 670; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 671; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v8 672; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v0, v8 673; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v0 674; GFX8-NEXT: v_bfrev_b32_e32 v16, 1 675; GFX8-NEXT: v_bfrev_b32_e32 v17, -2 676; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 677; GFX8-NEXT: v_cndmask_b32_e64 v0, v16, v17, s[6:7] 678; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 679; GFX8-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc 680; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v1, v9 681; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v9 682; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v1 683; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 684; GFX8-NEXT: v_cndmask_b32_e64 v1, v16, v17, s[6:7] 685; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 686; GFX8-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc 687; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v2, v10 688; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v10 689; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v2 690; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 691; GFX8-NEXT: v_cndmask_b32_e64 v2, v16, v17, s[6:7] 692; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 693; GFX8-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc 694; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v3, v11 695; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v11 696; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v3 697; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 698; GFX8-NEXT: v_cndmask_b32_e64 v3, v16, v17, s[6:7] 699; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 700; GFX8-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc 701; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v4, v12 702; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v12 703; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v4 704; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 705; GFX8-NEXT: v_cndmask_b32_e64 v4, v16, v17, s[6:7] 706; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 707; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc 708; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v5, v13 709; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v13 710; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v5 711; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 712; GFX8-NEXT: v_cndmask_b32_e64 v5, v16, v17, s[6:7] 713; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 714; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc 715; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v6, v14 716; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v14 717; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v6 718; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 719; GFX8-NEXT: v_cndmask_b32_e64 v6, v16, v17, s[6:7] 720; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 721; GFX8-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc 722; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v7, v15 723; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v15 724; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v7 725; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 726; GFX8-NEXT: v_cndmask_b32_e64 v7, v16, v17, s[6:7] 727; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 728; GFX8-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc 729; GFX8-NEXT: s_setpc_b64 s[30:31] 730; 731; GFX9-LABEL: v_ssubsat_v8i32: 732; GFX9: ; %bb.0: 733; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 734; GFX9-NEXT: v_sub_i32 v0, v0, v8 clamp 735; GFX9-NEXT: v_sub_i32 v1, v1, v9 clamp 736; GFX9-NEXT: v_sub_i32 v2, v2, v10 clamp 737; GFX9-NEXT: v_sub_i32 v3, v3, v11 clamp 738; GFX9-NEXT: v_sub_i32 v4, v4, v12 clamp 739; GFX9-NEXT: v_sub_i32 v5, v5, v13 clamp 740; GFX9-NEXT: v_sub_i32 v6, v6, v14 clamp 741; GFX9-NEXT: v_sub_i32 v7, v7, v15 clamp 742; GFX9-NEXT: s_setpc_b64 s[30:31] 743; 744; GFX10-LABEL: v_ssubsat_v8i32: 745; GFX10: ; %bb.0: 746; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 747; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 748; GFX10-NEXT: v_sub_nc_i32 v0, v0, v8 clamp 749; GFX10-NEXT: v_sub_nc_i32 v1, v1, v9 clamp 750; GFX10-NEXT: v_sub_nc_i32 v2, v2, v10 clamp 751; GFX10-NEXT: v_sub_nc_i32 v3, v3, v11 clamp 752; GFX10-NEXT: v_sub_nc_i32 v4, v4, v12 clamp 753; GFX10-NEXT: v_sub_nc_i32 v5, v5, v13 clamp 754; GFX10-NEXT: v_sub_nc_i32 v6, v6, v14 clamp 755; GFX10-NEXT: v_sub_nc_i32 v7, v7, v15 clamp 756; GFX10-NEXT: s_setpc_b64 s[30:31] 757 %result = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> %lhs, <8 x i32> %rhs) 758 ret <8 x i32> %result 759} 760 761define <16 x i32> @v_ssubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) { 762; GFX6-LABEL: v_ssubsat_v16i32: 763; GFX6: ; %bb.0: 764; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 765; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v16 766; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v0, v16 767; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v0 768; GFX6-NEXT: v_bfrev_b32_e32 v32, 1 769; GFX6-NEXT: v_bfrev_b32_e32 v33, -2 770; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 771; GFX6-NEXT: v_cndmask_b32_e64 v0, v32, v33, s[6:7] 772; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 773; GFX6-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc 774; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v1, v17 775; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v17 776; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v1 777; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 778; GFX6-NEXT: v_cndmask_b32_e64 v1, v32, v33, s[6:7] 779; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 780; GFX6-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc 781; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v2, v18 782; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v18 783; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v2 784; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 785; GFX6-NEXT: v_cndmask_b32_e64 v2, v32, v33, s[6:7] 786; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 787; GFX6-NEXT: v_cndmask_b32_e32 v2, v16, v2, vcc 788; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v3, v19 789; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v19 790; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v3 791; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 792; GFX6-NEXT: v_cndmask_b32_e64 v3, v32, v33, s[6:7] 793; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 794; GFX6-NEXT: v_cndmask_b32_e32 v3, v16, v3, vcc 795; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v4, v20 796; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v20 797; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v4 798; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 799; GFX6-NEXT: v_cndmask_b32_e64 v4, v32, v33, s[6:7] 800; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 801; GFX6-NEXT: v_cndmask_b32_e32 v4, v16, v4, vcc 802; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v5, v21 803; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v21 804; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v5 805; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 806; GFX6-NEXT: v_cndmask_b32_e64 v5, v32, v33, s[6:7] 807; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 808; GFX6-NEXT: v_cndmask_b32_e32 v5, v16, v5, vcc 809; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v6, v22 810; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v22 811; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v6 812; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 813; GFX6-NEXT: v_cndmask_b32_e64 v6, v32, v33, s[6:7] 814; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 815; GFX6-NEXT: v_cndmask_b32_e32 v6, v16, v6, vcc 816; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v7, v23 817; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v23 818; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v7 819; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 820; GFX6-NEXT: v_cndmask_b32_e64 v7, v32, v33, s[6:7] 821; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 822; GFX6-NEXT: v_cndmask_b32_e32 v7, v16, v7, vcc 823; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v8, v24 824; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v24 825; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v8 826; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 827; GFX6-NEXT: v_cndmask_b32_e64 v8, v32, v33, s[6:7] 828; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 829; GFX6-NEXT: v_cndmask_b32_e32 v8, v16, v8, vcc 830; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v9, v25 831; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v25 832; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v9 833; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 834; GFX6-NEXT: v_cndmask_b32_e64 v9, v32, v33, s[6:7] 835; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 836; GFX6-NEXT: v_cndmask_b32_e32 v9, v16, v9, vcc 837; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v10, v26 838; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v26 839; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v10 840; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 841; GFX6-NEXT: v_cndmask_b32_e64 v10, v32, v33, s[6:7] 842; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 843; GFX6-NEXT: v_cndmask_b32_e32 v10, v16, v10, vcc 844; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v11, v27 845; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v27 846; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v11 847; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 848; GFX6-NEXT: v_cndmask_b32_e64 v11, v32, v33, s[6:7] 849; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 850; GFX6-NEXT: v_cndmask_b32_e32 v11, v16, v11, vcc 851; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v12, v28 852; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v28 853; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v12 854; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 855; GFX6-NEXT: v_cndmask_b32_e64 v12, v32, v33, s[6:7] 856; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 857; GFX6-NEXT: v_cndmask_b32_e32 v12, v16, v12, vcc 858; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v13, v29 859; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v29 860; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v13 861; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 862; GFX6-NEXT: v_cndmask_b32_e64 v13, v32, v33, s[6:7] 863; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 864; GFX6-NEXT: v_cndmask_b32_e32 v13, v16, v13, vcc 865; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v14, v30 866; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v30 867; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v14 868; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 869; GFX6-NEXT: v_cndmask_b32_e64 v14, v32, v33, s[6:7] 870; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 871; GFX6-NEXT: v_cndmask_b32_e32 v14, v16, v14, vcc 872; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v15, v31 873; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v31 874; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v15 875; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 876; GFX6-NEXT: v_cndmask_b32_e64 v15, v32, v33, s[6:7] 877; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] 878; GFX6-NEXT: v_cndmask_b32_e32 v15, v16, v15, vcc 879; GFX6-NEXT: s_setpc_b64 s[30:31] 880; 881; GFX8-LABEL: v_ssubsat_v16i32: 882; GFX8: ; %bb.0: 883; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 884; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v16 885; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v0, v16 886; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v0 887; GFX8-NEXT: v_bfrev_b32_e32 v32, 1 888; GFX8-NEXT: v_bfrev_b32_e32 v33, -2 889; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 890; GFX8-NEXT: v_cndmask_b32_e64 v0, v32, v33, s[6:7] 891; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 892; GFX8-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc 893; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v1, v17 894; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v17 895; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v1 896; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 897; GFX8-NEXT: v_cndmask_b32_e64 v1, v32, v33, s[6:7] 898; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 899; GFX8-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc 900; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v2, v18 901; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v18 902; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v2 903; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 904; GFX8-NEXT: v_cndmask_b32_e64 v2, v32, v33, s[6:7] 905; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 906; GFX8-NEXT: v_cndmask_b32_e32 v2, v16, v2, vcc 907; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v3, v19 908; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v19 909; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v3 910; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 911; GFX8-NEXT: v_cndmask_b32_e64 v3, v32, v33, s[6:7] 912; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 913; GFX8-NEXT: v_cndmask_b32_e32 v3, v16, v3, vcc 914; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v4, v20 915; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v20 916; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v4 917; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 918; GFX8-NEXT: v_cndmask_b32_e64 v4, v32, v33, s[6:7] 919; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 920; GFX8-NEXT: v_cndmask_b32_e32 v4, v16, v4, vcc 921; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v5, v21 922; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v21 923; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v5 924; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 925; GFX8-NEXT: v_cndmask_b32_e64 v5, v32, v33, s[6:7] 926; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 927; GFX8-NEXT: v_cndmask_b32_e32 v5, v16, v5, vcc 928; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v6, v22 929; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v22 930; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v6 931; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 932; GFX8-NEXT: v_cndmask_b32_e64 v6, v32, v33, s[6:7] 933; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 934; GFX8-NEXT: v_cndmask_b32_e32 v6, v16, v6, vcc 935; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v7, v23 936; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v23 937; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v7 938; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 939; GFX8-NEXT: v_cndmask_b32_e64 v7, v32, v33, s[6:7] 940; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 941; GFX8-NEXT: v_cndmask_b32_e32 v7, v16, v7, vcc 942; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v8, v24 943; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v24 944; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v8 945; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 946; GFX8-NEXT: v_cndmask_b32_e64 v8, v32, v33, s[6:7] 947; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 948; GFX8-NEXT: v_cndmask_b32_e32 v8, v16, v8, vcc 949; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v9, v25 950; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v25 951; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v9 952; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 953; GFX8-NEXT: v_cndmask_b32_e64 v9, v32, v33, s[6:7] 954; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 955; GFX8-NEXT: v_cndmask_b32_e32 v9, v16, v9, vcc 956; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v10, v26 957; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v26 958; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v10 959; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 960; GFX8-NEXT: v_cndmask_b32_e64 v10, v32, v33, s[6:7] 961; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 962; GFX8-NEXT: v_cndmask_b32_e32 v10, v16, v10, vcc 963; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v11, v27 964; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v27 965; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v11 966; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 967; GFX8-NEXT: v_cndmask_b32_e64 v11, v32, v33, s[6:7] 968; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 969; GFX8-NEXT: v_cndmask_b32_e32 v11, v16, v11, vcc 970; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v12, v28 971; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v28 972; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v12 973; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 974; GFX8-NEXT: v_cndmask_b32_e64 v12, v32, v33, s[6:7] 975; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 976; GFX8-NEXT: v_cndmask_b32_e32 v12, v16, v12, vcc 977; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v13, v29 978; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v29 979; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v13 980; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 981; GFX8-NEXT: v_cndmask_b32_e64 v13, v32, v33, s[6:7] 982; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 983; GFX8-NEXT: v_cndmask_b32_e32 v13, v16, v13, vcc 984; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v14, v30 985; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v30 986; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v14 987; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 988; GFX8-NEXT: v_cndmask_b32_e64 v14, v32, v33, s[6:7] 989; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 990; GFX8-NEXT: v_cndmask_b32_e32 v14, v16, v14, vcc 991; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v15, v31 992; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v31 993; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v15 994; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 995; GFX8-NEXT: v_cndmask_b32_e64 v15, v32, v33, s[6:7] 996; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] 997; GFX8-NEXT: v_cndmask_b32_e32 v15, v16, v15, vcc 998; GFX8-NEXT: s_setpc_b64 s[30:31] 999; 1000; GFX9-LABEL: v_ssubsat_v16i32: 1001; GFX9: ; %bb.0: 1002; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1003; GFX9-NEXT: v_sub_i32 v0, v0, v16 clamp 1004; GFX9-NEXT: v_sub_i32 v1, v1, v17 clamp 1005; GFX9-NEXT: v_sub_i32 v2, v2, v18 clamp 1006; GFX9-NEXT: v_sub_i32 v3, v3, v19 clamp 1007; GFX9-NEXT: v_sub_i32 v4, v4, v20 clamp 1008; GFX9-NEXT: v_sub_i32 v5, v5, v21 clamp 1009; GFX9-NEXT: v_sub_i32 v6, v6, v22 clamp 1010; GFX9-NEXT: v_sub_i32 v7, v7, v23 clamp 1011; GFX9-NEXT: v_sub_i32 v8, v8, v24 clamp 1012; GFX9-NEXT: v_sub_i32 v9, v9, v25 clamp 1013; GFX9-NEXT: v_sub_i32 v10, v10, v26 clamp 1014; GFX9-NEXT: v_sub_i32 v11, v11, v27 clamp 1015; GFX9-NEXT: v_sub_i32 v12, v12, v28 clamp 1016; GFX9-NEXT: v_sub_i32 v13, v13, v29 clamp 1017; GFX9-NEXT: v_sub_i32 v14, v14, v30 clamp 1018; GFX9-NEXT: v_sub_i32 v15, v15, v31 clamp 1019; GFX9-NEXT: s_setpc_b64 s[30:31] 1020; 1021; GFX10-LABEL: v_ssubsat_v16i32: 1022; GFX10: ; %bb.0: 1023; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1024; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1025; GFX10-NEXT: v_sub_nc_i32 v0, v0, v16 clamp 1026; GFX10-NEXT: v_sub_nc_i32 v1, v1, v17 clamp 1027; GFX10-NEXT: v_sub_nc_i32 v2, v2, v18 clamp 1028; GFX10-NEXT: v_sub_nc_i32 v3, v3, v19 clamp 1029; GFX10-NEXT: v_sub_nc_i32 v4, v4, v20 clamp 1030; GFX10-NEXT: v_sub_nc_i32 v5, v5, v21 clamp 1031; GFX10-NEXT: v_sub_nc_i32 v6, v6, v22 clamp 1032; GFX10-NEXT: v_sub_nc_i32 v7, v7, v23 clamp 1033; GFX10-NEXT: v_sub_nc_i32 v8, v8, v24 clamp 1034; GFX10-NEXT: v_sub_nc_i32 v9, v9, v25 clamp 1035; GFX10-NEXT: v_sub_nc_i32 v10, v10, v26 clamp 1036; GFX10-NEXT: v_sub_nc_i32 v11, v11, v27 clamp 1037; GFX10-NEXT: v_sub_nc_i32 v12, v12, v28 clamp 1038; GFX10-NEXT: v_sub_nc_i32 v13, v13, v29 clamp 1039; GFX10-NEXT: v_sub_nc_i32 v14, v14, v30 clamp 1040; GFX10-NEXT: v_sub_nc_i32 v15, v15, v31 clamp 1041; GFX10-NEXT: s_setpc_b64 s[30:31] 1042 %result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) 1043 ret <16 x i32> %result 1044} 1045 1046 1047define i64 @v_ssubsat_i64(i64 %lhs, i64 %rhs) { 1048; GFX6-LABEL: v_ssubsat_i64: 1049; GFX6: ; %bb.0: 1050; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1051; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v0, v2 1052; GFX6-NEXT: v_subb_u32_e32 v5, vcc, v1, v3, vcc 1053; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1] 1054; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3] 1055; GFX6-NEXT: v_bfrev_b32_e32 v1, 1 1056; GFX6-NEXT: s_xor_b64 vcc, s[4:5], vcc 1057; GFX6-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[4:5] 1058; GFX6-NEXT: v_bfrev_b32_e32 v2, -2 1059; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v5 1060; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[4:5] 1061; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc 1062; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc 1063; GFX6-NEXT: s_setpc_b64 s[30:31] 1064; 1065; GFX8-LABEL: v_ssubsat_i64: 1066; GFX8: ; %bb.0: 1067; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1068; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v0, v2 1069; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v1, v3, vcc 1070; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1] 1071; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3] 1072; GFX8-NEXT: v_bfrev_b32_e32 v1, 1 1073; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc 1074; GFX8-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[4:5] 1075; GFX8-NEXT: v_bfrev_b32_e32 v2, -2 1076; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v5 1077; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[4:5] 1078; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc 1079; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc 1080; GFX8-NEXT: s_setpc_b64 s[30:31] 1081; 1082; GFX9-LABEL: v_ssubsat_i64: 1083; GFX9: ; %bb.0: 1084; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1085; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v0, v2 1086; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v1, v3, vcc 1087; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1] 1088; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3] 1089; GFX9-NEXT: v_bfrev_b32_e32 v1, 1 1090; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc 1091; GFX9-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[4:5] 1092; GFX9-NEXT: v_bfrev_b32_e32 v2, -2 1093; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v5 1094; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[4:5] 1095; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc 1096; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc 1097; GFX9-NEXT: s_setpc_b64 s[30:31] 1098; 1099; GFX10-LABEL: v_ssubsat_i64: 1100; GFX10: ; %bb.0: 1101; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1102; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1103; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v2 1104; GFX10-NEXT: v_bfrev_b32_e32 v6, -2 1105; GFX10-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo 1106; GFX10-NEXT: v_cmp_lt_i64_e64 s4, 0, v[2:3] 1107; GFX10-NEXT: v_cmp_gt_i64_e64 s5, 0, v[4:5] 1108; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1] 1109; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v5 1110; GFX10-NEXT: v_cndmask_b32_e64 v1, 0x80000000, v6, s5 1111; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo 1112; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo 1113; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo 1114; GFX10-NEXT: s_setpc_b64 s[30:31] 1115 %result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs) 1116 ret i64 %result 1117} 1118 1119declare i8 @llvm.ssub.sat.i8(i8, i8) #0 1120declare i16 @llvm.ssub.sat.i16(i16, i16) #0 1121declare <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16>, <2 x i16>) #0 1122declare <3 x i16> @llvm.ssub.sat.v3i16(<3 x i16>, <3 x i16>) #0 1123declare <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16>, <4 x i16>) #0 1124declare i32 @llvm.ssub.sat.i32(i32, i32) #0 1125declare <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32>, <2 x i32>) #0 1126declare <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32>, <3 x i32>) #0 1127declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>) #0 1128declare <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32>, <8 x i32>) #0 1129declare <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32>, <16 x i32>) #0 1130declare i64 @llvm.ssub.sat.i64(i64, i64) #0 1131 1132attributes #0 = { nounwind readnone speculatable willreturn } 1133