1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_srem(i64 addrspace(1)* %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_srem:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
9; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
10; GCN-NEXT:    s_mov_b32 s7, 0xf000
11; GCN-NEXT:    s_mov_b32 s6, -1
12; GCN-NEXT:    s_waitcnt lgkmcnt(0)
13; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
14; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
15; GCN-NEXT:    s_sub_u32 s0, 0, s12
16; GCN-NEXT:    s_subb_u32 s1, 0, s13
17; GCN-NEXT:    s_mov_b32 s4, s8
18; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
19; GCN-NEXT:    v_rcp_f32_e32 v0, v0
20; GCN-NEXT:    v_mov_b32_e32 v1, 0
21; GCN-NEXT:    s_mov_b32 s5, s9
22; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
23; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
24; GCN-NEXT:    v_trunc_f32_e32 v2, v2
25; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
26; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
27; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
28; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
29; GCN-NEXT:    v_mul_hi_u32 v4, s0, v0
30; GCN-NEXT:    v_mul_lo_u32 v6, s1, v0
31; GCN-NEXT:    v_mul_lo_u32 v5, s0, v0
32; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
33; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
34; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
35; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
36; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
37; GCN-NEXT:    v_mul_lo_u32 v7, v2, v5
38; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
39; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
40; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
41; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
42; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
43; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
44; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
45; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
46; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
47; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
48; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
49; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
50; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
51; GCN-NEXT:    v_mul_hi_u32 v4, s0, v0
52; GCN-NEXT:    v_mul_lo_u32 v5, s1, v0
53; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
54; GCN-NEXT:    v_mul_lo_u32 v4, s0, v0
55; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
56; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
57; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
58; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
59; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
60; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
61; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
62; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
63; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
64; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
65; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
66; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
67; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v1, vcc
68; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
69; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
70; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
71; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
72; GCN-NEXT:    v_mul_lo_u32 v3, s10, v2
73; GCN-NEXT:    v_mul_hi_u32 v4, s10, v0
74; GCN-NEXT:    v_mul_hi_u32 v5, s10, v2
75; GCN-NEXT:    v_mul_hi_u32 v6, s11, v2
76; GCN-NEXT:    v_mul_lo_u32 v2, s11, v2
77; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
78; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
79; GCN-NEXT:    v_mul_lo_u32 v5, s11, v0
80; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
81; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
82; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
83; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
84; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
85; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
86; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
87; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
88; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
89; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
90; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
91; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
92; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s11, v1
93; GCN-NEXT:    v_mov_b32_e32 v3, s13
94; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s10, v0
95; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
96; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
97; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
98; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
99; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
100; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
101; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
102; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
103; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
104; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
105; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
106; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
107; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
108; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
109; GCN-NEXT:    v_mov_b32_e32 v5, s11
110; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
111; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
112; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
113; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
114; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
115; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
116; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
117; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
118; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
119; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
120; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
121; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
122; GCN-NEXT:    s_endpgm
123;
124; GCN-IR-LABEL: s_test_srem:
125; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
126; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
127; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
128; GCN-IR-NEXT:    s_mov_b64 s[6:7], 0
129; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
130; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[4:5], 0
131; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
132; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s4
133; GCN-IR-NEXT:    s_or_b64 s[14:15], s[8:9], s[10:11]
134; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s2
135; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
136; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s5
137; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
138; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s3
139; GCN-IR-NEXT:    s_min_u32 s8, s12, s8
140; GCN-IR-NEXT:    s_min_u32 s12, s10, s11
141; GCN-IR-NEXT:    s_sub_u32 s10, s8, s12
142; GCN-IR-NEXT:    s_subb_u32 s11, 0, 0
143; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[16:17], s[10:11], 63
144; GCN-IR-NEXT:    s_mov_b32 s9, 0
145; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[16:17]
146; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[16:17], s[10:11], 63
147; GCN-IR-NEXT:    s_xor_b64 s[18:19], s[14:15], -1
148; GCN-IR-NEXT:    s_and_b64 s[16:17], s[18:19], s[16:17]
149; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[16:17]
150; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_5
151; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
152; GCN-IR-NEXT:    s_add_u32 s14, s10, 1
153; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
154; GCN-IR-NEXT:    s_addc_u32 s15, s11, 0
155; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
156; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[14:15], v[0:1]
157; GCN-IR-NEXT:    s_sub_i32 s10, 63, s10
158; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
159; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[2:3], s10
160; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_4
161; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
162; GCN-IR-NEXT:    s_lshr_b64 s[14:15], s[2:3], s14
163; GCN-IR-NEXT:    s_add_u32 s16, s4, -1
164; GCN-IR-NEXT:    s_addc_u32 s17, s5, -1
165; GCN-IR-NEXT:    s_not_b64 s[6:7], s[8:9]
166; GCN-IR-NEXT:    s_mov_b32 s13, s9
167; GCN-IR-NEXT:    s_add_u32 s8, s6, s12
168; GCN-IR-NEXT:    s_addc_u32 s9, s7, s9
169; GCN-IR-NEXT:    s_mov_b64 s[12:13], 0
170; GCN-IR-NEXT:    s_mov_b32 s7, 0
171; GCN-IR-NEXT:  .LBB0_3: ; %udiv-do-while
172; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
173; GCN-IR-NEXT:    s_lshl_b64 s[14:15], s[14:15], 1
174; GCN-IR-NEXT:    s_lshr_b32 s6, s11, 31
175; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
176; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[6:7]
177; GCN-IR-NEXT:    s_or_b64 s[10:11], s[12:13], s[10:11]
178; GCN-IR-NEXT:    s_sub_u32 s6, s16, s14
179; GCN-IR-NEXT:    s_subb_u32 s6, s17, s15
180; GCN-IR-NEXT:    s_ashr_i32 s12, s6, 31
181; GCN-IR-NEXT:    s_mov_b32 s13, s12
182; GCN-IR-NEXT:    s_and_b32 s6, s12, 1
183; GCN-IR-NEXT:    s_and_b64 s[18:19], s[12:13], s[4:5]
184; GCN-IR-NEXT:    s_sub_u32 s14, s14, s18
185; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
186; GCN-IR-NEXT:    s_subb_u32 s15, s15, s19
187; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
188; GCN-IR-NEXT:    s_add_u32 s8, s8, 1
189; GCN-IR-NEXT:    s_addc_u32 s9, s9, 0
190; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
191; GCN-IR-NEXT:    s_mov_b64 s[12:13], s[6:7]
192; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_3
193; GCN-IR-NEXT:  .LBB0_4: ; %Flow6
194; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[10:11], 1
195; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], s[8:9]
196; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
197; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
198; GCN-IR-NEXT:    s_branch .LBB0_6
199; GCN-IR-NEXT:  .LBB0_5:
200; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
201; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[14:15]
202; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
203; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[14:15]
204; GCN-IR-NEXT:  .LBB0_6: ; %udiv-end
205; GCN-IR-NEXT:    v_mul_lo_u32 v1, s4, v1
206; GCN-IR-NEXT:    v_mul_hi_u32 v2, s4, v0
207; GCN-IR-NEXT:    v_mul_lo_u32 v3, s5, v0
208; GCN-IR-NEXT:    v_mul_lo_u32 v0, s4, v0
209; GCN-IR-NEXT:    s_mov_b32 s11, 0xf000
210; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
211; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
212; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
213; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
214; GCN-IR-NEXT:    s_mov_b32 s10, -1
215; GCN-IR-NEXT:    s_mov_b32 s8, s0
216; GCN-IR-NEXT:    s_mov_b32 s9, s1
217; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
218; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
219; GCN-IR-NEXT:    s_endpgm
220  %result = urem i64 %x, %y
221  store i64 %result, i64 addrspace(1)* %out
222  ret void
223}
224
225define i64 @v_test_srem(i64 %x, i64 %y) {
226; GCN-LABEL: v_test_srem:
227; GCN:       ; %bb.0:
228; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
229; GCN-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
230; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
231; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
232; GCN-NEXT:    v_xor_b32_e32 v3, v3, v4
233; GCN-NEXT:    v_xor_b32_e32 v2, v2, v4
234; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v2
235; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v3
236; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v2
237; GCN-NEXT:    v_subb_u32_e32 v7, vcc, 0, v3, vcc
238; GCN-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
239; GCN-NEXT:    v_rcp_f32_e32 v4, v4
240; GCN-NEXT:    v_mov_b32_e32 v13, 0
241; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
242; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
243; GCN-NEXT:    v_trunc_f32_e32 v5, v5
244; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
245; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
246; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
247; GCN-NEXT:    v_mul_hi_u32 v8, v6, v4
248; GCN-NEXT:    v_mul_lo_u32 v9, v6, v5
249; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
250; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
251; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
252; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
253; GCN-NEXT:    v_mul_lo_u32 v10, v4, v8
254; GCN-NEXT:    v_mul_hi_u32 v11, v4, v9
255; GCN-NEXT:    v_mul_hi_u32 v12, v4, v8
256; GCN-NEXT:    v_mul_hi_u32 v14, v5, v8
257; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
258; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
259; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
260; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
261; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
262; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
263; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v11, v9, vcc
264; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v13, vcc
265; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
266; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
267; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
268; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v9, vcc
269; GCN-NEXT:    v_mul_lo_u32 v8, v6, v5
270; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
271; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
272; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
273; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
274; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
275; GCN-NEXT:    v_mul_lo_u32 v10, v4, v7
276; GCN-NEXT:    v_mul_hi_u32 v11, v4, v6
277; GCN-NEXT:    v_mul_hi_u32 v12, v4, v7
278; GCN-NEXT:    v_mul_hi_u32 v9, v5, v6
279; GCN-NEXT:    v_mul_lo_u32 v6, v5, v6
280; GCN-NEXT:    v_mul_hi_u32 v8, v5, v7
281; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
282; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
283; GCN-NEXT:    v_mul_lo_u32 v7, v5, v7
284; GCN-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
285; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
286; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v8, v13, vcc
287; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
288; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
289; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
290; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
291; GCN-NEXT:    v_ashrrev_i32_e32 v6, 31, v1
292; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
293; GCN-NEXT:    v_xor_b32_e32 v0, v0, v6
294; GCN-NEXT:    v_mul_lo_u32 v7, v0, v5
295; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
296; GCN-NEXT:    v_mul_hi_u32 v9, v0, v5
297; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v6, vcc
298; GCN-NEXT:    v_xor_b32_e32 v1, v1, v6
299; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
300; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
301; GCN-NEXT:    v_mul_lo_u32 v9, v1, v4
302; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
303; GCN-NEXT:    v_mul_hi_u32 v10, v1, v5
304; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
305; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
306; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
307; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v10, v13, vcc
308; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
309; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
310; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
311; GCN-NEXT:    v_mul_hi_u32 v7, v2, v4
312; GCN-NEXT:    v_mul_lo_u32 v8, v3, v4
313; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
314; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
315; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
316; GCN-NEXT:    v_sub_i32_e32 v7, vcc, v1, v5
317; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
318; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v7, v3, vcc
319; GCN-NEXT:    v_sub_i32_e64 v7, s[4:5], v0, v2
320; GCN-NEXT:    v_subbrev_u32_e64 v8, s[6:7], 0, v4, s[4:5]
321; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v8, v3
322; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[6:7]
323; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v7, v2
324; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
325; GCN-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[6:7]
326; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v8, v3
327; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v3, s[4:5]
328; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
329; GCN-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[6:7]
330; GCN-NEXT:    v_sub_i32_e64 v10, s[4:5], v7, v2
331; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
332; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
333; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
334; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
335; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
336; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v9
337; GCN-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
338; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
339; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v10, s[4:5]
340; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v4, s[4:5]
341; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
342; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
343; GCN-NEXT:    v_xor_b32_e32 v0, v0, v6
344; GCN-NEXT:    v_xor_b32_e32 v1, v1, v6
345; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
346; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
347; GCN-NEXT:    s_setpc_b64 s[30:31]
348;
349; GCN-IR-LABEL: v_test_srem:
350; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
351; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
352; GCN-IR-NEXT:    v_ashrrev_i32_e32 v4, 31, v1
353; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v4
354; GCN-IR-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
355; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v4
356; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
357; GCN-IR-NEXT:    v_xor_b32_e32 v2, v2, v6
358; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc
359; GCN-IR-NEXT:    v_xor_b32_e32 v3, v3, v6
360; GCN-IR-NEXT:    v_sub_i32_e32 v5, vcc, v2, v6
361; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v3, v6, vcc
362; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[5:6]
363; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
364; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v5
365; GCN-IR-NEXT:    s_or_b64 s[6:7], vcc, s[4:5]
366; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, 32, v3
367; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v6
368; GCN-IR-NEXT:    v_min_u32_e32 v3, v3, v7
369; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v0
370; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 32, v7
371; GCN-IR-NEXT:    v_ffbh_u32_e32 v8, v1
372; GCN-IR-NEXT:    v_min_u32_e32 v12, v7, v8
373; GCN-IR-NEXT:    v_sub_i32_e32 v7, vcc, v3, v12
374; GCN-IR-NEXT:    v_subb_u32_e64 v8, s[4:5], 0, 0, vcc
375; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[7:8]
376; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[4:5], 63, v[7:8]
377; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], vcc
378; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
379; GCN-IR-NEXT:    s_xor_b64 s[8:9], s[6:7], -1
380; GCN-IR-NEXT:    v_mov_b32_e32 v2, v4
381; GCN-IR-NEXT:    v_mov_b32_e32 v13, v11
382; GCN-IR-NEXT:    v_cndmask_b32_e64 v10, v1, 0, s[6:7]
383; GCN-IR-NEXT:    s_and_b64 s[4:5], s[8:9], s[4:5]
384; GCN-IR-NEXT:    v_cndmask_b32_e64 v9, v0, 0, s[6:7]
385; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
386; GCN-IR-NEXT:    s_cbranch_execz .LBB1_6
387; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
388; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, 1, v7
389; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, 0, v8, vcc
390; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[14:15], v[7:8]
391; GCN-IR-NEXT:    v_sub_i32_e64 v7, s[4:5], 63, v7
392; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[0:1], v7
393; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
394; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
395; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
396; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
397; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
398; GCN-IR-NEXT:    s_cbranch_execz .LBB1_5
399; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
400; GCN-IR-NEXT:    v_add_i32_e32 v18, vcc, -1, v5
401; GCN-IR-NEXT:    v_addc_u32_e32 v19, vcc, -1, v6, vcc
402; GCN-IR-NEXT:    v_not_b32_e32 v3, v3
403; GCN-IR-NEXT:    v_lshr_b64 v[14:15], v[0:1], v14
404; GCN-IR-NEXT:    v_not_b32_e32 v9, v11
405; GCN-IR-NEXT:    v_add_i32_e32 v11, vcc, v3, v12
406; GCN-IR-NEXT:    v_mov_b32_e32 v16, 0
407; GCN-IR-NEXT:    v_addc_u32_e32 v12, vcc, v9, v13, vcc
408; GCN-IR-NEXT:    v_mov_b32_e32 v17, 0
409; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
410; GCN-IR-NEXT:  .LBB1_3: ; %udiv-do-while
411; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
412; GCN-IR-NEXT:    v_lshl_b64 v[14:15], v[14:15], 1
413; GCN-IR-NEXT:    v_lshrrev_b32_e32 v3, 31, v8
414; GCN-IR-NEXT:    v_or_b32_e32 v3, v14, v3
415; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
416; GCN-IR-NEXT:    v_sub_i32_e32 v9, vcc, v18, v3
417; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, v19, v15, vcc
418; GCN-IR-NEXT:    v_or_b32_e32 v7, v16, v7
419; GCN-IR-NEXT:    v_add_i32_e32 v16, vcc, 1, v11
420; GCN-IR-NEXT:    v_or_b32_e32 v8, v17, v8
421; GCN-IR-NEXT:    v_ashrrev_i32_e32 v13, 31, v9
422; GCN-IR-NEXT:    v_addc_u32_e32 v17, vcc, 0, v12, vcc
423; GCN-IR-NEXT:    v_and_b32_e32 v9, 1, v13
424; GCN-IR-NEXT:    v_and_b32_e32 v20, v13, v6
425; GCN-IR-NEXT:    v_and_b32_e32 v13, v13, v5
426; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[16:17], v[11:12]
427; GCN-IR-NEXT:    v_mov_b32_e32 v11, v16
428; GCN-IR-NEXT:    v_sub_i32_e64 v14, s[4:5], v3, v13
429; GCN-IR-NEXT:    v_mov_b32_e32 v12, v17
430; GCN-IR-NEXT:    v_mov_b32_e32 v17, v10
431; GCN-IR-NEXT:    v_subb_u32_e64 v15, s[4:5], v15, v20, s[4:5]
432; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
433; GCN-IR-NEXT:    v_mov_b32_e32 v16, v9
434; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
435; GCN-IR-NEXT:    s_cbranch_execnz .LBB1_3
436; GCN-IR-NEXT:  ; %bb.4: ; %Flow
437; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
438; GCN-IR-NEXT:  .LBB1_5: ; %Flow3
439; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
440; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
441; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v8
442; GCN-IR-NEXT:    v_or_b32_e32 v9, v9, v7
443; GCN-IR-NEXT:  .LBB1_6: ; %Flow4
444; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
445; GCN-IR-NEXT:    v_mul_lo_u32 v3, v5, v10
446; GCN-IR-NEXT:    v_mul_hi_u32 v7, v5, v9
447; GCN-IR-NEXT:    v_mul_lo_u32 v6, v6, v9
448; GCN-IR-NEXT:    v_mul_lo_u32 v5, v5, v9
449; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
450; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
451; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v5
452; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
453; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v4
454; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
455; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
456; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
457; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
458  %result = srem i64 %x, %y
459  ret i64 %result
460}
461
462define amdgpu_kernel void @s_test_srem23_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
463; GCN-LABEL: s_test_srem23_64:
464; GCN:       ; %bb.0:
465; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
466; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
467; GCN-NEXT:    s_mov_b32 s7, 0xf000
468; GCN-NEXT:    s_mov_b32 s6, -1
469; GCN-NEXT:    s_waitcnt lgkmcnt(0)
470; GCN-NEXT:    s_ashr_i64 s[4:5], s[4:5], 41
471; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
472; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 41
473; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s2
474; GCN-NEXT:    s_xor_b32 s3, s2, s4
475; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
476; GCN-NEXT:    s_ashr_i32 s3, s3, 30
477; GCN-NEXT:    s_or_b32 s3, s3, 1
478; GCN-NEXT:    v_mov_b32_e32 v3, s3
479; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
480; GCN-NEXT:    v_trunc_f32_e32 v2, v2
481; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
482; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
483; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
484; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
485; GCN-NEXT:    s_mov_b32 s5, s1
486; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
487; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
488; GCN-NEXT:    s_mov_b32 s4, s0
489; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
490; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 23
491; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
492; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
493; GCN-NEXT:    s_endpgm
494;
495; GCN-IR-LABEL: s_test_srem23_64:
496; GCN-IR:       ; %bb.0:
497; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
498; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
499; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
500; GCN-IR-NEXT:    s_mov_b32 s6, -1
501; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
502; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[4:5], 41
503; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
504; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 41
505; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s2
506; GCN-IR-NEXT:    s_xor_b32 s3, s2, s4
507; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
508; GCN-IR-NEXT:    s_ashr_i32 s3, s3, 30
509; GCN-IR-NEXT:    s_or_b32 s3, s3, 1
510; GCN-IR-NEXT:    v_mov_b32_e32 v3, s3
511; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
512; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
513; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
514; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
515; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
516; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
517; GCN-IR-NEXT:    s_mov_b32 s5, s1
518; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
519; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
520; GCN-IR-NEXT:    s_mov_b32 s4, s0
521; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
522; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 23
523; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
524; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
525; GCN-IR-NEXT:    s_endpgm
526  %1 = ashr i64 %x, 41
527  %2 = ashr i64 %y, 41
528  %result = srem i64 %1, %2
529  store i64 %result, i64 addrspace(1)* %out
530  ret void
531}
532
533define amdgpu_kernel void @s_test_srem24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
534; GCN-LABEL: s_test_srem24_64:
535; GCN:       ; %bb.0:
536; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
537; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
538; GCN-NEXT:    s_mov_b32 s7, 0xf000
539; GCN-NEXT:    s_mov_b32 s6, -1
540; GCN-NEXT:    s_waitcnt lgkmcnt(0)
541; GCN-NEXT:    s_ashr_i64 s[4:5], s[4:5], 40
542; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
543; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
544; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s2
545; GCN-NEXT:    s_xor_b32 s3, s2, s4
546; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
547; GCN-NEXT:    s_ashr_i32 s3, s3, 30
548; GCN-NEXT:    s_or_b32 s3, s3, 1
549; GCN-NEXT:    v_mov_b32_e32 v3, s3
550; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
551; GCN-NEXT:    v_trunc_f32_e32 v2, v2
552; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
553; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
554; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
555; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
556; GCN-NEXT:    s_mov_b32 s5, s1
557; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
558; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
559; GCN-NEXT:    s_mov_b32 s4, s0
560; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
561; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
562; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
563; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
564; GCN-NEXT:    s_endpgm
565;
566; GCN-IR-LABEL: s_test_srem24_64:
567; GCN-IR:       ; %bb.0:
568; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
569; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
570; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
571; GCN-IR-NEXT:    s_mov_b32 s6, -1
572; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
573; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[4:5], 40
574; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
575; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
576; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s2
577; GCN-IR-NEXT:    s_xor_b32 s3, s2, s4
578; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
579; GCN-IR-NEXT:    s_ashr_i32 s3, s3, 30
580; GCN-IR-NEXT:    s_or_b32 s3, s3, 1
581; GCN-IR-NEXT:    v_mov_b32_e32 v3, s3
582; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
583; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
584; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
585; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
586; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
587; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
588; GCN-IR-NEXT:    s_mov_b32 s5, s1
589; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
590; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
591; GCN-IR-NEXT:    s_mov_b32 s4, s0
592; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
593; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
594; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
595; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
596; GCN-IR-NEXT:    s_endpgm
597  %1 = ashr i64 %x, 40
598  %2 = ashr i64 %y, 40
599  %result = srem i64 %1, %2
600  store i64 %result, i64 addrspace(1)* %out
601  ret void
602}
603
604define i64 @v_test_srem24_64(i64 %x, i64 %y) {
605; GCN-LABEL: v_test_srem24_64:
606; GCN:       ; %bb.0:
607; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
608; GCN-NEXT:    v_ashr_i64 v[2:3], v[2:3], 40
609; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
610; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
611; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
612; GCN-NEXT:    v_xor_b32_e32 v5, v0, v2
613; GCN-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
614; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v3
615; GCN-NEXT:    v_or_b32_e32 v5, 1, v5
616; GCN-NEXT:    v_mul_f32_e32 v4, v1, v4
617; GCN-NEXT:    v_trunc_f32_e32 v4, v4
618; GCN-NEXT:    v_mad_f32 v1, -v4, v3, v1
619; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
620; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
621; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
622; GCN-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
623; GCN-NEXT:    v_mul_lo_u32 v1, v1, v2
624; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
625; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
626; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
627; GCN-NEXT:    s_setpc_b64 s[30:31]
628;
629; GCN-IR-LABEL: v_test_srem24_64:
630; GCN-IR:       ; %bb.0:
631; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
632; GCN-IR-NEXT:    v_ashr_i64 v[2:3], v[2:3], 40
633; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
634; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v3, v2
635; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
636; GCN-IR-NEXT:    v_xor_b32_e32 v5, v0, v2
637; GCN-IR-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
638; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v4, v3
639; GCN-IR-NEXT:    v_or_b32_e32 v5, 1, v5
640; GCN-IR-NEXT:    v_mul_f32_e32 v4, v1, v4
641; GCN-IR-NEXT:    v_trunc_f32_e32 v4, v4
642; GCN-IR-NEXT:    v_mad_f32 v1, -v4, v3, v1
643; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v4, v4
644; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
645; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
646; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
647; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v2
648; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
649; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
650; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
651; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
652  %1 = ashr i64 %x, 40
653  %2 = ashr i64 %y, 40
654  %result = srem i64 %1, %2
655  ret i64 %result
656}
657
658define amdgpu_kernel void @s_test_srem25_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
659; GCN-LABEL: s_test_srem25_64:
660; GCN:       ; %bb.0:
661; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
662; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
663; GCN-NEXT:    s_mov_b32 s7, 0xf000
664; GCN-NEXT:    s_mov_b32 s6, -1
665; GCN-NEXT:    s_waitcnt lgkmcnt(0)
666; GCN-NEXT:    s_ashr_i64 s[4:5], s[4:5], 39
667; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
668; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 39
669; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s2
670; GCN-NEXT:    s_xor_b32 s3, s2, s4
671; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
672; GCN-NEXT:    s_ashr_i32 s3, s3, 30
673; GCN-NEXT:    s_or_b32 s3, s3, 1
674; GCN-NEXT:    v_mov_b32_e32 v3, s3
675; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
676; GCN-NEXT:    v_trunc_f32_e32 v2, v2
677; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
678; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
679; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
680; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
681; GCN-NEXT:    s_mov_b32 s5, s1
682; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
683; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
684; GCN-NEXT:    s_mov_b32 s4, s0
685; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
686; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 25
687; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
688; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
689; GCN-NEXT:    s_endpgm
690;
691; GCN-IR-LABEL: s_test_srem25_64:
692; GCN-IR:       ; %bb.0:
693; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
694; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
695; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
696; GCN-IR-NEXT:    s_mov_b32 s6, -1
697; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
698; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[4:5], 39
699; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
700; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 39
701; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s2
702; GCN-IR-NEXT:    s_xor_b32 s3, s2, s4
703; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
704; GCN-IR-NEXT:    s_ashr_i32 s3, s3, 30
705; GCN-IR-NEXT:    s_or_b32 s3, s3, 1
706; GCN-IR-NEXT:    v_mov_b32_e32 v3, s3
707; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
708; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
709; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
710; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
711; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
712; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
713; GCN-IR-NEXT:    s_mov_b32 s5, s1
714; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
715; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
716; GCN-IR-NEXT:    s_mov_b32 s4, s0
717; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
718; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 25
719; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
720; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
721; GCN-IR-NEXT:    s_endpgm
722  %1 = ashr i64 %x, 39
723  %2 = ashr i64 %y, 39
724  %result = srem i64 %1, %2
725  store i64 %result, i64 addrspace(1)* %out
726  ret void
727}
728
729define amdgpu_kernel void @s_test_srem31_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
730; GCN-LABEL: s_test_srem31_64:
731; GCN:       ; %bb.0:
732; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
733; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
734; GCN-NEXT:    s_mov_b32 s7, 0xf000
735; GCN-NEXT:    s_mov_b32 s6, -1
736; GCN-NEXT:    s_waitcnt lgkmcnt(0)
737; GCN-NEXT:    s_ashr_i64 s[4:5], s[4:5], 33
738; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
739; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 33
740; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s2
741; GCN-NEXT:    s_xor_b32 s3, s2, s4
742; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
743; GCN-NEXT:    s_ashr_i32 s3, s3, 30
744; GCN-NEXT:    s_or_b32 s3, s3, 1
745; GCN-NEXT:    v_mov_b32_e32 v3, s3
746; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
747; GCN-NEXT:    v_trunc_f32_e32 v2, v2
748; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
749; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
750; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
751; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
752; GCN-NEXT:    s_mov_b32 s5, s1
753; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
754; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
755; GCN-NEXT:    s_mov_b32 s4, s0
756; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
757; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 31
758; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
759; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
760; GCN-NEXT:    s_endpgm
761;
762; GCN-IR-LABEL: s_test_srem31_64:
763; GCN-IR:       ; %bb.0:
764; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
765; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
766; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
767; GCN-IR-NEXT:    s_mov_b32 s6, -1
768; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
769; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[4:5], 33
770; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
771; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 33
772; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s2
773; GCN-IR-NEXT:    s_xor_b32 s3, s2, s4
774; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
775; GCN-IR-NEXT:    s_ashr_i32 s3, s3, 30
776; GCN-IR-NEXT:    s_or_b32 s3, s3, 1
777; GCN-IR-NEXT:    v_mov_b32_e32 v3, s3
778; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
779; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
780; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
781; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
782; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
783; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
784; GCN-IR-NEXT:    s_mov_b32 s5, s1
785; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
786; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
787; GCN-IR-NEXT:    s_mov_b32 s4, s0
788; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
789; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 31
790; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
791; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
792; GCN-IR-NEXT:    s_endpgm
793  %1 = ashr i64 %x, 33
794  %2 = ashr i64 %y, 33
795  %result = srem i64 %1, %2
796  store i64 %result, i64 addrspace(1)* %out
797  ret void
798}
799
800; 32 known sign bits
801define amdgpu_kernel void @s_test_srem32_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
802; GCN-LABEL: s_test_srem32_64:
803; GCN:       ; %bb.0:
804; GCN-NEXT:    s_load_dword s4, s[0:1], 0xe
805; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
806; GCN-NEXT:    s_mov_b32 s7, 0xf000
807; GCN-NEXT:    s_mov_b32 s6, -1
808; GCN-NEXT:    s_waitcnt lgkmcnt(0)
809; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
810; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s3
811; GCN-NEXT:    s_xor_b32 s2, s3, s4
812; GCN-NEXT:    s_ashr_i32 s2, s2, 30
813; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
814; GCN-NEXT:    s_or_b32 s2, s2, 1
815; GCN-NEXT:    v_mov_b32_e32 v3, s2
816; GCN-NEXT:    s_mov_b32 s5, s1
817; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
818; GCN-NEXT:    v_trunc_f32_e32 v2, v2
819; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
820; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
821; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
822; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
823; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
824; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
825; GCN-NEXT:    s_mov_b32 s4, s0
826; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s3, v0
827; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
828; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
829; GCN-NEXT:    s_endpgm
830;
831; GCN-IR-LABEL: s_test_srem32_64:
832; GCN-IR:       ; %bb.0:
833; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xe
834; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
835; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
836; GCN-IR-NEXT:    s_mov_b32 s6, -1
837; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
838; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
839; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s3
840; GCN-IR-NEXT:    s_xor_b32 s2, s3, s4
841; GCN-IR-NEXT:    s_ashr_i32 s2, s2, 30
842; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
843; GCN-IR-NEXT:    s_or_b32 s2, s2, 1
844; GCN-IR-NEXT:    v_mov_b32_e32 v3, s2
845; GCN-IR-NEXT:    s_mov_b32 s5, s1
846; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
847; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
848; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
849; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
850; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
851; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
852; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
853; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
854; GCN-IR-NEXT:    s_mov_b32 s4, s0
855; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s3, v0
856; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
857; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
858; GCN-IR-NEXT:    s_endpgm
859  %1 = ashr i64 %x, 32
860  %2 = ashr i64 %y, 32
861  %result = srem i64 %1, %2
862  store i64 %result, i64 addrspace(1)* %out
863  ret void
864}
865
866; 33 known sign bits
867define amdgpu_kernel void @s_test_srem33_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
868; GCN-LABEL: s_test_srem33_64:
869; GCN:       ; %bb.0:
870; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
871; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
872; GCN-NEXT:    v_mov_b32_e32 v6, 0
873; GCN-NEXT:    s_mov_b32 s7, 0xf000
874; GCN-NEXT:    s_mov_b32 s6, -1
875; GCN-NEXT:    s_waitcnt lgkmcnt(0)
876; GCN-NEXT:    s_ashr_i64 s[2:3], s[10:11], 31
877; GCN-NEXT:    s_ashr_i64 s[4:5], s[0:1], 31
878; GCN-NEXT:    s_ashr_i32 s0, s1, 31
879; GCN-NEXT:    s_add_u32 s4, s4, s0
880; GCN-NEXT:    s_mov_b32 s1, s0
881; GCN-NEXT:    s_addc_u32 s5, s5, s0
882; GCN-NEXT:    s_xor_b64 s[12:13], s[4:5], s[0:1]
883; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
884; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
885; GCN-NEXT:    s_sub_u32 s0, 0, s12
886; GCN-NEXT:    s_subb_u32 s1, 0, s13
887; GCN-NEXT:    s_ashr_i32 s10, s11, 31
888; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
889; GCN-NEXT:    v_rcp_f32_e32 v0, v0
890; GCN-NEXT:    s_mov_b32 s11, s10
891; GCN-NEXT:    s_mov_b32 s4, s8
892; GCN-NEXT:    s_mov_b32 s5, s9
893; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
894; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
895; GCN-NEXT:    v_trunc_f32_e32 v1, v1
896; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
897; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
898; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
899; GCN-NEXT:    v_mul_lo_u32 v2, s0, v1
900; GCN-NEXT:    v_mul_hi_u32 v3, s0, v0
901; GCN-NEXT:    v_mul_lo_u32 v5, s1, v0
902; GCN-NEXT:    v_mul_lo_u32 v4, s0, v0
903; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
904; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
905; GCN-NEXT:    v_mul_hi_u32 v3, v0, v4
906; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
907; GCN-NEXT:    v_mul_hi_u32 v7, v0, v2
908; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
909; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
910; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
911; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
912; GCN-NEXT:    v_mul_lo_u32 v7, v1, v4
913; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
914; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
915; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
916; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
917; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
918; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
919; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
920; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
921; GCN-NEXT:    v_mul_lo_u32 v2, s0, v1
922; GCN-NEXT:    v_mul_hi_u32 v3, s0, v0
923; GCN-NEXT:    v_mul_lo_u32 v4, s1, v0
924; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
925; GCN-NEXT:    v_mul_lo_u32 v3, s0, v0
926; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
927; GCN-NEXT:    v_mul_lo_u32 v7, v0, v2
928; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
929; GCN-NEXT:    v_mul_hi_u32 v9, v0, v2
930; GCN-NEXT:    v_mul_hi_u32 v5, v1, v3
931; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
932; GCN-NEXT:    v_mul_hi_u32 v4, v1, v2
933; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
934; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
935; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
936; GCN-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
937; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v5, vcc
938; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
939; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
940; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
941; GCN-NEXT:    s_add_u32 s0, s2, s10
942; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
943; GCN-NEXT:    s_addc_u32 s1, s3, s10
944; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
945; GCN-NEXT:    s_xor_b64 s[14:15], s[0:1], s[10:11]
946; GCN-NEXT:    v_mul_lo_u32 v2, s14, v1
947; GCN-NEXT:    v_mul_hi_u32 v3, s14, v0
948; GCN-NEXT:    v_mul_hi_u32 v4, s14, v1
949; GCN-NEXT:    v_mul_hi_u32 v5, s15, v1
950; GCN-NEXT:    v_mul_lo_u32 v1, s15, v1
951; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
952; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
953; GCN-NEXT:    v_mul_lo_u32 v4, s15, v0
954; GCN-NEXT:    v_mul_hi_u32 v0, s15, v0
955; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
956; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
957; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v6, vcc
958; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
959; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
960; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
961; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
962; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
963; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
964; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
965; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
966; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s15, v1
967; GCN-NEXT:    v_mov_b32_e32 v3, s13
968; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s14, v0
969; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
970; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
971; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
972; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
973; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
974; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
975; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
976; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
977; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
978; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
979; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
980; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
981; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
982; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
983; GCN-NEXT:    v_mov_b32_e32 v5, s15
984; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
985; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
986; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
987; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
988; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
989; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
990; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
991; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
992; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
993; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
994; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
995; GCN-NEXT:    v_xor_b32_e32 v0, s10, v0
996; GCN-NEXT:    v_xor_b32_e32 v1, s10, v1
997; GCN-NEXT:    v_mov_b32_e32 v2, s10
998; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s10, v0
999; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1000; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1001; GCN-NEXT:    s_endpgm
1002;
1003; GCN-IR-LABEL: s_test_srem33_64:
1004; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1005; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1006; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
1007; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1008; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[6:7], 31
1009; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 31
1010; GCN-IR-NEXT:    s_ashr_i32 s0, s7, 31
1011; GCN-IR-NEXT:    s_ashr_i32 s6, s1, 31
1012; GCN-IR-NEXT:    s_mov_b32 s1, s0
1013; GCN-IR-NEXT:    s_mov_b32 s7, s6
1014; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[2:3], s[0:1]
1015; GCN-IR-NEXT:    s_xor_b64 s[8:9], s[8:9], s[6:7]
1016; GCN-IR-NEXT:    s_sub_u32 s2, s2, s0
1017; GCN-IR-NEXT:    s_subb_u32 s3, s3, s0
1018; GCN-IR-NEXT:    s_sub_u32 s8, s8, s6
1019; GCN-IR-NEXT:    s_subb_u32 s9, s9, s6
1020; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[8:9], 0
1021; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[2:3], 0
1022; GCN-IR-NEXT:    s_mov_b64 s[6:7], 0
1023; GCN-IR-NEXT:    s_or_b64 s[16:17], s[10:11], s[12:13]
1024; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s8
1025; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s2
1026; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
1027; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s9
1028; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
1029; GCN-IR-NEXT:    s_flbit_i32_b32 s13, s3
1030; GCN-IR-NEXT:    s_min_u32 s10, s10, s11
1031; GCN-IR-NEXT:    s_min_u32 s14, s12, s13
1032; GCN-IR-NEXT:    s_sub_u32 s12, s10, s14
1033; GCN-IR-NEXT:    s_subb_u32 s13, 0, 0
1034; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[18:19], s[12:13], 63
1035; GCN-IR-NEXT:    s_mov_b32 s11, 0
1036; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[18:19]
1037; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[18:19], s[12:13], 63
1038; GCN-IR-NEXT:    s_xor_b64 s[20:21], s[16:17], -1
1039; GCN-IR-NEXT:    s_and_b64 s[18:19], s[20:21], s[18:19]
1040; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[18:19]
1041; GCN-IR-NEXT:    s_cbranch_vccz .LBB8_5
1042; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1043; GCN-IR-NEXT:    s_add_u32 s16, s12, 1
1044; GCN-IR-NEXT:    v_mov_b32_e32 v0, s12
1045; GCN-IR-NEXT:    s_addc_u32 s17, s13, 0
1046; GCN-IR-NEXT:    v_mov_b32_e32 v1, s13
1047; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[16:17], v[0:1]
1048; GCN-IR-NEXT:    s_sub_i32 s12, 63, s12
1049; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1050; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[2:3], s12
1051; GCN-IR-NEXT:    s_cbranch_vccz .LBB8_4
1052; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1053; GCN-IR-NEXT:    s_lshr_b64 s[16:17], s[2:3], s16
1054; GCN-IR-NEXT:    s_add_u32 s18, s8, -1
1055; GCN-IR-NEXT:    s_addc_u32 s19, s9, -1
1056; GCN-IR-NEXT:    s_not_b64 s[6:7], s[10:11]
1057; GCN-IR-NEXT:    s_mov_b32 s15, s11
1058; GCN-IR-NEXT:    s_add_u32 s10, s6, s14
1059; GCN-IR-NEXT:    s_addc_u32 s11, s7, s11
1060; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
1061; GCN-IR-NEXT:    s_mov_b32 s7, 0
1062; GCN-IR-NEXT:  .LBB8_3: ; %udiv-do-while
1063; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1064; GCN-IR-NEXT:    s_lshl_b64 s[16:17], s[16:17], 1
1065; GCN-IR-NEXT:    s_lshr_b32 s6, s13, 31
1066; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
1067; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[6:7]
1068; GCN-IR-NEXT:    s_or_b64 s[12:13], s[14:15], s[12:13]
1069; GCN-IR-NEXT:    s_sub_u32 s6, s18, s16
1070; GCN-IR-NEXT:    s_subb_u32 s6, s19, s17
1071; GCN-IR-NEXT:    s_ashr_i32 s14, s6, 31
1072; GCN-IR-NEXT:    s_mov_b32 s15, s14
1073; GCN-IR-NEXT:    s_and_b32 s6, s14, 1
1074; GCN-IR-NEXT:    s_and_b64 s[20:21], s[14:15], s[8:9]
1075; GCN-IR-NEXT:    s_sub_u32 s16, s16, s20
1076; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1077; GCN-IR-NEXT:    s_subb_u32 s17, s17, s21
1078; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
1079; GCN-IR-NEXT:    s_add_u32 s10, s10, 1
1080; GCN-IR-NEXT:    s_addc_u32 s11, s11, 0
1081; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
1082; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[6:7]
1083; GCN-IR-NEXT:    s_cbranch_vccz .LBB8_3
1084; GCN-IR-NEXT:  .LBB8_4: ; %Flow6
1085; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[12:13], 1
1086; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], s[10:11]
1087; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1088; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
1089; GCN-IR-NEXT:    s_branch .LBB8_6
1090; GCN-IR-NEXT:  .LBB8_5:
1091; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
1092; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[16:17]
1093; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1094; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[16:17]
1095; GCN-IR-NEXT:  .LBB8_6: ; %udiv-end
1096; GCN-IR-NEXT:    v_mul_lo_u32 v1, s8, v1
1097; GCN-IR-NEXT:    v_mul_hi_u32 v2, s8, v0
1098; GCN-IR-NEXT:    v_mul_lo_u32 v3, s9, v0
1099; GCN-IR-NEXT:    v_mul_lo_u32 v0, s8, v0
1100; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1101; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1102; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1103; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
1104; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1105; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
1106; GCN-IR-NEXT:    v_xor_b32_e32 v0, s0, v0
1107; GCN-IR-NEXT:    v_xor_b32_e32 v1, s1, v1
1108; GCN-IR-NEXT:    v_mov_b32_e32 v2, s1
1109; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
1110; GCN-IR-NEXT:    s_mov_b32 s6, -1
1111; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1112; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1113; GCN-IR-NEXT:    s_endpgm
1114  %1 = ashr i64 %x, 31
1115  %2 = ashr i64 %y, 31
1116  %result = srem i64 %1, %2
1117  store i64 %result, i64 addrspace(1)* %out
1118  ret void
1119}
1120
1121define amdgpu_kernel void @s_test_srem24_48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
1122; GCN-LABEL: s_test_srem24_48:
1123; GCN:       ; %bb.0:
1124; GCN-NEXT:    s_load_dword s2, s[0:1], 0xc
1125; GCN-NEXT:    s_load_dword s3, s[0:1], 0xe
1126; GCN-NEXT:    s_load_dword s6, s[0:1], 0xd
1127; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
1128; GCN-NEXT:    s_load_dword s0, s[0:1], 0xb
1129; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1130; GCN-NEXT:    s_sext_i32_i16 s1, s2
1131; GCN-NEXT:    s_sext_i32_i16 s2, s3
1132; GCN-NEXT:    v_mov_b32_e32 v0, s6
1133; GCN-NEXT:    v_alignbit_b32 v0, s2, v0, 24
1134; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
1135; GCN-NEXT:    v_mov_b32_e32 v2, s0
1136; GCN-NEXT:    v_alignbit_b32 v2, s1, v2, 24
1137; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
1138; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v1
1139; GCN-NEXT:    v_xor_b32_e32 v5, v2, v0
1140; GCN-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
1141; GCN-NEXT:    v_or_b32_e32 v5, 1, v5
1142; GCN-NEXT:    v_mul_f32_e32 v4, v3, v4
1143; GCN-NEXT:    v_trunc_f32_e32 v4, v4
1144; GCN-NEXT:    v_mad_f32 v3, -v4, v1, v3
1145; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
1146; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1147; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
1148; GCN-NEXT:    s_mov_b32 s7, 0xf000
1149; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
1150; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
1151; GCN-NEXT:    s_mov_b32 s6, -1
1152; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v2, v0
1153; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1154; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1155; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
1156; GCN-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
1157; GCN-NEXT:    s_endpgm
1158;
1159; GCN-IR-LABEL: s_test_srem24_48:
1160; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1161; GCN-IR-NEXT:    s_load_dword s3, s[0:1], 0xc
1162; GCN-IR-NEXT:    s_load_dword s5, s[0:1], 0xe
1163; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xb
1164; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xd
1165; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
1166; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1167; GCN-IR-NEXT:    s_sext_i32_i16 s3, s3
1168; GCN-IR-NEXT:    s_sext_i32_i16 s5, s5
1169; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[2:3], 24
1170; GCN-IR-NEXT:    s_ashr_i32 s2, s3, 31
1171; GCN-IR-NEXT:    s_ashr_i32 s10, s5, 31
1172; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[4:5], 24
1173; GCN-IR-NEXT:    s_mov_b32 s3, s2
1174; GCN-IR-NEXT:    s_mov_b32 s11, s10
1175; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[6:7], s[2:3]
1176; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[8:9], s[10:11]
1177; GCN-IR-NEXT:    s_sub_u32 s4, s4, s2
1178; GCN-IR-NEXT:    s_subb_u32 s5, s5, s2
1179; GCN-IR-NEXT:    s_sub_u32 s6, s6, s10
1180; GCN-IR-NEXT:    s_subb_u32 s7, s7, s10
1181; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
1182; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[4:5], 0
1183; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1184; GCN-IR-NEXT:    s_or_b64 s[16:17], s[10:11], s[12:13]
1185; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s6
1186; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s4
1187; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
1188; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s7
1189; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
1190; GCN-IR-NEXT:    s_flbit_i32_b32 s13, s5
1191; GCN-IR-NEXT:    s_min_u32 s10, s10, s11
1192; GCN-IR-NEXT:    s_min_u32 s14, s12, s13
1193; GCN-IR-NEXT:    s_sub_u32 s12, s10, s14
1194; GCN-IR-NEXT:    s_subb_u32 s13, 0, 0
1195; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[18:19], s[12:13], 63
1196; GCN-IR-NEXT:    s_mov_b32 s11, 0
1197; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[18:19]
1198; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[18:19], s[12:13], 63
1199; GCN-IR-NEXT:    s_xor_b64 s[20:21], s[16:17], -1
1200; GCN-IR-NEXT:    s_and_b64 s[18:19], s[20:21], s[18:19]
1201; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[18:19]
1202; GCN-IR-NEXT:    s_cbranch_vccz .LBB9_5
1203; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1204; GCN-IR-NEXT:    s_add_u32 s16, s12, 1
1205; GCN-IR-NEXT:    v_mov_b32_e32 v0, s12
1206; GCN-IR-NEXT:    s_addc_u32 s17, s13, 0
1207; GCN-IR-NEXT:    v_mov_b32_e32 v1, s13
1208; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[16:17], v[0:1]
1209; GCN-IR-NEXT:    s_sub_i32 s12, 63, s12
1210; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1211; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[4:5], s12
1212; GCN-IR-NEXT:    s_cbranch_vccz .LBB9_4
1213; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1214; GCN-IR-NEXT:    s_lshr_b64 s[16:17], s[4:5], s16
1215; GCN-IR-NEXT:    s_add_u32 s18, s6, -1
1216; GCN-IR-NEXT:    s_addc_u32 s19, s7, -1
1217; GCN-IR-NEXT:    s_not_b64 s[8:9], s[10:11]
1218; GCN-IR-NEXT:    s_mov_b32 s15, s11
1219; GCN-IR-NEXT:    s_add_u32 s10, s8, s14
1220; GCN-IR-NEXT:    s_addc_u32 s11, s9, s11
1221; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
1222; GCN-IR-NEXT:    s_mov_b32 s9, 0
1223; GCN-IR-NEXT:  .LBB9_3: ; %udiv-do-while
1224; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1225; GCN-IR-NEXT:    s_lshl_b64 s[16:17], s[16:17], 1
1226; GCN-IR-NEXT:    s_lshr_b32 s8, s13, 31
1227; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
1228; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[8:9]
1229; GCN-IR-NEXT:    s_or_b64 s[12:13], s[14:15], s[12:13]
1230; GCN-IR-NEXT:    s_sub_u32 s8, s18, s16
1231; GCN-IR-NEXT:    s_subb_u32 s8, s19, s17
1232; GCN-IR-NEXT:    s_ashr_i32 s14, s8, 31
1233; GCN-IR-NEXT:    s_mov_b32 s15, s14
1234; GCN-IR-NEXT:    s_and_b32 s8, s14, 1
1235; GCN-IR-NEXT:    s_and_b64 s[20:21], s[14:15], s[6:7]
1236; GCN-IR-NEXT:    s_sub_u32 s16, s16, s20
1237; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1238; GCN-IR-NEXT:    s_subb_u32 s17, s17, s21
1239; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
1240; GCN-IR-NEXT:    s_add_u32 s10, s10, 1
1241; GCN-IR-NEXT:    s_addc_u32 s11, s11, 0
1242; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
1243; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[8:9]
1244; GCN-IR-NEXT:    s_cbranch_vccz .LBB9_3
1245; GCN-IR-NEXT:  .LBB9_4: ; %Flow3
1246; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[12:13], 1
1247; GCN-IR-NEXT:    s_or_b64 s[8:9], s[8:9], s[10:11]
1248; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
1249; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
1250; GCN-IR-NEXT:    s_branch .LBB9_6
1251; GCN-IR-NEXT:  .LBB9_5:
1252; GCN-IR-NEXT:    v_mov_b32_e32 v0, s5
1253; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[16:17]
1254; GCN-IR-NEXT:    v_mov_b32_e32 v0, s4
1255; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[16:17]
1256; GCN-IR-NEXT:  .LBB9_6: ; %udiv-end
1257; GCN-IR-NEXT:    v_mul_lo_u32 v1, s6, v1
1258; GCN-IR-NEXT:    v_mul_hi_u32 v2, s6, v0
1259; GCN-IR-NEXT:    v_mul_lo_u32 v3, s7, v0
1260; GCN-IR-NEXT:    v_mul_lo_u32 v0, s6, v0
1261; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1262; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1263; GCN-IR-NEXT:    v_mov_b32_e32 v2, s5
1264; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
1265; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
1266; GCN-IR-NEXT:    v_xor_b32_e32 v0, s2, v0
1267; GCN-IR-NEXT:    v_xor_b32_e32 v1, s3, v1
1268; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
1269; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
1270; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1271; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1272; GCN-IR-NEXT:    s_mov_b32 s2, -1
1273; GCN-IR-NEXT:    buffer_store_short v1, off, s[0:3], 0 offset:4
1274; GCN-IR-NEXT:    buffer_store_dword v0, off, s[0:3], 0
1275; GCN-IR-NEXT:    s_endpgm
1276  %1 = ashr i48 %x, 24
1277  %2 = ashr i48 %y, 24
1278  %result = srem i48 %1, %2
1279  store i48 %result, i48 addrspace(1)* %out
1280  ret void
1281}
1282
1283define amdgpu_kernel void @s_test_srem_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1284; GCN-LABEL: s_test_srem_k_num_i64:
1285; GCN:       ; %bb.0:
1286; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1287; GCN-NEXT:    s_mov_b32 s7, 0xf000
1288; GCN-NEXT:    s_mov_b32 s6, -1
1289; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1290; GCN-NEXT:    s_ashr_i32 s4, s3, 31
1291; GCN-NEXT:    s_add_u32 s2, s2, s4
1292; GCN-NEXT:    s_mov_b32 s5, s4
1293; GCN-NEXT:    s_addc_u32 s3, s3, s4
1294; GCN-NEXT:    s_xor_b64 s[8:9], s[2:3], s[4:5]
1295; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
1296; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s9
1297; GCN-NEXT:    s_sub_u32 s2, 0, s8
1298; GCN-NEXT:    s_subb_u32 s3, 0, s9
1299; GCN-NEXT:    s_mov_b32 s4, s0
1300; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
1301; GCN-NEXT:    v_rcp_f32_e32 v0, v0
1302; GCN-NEXT:    v_mov_b32_e32 v1, 0
1303; GCN-NEXT:    s_mov_b32 s5, s1
1304; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
1305; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
1306; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1307; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
1308; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1309; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
1310; GCN-NEXT:    v_mul_lo_u32 v3, s2, v2
1311; GCN-NEXT:    v_mul_hi_u32 v4, s2, v0
1312; GCN-NEXT:    v_mul_lo_u32 v6, s3, v0
1313; GCN-NEXT:    v_mul_lo_u32 v5, s2, v0
1314; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1315; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
1316; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
1317; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
1318; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
1319; GCN-NEXT:    v_mul_hi_u32 v7, v2, v5
1320; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
1321; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
1322; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
1323; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
1324; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
1325; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1326; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v7, vcc
1327; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
1328; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1329; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
1330; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
1331; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
1332; GCN-NEXT:    v_mul_lo_u32 v3, s2, v2
1333; GCN-NEXT:    v_mul_hi_u32 v4, s2, v0
1334; GCN-NEXT:    v_mul_lo_u32 v5, s3, v0
1335; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1336; GCN-NEXT:    v_mul_lo_u32 v4, s2, v0
1337; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
1338; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
1339; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
1340; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
1341; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
1342; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
1343; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
1344; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1345; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
1346; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
1347; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
1348; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
1349; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v5, v1, vcc
1350; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1351; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1352; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
1353; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
1354; GCN-NEXT:    v_mul_lo_u32 v2, v1, 24
1355; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
1356; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
1357; GCN-NEXT:    v_mov_b32_e32 v3, s9
1358; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1359; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v1, vcc
1360; GCN-NEXT:    v_mul_lo_u32 v1, s9, v0
1361; GCN-NEXT:    v_mul_hi_u32 v2, s8, v0
1362; GCN-NEXT:    v_mul_lo_u32 v0, s8, v0
1363; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1364; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
1365; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1366; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
1367; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s8, v0
1368; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
1369; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s9, v5
1370; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
1371; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s8, v4
1372; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
1373; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
1374; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s9, v5
1375; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s8, v4
1376; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
1377; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
1378; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1379; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
1380; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
1381; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
1382; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
1383; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
1384; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1385; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v1
1386; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
1387; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
1388; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1389; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
1390; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1391; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1392; GCN-NEXT:    s_endpgm
1393;
1394; GCN-IR-LABEL: s_test_srem_k_num_i64:
1395; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1396; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1397; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1398; GCN-IR-NEXT:    s_ashr_i32 s6, s3, 31
1399; GCN-IR-NEXT:    s_mov_b32 s7, s6
1400; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[2:3], s[6:7]
1401; GCN-IR-NEXT:    s_sub_u32 s4, s2, s6
1402; GCN-IR-NEXT:    s_subb_u32 s5, s3, s6
1403; GCN-IR-NEXT:    s_flbit_i32_b32 s2, s4
1404; GCN-IR-NEXT:    s_add_i32 s2, s2, 32
1405; GCN-IR-NEXT:    s_flbit_i32_b32 s3, s5
1406; GCN-IR-NEXT:    s_min_u32 s6, s2, s3
1407; GCN-IR-NEXT:    s_add_u32 s8, s6, 0xffffffc5
1408; GCN-IR-NEXT:    s_addc_u32 s9, 0, -1
1409; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[4:5], 0
1410; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[12:13], s[8:9], 63
1411; GCN-IR-NEXT:    s_mov_b64 s[2:3], 0
1412; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
1413; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[12:13], s[8:9], 63
1414; GCN-IR-NEXT:    s_xor_b64 s[14:15], s[10:11], -1
1415; GCN-IR-NEXT:    s_and_b64 s[12:13], s[14:15], s[12:13]
1416; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
1417; GCN-IR-NEXT:    s_cbranch_vccz .LBB10_5
1418; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1419; GCN-IR-NEXT:    s_add_u32 s10, s8, 1
1420; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
1421; GCN-IR-NEXT:    s_addc_u32 s11, s9, 0
1422; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
1423; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
1424; GCN-IR-NEXT:    s_sub_i32 s7, 63, s8
1425; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1426; GCN-IR-NEXT:    s_lshl_b64 s[8:9], 24, s7
1427; GCN-IR-NEXT:    s_cbranch_vccz .LBB10_4
1428; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1429; GCN-IR-NEXT:    s_lshr_b64 s[12:13], 24, s10
1430; GCN-IR-NEXT:    s_add_u32 s14, s4, -1
1431; GCN-IR-NEXT:    s_addc_u32 s15, s5, -1
1432; GCN-IR-NEXT:    s_sub_u32 s6, 58, s6
1433; GCN-IR-NEXT:    s_subb_u32 s7, 0, 0
1434; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1435; GCN-IR-NEXT:    s_mov_b32 s3, 0
1436; GCN-IR-NEXT:  .LBB10_3: ; %udiv-do-while
1437; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1438; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
1439; GCN-IR-NEXT:    s_lshr_b32 s2, s9, 31
1440; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
1441; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[2:3]
1442; GCN-IR-NEXT:    s_or_b64 s[8:9], s[10:11], s[8:9]
1443; GCN-IR-NEXT:    s_sub_u32 s2, s14, s12
1444; GCN-IR-NEXT:    s_subb_u32 s2, s15, s13
1445; GCN-IR-NEXT:    s_ashr_i32 s10, s2, 31
1446; GCN-IR-NEXT:    s_mov_b32 s11, s10
1447; GCN-IR-NEXT:    s_and_b32 s2, s10, 1
1448; GCN-IR-NEXT:    s_and_b64 s[16:17], s[10:11], s[4:5]
1449; GCN-IR-NEXT:    s_sub_u32 s12, s12, s16
1450; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1451; GCN-IR-NEXT:    s_subb_u32 s13, s13, s17
1452; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
1453; GCN-IR-NEXT:    s_add_u32 s6, s6, 1
1454; GCN-IR-NEXT:    s_addc_u32 s7, s7, 0
1455; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1]
1456; GCN-IR-NEXT:    s_mov_b64 s[10:11], s[2:3]
1457; GCN-IR-NEXT:    s_cbranch_vccz .LBB10_3
1458; GCN-IR-NEXT:  .LBB10_4: ; %Flow5
1459; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[8:9], 1
1460; GCN-IR-NEXT:    s_or_b64 s[2:3], s[2:3], s[6:7]
1461; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1462; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
1463; GCN-IR-NEXT:    s_branch .LBB10_6
1464; GCN-IR-NEXT:  .LBB10_5:
1465; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1466; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, 24, 0, s[10:11]
1467; GCN-IR-NEXT:  .LBB10_6: ; %udiv-end
1468; GCN-IR-NEXT:    v_mul_lo_u32 v1, s4, v1
1469; GCN-IR-NEXT:    v_mul_hi_u32 v2, s4, v0
1470; GCN-IR-NEXT:    v_mul_lo_u32 v3, s5, v0
1471; GCN-IR-NEXT:    v_mul_lo_u32 v0, s4, v0
1472; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1473; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1474; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1475; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1476; GCN-IR-NEXT:    s_mov_b32 s2, -1
1477; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1478; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1479; GCN-IR-NEXT:    s_endpgm
1480  %result = srem i64 24, %x
1481  store i64 %result, i64 addrspace(1)* %out
1482  ret void
1483}
1484
1485define i64 @v_test_srem_k_num_i64(i64 %x) {
1486; GCN-LABEL: v_test_srem_k_num_i64:
1487; GCN:       ; %bb.0:
1488; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1489; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1490; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1491; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1492; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1493; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1494; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1495; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1496; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1497; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1498; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
1499; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1500; GCN-NEXT:    v_mov_b32_e32 v11, 0
1501; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1502; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1503; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1504; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1505; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1506; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1507; GCN-NEXT:    v_mul_hi_u32 v6, v4, v2
1508; GCN-NEXT:    v_mul_lo_u32 v7, v4, v3
1509; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1510; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
1511; GCN-NEXT:    v_mul_lo_u32 v7, v4, v2
1512; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1513; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
1514; GCN-NEXT:    v_mul_hi_u32 v9, v2, v7
1515; GCN-NEXT:    v_mul_hi_u32 v10, v2, v6
1516; GCN-NEXT:    v_mul_hi_u32 v12, v3, v6
1517; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1518; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1519; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
1520; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
1521; GCN-NEXT:    v_mul_hi_u32 v7, v3, v7
1522; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
1523; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v7, vcc
1524; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v11, vcc
1525; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1526; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
1527; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
1528; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v7, vcc
1529; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1530; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1531; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1532; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1533; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1534; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
1535; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
1536; GCN-NEXT:    v_mul_hi_u32 v9, v2, v4
1537; GCN-NEXT:    v_mul_hi_u32 v10, v2, v5
1538; GCN-NEXT:    v_mul_hi_u32 v7, v3, v4
1539; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1540; GCN-NEXT:    v_mul_hi_u32 v6, v3, v5
1541; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1542; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
1543; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
1544; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
1545; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
1546; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v11, vcc
1547; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1548; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
1549; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1550; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
1551; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
1552; GCN-NEXT:    v_mul_hi_u32 v2, v2, 24
1553; GCN-NEXT:    v_mul_hi_u32 v3, v3, 24
1554; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1555; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
1556; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
1557; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1558; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
1559; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1560; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
1561; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 24, v2
1562; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
1563; GCN-NEXT:    v_sub_i32_e64 v5, s[4:5], v2, v0
1564; GCN-NEXT:    v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
1565; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v1
1566; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[6:7]
1567; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v5, v0
1568; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
1569; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v6, v1
1570; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
1571; GCN-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[6:7]
1572; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v5, v0
1573; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1574; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
1575; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1576; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1577; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
1578; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v0
1579; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1580; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1581; GCN-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
1582; GCN-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[4:5]
1583; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1584; GCN-NEXT:    v_cndmask_b32_e64 v1, v6, v4, s[4:5]
1585; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1586; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1587; GCN-NEXT:    s_setpc_b64 s[30:31]
1588;
1589; GCN-IR-LABEL: v_test_srem_k_num_i64:
1590; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1591; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1592; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1593; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1594; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
1595; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1596; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1597; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1598; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1599; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1600; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1601; GCN-IR-NEXT:    s_movk_i32 s6, 0xffc5
1602; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, s6, v6
1603; GCN-IR-NEXT:    v_addc_u32_e64 v4, s[6:7], 0, -1, vcc
1604; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1605; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[3:4]
1606; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1607; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1608; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[3:4]
1609; GCN-IR-NEXT:    v_cndmask_b32_e64 v2, 24, 0, s[4:5]
1610; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1611; GCN-IR-NEXT:    v_mov_b32_e32 v5, v7
1612; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1613; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1614; GCN-IR-NEXT:    s_cbranch_execz .LBB11_6
1615; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1616; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v3
1617; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v4, vcc
1618; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v3
1619; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[8:9], v[3:4]
1620; GCN-IR-NEXT:    v_lshl_b64 v[2:3], 24, v2
1621; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1622; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1623; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1624; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1625; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1626; GCN-IR-NEXT:    s_cbranch_execz .LBB11_5
1627; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1628; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, -1, v0
1629; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, -1, v1, vcc
1630; GCN-IR-NEXT:    v_lshr_b64 v[8:9], 24, v8
1631; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, 58, v6
1632; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1633; GCN-IR-NEXT:    v_subb_u32_e32 v7, vcc, 0, v7, vcc
1634; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1635; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1636; GCN-IR-NEXT:  .LBB11_3: ; %udiv-do-while
1637; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1638; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1639; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1640; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1641; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1642; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, v12, v8
1643; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, v13, v9, vcc
1644; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1645; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1646; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1647; GCN-IR-NEXT:    v_and_b32_e32 v14, v10, v1
1648; GCN-IR-NEXT:    v_and_b32_e32 v15, v10, v0
1649; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v6
1650; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1651; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v7, vcc
1652; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7]
1653; GCN-IR-NEXT:    v_mov_b32_e32 v6, v10
1654; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v15
1655; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1656; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1657; GCN-IR-NEXT:    v_subb_u32_e64 v9, s[4:5], v9, v14, s[4:5]
1658; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1659; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1660; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1661; GCN-IR-NEXT:    s_cbranch_execnz .LBB11_3
1662; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1663; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1664; GCN-IR-NEXT:  .LBB11_5: ; %Flow3
1665; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1666; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1667; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1668; GCN-IR-NEXT:    v_or_b32_e32 v2, v4, v2
1669; GCN-IR-NEXT:  .LBB11_6: ; %Flow4
1670; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1671; GCN-IR-NEXT:    v_mul_lo_u32 v3, v0, v5
1672; GCN-IR-NEXT:    v_mul_hi_u32 v4, v0, v2
1673; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v2
1674; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, v2
1675; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1676; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
1677; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1678; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1679; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1680  %result = srem i64 24, %x
1681  ret i64 %result
1682}
1683
1684define i64 @v_test_srem_pow2_k_num_i64(i64 %x) {
1685; GCN-LABEL: v_test_srem_pow2_k_num_i64:
1686; GCN:       ; %bb.0:
1687; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1688; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1689; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1690; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1691; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1692; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1693; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1694; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1695; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1696; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1697; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
1698; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1699; GCN-NEXT:    v_mov_b32_e32 v11, 0
1700; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1701; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1702; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1703; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1704; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1705; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1706; GCN-NEXT:    v_mul_hi_u32 v6, v4, v2
1707; GCN-NEXT:    v_mul_lo_u32 v7, v4, v3
1708; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1709; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
1710; GCN-NEXT:    v_mul_lo_u32 v7, v4, v2
1711; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1712; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
1713; GCN-NEXT:    v_mul_hi_u32 v9, v2, v7
1714; GCN-NEXT:    v_mul_hi_u32 v10, v2, v6
1715; GCN-NEXT:    v_mul_hi_u32 v12, v3, v6
1716; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1717; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1718; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
1719; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
1720; GCN-NEXT:    v_mul_hi_u32 v7, v3, v7
1721; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
1722; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v7, vcc
1723; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v11, vcc
1724; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1725; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
1726; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
1727; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v7, vcc
1728; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1729; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1730; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1731; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1732; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1733; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
1734; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
1735; GCN-NEXT:    v_mul_hi_u32 v9, v2, v4
1736; GCN-NEXT:    v_mul_hi_u32 v10, v2, v5
1737; GCN-NEXT:    v_mul_hi_u32 v7, v3, v4
1738; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1739; GCN-NEXT:    v_mul_hi_u32 v6, v3, v5
1740; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1741; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
1742; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
1743; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
1744; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
1745; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v11, vcc
1746; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1747; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
1748; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1749; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v3, v5, vcc
1750; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1751; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
1752; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1753; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
1754; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1755; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
1756; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0x8000, v2
1757; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
1758; GCN-NEXT:    v_sub_i32_e64 v5, s[4:5], v2, v0
1759; GCN-NEXT:    v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
1760; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v1
1761; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[6:7]
1762; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v5, v0
1763; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
1764; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v6, v1
1765; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
1766; GCN-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[6:7]
1767; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v5, v0
1768; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1769; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
1770; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1771; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1772; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
1773; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v0
1774; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1775; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1776; GCN-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
1777; GCN-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[4:5]
1778; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1779; GCN-NEXT:    v_cndmask_b32_e64 v1, v6, v4, s[4:5]
1780; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1781; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1782; GCN-NEXT:    s_setpc_b64 s[30:31]
1783;
1784; GCN-IR-LABEL: v_test_srem_pow2_k_num_i64:
1785; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1786; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1787; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1788; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1789; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
1790; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1791; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1792; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1793; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1794; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1795; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1796; GCN-IR-NEXT:    s_movk_i32 s6, 0xffd0
1797; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, s6, v6
1798; GCN-IR-NEXT:    v_addc_u32_e64 v3, s[6:7], 0, -1, vcc
1799; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1800; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[2:3]
1801; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0x8000
1802; GCN-IR-NEXT:    v_mov_b32_e32 v4, s8
1803; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1804; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[2:3]
1805; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1806; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v4, 0, s[4:5]
1807; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1808; GCN-IR-NEXT:    v_mov_b32_e32 v5, v7
1809; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1810; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1811; GCN-IR-NEXT:    s_cbranch_execz .LBB12_6
1812; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1813; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v2
1814; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v3, vcc
1815; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[8:9], v[2:3]
1816; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v2
1817; GCN-IR-NEXT:    v_lshl_b64 v[2:3], s[8:9], v2
1818; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1819; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1820; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1821; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1822; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1823; GCN-IR-NEXT:    s_cbranch_execz .LBB12_5
1824; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1825; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, -1, v0
1826; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0x8000
1827; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, -1, v1, vcc
1828; GCN-IR-NEXT:    v_lshr_b64 v[8:9], s[4:5], v8
1829; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, 47, v6
1830; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1831; GCN-IR-NEXT:    v_subb_u32_e32 v7, vcc, 0, v7, vcc
1832; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1833; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1834; GCN-IR-NEXT:  .LBB12_3: ; %udiv-do-while
1835; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1836; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1837; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1838; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1839; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1840; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, v12, v8
1841; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, v13, v9, vcc
1842; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1843; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1844; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1845; GCN-IR-NEXT:    v_and_b32_e32 v14, v10, v1
1846; GCN-IR-NEXT:    v_and_b32_e32 v15, v10, v0
1847; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v6
1848; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1849; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v7, vcc
1850; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7]
1851; GCN-IR-NEXT:    v_mov_b32_e32 v6, v10
1852; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v15
1853; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1854; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1855; GCN-IR-NEXT:    v_subb_u32_e64 v9, s[4:5], v9, v14, s[4:5]
1856; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1857; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1858; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1859; GCN-IR-NEXT:    s_cbranch_execnz .LBB12_3
1860; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1861; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1862; GCN-IR-NEXT:  .LBB12_5: ; %Flow3
1863; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1864; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1865; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1866; GCN-IR-NEXT:    v_or_b32_e32 v4, v4, v2
1867; GCN-IR-NEXT:  .LBB12_6: ; %Flow4
1868; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1869; GCN-IR-NEXT:    v_mul_lo_u32 v2, v0, v5
1870; GCN-IR-NEXT:    v_mul_hi_u32 v3, v0, v4
1871; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v4
1872; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, v4
1873; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1874; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1875; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1876; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1877; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1878  %result = srem i64 32768, %x
1879  ret i64 %result
1880}
1881
1882define i64 @v_test_srem_pow2_k_den_i64(i64 %x) {
1883; GCN-LABEL: v_test_srem_pow2_k_den_i64:
1884; GCN:       ; %bb.0:
1885; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1886; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1887; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1888; GCN-NEXT:    v_add_i32_e32 v2, vcc, v0, v2
1889; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
1890; GCN-NEXT:    v_and_b32_e32 v2, 0xffff8000, v2
1891; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1892; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1893; GCN-NEXT:    s_setpc_b64 s[30:31]
1894;
1895; GCN-IR-LABEL: v_test_srem_pow2_k_den_i64:
1896; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1897; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1898; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1899; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1900; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
1901; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1902; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1903; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v0
1904; GCN-IR-NEXT:    v_add_i32_e64 v3, s[4:5], 32, v3
1905; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v1
1906; GCN-IR-NEXT:    v_min_u32_e32 v8, v3, v4
1907; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 48, v8
1908; GCN-IR-NEXT:    v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5]
1909; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1910; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
1911; GCN-IR-NEXT:    v_mov_b32_e32 v3, v2
1912; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1913; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1914; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1915; GCN-IR-NEXT:    v_cndmask_b32_e64 v7, v1, 0, s[4:5]
1916; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v0, 0, s[4:5]
1917; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1918; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1919; GCN-IR-NEXT:    s_cbranch_execz .LBB13_6
1920; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1921; GCN-IR-NEXT:    v_add_i32_e32 v9, vcc, 1, v4
1922; GCN-IR-NEXT:    v_addc_u32_e32 v10, vcc, 0, v5, vcc
1923; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[9:10], v[4:5]
1924; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v4
1925; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[0:1], v4
1926; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1927; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1928; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1929; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1930; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1931; GCN-IR-NEXT:    s_cbranch_execz .LBB13_5
1932; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1933; GCN-IR-NEXT:    v_lshr_b64 v[10:11], v[0:1], v9
1934; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 0xffffffcf, v8
1935; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1936; GCN-IR-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, -1, vcc
1937; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1938; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1939; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
1940; GCN-IR-NEXT:  .LBB13_3: ; %udiv-do-while
1941; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1942; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
1943; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
1944; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v6
1945; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
1946; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, s12, v10
1947; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, 0, v11, vcc
1948; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
1949; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v6
1950; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v12
1951; GCN-IR-NEXT:    v_and_b32_e32 v14, 0x8000, v12
1952; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
1953; GCN-IR-NEXT:    v_or_b32_e32 v5, v13, v5
1954; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
1955; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
1956; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
1957; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v14
1958; GCN-IR-NEXT:    v_mov_b32_e32 v9, v13
1959; GCN-IR-NEXT:    v_mov_b32_e32 v13, v7
1960; GCN-IR-NEXT:    v_subbrev_u32_e64 v11, s[4:5], 0, v11, s[4:5]
1961; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1962; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
1963; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1964; GCN-IR-NEXT:    s_cbranch_execnz .LBB13_3
1965; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1966; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1967; GCN-IR-NEXT:  .LBB13_5: ; %Flow3
1968; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1969; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
1970; GCN-IR-NEXT:    v_or_b32_e32 v7, v7, v5
1971; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v4
1972; GCN-IR-NEXT:  .LBB13_6: ; %Flow4
1973; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1974; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[6:7], 15
1975; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
1976; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
1977; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1978; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v3
1979; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1980; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1981; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1982  %result = srem i64 %x, 32768
1983  ret i64 %result
1984}
1985
1986define amdgpu_kernel void @s_test_srem24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1987; GCN-LABEL: s_test_srem24_k_num_i64:
1988; GCN:       ; %bb.0:
1989; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1990; GCN-NEXT:    s_mov_b32 s6, 0x41c00000
1991; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1992; GCN-NEXT:    s_ashr_i64 s[4:5], s[2:3], 40
1993; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
1994; GCN-NEXT:    s_ashr_i32 s5, s4, 30
1995; GCN-NEXT:    s_or_b32 s5, s5, 1
1996; GCN-NEXT:    v_mov_b32_e32 v3, s5
1997; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1998; GCN-NEXT:    s_mov_b32 s3, 0xf000
1999; GCN-NEXT:    s_mov_b32 s2, -1
2000; GCN-NEXT:    v_mul_f32_e32 v1, s6, v1
2001; GCN-NEXT:    v_trunc_f32_e32 v1, v1
2002; GCN-NEXT:    v_mad_f32 v2, -v1, v0, s6
2003; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
2004; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
2005; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
2006; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
2007; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
2008; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2009; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2010; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2011; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2012; GCN-NEXT:    s_endpgm
2013;
2014; GCN-IR-LABEL: s_test_srem24_k_num_i64:
2015; GCN-IR:       ; %bb.0:
2016; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
2017; GCN-IR-NEXT:    s_mov_b32 s6, 0x41c00000
2018; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
2019; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[2:3], 40
2020; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
2021; GCN-IR-NEXT:    s_ashr_i32 s5, s4, 30
2022; GCN-IR-NEXT:    s_or_b32 s5, s5, 1
2023; GCN-IR-NEXT:    v_mov_b32_e32 v3, s5
2024; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
2025; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
2026; GCN-IR-NEXT:    s_mov_b32 s2, -1
2027; GCN-IR-NEXT:    v_mul_f32_e32 v1, s6, v1
2028; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
2029; GCN-IR-NEXT:    v_mad_f32 v2, -v1, v0, s6
2030; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
2031; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
2032; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
2033; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
2034; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
2035; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2036; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2037; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2038; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2039; GCN-IR-NEXT:    s_endpgm
2040  %x.shr = ashr i64 %x, 40
2041  %result = srem i64 24, %x.shr
2042  store i64 %result, i64 addrspace(1)* %out
2043  ret void
2044}
2045
2046define amdgpu_kernel void @s_test_srem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
2047; GCN-LABEL: s_test_srem24_k_den_i64:
2048; GCN:       ; %bb.0:
2049; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
2050; GCN-NEXT:    s_mov_b32 s4, 0x46b6fe00
2051; GCN-NEXT:    s_mov_b32 s7, 0xf000
2052; GCN-NEXT:    s_mov_b32 s6, -1
2053; GCN-NEXT:    s_waitcnt lgkmcnt(0)
2054; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
2055; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s2
2056; GCN-NEXT:    s_ashr_i32 s3, s2, 30
2057; GCN-NEXT:    s_or_b32 s3, s3, 1
2058; GCN-NEXT:    v_mov_b32_e32 v1, s3
2059; GCN-NEXT:    v_mul_f32_e32 v2, 0x38331158, v0
2060; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2061; GCN-NEXT:    v_mad_f32 v0, -v2, s4, v0
2062; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2063; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
2064; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
2065; GCN-NEXT:    s_movk_i32 s3, 0x5b7f
2066; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
2067; GCN-NEXT:    v_mul_lo_u32 v0, v0, s3
2068; GCN-NEXT:    s_mov_b32 s4, s0
2069; GCN-NEXT:    s_mov_b32 s5, s1
2070; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
2071; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2072; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2073; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
2074; GCN-NEXT:    s_endpgm
2075;
2076; GCN-IR-LABEL: s_test_srem24_k_den_i64:
2077; GCN-IR:       ; %bb.0:
2078; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
2079; GCN-IR-NEXT:    s_mov_b32 s4, 0x46b6fe00
2080; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
2081; GCN-IR-NEXT:    s_mov_b32 s6, -1
2082; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
2083; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
2084; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s2
2085; GCN-IR-NEXT:    s_ashr_i32 s3, s2, 30
2086; GCN-IR-NEXT:    s_or_b32 s3, s3, 1
2087; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
2088; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x38331158, v0
2089; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2090; GCN-IR-NEXT:    v_mad_f32 v0, -v2, s4, v0
2091; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2092; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
2093; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
2094; GCN-IR-NEXT:    s_movk_i32 s3, 0x5b7f
2095; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
2096; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s3
2097; GCN-IR-NEXT:    s_mov_b32 s4, s0
2098; GCN-IR-NEXT:    s_mov_b32 s5, s1
2099; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
2100; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2101; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2102; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
2103; GCN-IR-NEXT:    s_endpgm
2104  %x.shr = ashr i64 %x, 40
2105  %result = srem i64 %x.shr, 23423
2106  store i64 %result, i64 addrspace(1)* %out
2107  ret void
2108}
2109
2110define i64 @v_test_srem24_k_num_i64(i64 %x) {
2111; GCN-LABEL: v_test_srem24_k_num_i64:
2112; GCN:       ; %bb.0:
2113; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2114; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2115; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
2116; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
2117; GCN-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2118; GCN-NEXT:    v_or_b32_e32 v3, 1, v3
2119; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2120; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
2121; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2122; GCN-NEXT:    v_mad_f32 v4, -v2, v1, s4
2123; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2124; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2125; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2126; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2127; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
2128; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2129; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2130; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2131; GCN-NEXT:    s_setpc_b64 s[30:31]
2132;
2133; GCN-IR-LABEL: v_test_srem24_k_num_i64:
2134; GCN-IR:       ; %bb.0:
2135; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2136; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2137; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
2138; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2139; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2140; GCN-IR-NEXT:    v_or_b32_e32 v3, 1, v3
2141; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2142; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
2143; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2144; GCN-IR-NEXT:    v_mad_f32 v4, -v2, v1, s4
2145; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2146; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2147; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2148; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2149; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
2150; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2151; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2152; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2153; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2154  %x.shr = ashr i64 %x, 40
2155  %result = srem i64 24, %x.shr
2156  ret i64 %result
2157}
2158
2159define i64 @v_test_srem24_pow2_k_num_i64(i64 %x) {
2160; GCN-LABEL: v_test_srem24_pow2_k_num_i64:
2161; GCN:       ; %bb.0:
2162; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2163; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2164; GCN-NEXT:    s_mov_b32 s4, 0x47000000
2165; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
2166; GCN-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2167; GCN-NEXT:    v_or_b32_e32 v3, 1, v3
2168; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2169; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
2170; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2171; GCN-NEXT:    v_mad_f32 v4, -v2, v1, s4
2172; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2173; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2174; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2175; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2176; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
2177; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
2178; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2179; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2180; GCN-NEXT:    s_setpc_b64 s[30:31]
2181;
2182; GCN-IR-LABEL: v_test_srem24_pow2_k_num_i64:
2183; GCN-IR:       ; %bb.0:
2184; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2185; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2186; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2187; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2188; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2189; GCN-IR-NEXT:    v_or_b32_e32 v3, 1, v3
2190; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2191; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
2192; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2193; GCN-IR-NEXT:    v_mad_f32 v4, -v2, v1, s4
2194; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2195; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2196; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2197; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2198; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
2199; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
2200; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2201; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2202; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2203  %x.shr = ashr i64 %x, 40
2204  %result = srem i64 32768, %x.shr
2205  ret i64 %result
2206}
2207
2208define i64 @v_test_srem24_pow2_k_den_i64(i64 %x) {
2209; GCN-LABEL: v_test_srem24_pow2_k_den_i64:
2210; GCN:       ; %bb.0:
2211; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2212; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2213; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v1
2214; GCN-NEXT:    v_add_i32_e32 v2, vcc, v0, v2
2215; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
2216; GCN-NEXT:    v_and_b32_e32 v2, 0xffff8000, v2
2217; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
2218; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
2219; GCN-NEXT:    s_setpc_b64 s[30:31]
2220;
2221; GCN-IR-LABEL: v_test_srem24_pow2_k_den_i64:
2222; GCN-IR:       ; %bb.0:
2223; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2224; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2225; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2226; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2227; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 30, v0
2228; GCN-IR-NEXT:    v_or_b32_e32 v2, 1, v2
2229; GCN-IR-NEXT:    v_mul_f32_e32 v3, 0x38000000, v1
2230; GCN-IR-NEXT:    v_trunc_f32_e32 v3, v3
2231; GCN-IR-NEXT:    v_mad_f32 v1, -v3, s4, v1
2232; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v3
2233; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
2234; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
2235; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
2236; GCN-IR-NEXT:    v_lshlrev_b32_e32 v1, 15, v1
2237; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
2238; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2239; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2240; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2241  %x.shr = ashr i64 %x, 40
2242  %result = srem i64 %x.shr, 32768
2243  ret i64 %result
2244}
2245