1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_srem(i64 addrspace(1)* %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_srem:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
9; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
10; GCN-NEXT:    v_mov_b32_e32 v2, 0
11; GCN-NEXT:    s_mov_b32 s7, 0xf000
12; GCN-NEXT:    s_mov_b32 s6, -1
13; GCN-NEXT:    s_waitcnt lgkmcnt(0)
14; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
15; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
16; GCN-NEXT:    s_sub_u32 s0, 0, s12
17; GCN-NEXT:    s_subb_u32 s1, 0, s13
18; GCN-NEXT:    s_mov_b32 s4, s8
19; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
20; GCN-NEXT:    v_rcp_f32_e32 v0, v0
21; GCN-NEXT:    v_mov_b32_e32 v1, 0
22; GCN-NEXT:    s_mov_b32 s5, s9
23; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
24; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
25; GCN-NEXT:    v_trunc_f32_e32 v3, v3
26; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
27; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
28; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
29; GCN-NEXT:    v_mul_lo_u32 v4, s0, v3
30; GCN-NEXT:    v_mul_hi_u32 v5, s0, v0
31; GCN-NEXT:    v_mul_lo_u32 v7, s1, v0
32; GCN-NEXT:    v_mul_lo_u32 v6, s0, v0
33; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
34; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
35; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
36; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
37; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
38; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
39; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
40; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
41; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
42; GCN-NEXT:    v_mul_hi_u32 v9, v3, v4
43; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
44; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
45; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
46; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v1, vcc
47; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
48; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
49; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
50; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
51; GCN-NEXT:    v_mul_lo_u32 v4, s0, v3
52; GCN-NEXT:    v_mul_hi_u32 v5, s0, v0
53; GCN-NEXT:    v_mul_lo_u32 v6, s1, v0
54; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
55; GCN-NEXT:    v_mul_lo_u32 v5, s0, v0
56; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
57; GCN-NEXT:    v_mul_lo_u32 v8, v0, v4
58; GCN-NEXT:    v_mul_hi_u32 v9, v0, v5
59; GCN-NEXT:    v_mul_hi_u32 v10, v0, v4
60; GCN-NEXT:    v_mul_hi_u32 v7, v3, v5
61; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
62; GCN-NEXT:    v_mul_hi_u32 v6, v3, v4
63; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
64; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v2, v10, vcc
65; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
66; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
67; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v7, vcc
68; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v1, vcc
69; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
70; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
71; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
72; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
73; GCN-NEXT:    v_mul_lo_u32 v4, s10, v3
74; GCN-NEXT:    v_mul_hi_u32 v5, s10, v0
75; GCN-NEXT:    v_mul_hi_u32 v6, s10, v3
76; GCN-NEXT:    v_mul_hi_u32 v7, s11, v3
77; GCN-NEXT:    v_mul_lo_u32 v3, s11, v3
78; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
79; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
80; GCN-NEXT:    v_mul_lo_u32 v6, s11, v0
81; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
82; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
83; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
84; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
85; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
86; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
87; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
88; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
89; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
90; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
91; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
92; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
93; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s11, v1
94; GCN-NEXT:    v_mov_b32_e32 v3, s13
95; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s10, v0
96; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
97; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
98; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
99; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
100; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
101; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
102; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
103; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
104; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
105; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
106; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
107; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
108; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
109; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
110; GCN-NEXT:    v_mov_b32_e32 v5, s11
111; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
112; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
113; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
114; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
115; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
116; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
117; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
118; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
119; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
120; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
121; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
122; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
123; GCN-NEXT:    s_endpgm
124;
125; GCN-IR-LABEL: s_test_srem:
126; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
127; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
128; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
129; GCN-IR-NEXT:    s_mov_b64 s[2:3], 0
130; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
131; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
132; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[0:1], 0
133; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s0
134; GCN-IR-NEXT:    s_or_b64 s[14:15], s[8:9], s[10:11]
135; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s6
136; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
137; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s1
138; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
139; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s7
140; GCN-IR-NEXT:    s_min_u32 s8, s12, s8
141; GCN-IR-NEXT:    s_min_u32 s12, s10, s11
142; GCN-IR-NEXT:    s_sub_u32 s10, s8, s12
143; GCN-IR-NEXT:    s_subb_u32 s11, 0, 0
144; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[16:17], s[10:11], 63
145; GCN-IR-NEXT:    s_mov_b32 s9, 0
146; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[16:17]
147; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[16:17], s[10:11], 63
148; GCN-IR-NEXT:    s_xor_b64 s[18:19], s[14:15], -1
149; GCN-IR-NEXT:    s_and_b64 s[16:17], s[18:19], s[16:17]
150; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[16:17]
151; GCN-IR-NEXT:    s_cbranch_vccz BB0_5
152; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
153; GCN-IR-NEXT:    s_add_u32 s14, s10, 1
154; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
155; GCN-IR-NEXT:    s_addc_u32 s15, s11, 0
156; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
157; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[14:15], v[0:1]
158; GCN-IR-NEXT:    s_sub_i32 s10, 63, s10
159; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
160; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[6:7], s10
161; GCN-IR-NEXT:    s_cbranch_vccz BB0_4
162; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
163; GCN-IR-NEXT:    s_lshr_b64 s[14:15], s[6:7], s14
164; GCN-IR-NEXT:    s_add_u32 s16, s0, -1
165; GCN-IR-NEXT:    s_addc_u32 s17, s1, -1
166; GCN-IR-NEXT:    s_not_b64 s[2:3], s[8:9]
167; GCN-IR-NEXT:    s_mov_b32 s13, s9
168; GCN-IR-NEXT:    s_add_u32 s8, s2, s12
169; GCN-IR-NEXT:    s_addc_u32 s9, s3, s9
170; GCN-IR-NEXT:    s_mov_b64 s[12:13], 0
171; GCN-IR-NEXT:    s_mov_b32 s3, 0
172; GCN-IR-NEXT:  BB0_3: ; %udiv-do-while
173; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
174; GCN-IR-NEXT:    s_lshl_b64 s[14:15], s[14:15], 1
175; GCN-IR-NEXT:    s_lshr_b32 s2, s11, 31
176; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
177; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[2:3]
178; GCN-IR-NEXT:    s_or_b64 s[10:11], s[12:13], s[10:11]
179; GCN-IR-NEXT:    s_sub_u32 s2, s16, s14
180; GCN-IR-NEXT:    s_subb_u32 s2, s17, s15
181; GCN-IR-NEXT:    s_ashr_i32 s12, s2, 31
182; GCN-IR-NEXT:    s_mov_b32 s13, s12
183; GCN-IR-NEXT:    s_and_b32 s2, s12, 1
184; GCN-IR-NEXT:    s_and_b64 s[18:19], s[12:13], s[0:1]
185; GCN-IR-NEXT:    s_sub_u32 s14, s14, s18
186; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
187; GCN-IR-NEXT:    s_subb_u32 s15, s15, s19
188; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
189; GCN-IR-NEXT:    s_add_u32 s8, s8, 1
190; GCN-IR-NEXT:    s_addc_u32 s9, s9, 0
191; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
192; GCN-IR-NEXT:    s_mov_b64 s[12:13], s[2:3]
193; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
194; GCN-IR-NEXT:    s_cbranch_vccz BB0_3
195; GCN-IR-NEXT:  BB0_4: ; %Flow6
196; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[10:11], 1
197; GCN-IR-NEXT:    s_or_b64 s[2:3], s[2:3], s[8:9]
198; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
199; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
200; GCN-IR-NEXT:    s_branch BB0_6
201; GCN-IR-NEXT:  BB0_5:
202; GCN-IR-NEXT:    v_mov_b32_e32 v0, s7
203; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[14:15]
204; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
205; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[14:15]
206; GCN-IR-NEXT:  BB0_6: ; %udiv-end
207; GCN-IR-NEXT:    v_mul_lo_u32 v1, s0, v1
208; GCN-IR-NEXT:    v_mul_hi_u32 v2, s0, v0
209; GCN-IR-NEXT:    v_mul_lo_u32 v3, s1, v0
210; GCN-IR-NEXT:    v_mul_lo_u32 v0, s0, v0
211; GCN-IR-NEXT:    s_mov_b32 s11, 0xf000
212; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
213; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
214; GCN-IR-NEXT:    v_mov_b32_e32 v2, s7
215; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
216; GCN-IR-NEXT:    s_mov_b32 s10, -1
217; GCN-IR-NEXT:    s_mov_b32 s8, s4
218; GCN-IR-NEXT:    s_mov_b32 s9, s5
219; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
220; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
221; GCN-IR-NEXT:    s_endpgm
222  %result = urem i64 %x, %y
223  store i64 %result, i64 addrspace(1)* %out
224  ret void
225}
226
227define i64 @v_test_srem(i64 %x, i64 %y) {
228; GCN-LABEL: v_test_srem:
229; GCN:       ; %bb.0:
230; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
231; GCN-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
232; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
233; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
234; GCN-NEXT:    v_xor_b32_e32 v3, v3, v4
235; GCN-NEXT:    v_xor_b32_e32 v2, v2, v4
236; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v2
237; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v3
238; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v2
239; GCN-NEXT:    v_subb_u32_e32 v7, vcc, 0, v3, vcc
240; GCN-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
241; GCN-NEXT:    v_rcp_f32_e32 v4, v4
242; GCN-NEXT:    v_mov_b32_e32 v14, 0
243; GCN-NEXT:    v_mov_b32_e32 v13, 0
244; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
245; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
246; GCN-NEXT:    v_trunc_f32_e32 v5, v5
247; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
248; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
249; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
250; GCN-NEXT:    v_mul_hi_u32 v8, v6, v4
251; GCN-NEXT:    v_mul_lo_u32 v9, v6, v5
252; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
253; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
254; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
255; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
256; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
257; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
258; GCN-NEXT:    v_mul_hi_u32 v10, v4, v8
259; GCN-NEXT:    v_mul_hi_u32 v15, v5, v8
260; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
261; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
262; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
263; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
264; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v10, vcc
265; GCN-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
266; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v10, v9, vcc
267; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v15, v13, vcc
268; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
269; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v10, vcc
270; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
271; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v9, vcc
272; GCN-NEXT:    v_mul_lo_u32 v8, v6, v5
273; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
274; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
275; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
276; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
277; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
278; GCN-NEXT:    v_mul_lo_u32 v10, v4, v7
279; GCN-NEXT:    v_mul_hi_u32 v11, v4, v6
280; GCN-NEXT:    v_mul_hi_u32 v12, v4, v7
281; GCN-NEXT:    v_mul_hi_u32 v9, v5, v6
282; GCN-NEXT:    v_mul_lo_u32 v6, v5, v6
283; GCN-NEXT:    v_mul_hi_u32 v8, v5, v7
284; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
285; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v14, v12, vcc
286; GCN-NEXT:    v_mul_lo_u32 v7, v5, v7
287; GCN-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
288; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
289; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v8, v13, vcc
290; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
291; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v14, v8, vcc
292; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
293; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
294; GCN-NEXT:    v_ashrrev_i32_e32 v6, 31, v1
295; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
296; GCN-NEXT:    v_xor_b32_e32 v0, v0, v6
297; GCN-NEXT:    v_mul_lo_u32 v7, v0, v5
298; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
299; GCN-NEXT:    v_mul_hi_u32 v9, v0, v5
300; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v6, vcc
301; GCN-NEXT:    v_xor_b32_e32 v1, v1, v6
302; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
303; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v14, v9, vcc
304; GCN-NEXT:    v_mul_lo_u32 v9, v1, v4
305; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
306; GCN-NEXT:    v_mul_hi_u32 v10, v1, v5
307; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
308; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
309; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
310; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v10, v13, vcc
311; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
312; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v14, v7, vcc
313; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
314; GCN-NEXT:    v_mul_hi_u32 v7, v2, v4
315; GCN-NEXT:    v_mul_lo_u32 v8, v3, v4
316; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
317; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
318; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
319; GCN-NEXT:    v_sub_i32_e32 v7, vcc, v1, v5
320; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
321; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v7, v3, vcc
322; GCN-NEXT:    v_sub_i32_e64 v7, s[4:5], v0, v2
323; GCN-NEXT:    v_subbrev_u32_e64 v8, s[6:7], 0, v4, s[4:5]
324; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v8, v3
325; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[6:7]
326; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v7, v2
327; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
328; GCN-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[6:7]
329; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v8, v3
330; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v3, s[4:5]
331; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
332; GCN-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[6:7]
333; GCN-NEXT:    v_sub_i32_e64 v10, s[4:5], v7, v2
334; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
335; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
336; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
337; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
338; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
339; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v9
340; GCN-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
341; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
342; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v10, s[4:5]
343; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v4, s[4:5]
344; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
345; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
346; GCN-NEXT:    v_xor_b32_e32 v0, v0, v6
347; GCN-NEXT:    v_xor_b32_e32 v1, v1, v6
348; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
349; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
350; GCN-NEXT:    s_setpc_b64 s[30:31]
351;
352; GCN-IR-LABEL: v_test_srem:
353; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
354; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
355; GCN-IR-NEXT:    v_ashrrev_i32_e32 v4, 31, v1
356; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v4
357; GCN-IR-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
358; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v4
359; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
360; GCN-IR-NEXT:    v_xor_b32_e32 v2, v2, v6
361; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc
362; GCN-IR-NEXT:    v_xor_b32_e32 v3, v3, v6
363; GCN-IR-NEXT:    v_sub_i32_e32 v5, vcc, v2, v6
364; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v3, v6, vcc
365; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[5:6]
366; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
367; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v5
368; GCN-IR-NEXT:    s_or_b64 s[6:7], vcc, s[4:5]
369; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, 32, v3
370; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v6
371; GCN-IR-NEXT:    v_min_u32_e32 v3, v3, v7
372; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v0
373; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 32, v7
374; GCN-IR-NEXT:    v_ffbh_u32_e32 v8, v1
375; GCN-IR-NEXT:    v_min_u32_e32 v12, v7, v8
376; GCN-IR-NEXT:    v_sub_i32_e32 v7, vcc, v3, v12
377; GCN-IR-NEXT:    v_subb_u32_e64 v8, s[4:5], 0, 0, vcc
378; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[7:8]
379; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[4:5], 63, v[7:8]
380; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], vcc
381; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
382; GCN-IR-NEXT:    s_xor_b64 s[8:9], s[6:7], -1
383; GCN-IR-NEXT:    v_mov_b32_e32 v2, v4
384; GCN-IR-NEXT:    v_mov_b32_e32 v13, v11
385; GCN-IR-NEXT:    v_cndmask_b32_e64 v10, v1, 0, s[6:7]
386; GCN-IR-NEXT:    s_and_b64 s[4:5], s[8:9], s[4:5]
387; GCN-IR-NEXT:    v_cndmask_b32_e64 v9, v0, 0, s[6:7]
388; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
389; GCN-IR-NEXT:    s_cbranch_execz BB1_6
390; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
391; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, 1, v7
392; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, 0, v8, vcc
393; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[14:15], v[7:8]
394; GCN-IR-NEXT:    v_sub_i32_e64 v7, s[4:5], 63, v7
395; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[0:1], v7
396; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
397; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
398; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
399; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
400; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
401; GCN-IR-NEXT:    s_cbranch_execz BB1_5
402; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
403; GCN-IR-NEXT:    v_add_i32_e32 v18, vcc, -1, v5
404; GCN-IR-NEXT:    v_addc_u32_e32 v19, vcc, -1, v6, vcc
405; GCN-IR-NEXT:    v_not_b32_e32 v3, v3
406; GCN-IR-NEXT:    v_lshr_b64 v[14:15], v[0:1], v14
407; GCN-IR-NEXT:    v_not_b32_e32 v9, v11
408; GCN-IR-NEXT:    v_add_i32_e32 v11, vcc, v3, v12
409; GCN-IR-NEXT:    v_mov_b32_e32 v16, 0
410; GCN-IR-NEXT:    v_addc_u32_e32 v12, vcc, v9, v13, vcc
411; GCN-IR-NEXT:    v_mov_b32_e32 v17, 0
412; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
413; GCN-IR-NEXT:  BB1_3: ; %udiv-do-while
414; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
415; GCN-IR-NEXT:    v_lshl_b64 v[14:15], v[14:15], 1
416; GCN-IR-NEXT:    v_lshrrev_b32_e32 v3, 31, v8
417; GCN-IR-NEXT:    v_or_b32_e32 v3, v14, v3
418; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
419; GCN-IR-NEXT:    v_sub_i32_e32 v9, vcc, v18, v3
420; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, v19, v15, vcc
421; GCN-IR-NEXT:    v_or_b32_e32 v7, v16, v7
422; GCN-IR-NEXT:    v_add_i32_e32 v16, vcc, 1, v11
423; GCN-IR-NEXT:    v_or_b32_e32 v8, v17, v8
424; GCN-IR-NEXT:    v_ashrrev_i32_e32 v13, 31, v9
425; GCN-IR-NEXT:    v_addc_u32_e32 v17, vcc, 0, v12, vcc
426; GCN-IR-NEXT:    v_and_b32_e32 v9, 1, v13
427; GCN-IR-NEXT:    v_and_b32_e32 v20, v13, v6
428; GCN-IR-NEXT:    v_and_b32_e32 v13, v13, v5
429; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[16:17], v[11:12]
430; GCN-IR-NEXT:    v_mov_b32_e32 v11, v16
431; GCN-IR-NEXT:    v_sub_i32_e64 v14, s[4:5], v3, v13
432; GCN-IR-NEXT:    v_mov_b32_e32 v12, v17
433; GCN-IR-NEXT:    v_mov_b32_e32 v17, v10
434; GCN-IR-NEXT:    v_subb_u32_e64 v15, s[4:5], v15, v20, s[4:5]
435; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
436; GCN-IR-NEXT:    v_mov_b32_e32 v16, v9
437; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
438; GCN-IR-NEXT:    s_cbranch_execnz BB1_3
439; GCN-IR-NEXT:  ; %bb.4: ; %Flow
440; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
441; GCN-IR-NEXT:  BB1_5: ; %Flow3
442; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
443; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
444; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v8
445; GCN-IR-NEXT:    v_or_b32_e32 v9, v9, v7
446; GCN-IR-NEXT:  BB1_6: ; %Flow4
447; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
448; GCN-IR-NEXT:    v_mul_lo_u32 v3, v5, v10
449; GCN-IR-NEXT:    v_mul_hi_u32 v7, v5, v9
450; GCN-IR-NEXT:    v_mul_lo_u32 v6, v6, v9
451; GCN-IR-NEXT:    v_mul_lo_u32 v5, v5, v9
452; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
453; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
454; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v5
455; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
456; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v4
457; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
458; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
459; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
460; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
461  %result = srem i64 %x, %y
462  ret i64 %result
463}
464
465define amdgpu_kernel void @s_test_srem23_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
466; GCN-LABEL: s_test_srem23_64:
467; GCN:       ; %bb.0:
468; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
469; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
470; GCN-NEXT:    s_mov_b32 s3, 0xf000
471; GCN-NEXT:    s_mov_b32 s2, -1
472; GCN-NEXT:    s_waitcnt lgkmcnt(0)
473; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 41
474; GCN-NEXT:    s_ashr_i64 s[0:1], s[0:1], 41
475; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
476; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s6
477; GCN-NEXT:    s_xor_b32 s1, s6, s0
478; GCN-NEXT:    s_ashr_i32 s1, s1, 30
479; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
480; GCN-NEXT:    s_or_b32 s1, s1, 1
481; GCN-NEXT:    v_mov_b32_e32 v3, s1
482; GCN-NEXT:    s_mov_b32 s1, s5
483; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
484; GCN-NEXT:    v_trunc_f32_e32 v2, v2
485; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
486; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
487; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
488; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
489; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
490; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
491; GCN-NEXT:    s_mov_b32 s0, s4
492; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
493; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 23
494; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
495; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
496; GCN-NEXT:    s_endpgm
497;
498; GCN-IR-LABEL: s_test_srem23_64:
499; GCN-IR:       ; %bb.0:
500; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
501; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
502; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
503; GCN-IR-NEXT:    s_mov_b32 s2, -1
504; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
505; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 41
506; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[0:1], 41
507; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
508; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s6
509; GCN-IR-NEXT:    s_xor_b32 s1, s6, s0
510; GCN-IR-NEXT:    s_ashr_i32 s1, s1, 30
511; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
512; GCN-IR-NEXT:    s_or_b32 s1, s1, 1
513; GCN-IR-NEXT:    v_mov_b32_e32 v3, s1
514; GCN-IR-NEXT:    s_mov_b32 s1, s5
515; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
516; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
517; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
518; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
519; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
520; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
521; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
522; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
523; GCN-IR-NEXT:    s_mov_b32 s0, s4
524; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
525; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 23
526; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
527; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
528; GCN-IR-NEXT:    s_endpgm
529  %1 = ashr i64 %x, 41
530  %2 = ashr i64 %y, 41
531  %result = srem i64 %1, %2
532  store i64 %result, i64 addrspace(1)* %out
533  ret void
534}
535
536define amdgpu_kernel void @s_test_srem24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
537; GCN-LABEL: s_test_srem24_64:
538; GCN:       ; %bb.0:
539; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
540; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
541; GCN-NEXT:    s_mov_b32 s3, 0xf000
542; GCN-NEXT:    s_mov_b32 s2, -1
543; GCN-NEXT:    s_waitcnt lgkmcnt(0)
544; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
545; GCN-NEXT:    s_ashr_i64 s[0:1], s[0:1], 40
546; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
547; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s6
548; GCN-NEXT:    s_xor_b32 s1, s6, s0
549; GCN-NEXT:    s_ashr_i32 s1, s1, 30
550; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
551; GCN-NEXT:    s_or_b32 s1, s1, 1
552; GCN-NEXT:    v_mov_b32_e32 v3, s1
553; GCN-NEXT:    s_mov_b32 s1, s5
554; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
555; GCN-NEXT:    v_trunc_f32_e32 v2, v2
556; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
557; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
558; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
559; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
560; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
561; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
562; GCN-NEXT:    s_mov_b32 s0, s4
563; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
564; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
565; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
566; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
567; GCN-NEXT:    s_endpgm
568;
569; GCN-IR-LABEL: s_test_srem24_64:
570; GCN-IR:       ; %bb.0:
571; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
572; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
573; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
574; GCN-IR-NEXT:    s_mov_b32 s2, -1
575; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
576; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
577; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[0:1], 40
578; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
579; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s6
580; GCN-IR-NEXT:    s_xor_b32 s1, s6, s0
581; GCN-IR-NEXT:    s_ashr_i32 s1, s1, 30
582; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
583; GCN-IR-NEXT:    s_or_b32 s1, s1, 1
584; GCN-IR-NEXT:    v_mov_b32_e32 v3, s1
585; GCN-IR-NEXT:    s_mov_b32 s1, s5
586; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
587; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
588; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
589; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
590; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
591; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
592; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
593; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
594; GCN-IR-NEXT:    s_mov_b32 s0, s4
595; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
596; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
597; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
598; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
599; GCN-IR-NEXT:    s_endpgm
600  %1 = ashr i64 %x, 40
601  %2 = ashr i64 %y, 40
602  %result = srem i64 %1, %2
603  store i64 %result, i64 addrspace(1)* %out
604  ret void
605}
606
607define i64 @v_test_srem24_64(i64 %x, i64 %y) {
608; GCN-LABEL: v_test_srem24_64:
609; GCN:       ; %bb.0:
610; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
611; GCN-NEXT:    v_ashr_i64 v[2:3], v[2:3], 40
612; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
613; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
614; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
615; GCN-NEXT:    v_xor_b32_e32 v5, v0, v2
616; GCN-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
617; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v3
618; GCN-NEXT:    v_or_b32_e32 v5, 1, v5
619; GCN-NEXT:    v_mul_f32_e32 v4, v1, v4
620; GCN-NEXT:    v_trunc_f32_e32 v4, v4
621; GCN-NEXT:    v_mad_f32 v1, -v4, v3, v1
622; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
623; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
624; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
625; GCN-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
626; GCN-NEXT:    v_mul_lo_u32 v1, v1, v2
627; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
628; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
629; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
630; GCN-NEXT:    s_setpc_b64 s[30:31]
631;
632; GCN-IR-LABEL: v_test_srem24_64:
633; GCN-IR:       ; %bb.0:
634; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
635; GCN-IR-NEXT:    v_ashr_i64 v[2:3], v[2:3], 40
636; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
637; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v3, v2
638; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
639; GCN-IR-NEXT:    v_xor_b32_e32 v5, v0, v2
640; GCN-IR-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
641; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v4, v3
642; GCN-IR-NEXT:    v_or_b32_e32 v5, 1, v5
643; GCN-IR-NEXT:    v_mul_f32_e32 v4, v1, v4
644; GCN-IR-NEXT:    v_trunc_f32_e32 v4, v4
645; GCN-IR-NEXT:    v_mad_f32 v1, -v4, v3, v1
646; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v4, v4
647; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
648; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
649; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
650; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v2
651; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
652; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
653; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
654; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
655  %1 = ashr i64 %x, 40
656  %2 = ashr i64 %y, 40
657  %result = srem i64 %1, %2
658  ret i64 %result
659}
660
661define amdgpu_kernel void @s_test_srem25_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
662; GCN-LABEL: s_test_srem25_64:
663; GCN:       ; %bb.0:
664; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
665; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
666; GCN-NEXT:    s_mov_b32 s3, 0xf000
667; GCN-NEXT:    s_mov_b32 s2, -1
668; GCN-NEXT:    s_waitcnt lgkmcnt(0)
669; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 39
670; GCN-NEXT:    s_ashr_i64 s[0:1], s[0:1], 39
671; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
672; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s6
673; GCN-NEXT:    s_xor_b32 s1, s6, s0
674; GCN-NEXT:    s_ashr_i32 s1, s1, 30
675; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
676; GCN-NEXT:    s_or_b32 s1, s1, 1
677; GCN-NEXT:    v_mov_b32_e32 v3, s1
678; GCN-NEXT:    s_mov_b32 s1, s5
679; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
680; GCN-NEXT:    v_trunc_f32_e32 v2, v2
681; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
682; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
683; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
684; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
685; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
686; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
687; GCN-NEXT:    s_mov_b32 s0, s4
688; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
689; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 25
690; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
691; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
692; GCN-NEXT:    s_endpgm
693;
694; GCN-IR-LABEL: s_test_srem25_64:
695; GCN-IR:       ; %bb.0:
696; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
697; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
698; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
699; GCN-IR-NEXT:    s_mov_b32 s2, -1
700; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
701; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 39
702; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[0:1], 39
703; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
704; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s6
705; GCN-IR-NEXT:    s_xor_b32 s1, s6, s0
706; GCN-IR-NEXT:    s_ashr_i32 s1, s1, 30
707; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
708; GCN-IR-NEXT:    s_or_b32 s1, s1, 1
709; GCN-IR-NEXT:    v_mov_b32_e32 v3, s1
710; GCN-IR-NEXT:    s_mov_b32 s1, s5
711; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
712; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
713; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
714; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
715; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
716; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
717; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
718; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
719; GCN-IR-NEXT:    s_mov_b32 s0, s4
720; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
721; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 25
722; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
723; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
724; GCN-IR-NEXT:    s_endpgm
725  %1 = ashr i64 %x, 39
726  %2 = ashr i64 %y, 39
727  %result = srem i64 %1, %2
728  store i64 %result, i64 addrspace(1)* %out
729  ret void
730}
731
732define amdgpu_kernel void @s_test_srem31_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
733; GCN-LABEL: s_test_srem31_64:
734; GCN:       ; %bb.0:
735; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
736; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
737; GCN-NEXT:    s_mov_b32 s3, 0xf000
738; GCN-NEXT:    s_mov_b32 s2, -1
739; GCN-NEXT:    s_waitcnt lgkmcnt(0)
740; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 33
741; GCN-NEXT:    s_ashr_i64 s[0:1], s[0:1], 33
742; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
743; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s6
744; GCN-NEXT:    s_xor_b32 s1, s6, s0
745; GCN-NEXT:    s_ashr_i32 s1, s1, 30
746; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
747; GCN-NEXT:    s_or_b32 s1, s1, 1
748; GCN-NEXT:    v_mov_b32_e32 v3, s1
749; GCN-NEXT:    s_mov_b32 s1, s5
750; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
751; GCN-NEXT:    v_trunc_f32_e32 v2, v2
752; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
753; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
754; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
755; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
756; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
757; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
758; GCN-NEXT:    s_mov_b32 s0, s4
759; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
760; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 31
761; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
762; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
763; GCN-NEXT:    s_endpgm
764;
765; GCN-IR-LABEL: s_test_srem31_64:
766; GCN-IR:       ; %bb.0:
767; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
768; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
769; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
770; GCN-IR-NEXT:    s_mov_b32 s2, -1
771; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
772; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 33
773; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[0:1], 33
774; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
775; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s6
776; GCN-IR-NEXT:    s_xor_b32 s1, s6, s0
777; GCN-IR-NEXT:    s_ashr_i32 s1, s1, 30
778; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
779; GCN-IR-NEXT:    s_or_b32 s1, s1, 1
780; GCN-IR-NEXT:    v_mov_b32_e32 v3, s1
781; GCN-IR-NEXT:    s_mov_b32 s1, s5
782; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
783; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
784; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
785; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
786; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
787; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
788; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
789; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
790; GCN-IR-NEXT:    s_mov_b32 s0, s4
791; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
792; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 31
793; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
794; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
795; GCN-IR-NEXT:    s_endpgm
796  %1 = ashr i64 %x, 33
797  %2 = ashr i64 %y, 33
798  %result = srem i64 %1, %2
799  store i64 %result, i64 addrspace(1)* %out
800  ret void
801}
802
803; 32 known sign bits
804define amdgpu_kernel void @s_test_srem32_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
805; GCN-LABEL: s_test_srem32_64:
806; GCN:       ; %bb.0:
807; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
808; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
809; GCN-NEXT:    s_mov_b32 s3, 0xf000
810; GCN-NEXT:    s_mov_b32 s2, -1
811; GCN-NEXT:    s_waitcnt lgkmcnt(0)
812; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s7
813; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
814; GCN-NEXT:    s_xor_b32 s1, s7, s0
815; GCN-NEXT:    s_ashr_i32 s1, s1, 30
816; GCN-NEXT:    s_or_b32 s1, s1, 1
817; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
818; GCN-NEXT:    v_mov_b32_e32 v3, s1
819; GCN-NEXT:    s_mov_b32 s1, s5
820; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
821; GCN-NEXT:    v_trunc_f32_e32 v2, v2
822; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
823; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
824; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
825; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
826; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
827; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
828; GCN-NEXT:    s_mov_b32 s0, s4
829; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s7, v0
830; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
831; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
832; GCN-NEXT:    s_endpgm
833;
834; GCN-IR-LABEL: s_test_srem32_64:
835; GCN-IR:       ; %bb.0:
836; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
837; GCN-IR-NEXT:    s_load_dword s0, s[0:1], 0xe
838; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
839; GCN-IR-NEXT:    s_mov_b32 s2, -1
840; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
841; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s7
842; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
843; GCN-IR-NEXT:    s_xor_b32 s1, s7, s0
844; GCN-IR-NEXT:    s_ashr_i32 s1, s1, 30
845; GCN-IR-NEXT:    s_or_b32 s1, s1, 1
846; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
847; GCN-IR-NEXT:    v_mov_b32_e32 v3, s1
848; GCN-IR-NEXT:    s_mov_b32 s1, s5
849; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
850; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
851; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
852; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
853; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
854; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
855; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
856; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
857; GCN-IR-NEXT:    s_mov_b32 s0, s4
858; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s7, v0
859; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
860; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
861; GCN-IR-NEXT:    s_endpgm
862  %1 = ashr i64 %x, 32
863  %2 = ashr i64 %y, 32
864  %result = srem i64 %1, %2
865  store i64 %result, i64 addrspace(1)* %out
866  ret void
867}
868
869; 33 known sign bits
870define amdgpu_kernel void @s_test_srem33_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
871; GCN-LABEL: s_test_srem33_64:
872; GCN:       ; %bb.0:
873; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
874; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
875; GCN-NEXT:    v_mov_b32_e32 v7, 0
876; GCN-NEXT:    s_mov_b32 s7, 0xf000
877; GCN-NEXT:    s_mov_b32 s6, -1
878; GCN-NEXT:    s_waitcnt lgkmcnt(0)
879; GCN-NEXT:    s_ashr_i64 s[2:3], s[10:11], 31
880; GCN-NEXT:    s_ashr_i64 s[4:5], s[0:1], 31
881; GCN-NEXT:    s_ashr_i32 s0, s1, 31
882; GCN-NEXT:    s_add_u32 s4, s4, s0
883; GCN-NEXT:    s_mov_b32 s1, s0
884; GCN-NEXT:    s_addc_u32 s5, s5, s0
885; GCN-NEXT:    s_xor_b64 s[12:13], s[4:5], s[0:1]
886; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
887; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
888; GCN-NEXT:    s_sub_u32 s0, 0, s12
889; GCN-NEXT:    s_subb_u32 s1, 0, s13
890; GCN-NEXT:    s_ashr_i32 s10, s11, 31
891; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
892; GCN-NEXT:    v_rcp_f32_e32 v0, v0
893; GCN-NEXT:    v_mov_b32_e32 v1, 0
894; GCN-NEXT:    s_mov_b32 s11, s10
895; GCN-NEXT:    s_mov_b32 s4, s8
896; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
897; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
898; GCN-NEXT:    v_trunc_f32_e32 v2, v2
899; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
900; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
901; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
902; GCN-NEXT:    s_mov_b32 s5, s9
903; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
904; GCN-NEXT:    v_mul_hi_u32 v4, s0, v0
905; GCN-NEXT:    v_mul_lo_u32 v6, s1, v0
906; GCN-NEXT:    v_mul_lo_u32 v5, s0, v0
907; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
908; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
909; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
910; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
911; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
912; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
913; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
914; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
915; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v7, v8, vcc
916; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
917; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
918; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
919; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
920; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
921; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
922; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
923; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
924; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
925; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
926; GCN-NEXT:    v_mul_hi_u32 v4, s0, v0
927; GCN-NEXT:    v_mul_lo_u32 v5, s1, v0
928; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
929; GCN-NEXT:    v_mul_lo_u32 v4, s0, v0
930; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
931; GCN-NEXT:    v_mul_lo_u32 v8, v0, v3
932; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
933; GCN-NEXT:    v_mul_hi_u32 v10, v0, v3
934; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
935; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
936; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
937; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
938; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v7, v10, vcc
939; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
940; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
941; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v6, vcc
942; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v1, vcc
943; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
944; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
945; GCN-NEXT:    s_add_u32 s0, s2, s10
946; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
947; GCN-NEXT:    s_addc_u32 s1, s3, s10
948; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
949; GCN-NEXT:    s_xor_b64 s[14:15], s[0:1], s[10:11]
950; GCN-NEXT:    v_mul_lo_u32 v3, s14, v2
951; GCN-NEXT:    v_mul_hi_u32 v4, s14, v0
952; GCN-NEXT:    v_mul_hi_u32 v5, s14, v2
953; GCN-NEXT:    v_mul_hi_u32 v6, s15, v2
954; GCN-NEXT:    v_mul_lo_u32 v2, s15, v2
955; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
956; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
957; GCN-NEXT:    v_mul_lo_u32 v5, s15, v0
958; GCN-NEXT:    v_mul_hi_u32 v0, s15, v0
959; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
960; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
961; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
962; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
963; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
964; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
965; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
966; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
967; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
968; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
969; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
970; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s15, v1
971; GCN-NEXT:    v_mov_b32_e32 v3, s13
972; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s14, v0
973; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
974; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
975; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
976; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
977; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
978; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
979; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
980; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
981; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
982; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
983; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
984; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
985; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
986; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
987; GCN-NEXT:    v_mov_b32_e32 v5, s15
988; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
989; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
990; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
991; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
992; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
993; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
994; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
995; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
996; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
997; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
998; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
999; GCN-NEXT:    v_xor_b32_e32 v0, s10, v0
1000; GCN-NEXT:    v_xor_b32_e32 v1, s10, v1
1001; GCN-NEXT:    v_mov_b32_e32 v2, s10
1002; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s10, v0
1003; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1004; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1005; GCN-NEXT:    s_endpgm
1006;
1007; GCN-IR-LABEL: s_test_srem33_64:
1008; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1009; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1010; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
1011; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1012; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[6:7], 31
1013; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 31
1014; GCN-IR-NEXT:    s_ashr_i32 s0, s7, 31
1015; GCN-IR-NEXT:    s_ashr_i32 s6, s1, 31
1016; GCN-IR-NEXT:    s_mov_b32 s1, s0
1017; GCN-IR-NEXT:    s_mov_b32 s7, s6
1018; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[2:3], s[0:1]
1019; GCN-IR-NEXT:    s_xor_b64 s[8:9], s[8:9], s[6:7]
1020; GCN-IR-NEXT:    s_sub_u32 s2, s2, s0
1021; GCN-IR-NEXT:    s_subb_u32 s3, s3, s0
1022; GCN-IR-NEXT:    s_sub_u32 s8, s8, s6
1023; GCN-IR-NEXT:    s_subb_u32 s9, s9, s6
1024; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[8:9], 0
1025; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[2:3], 0
1026; GCN-IR-NEXT:    s_mov_b64 s[6:7], 0
1027; GCN-IR-NEXT:    s_or_b64 s[16:17], s[10:11], s[12:13]
1028; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s8
1029; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s2
1030; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
1031; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s9
1032; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
1033; GCN-IR-NEXT:    s_flbit_i32_b32 s13, s3
1034; GCN-IR-NEXT:    s_min_u32 s10, s10, s11
1035; GCN-IR-NEXT:    s_min_u32 s14, s12, s13
1036; GCN-IR-NEXT:    s_sub_u32 s12, s10, s14
1037; GCN-IR-NEXT:    s_subb_u32 s13, 0, 0
1038; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[18:19], s[12:13], 63
1039; GCN-IR-NEXT:    s_mov_b32 s11, 0
1040; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[18:19]
1041; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[18:19], s[12:13], 63
1042; GCN-IR-NEXT:    s_xor_b64 s[20:21], s[16:17], -1
1043; GCN-IR-NEXT:    s_and_b64 s[18:19], s[20:21], s[18:19]
1044; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[18:19]
1045; GCN-IR-NEXT:    s_cbranch_vccz BB8_5
1046; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1047; GCN-IR-NEXT:    s_add_u32 s16, s12, 1
1048; GCN-IR-NEXT:    v_mov_b32_e32 v0, s12
1049; GCN-IR-NEXT:    s_addc_u32 s17, s13, 0
1050; GCN-IR-NEXT:    v_mov_b32_e32 v1, s13
1051; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[16:17], v[0:1]
1052; GCN-IR-NEXT:    s_sub_i32 s12, 63, s12
1053; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1054; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[2:3], s12
1055; GCN-IR-NEXT:    s_cbranch_vccz BB8_4
1056; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1057; GCN-IR-NEXT:    s_lshr_b64 s[16:17], s[2:3], s16
1058; GCN-IR-NEXT:    s_add_u32 s18, s8, -1
1059; GCN-IR-NEXT:    s_addc_u32 s19, s9, -1
1060; GCN-IR-NEXT:    s_not_b64 s[6:7], s[10:11]
1061; GCN-IR-NEXT:    s_mov_b32 s15, s11
1062; GCN-IR-NEXT:    s_add_u32 s10, s6, s14
1063; GCN-IR-NEXT:    s_addc_u32 s11, s7, s11
1064; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
1065; GCN-IR-NEXT:    s_mov_b32 s7, 0
1066; GCN-IR-NEXT:  BB8_3: ; %udiv-do-while
1067; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1068; GCN-IR-NEXT:    s_lshl_b64 s[16:17], s[16:17], 1
1069; GCN-IR-NEXT:    s_lshr_b32 s6, s13, 31
1070; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
1071; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[6:7]
1072; GCN-IR-NEXT:    s_or_b64 s[12:13], s[14:15], s[12:13]
1073; GCN-IR-NEXT:    s_sub_u32 s6, s18, s16
1074; GCN-IR-NEXT:    s_subb_u32 s6, s19, s17
1075; GCN-IR-NEXT:    s_ashr_i32 s14, s6, 31
1076; GCN-IR-NEXT:    s_mov_b32 s15, s14
1077; GCN-IR-NEXT:    s_and_b32 s6, s14, 1
1078; GCN-IR-NEXT:    s_and_b64 s[20:21], s[14:15], s[8:9]
1079; GCN-IR-NEXT:    s_sub_u32 s16, s16, s20
1080; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1081; GCN-IR-NEXT:    s_subb_u32 s17, s17, s21
1082; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
1083; GCN-IR-NEXT:    s_add_u32 s10, s10, 1
1084; GCN-IR-NEXT:    s_addc_u32 s11, s11, 0
1085; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
1086; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[6:7]
1087; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1088; GCN-IR-NEXT:    s_cbranch_vccz BB8_3
1089; GCN-IR-NEXT:  BB8_4: ; %Flow6
1090; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[12:13], 1
1091; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], s[10:11]
1092; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1093; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
1094; GCN-IR-NEXT:    s_branch BB8_6
1095; GCN-IR-NEXT:  BB8_5:
1096; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
1097; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[16:17]
1098; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1099; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[16:17]
1100; GCN-IR-NEXT:  BB8_6: ; %udiv-end
1101; GCN-IR-NEXT:    v_mul_lo_u32 v1, s8, v1
1102; GCN-IR-NEXT:    v_mul_hi_u32 v2, s8, v0
1103; GCN-IR-NEXT:    v_mul_lo_u32 v3, s9, v0
1104; GCN-IR-NEXT:    v_mul_lo_u32 v0, s8, v0
1105; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1106; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1107; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1108; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
1109; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1110; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
1111; GCN-IR-NEXT:    v_xor_b32_e32 v0, s0, v0
1112; GCN-IR-NEXT:    v_xor_b32_e32 v1, s1, v1
1113; GCN-IR-NEXT:    v_mov_b32_e32 v2, s1
1114; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
1115; GCN-IR-NEXT:    s_mov_b32 s6, -1
1116; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1117; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1118; GCN-IR-NEXT:    s_endpgm
1119  %1 = ashr i64 %x, 31
1120  %2 = ashr i64 %y, 31
1121  %result = srem i64 %1, %2
1122  store i64 %result, i64 addrspace(1)* %out
1123  ret void
1124}
1125
1126define amdgpu_kernel void @s_test_srem24_48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
1127; GCN-LABEL: s_test_srem24_48:
1128; GCN:       ; %bb.0:
1129; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
1130; GCN-NEXT:    s_load_dword s2, s[0:1], 0xb
1131; GCN-NEXT:    s_load_dword s3, s[0:1], 0xc
1132; GCN-NEXT:    s_load_dword s6, s[0:1], 0xd
1133; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
1134; GCN-NEXT:    s_mov_b32 s7, 0xf000
1135; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1136; GCN-NEXT:    v_mov_b32_e32 v2, s2
1137; GCN-NEXT:    s_sext_i32_i16 s1, s3
1138; GCN-NEXT:    v_mov_b32_e32 v0, s6
1139; GCN-NEXT:    s_sext_i32_i16 s0, s0
1140; GCN-NEXT:    v_alignbit_b32 v0, s0, v0, 24
1141; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
1142; GCN-NEXT:    v_alignbit_b32 v2, s1, v2, 24
1143; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
1144; GCN-NEXT:    v_xor_b32_e32 v5, v2, v0
1145; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v1
1146; GCN-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
1147; GCN-NEXT:    v_or_b32_e32 v5, 1, v5
1148; GCN-NEXT:    s_mov_b32 s6, -1
1149; GCN-NEXT:    v_mul_f32_e32 v4, v3, v4
1150; GCN-NEXT:    v_trunc_f32_e32 v4, v4
1151; GCN-NEXT:    v_mad_f32 v3, -v4, v1, v3
1152; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
1153; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1154; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
1155; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
1156; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
1157; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v2, v0
1158; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1159; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1160; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
1161; GCN-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
1162; GCN-NEXT:    s_endpgm
1163;
1164; GCN-IR-LABEL: s_test_srem24_48:
1165; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1166; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
1167; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xb
1168; GCN-IR-NEXT:    s_load_dword s3, s[0:1], 0xc
1169; GCN-IR-NEXT:    s_load_dword s6, s[0:1], 0xd
1170; GCN-IR-NEXT:    s_load_dword s0, s[0:1], 0xe
1171; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1172; GCN-IR-NEXT:    s_sext_i32_i16 s3, s3
1173; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[2:3], 24
1174; GCN-IR-NEXT:    s_sext_i32_i16 s7, s0
1175; GCN-IR-NEXT:    s_ashr_i32 s0, s3, 31
1176; GCN-IR-NEXT:    s_ashr_i32 s12, s7, 31
1177; GCN-IR-NEXT:    s_ashr_i64 s[10:11], s[6:7], 24
1178; GCN-IR-NEXT:    s_mov_b32 s1, s0
1179; GCN-IR-NEXT:    s_mov_b32 s13, s12
1180; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[8:9], s[0:1]
1181; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[10:11], s[12:13]
1182; GCN-IR-NEXT:    s_sub_u32 s2, s2, s0
1183; GCN-IR-NEXT:    s_subb_u32 s3, s3, s0
1184; GCN-IR-NEXT:    s_sub_u32 s6, s6, s12
1185; GCN-IR-NEXT:    s_subb_u32 s7, s7, s12
1186; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
1187; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[2:3], 0
1188; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1189; GCN-IR-NEXT:    s_or_b64 s[16:17], s[10:11], s[12:13]
1190; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s6
1191; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s2
1192; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
1193; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s7
1194; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
1195; GCN-IR-NEXT:    s_flbit_i32_b32 s13, s3
1196; GCN-IR-NEXT:    s_min_u32 s10, s10, s11
1197; GCN-IR-NEXT:    s_min_u32 s14, s12, s13
1198; GCN-IR-NEXT:    s_sub_u32 s12, s10, s14
1199; GCN-IR-NEXT:    s_subb_u32 s13, 0, 0
1200; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[18:19], s[12:13], 63
1201; GCN-IR-NEXT:    s_mov_b32 s11, 0
1202; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[18:19]
1203; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[18:19], s[12:13], 63
1204; GCN-IR-NEXT:    s_xor_b64 s[20:21], s[16:17], -1
1205; GCN-IR-NEXT:    s_and_b64 s[18:19], s[20:21], s[18:19]
1206; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[18:19]
1207; GCN-IR-NEXT:    s_cbranch_vccz BB9_5
1208; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1209; GCN-IR-NEXT:    s_add_u32 s16, s12, 1
1210; GCN-IR-NEXT:    v_mov_b32_e32 v0, s12
1211; GCN-IR-NEXT:    s_addc_u32 s17, s13, 0
1212; GCN-IR-NEXT:    v_mov_b32_e32 v1, s13
1213; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[16:17], v[0:1]
1214; GCN-IR-NEXT:    s_sub_i32 s12, 63, s12
1215; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1216; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[2:3], s12
1217; GCN-IR-NEXT:    s_cbranch_vccz BB9_4
1218; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1219; GCN-IR-NEXT:    s_lshr_b64 s[16:17], s[2:3], s16
1220; GCN-IR-NEXT:    s_add_u32 s18, s6, -1
1221; GCN-IR-NEXT:    s_addc_u32 s19, s7, -1
1222; GCN-IR-NEXT:    s_not_b64 s[8:9], s[10:11]
1223; GCN-IR-NEXT:    s_mov_b32 s15, s11
1224; GCN-IR-NEXT:    s_add_u32 s10, s8, s14
1225; GCN-IR-NEXT:    s_addc_u32 s11, s9, s11
1226; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
1227; GCN-IR-NEXT:    s_mov_b32 s9, 0
1228; GCN-IR-NEXT:  BB9_3: ; %udiv-do-while
1229; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1230; GCN-IR-NEXT:    s_lshl_b64 s[16:17], s[16:17], 1
1231; GCN-IR-NEXT:    s_lshr_b32 s8, s13, 31
1232; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
1233; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[8:9]
1234; GCN-IR-NEXT:    s_or_b64 s[12:13], s[14:15], s[12:13]
1235; GCN-IR-NEXT:    s_sub_u32 s8, s18, s16
1236; GCN-IR-NEXT:    s_subb_u32 s8, s19, s17
1237; GCN-IR-NEXT:    s_ashr_i32 s14, s8, 31
1238; GCN-IR-NEXT:    s_mov_b32 s15, s14
1239; GCN-IR-NEXT:    s_and_b32 s8, s14, 1
1240; GCN-IR-NEXT:    s_and_b64 s[20:21], s[14:15], s[6:7]
1241; GCN-IR-NEXT:    s_sub_u32 s16, s16, s20
1242; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1243; GCN-IR-NEXT:    s_subb_u32 s17, s17, s21
1244; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
1245; GCN-IR-NEXT:    s_add_u32 s10, s10, 1
1246; GCN-IR-NEXT:    s_addc_u32 s11, s11, 0
1247; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
1248; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[8:9]
1249; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1250; GCN-IR-NEXT:    s_cbranch_vccz BB9_3
1251; GCN-IR-NEXT:  BB9_4: ; %Flow3
1252; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[12:13], 1
1253; GCN-IR-NEXT:    s_or_b64 s[8:9], s[8:9], s[10:11]
1254; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
1255; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
1256; GCN-IR-NEXT:    s_branch BB9_6
1257; GCN-IR-NEXT:  BB9_5:
1258; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
1259; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[16:17]
1260; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1261; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[16:17]
1262; GCN-IR-NEXT:  BB9_6: ; %udiv-end
1263; GCN-IR-NEXT:    v_mul_lo_u32 v1, s6, v1
1264; GCN-IR-NEXT:    v_mul_hi_u32 v2, s6, v0
1265; GCN-IR-NEXT:    v_mul_lo_u32 v3, s7, v0
1266; GCN-IR-NEXT:    v_mul_lo_u32 v0, s6, v0
1267; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1268; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1269; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1270; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
1271; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1272; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
1273; GCN-IR-NEXT:    v_xor_b32_e32 v0, s0, v0
1274; GCN-IR-NEXT:    v_xor_b32_e32 v1, s1, v1
1275; GCN-IR-NEXT:    v_mov_b32_e32 v2, s1
1276; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
1277; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1278; GCN-IR-NEXT:    s_mov_b32 s6, -1
1279; GCN-IR-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
1280; GCN-IR-NEXT:    buffer_store_dword v0, off, s[4:7], 0
1281; GCN-IR-NEXT:    s_endpgm
1282  %1 = ashr i48 %x, 24
1283  %2 = ashr i48 %y, 24
1284  %result = srem i48 %1, %2
1285  store i48 %result, i48 addrspace(1)* %out
1286  ret void
1287}
1288
1289define amdgpu_kernel void @s_test_srem_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1290; GCN-LABEL: s_test_srem_k_num_i64:
1291; GCN:       ; %bb.0:
1292; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1293; GCN-NEXT:    v_mov_b32_e32 v2, 0
1294; GCN-NEXT:    s_mov_b32 s7, 0xf000
1295; GCN-NEXT:    s_mov_b32 s6, -1
1296; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1297; GCN-NEXT:    s_ashr_i32 s4, s3, 31
1298; GCN-NEXT:    s_add_u32 s2, s2, s4
1299; GCN-NEXT:    s_mov_b32 s5, s4
1300; GCN-NEXT:    s_addc_u32 s3, s3, s4
1301; GCN-NEXT:    s_xor_b64 s[8:9], s[2:3], s[4:5]
1302; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
1303; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s9
1304; GCN-NEXT:    s_sub_u32 s2, 0, s8
1305; GCN-NEXT:    s_subb_u32 s3, 0, s9
1306; GCN-NEXT:    s_mov_b32 s4, s0
1307; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
1308; GCN-NEXT:    v_rcp_f32_e32 v0, v0
1309; GCN-NEXT:    v_mov_b32_e32 v1, 0
1310; GCN-NEXT:    s_mov_b32 s5, s1
1311; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
1312; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
1313; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1314; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
1315; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1316; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
1317; GCN-NEXT:    v_mul_lo_u32 v4, s2, v3
1318; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
1319; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
1320; GCN-NEXT:    v_mul_lo_u32 v6, s2, v0
1321; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1322; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
1323; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
1324; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
1325; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
1326; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
1327; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
1328; GCN-NEXT:    v_mul_hi_u32 v10, v3, v4
1329; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
1330; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
1331; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1332; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
1333; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
1334; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
1335; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1336; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
1337; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
1338; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
1339; GCN-NEXT:    v_mul_lo_u32 v4, s2, v3
1340; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
1341; GCN-NEXT:    v_mul_lo_u32 v6, s3, v0
1342; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1343; GCN-NEXT:    v_mul_lo_u32 v5, s2, v0
1344; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
1345; GCN-NEXT:    v_mul_lo_u32 v8, v0, v4
1346; GCN-NEXT:    v_mul_hi_u32 v9, v0, v5
1347; GCN-NEXT:    v_mul_hi_u32 v10, v0, v4
1348; GCN-NEXT:    v_mul_hi_u32 v7, v3, v5
1349; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
1350; GCN-NEXT:    v_mul_hi_u32 v6, v3, v4
1351; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1352; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v2, v10, vcc
1353; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1354; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
1355; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v7, vcc
1356; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
1357; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1358; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
1359; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
1360; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
1361; GCN-NEXT:    v_mul_lo_u32 v3, v1, 24
1362; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
1363; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
1364; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
1365; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v2, v1, vcc
1366; GCN-NEXT:    v_mul_lo_u32 v1, s9, v0
1367; GCN-NEXT:    v_mul_hi_u32 v2, s8, v0
1368; GCN-NEXT:    v_mul_lo_u32 v0, s8, v0
1369; GCN-NEXT:    v_mov_b32_e32 v3, s9
1370; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1371; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
1372; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1373; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
1374; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s8, v0
1375; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
1376; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s9, v5
1377; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
1378; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s8, v4
1379; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
1380; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
1381; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s9, v5
1382; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s8, v4
1383; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
1384; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
1385; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1386; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
1387; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
1388; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
1389; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
1390; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
1391; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1392; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v1
1393; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
1394; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
1395; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1396; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
1397; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1398; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1399; GCN-NEXT:    s_endpgm
1400;
1401; GCN-IR-LABEL: s_test_srem_k_num_i64:
1402; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1403; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1404; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1405; GCN-IR-NEXT:    s_ashr_i32 s6, s3, 31
1406; GCN-IR-NEXT:    s_mov_b32 s7, s6
1407; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[2:3], s[6:7]
1408; GCN-IR-NEXT:    s_sub_u32 s4, s2, s6
1409; GCN-IR-NEXT:    s_subb_u32 s5, s3, s6
1410; GCN-IR-NEXT:    s_flbit_i32_b32 s2, s4
1411; GCN-IR-NEXT:    s_add_i32 s2, s2, 32
1412; GCN-IR-NEXT:    s_flbit_i32_b32 s3, s5
1413; GCN-IR-NEXT:    s_min_u32 s6, s2, s3
1414; GCN-IR-NEXT:    s_add_u32 s8, s6, 0xffffffc5
1415; GCN-IR-NEXT:    s_addc_u32 s9, 0, -1
1416; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[4:5], 0
1417; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[12:13], s[8:9], 63
1418; GCN-IR-NEXT:    s_mov_b64 s[2:3], 0
1419; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
1420; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[12:13], s[8:9], 63
1421; GCN-IR-NEXT:    s_xor_b64 s[14:15], s[10:11], -1
1422; GCN-IR-NEXT:    s_and_b64 s[12:13], s[14:15], s[12:13]
1423; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
1424; GCN-IR-NEXT:    s_cbranch_vccz BB10_5
1425; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1426; GCN-IR-NEXT:    s_add_u32 s10, s8, 1
1427; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
1428; GCN-IR-NEXT:    s_addc_u32 s11, s9, 0
1429; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
1430; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
1431; GCN-IR-NEXT:    s_sub_i32 s7, 63, s8
1432; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1433; GCN-IR-NEXT:    s_lshl_b64 s[8:9], 24, s7
1434; GCN-IR-NEXT:    s_cbranch_vccz BB10_4
1435; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1436; GCN-IR-NEXT:    s_lshr_b64 s[12:13], 24, s10
1437; GCN-IR-NEXT:    s_add_u32 s14, s4, -1
1438; GCN-IR-NEXT:    s_addc_u32 s15, s5, -1
1439; GCN-IR-NEXT:    s_sub_u32 s6, 58, s6
1440; GCN-IR-NEXT:    s_subb_u32 s7, 0, 0
1441; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1442; GCN-IR-NEXT:    s_mov_b32 s3, 0
1443; GCN-IR-NEXT:  BB10_3: ; %udiv-do-while
1444; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1445; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
1446; GCN-IR-NEXT:    s_lshr_b32 s2, s9, 31
1447; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
1448; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[2:3]
1449; GCN-IR-NEXT:    s_or_b64 s[8:9], s[10:11], s[8:9]
1450; GCN-IR-NEXT:    s_sub_u32 s2, s14, s12
1451; GCN-IR-NEXT:    s_subb_u32 s2, s15, s13
1452; GCN-IR-NEXT:    s_ashr_i32 s10, s2, 31
1453; GCN-IR-NEXT:    s_mov_b32 s11, s10
1454; GCN-IR-NEXT:    s_and_b32 s2, s10, 1
1455; GCN-IR-NEXT:    s_and_b64 s[16:17], s[10:11], s[4:5]
1456; GCN-IR-NEXT:    s_sub_u32 s12, s12, s16
1457; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1458; GCN-IR-NEXT:    s_subb_u32 s13, s13, s17
1459; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
1460; GCN-IR-NEXT:    s_add_u32 s6, s6, 1
1461; GCN-IR-NEXT:    s_addc_u32 s7, s7, 0
1462; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1]
1463; GCN-IR-NEXT:    s_mov_b64 s[10:11], s[2:3]
1464; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1465; GCN-IR-NEXT:    s_cbranch_vccz BB10_3
1466; GCN-IR-NEXT:  BB10_4: ; %Flow5
1467; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[8:9], 1
1468; GCN-IR-NEXT:    s_or_b64 s[2:3], s[2:3], s[6:7]
1469; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1470; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
1471; GCN-IR-NEXT:    s_branch BB10_6
1472; GCN-IR-NEXT:  BB10_5:
1473; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1474; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, 24, 0, s[10:11]
1475; GCN-IR-NEXT:  BB10_6: ; %udiv-end
1476; GCN-IR-NEXT:    v_mul_lo_u32 v1, s4, v1
1477; GCN-IR-NEXT:    v_mul_hi_u32 v2, s4, v0
1478; GCN-IR-NEXT:    v_mul_lo_u32 v3, s5, v0
1479; GCN-IR-NEXT:    v_mul_lo_u32 v0, s4, v0
1480; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1481; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1482; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1483; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1484; GCN-IR-NEXT:    s_mov_b32 s2, -1
1485; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1486; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1487; GCN-IR-NEXT:    s_endpgm
1488  %result = srem i64 24, %x
1489  store i64 %result, i64 addrspace(1)* %out
1490  ret void
1491}
1492
1493define i64 @v_test_srem_k_num_i64(i64 %x) {
1494; GCN-LABEL: v_test_srem_k_num_i64:
1495; GCN:       ; %bb.0:
1496; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1497; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1498; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1499; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1500; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1501; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1502; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1503; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1504; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1505; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1506; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
1507; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1508; GCN-NEXT:    v_mov_b32_e32 v12, 0
1509; GCN-NEXT:    v_mov_b32_e32 v11, 0
1510; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1511; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1512; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1513; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1514; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1515; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1516; GCN-NEXT:    v_mul_hi_u32 v6, v4, v2
1517; GCN-NEXT:    v_mul_lo_u32 v7, v4, v3
1518; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1519; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
1520; GCN-NEXT:    v_mul_lo_u32 v7, v4, v2
1521; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1522; GCN-NEXT:    v_mul_lo_u32 v9, v2, v6
1523; GCN-NEXT:    v_mul_hi_u32 v10, v2, v7
1524; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
1525; GCN-NEXT:    v_mul_hi_u32 v13, v3, v6
1526; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1527; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1528; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
1529; GCN-NEXT:    v_mul_hi_u32 v7, v3, v7
1530; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v8, vcc
1531; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
1532; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v7, vcc
1533; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v11, vcc
1534; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1535; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v8, vcc
1536; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
1537; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v7, vcc
1538; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1539; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1540; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1541; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1542; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1543; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
1544; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
1545; GCN-NEXT:    v_mul_hi_u32 v9, v2, v4
1546; GCN-NEXT:    v_mul_hi_u32 v10, v2, v5
1547; GCN-NEXT:    v_mul_hi_u32 v7, v3, v4
1548; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1549; GCN-NEXT:    v_mul_hi_u32 v6, v3, v5
1550; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1551; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v12, v10, vcc
1552; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
1553; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
1554; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
1555; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v11, vcc
1556; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1557; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
1558; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1559; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
1560; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
1561; GCN-NEXT:    v_mul_hi_u32 v2, v2, 24
1562; GCN-NEXT:    v_mul_hi_u32 v3, v3, 24
1563; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1564; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v12, v3, vcc
1565; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
1566; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1567; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
1568; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1569; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
1570; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 24, v2
1571; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
1572; GCN-NEXT:    v_sub_i32_e64 v5, s[4:5], v2, v0
1573; GCN-NEXT:    v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
1574; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v1
1575; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[6:7]
1576; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v5, v0
1577; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
1578; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v6, v1
1579; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
1580; GCN-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[6:7]
1581; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v5, v0
1582; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1583; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
1584; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1585; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1586; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
1587; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v0
1588; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1589; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1590; GCN-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
1591; GCN-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[4:5]
1592; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1593; GCN-NEXT:    v_cndmask_b32_e64 v1, v6, v4, s[4:5]
1594; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1595; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1596; GCN-NEXT:    s_setpc_b64 s[30:31]
1597;
1598; GCN-IR-LABEL: v_test_srem_k_num_i64:
1599; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1600; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1601; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1602; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1603; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
1604; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1605; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1606; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1607; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1608; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1609; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1610; GCN-IR-NEXT:    s_movk_i32 s6, 0xffc5
1611; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, s6, v6
1612; GCN-IR-NEXT:    v_addc_u32_e64 v4, s[6:7], 0, -1, vcc
1613; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1614; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[3:4]
1615; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1616; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1617; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[3:4]
1618; GCN-IR-NEXT:    v_cndmask_b32_e64 v2, 24, 0, s[4:5]
1619; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1620; GCN-IR-NEXT:    v_mov_b32_e32 v5, v7
1621; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1622; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1623; GCN-IR-NEXT:    s_cbranch_execz BB11_6
1624; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1625; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v3
1626; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v4, vcc
1627; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v3
1628; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[8:9], v[3:4]
1629; GCN-IR-NEXT:    v_lshl_b64 v[2:3], 24, v2
1630; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1631; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1632; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1633; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1634; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1635; GCN-IR-NEXT:    s_cbranch_execz BB11_5
1636; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1637; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, -1, v0
1638; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, -1, v1, vcc
1639; GCN-IR-NEXT:    v_lshr_b64 v[8:9], 24, v8
1640; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, 58, v6
1641; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1642; GCN-IR-NEXT:    v_subb_u32_e32 v7, vcc, 0, v7, vcc
1643; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1644; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1645; GCN-IR-NEXT:  BB11_3: ; %udiv-do-while
1646; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1647; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1648; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1649; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1650; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1651; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, v12, v8
1652; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, v13, v9, vcc
1653; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1654; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1655; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1656; GCN-IR-NEXT:    v_and_b32_e32 v14, v10, v1
1657; GCN-IR-NEXT:    v_and_b32_e32 v15, v10, v0
1658; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v6
1659; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1660; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v7, vcc
1661; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7]
1662; GCN-IR-NEXT:    v_mov_b32_e32 v6, v10
1663; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v15
1664; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1665; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1666; GCN-IR-NEXT:    v_subb_u32_e64 v9, s[4:5], v9, v14, s[4:5]
1667; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1668; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1669; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1670; GCN-IR-NEXT:    s_cbranch_execnz BB11_3
1671; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1672; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1673; GCN-IR-NEXT:  BB11_5: ; %Flow3
1674; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1675; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1676; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1677; GCN-IR-NEXT:    v_or_b32_e32 v2, v4, v2
1678; GCN-IR-NEXT:  BB11_6: ; %Flow4
1679; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1680; GCN-IR-NEXT:    v_mul_lo_u32 v3, v0, v5
1681; GCN-IR-NEXT:    v_mul_hi_u32 v4, v0, v2
1682; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v2
1683; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, v2
1684; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1685; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
1686; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1687; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1688; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1689  %result = srem i64 24, %x
1690  ret i64 %result
1691}
1692
1693define i64 @v_test_srem_pow2_k_num_i64(i64 %x) {
1694; GCN-LABEL: v_test_srem_pow2_k_num_i64:
1695; GCN:       ; %bb.0:
1696; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1697; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1698; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1699; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1700; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1701; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1702; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1703; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1704; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1705; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1706; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
1707; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1708; GCN-NEXT:    v_mov_b32_e32 v12, 0
1709; GCN-NEXT:    v_mov_b32_e32 v11, 0
1710; GCN-NEXT:    s_mov_b32 s4, 0x8000
1711; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1712; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1713; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1714; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1715; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1716; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1717; GCN-NEXT:    v_mul_hi_u32 v6, v4, v2
1718; GCN-NEXT:    v_mul_lo_u32 v7, v4, v3
1719; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1720; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
1721; GCN-NEXT:    v_mul_lo_u32 v7, v4, v2
1722; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1723; GCN-NEXT:    v_mul_lo_u32 v9, v2, v6
1724; GCN-NEXT:    v_mul_hi_u32 v10, v2, v7
1725; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
1726; GCN-NEXT:    v_mul_hi_u32 v13, v3, v6
1727; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1728; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1729; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
1730; GCN-NEXT:    v_mul_hi_u32 v7, v3, v7
1731; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v8, vcc
1732; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
1733; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v7, vcc
1734; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v11, vcc
1735; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1736; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v8, vcc
1737; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
1738; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v7, vcc
1739; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1740; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1741; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1742; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1743; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1744; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
1745; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
1746; GCN-NEXT:    v_mul_hi_u32 v9, v2, v4
1747; GCN-NEXT:    v_mul_hi_u32 v10, v2, v5
1748; GCN-NEXT:    v_mul_hi_u32 v7, v3, v4
1749; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1750; GCN-NEXT:    v_mul_hi_u32 v6, v3, v5
1751; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1752; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v12, v10, vcc
1753; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
1754; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
1755; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
1756; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v11, vcc
1757; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1758; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
1759; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1760; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
1761; GCN-NEXT:    v_lshrrev_b32_e32 v4, 17, v3
1762; GCN-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
1763; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1764; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
1765; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v12, v4, vcc
1766; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
1767; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1768; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
1769; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1770; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
1771; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s4, v2
1772; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
1773; GCN-NEXT:    v_sub_i32_e64 v5, s[4:5], v2, v0
1774; GCN-NEXT:    v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
1775; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v1
1776; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[6:7]
1777; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v5, v0
1778; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
1779; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v6, v1
1780; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
1781; GCN-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[6:7]
1782; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v5, v0
1783; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1784; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
1785; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1786; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1787; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
1788; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v0
1789; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1790; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1791; GCN-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
1792; GCN-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[4:5]
1793; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1794; GCN-NEXT:    v_cndmask_b32_e64 v1, v6, v4, s[4:5]
1795; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1796; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1797; GCN-NEXT:    s_setpc_b64 s[30:31]
1798;
1799; GCN-IR-LABEL: v_test_srem_pow2_k_num_i64:
1800; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1801; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1802; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1803; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1804; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
1805; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1806; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1807; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1808; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1809; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1810; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1811; GCN-IR-NEXT:    s_movk_i32 s6, 0xffd0
1812; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, s6, v6
1813; GCN-IR-NEXT:    v_addc_u32_e64 v3, s[6:7], 0, -1, vcc
1814; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1815; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[2:3]
1816; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0x8000
1817; GCN-IR-NEXT:    v_mov_b32_e32 v4, s8
1818; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1819; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[2:3]
1820; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1821; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v4, 0, s[4:5]
1822; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1823; GCN-IR-NEXT:    v_mov_b32_e32 v5, v7
1824; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1825; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1826; GCN-IR-NEXT:    s_cbranch_execz BB12_6
1827; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1828; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v2
1829; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v3, vcc
1830; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[8:9], v[2:3]
1831; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v2
1832; GCN-IR-NEXT:    v_lshl_b64 v[2:3], s[8:9], v2
1833; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1834; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1835; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1836; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1837; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1838; GCN-IR-NEXT:    s_cbranch_execz BB12_5
1839; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1840; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, -1, v0
1841; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0x8000
1842; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, -1, v1, vcc
1843; GCN-IR-NEXT:    v_lshr_b64 v[8:9], s[4:5], v8
1844; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, 47, v6
1845; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1846; GCN-IR-NEXT:    v_subb_u32_e32 v7, vcc, 0, v7, vcc
1847; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1848; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1849; GCN-IR-NEXT:  BB12_3: ; %udiv-do-while
1850; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1851; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1852; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1853; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1854; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1855; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, v12, v8
1856; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, v13, v9, vcc
1857; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1858; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1859; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1860; GCN-IR-NEXT:    v_and_b32_e32 v14, v10, v1
1861; GCN-IR-NEXT:    v_and_b32_e32 v15, v10, v0
1862; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v6
1863; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1864; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v7, vcc
1865; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7]
1866; GCN-IR-NEXT:    v_mov_b32_e32 v6, v10
1867; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v15
1868; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1869; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1870; GCN-IR-NEXT:    v_subb_u32_e64 v9, s[4:5], v9, v14, s[4:5]
1871; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1872; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1873; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1874; GCN-IR-NEXT:    s_cbranch_execnz BB12_3
1875; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1876; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1877; GCN-IR-NEXT:  BB12_5: ; %Flow3
1878; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1879; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1880; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1881; GCN-IR-NEXT:    v_or_b32_e32 v4, v4, v2
1882; GCN-IR-NEXT:  BB12_6: ; %Flow4
1883; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1884; GCN-IR-NEXT:    v_mul_lo_u32 v2, v0, v5
1885; GCN-IR-NEXT:    v_mul_hi_u32 v3, v0, v4
1886; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v4
1887; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, v4
1888; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1889; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1890; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1891; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1892; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1893  %result = srem i64 32768, %x
1894  ret i64 %result
1895}
1896
1897define i64 @v_test_srem_pow2_k_den_i64(i64 %x) {
1898; GCN-LABEL: v_test_srem_pow2_k_den_i64:
1899; GCN:       ; %bb.0:
1900; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1901; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1902; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1903; GCN-NEXT:    v_add_i32_e32 v2, vcc, v0, v2
1904; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
1905; GCN-NEXT:    v_and_b32_e32 v2, 0xffff8000, v2
1906; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1907; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1908; GCN-NEXT:    s_setpc_b64 s[30:31]
1909;
1910; GCN-IR-LABEL: v_test_srem_pow2_k_den_i64:
1911; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1912; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1913; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1914; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1915; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
1916; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1917; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1918; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v0
1919; GCN-IR-NEXT:    v_add_i32_e64 v3, s[4:5], 32, v3
1920; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v1
1921; GCN-IR-NEXT:    v_min_u32_e32 v8, v3, v4
1922; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 48, v8
1923; GCN-IR-NEXT:    v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5]
1924; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1925; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
1926; GCN-IR-NEXT:    v_mov_b32_e32 v3, v2
1927; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1928; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1929; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1930; GCN-IR-NEXT:    v_cndmask_b32_e64 v7, v1, 0, s[4:5]
1931; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v0, 0, s[4:5]
1932; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1933; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1934; GCN-IR-NEXT:    s_cbranch_execz BB13_6
1935; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1936; GCN-IR-NEXT:    v_add_i32_e32 v9, vcc, 1, v4
1937; GCN-IR-NEXT:    v_addc_u32_e32 v10, vcc, 0, v5, vcc
1938; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[9:10], v[4:5]
1939; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v4
1940; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[0:1], v4
1941; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1942; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1943; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1944; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1945; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1946; GCN-IR-NEXT:    s_cbranch_execz BB13_5
1947; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1948; GCN-IR-NEXT:    v_lshr_b64 v[10:11], v[0:1], v9
1949; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 0xffffffcf, v8
1950; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1951; GCN-IR-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, -1, vcc
1952; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1953; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1954; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
1955; GCN-IR-NEXT:  BB13_3: ; %udiv-do-while
1956; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1957; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
1958; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
1959; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v6
1960; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
1961; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, s12, v10
1962; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, 0, v11, vcc
1963; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
1964; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v6
1965; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v12
1966; GCN-IR-NEXT:    v_and_b32_e32 v15, 0x8000, v12
1967; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
1968; GCN-IR-NEXT:    v_or_b32_e32 v5, v13, v5
1969; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
1970; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
1971; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
1972; GCN-IR-NEXT:    v_mov_b32_e32 v14, 0
1973; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v15
1974; GCN-IR-NEXT:    v_mov_b32_e32 v9, v13
1975; GCN-IR-NEXT:    v_mov_b32_e32 v13, v7
1976; GCN-IR-NEXT:    v_subb_u32_e64 v11, s[4:5], v11, v14, s[4:5]
1977; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1978; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
1979; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1980; GCN-IR-NEXT:    s_cbranch_execnz BB13_3
1981; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1982; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1983; GCN-IR-NEXT:  BB13_5: ; %Flow3
1984; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1985; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
1986; GCN-IR-NEXT:    v_or_b32_e32 v7, v7, v5
1987; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v4
1988; GCN-IR-NEXT:  BB13_6: ; %Flow4
1989; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1990; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[6:7], 15
1991; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
1992; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
1993; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1994; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v3
1995; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1996; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1997; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1998  %result = srem i64 %x, 32768
1999  ret i64 %result
2000}
2001
2002define amdgpu_kernel void @s_test_srem24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
2003; GCN-LABEL: s_test_srem24_k_num_i64:
2004; GCN:       ; %bb.0:
2005; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
2006; GCN-NEXT:    s_mov_b32 s6, 0x41c00000
2007; GCN-NEXT:    s_waitcnt lgkmcnt(0)
2008; GCN-NEXT:    s_ashr_i64 s[4:5], s[2:3], 40
2009; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
2010; GCN-NEXT:    s_ashr_i32 s5, s4, 30
2011; GCN-NEXT:    s_or_b32 s5, s5, 1
2012; GCN-NEXT:    v_mov_b32_e32 v3, s5
2013; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
2014; GCN-NEXT:    s_mov_b32 s3, 0xf000
2015; GCN-NEXT:    s_mov_b32 s2, -1
2016; GCN-NEXT:    v_mul_f32_e32 v1, s6, v1
2017; GCN-NEXT:    v_trunc_f32_e32 v1, v1
2018; GCN-NEXT:    v_mad_f32 v2, -v1, v0, s6
2019; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
2020; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
2021; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
2022; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
2023; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
2024; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2025; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2026; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2027; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2028; GCN-NEXT:    s_endpgm
2029;
2030; GCN-IR-LABEL: s_test_srem24_k_num_i64:
2031; GCN-IR:       ; %bb.0:
2032; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
2033; GCN-IR-NEXT:    s_mov_b32 s6, 0x41c00000
2034; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
2035; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[2:3], 40
2036; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
2037; GCN-IR-NEXT:    s_ashr_i32 s5, s4, 30
2038; GCN-IR-NEXT:    s_or_b32 s5, s5, 1
2039; GCN-IR-NEXT:    v_mov_b32_e32 v3, s5
2040; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
2041; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
2042; GCN-IR-NEXT:    s_mov_b32 s2, -1
2043; GCN-IR-NEXT:    v_mul_f32_e32 v1, s6, v1
2044; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
2045; GCN-IR-NEXT:    v_mad_f32 v2, -v1, v0, s6
2046; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
2047; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
2048; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
2049; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
2050; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
2051; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2052; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2053; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2054; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2055; GCN-IR-NEXT:    s_endpgm
2056  %x.shr = ashr i64 %x, 40
2057  %result = srem i64 24, %x.shr
2058  store i64 %result, i64 addrspace(1)* %out
2059  ret void
2060}
2061
2062define amdgpu_kernel void @s_test_srem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
2063; GCN-LABEL: s_test_srem24_k_den_i64:
2064; GCN:       ; %bb.0:
2065; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
2066; GCN-NEXT:    s_mov_b32 s1, 0x46b6fe00
2067; GCN-NEXT:    s_mov_b32 s3, 0xf000
2068; GCN-NEXT:    s_mov_b32 s2, -1
2069; GCN-NEXT:    s_waitcnt lgkmcnt(0)
2070; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
2071; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s6
2072; GCN-NEXT:    s_ashr_i32 s0, s6, 30
2073; GCN-NEXT:    s_or_b32 s0, s0, 1
2074; GCN-NEXT:    v_mov_b32_e32 v1, s0
2075; GCN-NEXT:    v_mul_f32_e32 v2, 0x38331158, v0
2076; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2077; GCN-NEXT:    v_mad_f32 v0, -v2, s1, v0
2078; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2079; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s1
2080; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
2081; GCN-NEXT:    s_movk_i32 s0, 0x5b7f
2082; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
2083; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
2084; GCN-NEXT:    s_mov_b32 s0, s4
2085; GCN-NEXT:    s_mov_b32 s1, s5
2086; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
2087; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2088; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2089; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2090; GCN-NEXT:    s_endpgm
2091;
2092; GCN-IR-LABEL: s_test_srem24_k_den_i64:
2093; GCN-IR:       ; %bb.0:
2094; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
2095; GCN-IR-NEXT:    s_mov_b32 s1, 0x46b6fe00
2096; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
2097; GCN-IR-NEXT:    s_mov_b32 s2, -1
2098; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
2099; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
2100; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s6
2101; GCN-IR-NEXT:    s_ashr_i32 s0, s6, 30
2102; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
2103; GCN-IR-NEXT:    v_mov_b32_e32 v1, s0
2104; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x38331158, v0
2105; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2106; GCN-IR-NEXT:    v_mad_f32 v0, -v2, s1, v0
2107; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2108; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s1
2109; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
2110; GCN-IR-NEXT:    s_movk_i32 s0, 0x5b7f
2111; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
2112; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
2113; GCN-IR-NEXT:    s_mov_b32 s0, s4
2114; GCN-IR-NEXT:    s_mov_b32 s1, s5
2115; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
2116; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2117; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2118; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2119; GCN-IR-NEXT:    s_endpgm
2120  %x.shr = ashr i64 %x, 40
2121  %result = srem i64 %x.shr, 23423
2122  store i64 %result, i64 addrspace(1)* %out
2123  ret void
2124}
2125
2126define i64 @v_test_srem24_k_num_i64(i64 %x) {
2127; GCN-LABEL: v_test_srem24_k_num_i64:
2128; GCN:       ; %bb.0:
2129; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2130; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2131; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
2132; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
2133; GCN-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2134; GCN-NEXT:    v_or_b32_e32 v3, 1, v3
2135; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2136; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
2137; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2138; GCN-NEXT:    v_mad_f32 v4, -v2, v1, s4
2139; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2140; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2141; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2142; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2143; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
2144; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2145; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2146; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2147; GCN-NEXT:    s_setpc_b64 s[30:31]
2148;
2149; GCN-IR-LABEL: v_test_srem24_k_num_i64:
2150; GCN-IR:       ; %bb.0:
2151; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2152; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2153; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
2154; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2155; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2156; GCN-IR-NEXT:    v_or_b32_e32 v3, 1, v3
2157; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2158; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
2159; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2160; GCN-IR-NEXT:    v_mad_f32 v4, -v2, v1, s4
2161; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2162; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2163; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2164; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2165; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
2166; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2167; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2168; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2169; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2170  %x.shr = ashr i64 %x, 40
2171  %result = srem i64 24, %x.shr
2172  ret i64 %result
2173}
2174
2175define i64 @v_test_srem24_pow2_k_num_i64(i64 %x) {
2176; GCN-LABEL: v_test_srem24_pow2_k_num_i64:
2177; GCN:       ; %bb.0:
2178; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2179; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2180; GCN-NEXT:    s_mov_b32 s4, 0x47000000
2181; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
2182; GCN-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2183; GCN-NEXT:    v_or_b32_e32 v3, 1, v3
2184; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2185; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
2186; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2187; GCN-NEXT:    v_mad_f32 v4, -v2, v1, s4
2188; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2189; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2190; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2191; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2192; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
2193; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
2194; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2195; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2196; GCN-NEXT:    s_setpc_b64 s[30:31]
2197;
2198; GCN-IR-LABEL: v_test_srem24_pow2_k_num_i64:
2199; GCN-IR:       ; %bb.0:
2200; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2201; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2202; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2203; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2204; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2205; GCN-IR-NEXT:    v_or_b32_e32 v3, 1, v3
2206; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2207; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
2208; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2209; GCN-IR-NEXT:    v_mad_f32 v4, -v2, v1, s4
2210; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2211; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2212; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2213; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2214; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
2215; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
2216; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2217; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2218; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2219  %x.shr = ashr i64 %x, 40
2220  %result = srem i64 32768, %x.shr
2221  ret i64 %result
2222}
2223
2224define i64 @v_test_srem24_pow2_k_den_i64(i64 %x) {
2225; GCN-LABEL: v_test_srem24_pow2_k_den_i64:
2226; GCN:       ; %bb.0:
2227; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2228; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2229; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v1
2230; GCN-NEXT:    v_add_i32_e32 v2, vcc, v0, v2
2231; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
2232; GCN-NEXT:    v_and_b32_e32 v2, 0xffff8000, v2
2233; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
2234; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
2235; GCN-NEXT:    s_setpc_b64 s[30:31]
2236;
2237; GCN-IR-LABEL: v_test_srem24_pow2_k_den_i64:
2238; GCN-IR:       ; %bb.0:
2239; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2240; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2241; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2242; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2243; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 30, v0
2244; GCN-IR-NEXT:    v_or_b32_e32 v2, 1, v2
2245; GCN-IR-NEXT:    v_mul_f32_e32 v3, 0x38000000, v1
2246; GCN-IR-NEXT:    v_trunc_f32_e32 v3, v3
2247; GCN-IR-NEXT:    v_mad_f32 v1, -v3, s4, v1
2248; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v3
2249; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
2250; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
2251; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
2252; GCN-IR-NEXT:    v_lshlrev_b32_e32 v1, 15, v1
2253; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
2254; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2255; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2256; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2257  %x.shr = ashr i64 %x, 40
2258  %result = srem i64 %x.shr, 32768
2259  ret i64 %result
2260}
2261