1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_srem(i64 addrspace(1)* %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_srem:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
9; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
10; GCN-NEXT:    v_mov_b32_e32 v2, 0
11; GCN-NEXT:    s_mov_b32 s7, 0xf000
12; GCN-NEXT:    s_mov_b32 s6, -1
13; GCN-NEXT:    s_waitcnt lgkmcnt(0)
14; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
15; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
16; GCN-NEXT:    s_sub_u32 s2, 0, s12
17; GCN-NEXT:    s_subb_u32 s3, 0, s13
18; GCN-NEXT:    s_mov_b32 s4, s8
19; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
20; GCN-NEXT:    v_rcp_f32_e32 v0, v0
21; GCN-NEXT:    v_mov_b32_e32 v1, 0
22; GCN-NEXT:    s_mov_b32 s5, s9
23; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
24; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
25; GCN-NEXT:    v_trunc_f32_e32 v3, v3
26; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
27; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
28; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
29; GCN-NEXT:    v_mul_lo_u32 v4, s2, v3
30; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
31; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
32; GCN-NEXT:    v_mul_lo_u32 v6, s2, v0
33; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
34; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
35; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
36; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
37; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
38; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
39; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
40; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
41; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
42; GCN-NEXT:    v_mul_hi_u32 v9, v3, v4
43; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
44; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
45; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
46; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v1, vcc
47; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
48; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
49; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
50; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
51; GCN-NEXT:    v_mul_lo_u32 v6, s2, v4
52; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
53; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
54; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
55; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
56; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
57; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
58; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
59; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
60; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
61; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
62; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
63; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
64; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
65; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
66; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
67; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
68; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v1, vcc
69; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
70; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
71; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
72; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
73; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
74; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
75; GCN-NEXT:    v_mul_lo_u32 v4, s10, v3
76; GCN-NEXT:    v_mul_hi_u32 v5, s10, v0
77; GCN-NEXT:    v_mul_hi_u32 v6, s10, v3
78; GCN-NEXT:    v_mul_hi_u32 v7, s11, v3
79; GCN-NEXT:    v_mul_lo_u32 v3, s11, v3
80; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
81; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
82; GCN-NEXT:    v_mul_lo_u32 v6, s11, v0
83; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
84; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
85; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
86; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
87; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
88; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
89; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
90; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
91; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
92; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
93; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
94; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
95; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s11, v1
96; GCN-NEXT:    v_mov_b32_e32 v3, s13
97; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s10, v0
98; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
99; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
100; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
101; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
102; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
103; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
104; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
105; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
106; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
107; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
108; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
109; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
110; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
111; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
112; GCN-NEXT:    v_mov_b32_e32 v5, s11
113; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
114; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
115; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
116; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
117; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
118; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
119; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
120; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
121; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
122; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
123; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
124; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
125; GCN-NEXT:    s_endpgm
126;
127; GCN-IR-LABEL: s_test_srem:
128; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
129; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
130; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
131; GCN-IR-NEXT:    s_mov_b64 s[2:3], 0
132; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
133; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
134; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[0:1], 0
135; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s0
136; GCN-IR-NEXT:    s_or_b64 s[14:15], s[8:9], s[10:11]
137; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s6
138; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
139; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s1
140; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
141; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s7
142; GCN-IR-NEXT:    s_min_u32 s8, s12, s8
143; GCN-IR-NEXT:    s_min_u32 s12, s10, s11
144; GCN-IR-NEXT:    s_sub_u32 s10, s8, s12
145; GCN-IR-NEXT:    s_subb_u32 s11, 0, 0
146; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[16:17], s[10:11], 63
147; GCN-IR-NEXT:    s_mov_b32 s9, 0
148; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[16:17]
149; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[16:17], s[10:11], 63
150; GCN-IR-NEXT:    s_xor_b64 s[18:19], s[14:15], -1
151; GCN-IR-NEXT:    s_and_b64 s[16:17], s[18:19], s[16:17]
152; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[16:17]
153; GCN-IR-NEXT:    s_cbranch_vccz BB0_5
154; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
155; GCN-IR-NEXT:    s_add_u32 s14, s10, 1
156; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
157; GCN-IR-NEXT:    s_addc_u32 s15, s11, 0
158; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
159; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[14:15], v[0:1]
160; GCN-IR-NEXT:    s_sub_i32 s10, 63, s10
161; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
162; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[6:7], s10
163; GCN-IR-NEXT:    s_cbranch_vccz BB0_4
164; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
165; GCN-IR-NEXT:    s_lshr_b64 s[14:15], s[6:7], s14
166; GCN-IR-NEXT:    s_add_u32 s16, s0, -1
167; GCN-IR-NEXT:    s_addc_u32 s17, s1, -1
168; GCN-IR-NEXT:    s_not_b64 s[2:3], s[8:9]
169; GCN-IR-NEXT:    s_mov_b32 s13, s9
170; GCN-IR-NEXT:    s_add_u32 s8, s2, s12
171; GCN-IR-NEXT:    s_addc_u32 s9, s3, s9
172; GCN-IR-NEXT:    s_mov_b64 s[12:13], 0
173; GCN-IR-NEXT:    s_mov_b32 s3, 0
174; GCN-IR-NEXT:  BB0_3: ; %udiv-do-while
175; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
176; GCN-IR-NEXT:    s_lshl_b64 s[14:15], s[14:15], 1
177; GCN-IR-NEXT:    s_lshr_b32 s2, s11, 31
178; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
179; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[2:3]
180; GCN-IR-NEXT:    s_or_b64 s[10:11], s[12:13], s[10:11]
181; GCN-IR-NEXT:    s_sub_u32 s2, s16, s14
182; GCN-IR-NEXT:    s_subb_u32 s2, s17, s15
183; GCN-IR-NEXT:    s_ashr_i32 s12, s2, 31
184; GCN-IR-NEXT:    s_mov_b32 s13, s12
185; GCN-IR-NEXT:    s_and_b32 s2, s12, 1
186; GCN-IR-NEXT:    s_and_b64 s[18:19], s[12:13], s[0:1]
187; GCN-IR-NEXT:    s_sub_u32 s14, s14, s18
188; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
189; GCN-IR-NEXT:    s_subb_u32 s15, s15, s19
190; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
191; GCN-IR-NEXT:    s_add_u32 s8, s8, 1
192; GCN-IR-NEXT:    s_addc_u32 s9, s9, 0
193; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
194; GCN-IR-NEXT:    s_mov_b64 s[12:13], s[2:3]
195; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
196; GCN-IR-NEXT:    s_cbranch_vccz BB0_3
197; GCN-IR-NEXT:  BB0_4: ; %Flow6
198; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[10:11], 1
199; GCN-IR-NEXT:    s_or_b64 s[2:3], s[2:3], s[8:9]
200; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
201; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
202; GCN-IR-NEXT:    s_branch BB0_6
203; GCN-IR-NEXT:  BB0_5:
204; GCN-IR-NEXT:    v_mov_b32_e32 v0, s7
205; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[14:15]
206; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
207; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[14:15]
208; GCN-IR-NEXT:  BB0_6: ; %udiv-end
209; GCN-IR-NEXT:    v_mul_lo_u32 v1, s0, v1
210; GCN-IR-NEXT:    v_mul_hi_u32 v2, s0, v0
211; GCN-IR-NEXT:    v_mul_lo_u32 v3, s1, v0
212; GCN-IR-NEXT:    v_mul_lo_u32 v0, s0, v0
213; GCN-IR-NEXT:    s_mov_b32 s11, 0xf000
214; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
215; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
216; GCN-IR-NEXT:    v_mov_b32_e32 v2, s7
217; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
218; GCN-IR-NEXT:    s_mov_b32 s10, -1
219; GCN-IR-NEXT:    s_mov_b32 s8, s4
220; GCN-IR-NEXT:    s_mov_b32 s9, s5
221; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
222; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
223; GCN-IR-NEXT:    s_endpgm
224  %result = urem i64 %x, %y
225  store i64 %result, i64 addrspace(1)* %out
226  ret void
227}
228
229define i64 @v_test_srem(i64 %x, i64 %y) {
230; GCN-LABEL: v_test_srem:
231; GCN:       ; %bb.0:
232; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
233; GCN-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
234; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
235; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
236; GCN-NEXT:    v_xor_b32_e32 v3, v3, v4
237; GCN-NEXT:    v_xor_b32_e32 v2, v2, v4
238; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v2
239; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v3
240; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v2
241; GCN-NEXT:    v_subb_u32_e32 v7, vcc, 0, v3, vcc
242; GCN-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
243; GCN-NEXT:    v_rcp_f32_e32 v4, v4
244; GCN-NEXT:    v_mov_b32_e32 v14, 0
245; GCN-NEXT:    v_mov_b32_e32 v13, 0
246; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
247; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
248; GCN-NEXT:    v_trunc_f32_e32 v5, v5
249; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
250; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
251; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
252; GCN-NEXT:    v_mul_hi_u32 v8, v6, v4
253; GCN-NEXT:    v_mul_lo_u32 v9, v6, v5
254; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
255; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
256; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
257; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
258; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
259; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
260; GCN-NEXT:    v_mul_hi_u32 v10, v4, v8
261; GCN-NEXT:    v_mul_hi_u32 v15, v5, v8
262; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
263; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
264; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
265; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
266; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v10, vcc
267; GCN-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
268; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v10, v9, vcc
269; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v15, v13, vcc
270; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
271; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v10, vcc
272; GCN-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v8
273; GCN-NEXT:    v_addc_u32_e64 v8, vcc, v5, v9, s[4:5]
274; GCN-NEXT:    v_mul_lo_u32 v10, v6, v8
275; GCN-NEXT:    v_mul_hi_u32 v11, v6, v4
276; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
277; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
278; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
279; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
280; GCN-NEXT:    v_mul_lo_u32 v12, v4, v7
281; GCN-NEXT:    v_mul_hi_u32 v15, v4, v6
282; GCN-NEXT:    v_mul_hi_u32 v16, v4, v7
283; GCN-NEXT:    v_mul_hi_u32 v11, v8, v6
284; GCN-NEXT:    v_mul_lo_u32 v6, v8, v6
285; GCN-NEXT:    v_mul_hi_u32 v10, v8, v7
286; GCN-NEXT:    v_add_i32_e32 v12, vcc, v15, v12
287; GCN-NEXT:    v_addc_u32_e32 v15, vcc, v14, v16, vcc
288; GCN-NEXT:    v_mul_lo_u32 v7, v8, v7
289; GCN-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
290; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v15, v11, vcc
291; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v13, vcc
292; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
293; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v14, v8, vcc
294; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
295; GCN-NEXT:    v_addc_u32_e64 v5, vcc, v5, v7, s[4:5]
296; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
297; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
298; GCN-NEXT:    v_ashrrev_i32_e32 v6, 31, v1
299; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
300; GCN-NEXT:    v_xor_b32_e32 v0, v0, v6
301; GCN-NEXT:    v_mul_lo_u32 v7, v0, v5
302; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
303; GCN-NEXT:    v_mul_hi_u32 v9, v0, v5
304; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v6, vcc
305; GCN-NEXT:    v_xor_b32_e32 v1, v1, v6
306; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
307; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v14, v9, vcc
308; GCN-NEXT:    v_mul_lo_u32 v9, v1, v4
309; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
310; GCN-NEXT:    v_mul_hi_u32 v10, v1, v5
311; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
312; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
313; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
314; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v10, v13, vcc
315; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
316; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v14, v7, vcc
317; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
318; GCN-NEXT:    v_mul_hi_u32 v7, v2, v4
319; GCN-NEXT:    v_mul_lo_u32 v8, v3, v4
320; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
321; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
322; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
323; GCN-NEXT:    v_sub_i32_e32 v7, vcc, v1, v5
324; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
325; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v7, v3, vcc
326; GCN-NEXT:    v_sub_i32_e64 v7, s[4:5], v0, v2
327; GCN-NEXT:    v_subbrev_u32_e64 v8, s[6:7], 0, v4, s[4:5]
328; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v8, v3
329; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[6:7]
330; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v7, v2
331; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
332; GCN-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[6:7]
333; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v8, v3
334; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v3, s[4:5]
335; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
336; GCN-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[6:7]
337; GCN-NEXT:    v_sub_i32_e64 v10, s[4:5], v7, v2
338; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
339; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
340; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
341; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
342; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
343; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v9
344; GCN-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
345; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
346; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v10, s[4:5]
347; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v4, s[4:5]
348; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
349; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
350; GCN-NEXT:    v_xor_b32_e32 v0, v0, v6
351; GCN-NEXT:    v_xor_b32_e32 v1, v1, v6
352; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
353; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
354; GCN-NEXT:    s_setpc_b64 s[30:31]
355;
356; GCN-IR-LABEL: v_test_srem:
357; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
358; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
359; GCN-IR-NEXT:    v_ashrrev_i32_e32 v4, 31, v1
360; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v4
361; GCN-IR-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
362; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v4
363; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
364; GCN-IR-NEXT:    v_xor_b32_e32 v2, v2, v6
365; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc
366; GCN-IR-NEXT:    v_xor_b32_e32 v3, v3, v6
367; GCN-IR-NEXT:    v_sub_i32_e32 v5, vcc, v2, v6
368; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v3, v6, vcc
369; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[5:6]
370; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
371; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v5
372; GCN-IR-NEXT:    s_or_b64 s[6:7], vcc, s[4:5]
373; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, 32, v3
374; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v6
375; GCN-IR-NEXT:    v_min_u32_e32 v3, v3, v7
376; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v0
377; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 32, v7
378; GCN-IR-NEXT:    v_ffbh_u32_e32 v8, v1
379; GCN-IR-NEXT:    v_min_u32_e32 v12, v7, v8
380; GCN-IR-NEXT:    v_sub_i32_e32 v7, vcc, v3, v12
381; GCN-IR-NEXT:    v_subb_u32_e64 v8, s[4:5], 0, 0, vcc
382; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[7:8]
383; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[4:5], 63, v[7:8]
384; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], vcc
385; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
386; GCN-IR-NEXT:    s_xor_b64 s[8:9], s[6:7], -1
387; GCN-IR-NEXT:    v_mov_b32_e32 v2, v4
388; GCN-IR-NEXT:    v_mov_b32_e32 v13, v11
389; GCN-IR-NEXT:    v_cndmask_b32_e64 v10, v1, 0, s[6:7]
390; GCN-IR-NEXT:    s_and_b64 s[4:5], s[8:9], s[4:5]
391; GCN-IR-NEXT:    v_cndmask_b32_e64 v9, v0, 0, s[6:7]
392; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
393; GCN-IR-NEXT:    s_cbranch_execz BB1_6
394; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
395; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, 1, v7
396; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, 0, v8, vcc
397; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[14:15], v[7:8]
398; GCN-IR-NEXT:    v_sub_i32_e64 v7, s[4:5], 63, v7
399; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[0:1], v7
400; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
401; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
402; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
403; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
404; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
405; GCN-IR-NEXT:    s_cbranch_execz BB1_5
406; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
407; GCN-IR-NEXT:    v_add_i32_e32 v18, vcc, -1, v5
408; GCN-IR-NEXT:    v_addc_u32_e32 v19, vcc, -1, v6, vcc
409; GCN-IR-NEXT:    v_not_b32_e32 v3, v3
410; GCN-IR-NEXT:    v_lshr_b64 v[14:15], v[0:1], v14
411; GCN-IR-NEXT:    v_not_b32_e32 v9, v11
412; GCN-IR-NEXT:    v_add_i32_e32 v11, vcc, v3, v12
413; GCN-IR-NEXT:    v_mov_b32_e32 v16, 0
414; GCN-IR-NEXT:    v_addc_u32_e32 v12, vcc, v9, v13, vcc
415; GCN-IR-NEXT:    v_mov_b32_e32 v17, 0
416; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
417; GCN-IR-NEXT:  BB1_3: ; %udiv-do-while
418; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
419; GCN-IR-NEXT:    v_lshl_b64 v[14:15], v[14:15], 1
420; GCN-IR-NEXT:    v_lshrrev_b32_e32 v3, 31, v8
421; GCN-IR-NEXT:    v_or_b32_e32 v3, v14, v3
422; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
423; GCN-IR-NEXT:    v_sub_i32_e32 v9, vcc, v18, v3
424; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, v19, v15, vcc
425; GCN-IR-NEXT:    v_or_b32_e32 v7, v16, v7
426; GCN-IR-NEXT:    v_add_i32_e32 v16, vcc, 1, v11
427; GCN-IR-NEXT:    v_or_b32_e32 v8, v17, v8
428; GCN-IR-NEXT:    v_ashrrev_i32_e32 v13, 31, v9
429; GCN-IR-NEXT:    v_addc_u32_e32 v17, vcc, 0, v12, vcc
430; GCN-IR-NEXT:    v_and_b32_e32 v9, 1, v13
431; GCN-IR-NEXT:    v_and_b32_e32 v20, v13, v6
432; GCN-IR-NEXT:    v_and_b32_e32 v13, v13, v5
433; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[16:17], v[11:12]
434; GCN-IR-NEXT:    v_mov_b32_e32 v11, v16
435; GCN-IR-NEXT:    v_sub_i32_e64 v14, s[4:5], v3, v13
436; GCN-IR-NEXT:    v_mov_b32_e32 v12, v17
437; GCN-IR-NEXT:    v_mov_b32_e32 v17, v10
438; GCN-IR-NEXT:    v_subb_u32_e64 v15, s[4:5], v15, v20, s[4:5]
439; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
440; GCN-IR-NEXT:    v_mov_b32_e32 v16, v9
441; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
442; GCN-IR-NEXT:    s_cbranch_execnz BB1_3
443; GCN-IR-NEXT:  ; %bb.4: ; %Flow
444; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
445; GCN-IR-NEXT:  BB1_5: ; %Flow3
446; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
447; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
448; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v8
449; GCN-IR-NEXT:    v_or_b32_e32 v9, v9, v7
450; GCN-IR-NEXT:  BB1_6: ; %Flow4
451; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
452; GCN-IR-NEXT:    v_mul_lo_u32 v3, v5, v10
453; GCN-IR-NEXT:    v_mul_hi_u32 v7, v5, v9
454; GCN-IR-NEXT:    v_mul_lo_u32 v6, v6, v9
455; GCN-IR-NEXT:    v_mul_lo_u32 v5, v5, v9
456; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
457; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
458; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v5
459; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
460; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v4
461; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
462; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
463; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
464; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
465  %result = srem i64 %x, %y
466  ret i64 %result
467}
468
469define amdgpu_kernel void @s_test_srem23_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
470; GCN-LABEL: s_test_srem23_64:
471; GCN:       ; %bb.0:
472; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
473; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
474; GCN-NEXT:    s_mov_b32 s3, 0xf000
475; GCN-NEXT:    s_mov_b32 s2, -1
476; GCN-NEXT:    s_waitcnt lgkmcnt(0)
477; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 41
478; GCN-NEXT:    s_ashr_i64 s[0:1], s[0:1], 41
479; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
480; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s6
481; GCN-NEXT:    s_xor_b32 s1, s6, s0
482; GCN-NEXT:    s_ashr_i32 s1, s1, 30
483; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
484; GCN-NEXT:    s_or_b32 s1, s1, 1
485; GCN-NEXT:    v_mov_b32_e32 v3, s1
486; GCN-NEXT:    s_mov_b32 s1, s5
487; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
488; GCN-NEXT:    v_trunc_f32_e32 v2, v2
489; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
490; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
491; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
492; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
493; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
494; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
495; GCN-NEXT:    s_mov_b32 s0, s4
496; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
497; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 23
498; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
499; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
500; GCN-NEXT:    s_endpgm
501;
502; GCN-IR-LABEL: s_test_srem23_64:
503; GCN-IR:       ; %bb.0:
504; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
505; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
506; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
507; GCN-IR-NEXT:    s_mov_b32 s2, -1
508; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
509; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 41
510; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[0:1], 41
511; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
512; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s6
513; GCN-IR-NEXT:    s_xor_b32 s1, s6, s0
514; GCN-IR-NEXT:    s_ashr_i32 s1, s1, 30
515; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
516; GCN-IR-NEXT:    s_or_b32 s1, s1, 1
517; GCN-IR-NEXT:    v_mov_b32_e32 v3, s1
518; GCN-IR-NEXT:    s_mov_b32 s1, s5
519; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
520; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
521; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
522; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
523; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
524; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
525; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
526; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
527; GCN-IR-NEXT:    s_mov_b32 s0, s4
528; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
529; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 23
530; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
531; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
532; GCN-IR-NEXT:    s_endpgm
533  %1 = ashr i64 %x, 41
534  %2 = ashr i64 %y, 41
535  %result = srem i64 %1, %2
536  store i64 %result, i64 addrspace(1)* %out
537  ret void
538}
539
540define amdgpu_kernel void @s_test_srem24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
541; GCN-LABEL: s_test_srem24_64:
542; GCN:       ; %bb.0:
543; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
544; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
545; GCN-NEXT:    s_mov_b32 s3, 0xf000
546; GCN-NEXT:    s_mov_b32 s2, -1
547; GCN-NEXT:    s_waitcnt lgkmcnt(0)
548; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
549; GCN-NEXT:    s_ashr_i64 s[0:1], s[0:1], 40
550; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
551; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s6
552; GCN-NEXT:    s_xor_b32 s1, s6, s0
553; GCN-NEXT:    s_ashr_i32 s1, s1, 30
554; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
555; GCN-NEXT:    s_or_b32 s1, s1, 1
556; GCN-NEXT:    v_mov_b32_e32 v3, s1
557; GCN-NEXT:    s_mov_b32 s1, s5
558; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
559; GCN-NEXT:    v_trunc_f32_e32 v2, v2
560; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
561; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
562; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
563; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
564; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
565; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
566; GCN-NEXT:    s_mov_b32 s0, s4
567; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
568; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
569; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
570; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
571; GCN-NEXT:    s_endpgm
572;
573; GCN-IR-LABEL: s_test_srem24_64:
574; GCN-IR:       ; %bb.0:
575; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
576; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
577; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
578; GCN-IR-NEXT:    s_mov_b32 s2, -1
579; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
580; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
581; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[0:1], 40
582; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
583; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s6
584; GCN-IR-NEXT:    s_xor_b32 s1, s6, s0
585; GCN-IR-NEXT:    s_ashr_i32 s1, s1, 30
586; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
587; GCN-IR-NEXT:    s_or_b32 s1, s1, 1
588; GCN-IR-NEXT:    v_mov_b32_e32 v3, s1
589; GCN-IR-NEXT:    s_mov_b32 s1, s5
590; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
591; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
592; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
593; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
594; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
595; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
596; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
597; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
598; GCN-IR-NEXT:    s_mov_b32 s0, s4
599; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
600; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
601; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
602; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
603; GCN-IR-NEXT:    s_endpgm
604  %1 = ashr i64 %x, 40
605  %2 = ashr i64 %y, 40
606  %result = srem i64 %1, %2
607  store i64 %result, i64 addrspace(1)* %out
608  ret void
609}
610
611define i64 @v_test_srem24_64(i64 %x, i64 %y) {
612; GCN-LABEL: v_test_srem24_64:
613; GCN:       ; %bb.0:
614; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
615; GCN-NEXT:    v_ashr_i64 v[2:3], v[2:3], 40
616; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
617; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
618; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
619; GCN-NEXT:    v_xor_b32_e32 v5, v0, v2
620; GCN-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
621; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v3
622; GCN-NEXT:    v_or_b32_e32 v5, 1, v5
623; GCN-NEXT:    v_mul_f32_e32 v4, v1, v4
624; GCN-NEXT:    v_trunc_f32_e32 v4, v4
625; GCN-NEXT:    v_mad_f32 v1, -v4, v3, v1
626; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
627; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
628; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
629; GCN-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
630; GCN-NEXT:    v_mul_lo_u32 v1, v1, v2
631; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
632; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
633; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
634; GCN-NEXT:    s_setpc_b64 s[30:31]
635;
636; GCN-IR-LABEL: v_test_srem24_64:
637; GCN-IR:       ; %bb.0:
638; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
639; GCN-IR-NEXT:    v_ashr_i64 v[2:3], v[2:3], 40
640; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
641; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v3, v2
642; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
643; GCN-IR-NEXT:    v_xor_b32_e32 v5, v0, v2
644; GCN-IR-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
645; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v4, v3
646; GCN-IR-NEXT:    v_or_b32_e32 v5, 1, v5
647; GCN-IR-NEXT:    v_mul_f32_e32 v4, v1, v4
648; GCN-IR-NEXT:    v_trunc_f32_e32 v4, v4
649; GCN-IR-NEXT:    v_mad_f32 v1, -v4, v3, v1
650; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v4, v4
651; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
652; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
653; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
654; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v2
655; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
656; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
657; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
658; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
659  %1 = ashr i64 %x, 40
660  %2 = ashr i64 %y, 40
661  %result = srem i64 %1, %2
662  ret i64 %result
663}
664
665define amdgpu_kernel void @s_test_srem25_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
666; GCN-LABEL: s_test_srem25_64:
667; GCN:       ; %bb.0:
668; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
669; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
670; GCN-NEXT:    s_mov_b32 s3, 0xf000
671; GCN-NEXT:    s_mov_b32 s2, -1
672; GCN-NEXT:    s_waitcnt lgkmcnt(0)
673; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 39
674; GCN-NEXT:    s_ashr_i64 s[0:1], s[0:1], 39
675; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
676; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s6
677; GCN-NEXT:    s_xor_b32 s1, s6, s0
678; GCN-NEXT:    s_ashr_i32 s1, s1, 30
679; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
680; GCN-NEXT:    s_or_b32 s1, s1, 1
681; GCN-NEXT:    v_mov_b32_e32 v3, s1
682; GCN-NEXT:    s_mov_b32 s1, s5
683; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
684; GCN-NEXT:    v_trunc_f32_e32 v2, v2
685; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
686; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
687; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
688; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
689; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
690; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
691; GCN-NEXT:    s_mov_b32 s0, s4
692; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
693; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 25
694; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
695; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
696; GCN-NEXT:    s_endpgm
697;
698; GCN-IR-LABEL: s_test_srem25_64:
699; GCN-IR:       ; %bb.0:
700; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
701; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
702; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
703; GCN-IR-NEXT:    s_mov_b32 s2, -1
704; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
705; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 39
706; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[0:1], 39
707; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
708; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s6
709; GCN-IR-NEXT:    s_xor_b32 s1, s6, s0
710; GCN-IR-NEXT:    s_ashr_i32 s1, s1, 30
711; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
712; GCN-IR-NEXT:    s_or_b32 s1, s1, 1
713; GCN-IR-NEXT:    v_mov_b32_e32 v3, s1
714; GCN-IR-NEXT:    s_mov_b32 s1, s5
715; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
716; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
717; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
718; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
719; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
720; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
721; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
722; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
723; GCN-IR-NEXT:    s_mov_b32 s0, s4
724; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
725; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 25
726; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
727; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
728; GCN-IR-NEXT:    s_endpgm
729  %1 = ashr i64 %x, 39
730  %2 = ashr i64 %y, 39
731  %result = srem i64 %1, %2
732  store i64 %result, i64 addrspace(1)* %out
733  ret void
734}
735
736define amdgpu_kernel void @s_test_srem31_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
737; GCN-LABEL: s_test_srem31_64:
738; GCN:       ; %bb.0:
739; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
740; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
741; GCN-NEXT:    s_mov_b32 s3, 0xf000
742; GCN-NEXT:    s_mov_b32 s2, -1
743; GCN-NEXT:    s_waitcnt lgkmcnt(0)
744; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 33
745; GCN-NEXT:    s_ashr_i64 s[0:1], s[0:1], 33
746; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
747; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s6
748; GCN-NEXT:    s_xor_b32 s1, s6, s0
749; GCN-NEXT:    s_ashr_i32 s1, s1, 30
750; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
751; GCN-NEXT:    s_or_b32 s1, s1, 1
752; GCN-NEXT:    v_mov_b32_e32 v3, s1
753; GCN-NEXT:    s_mov_b32 s1, s5
754; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
755; GCN-NEXT:    v_trunc_f32_e32 v2, v2
756; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
757; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
758; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
759; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
760; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
761; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
762; GCN-NEXT:    s_mov_b32 s0, s4
763; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
764; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 31
765; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
766; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
767; GCN-NEXT:    s_endpgm
768;
769; GCN-IR-LABEL: s_test_srem31_64:
770; GCN-IR:       ; %bb.0:
771; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
772; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
773; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
774; GCN-IR-NEXT:    s_mov_b32 s2, -1
775; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
776; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 33
777; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[0:1], 33
778; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
779; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s6
780; GCN-IR-NEXT:    s_xor_b32 s1, s6, s0
781; GCN-IR-NEXT:    s_ashr_i32 s1, s1, 30
782; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
783; GCN-IR-NEXT:    s_or_b32 s1, s1, 1
784; GCN-IR-NEXT:    v_mov_b32_e32 v3, s1
785; GCN-IR-NEXT:    s_mov_b32 s1, s5
786; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
787; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
788; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
789; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
790; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
791; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
792; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
793; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
794; GCN-IR-NEXT:    s_mov_b32 s0, s4
795; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
796; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 31
797; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
798; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
799; GCN-IR-NEXT:    s_endpgm
800  %1 = ashr i64 %x, 33
801  %2 = ashr i64 %y, 33
802  %result = srem i64 %1, %2
803  store i64 %result, i64 addrspace(1)* %out
804  ret void
805}
806
807; 32 known sign bits
808define amdgpu_kernel void @s_test_srem32_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
809; GCN-LABEL: s_test_srem32_64:
810; GCN:       ; %bb.0:
811; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
812; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
813; GCN-NEXT:    s_mov_b32 s3, 0xf000
814; GCN-NEXT:    s_mov_b32 s2, -1
815; GCN-NEXT:    s_waitcnt lgkmcnt(0)
816; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s7
817; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
818; GCN-NEXT:    s_xor_b32 s1, s7, s0
819; GCN-NEXT:    s_ashr_i32 s1, s1, 30
820; GCN-NEXT:    s_or_b32 s1, s1, 1
821; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
822; GCN-NEXT:    v_mov_b32_e32 v3, s1
823; GCN-NEXT:    s_mov_b32 s1, s5
824; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
825; GCN-NEXT:    v_trunc_f32_e32 v2, v2
826; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
827; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
828; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
829; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
830; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
831; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
832; GCN-NEXT:    s_mov_b32 s0, s4
833; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s7, v0
834; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
835; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
836; GCN-NEXT:    s_endpgm
837;
838; GCN-IR-LABEL: s_test_srem32_64:
839; GCN-IR:       ; %bb.0:
840; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
841; GCN-IR-NEXT:    s_load_dword s0, s[0:1], 0xe
842; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
843; GCN-IR-NEXT:    s_mov_b32 s2, -1
844; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
845; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s7
846; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
847; GCN-IR-NEXT:    s_xor_b32 s1, s7, s0
848; GCN-IR-NEXT:    s_ashr_i32 s1, s1, 30
849; GCN-IR-NEXT:    s_or_b32 s1, s1, 1
850; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
851; GCN-IR-NEXT:    v_mov_b32_e32 v3, s1
852; GCN-IR-NEXT:    s_mov_b32 s1, s5
853; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
854; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
855; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
856; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
857; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
858; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
859; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
860; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
861; GCN-IR-NEXT:    s_mov_b32 s0, s4
862; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s7, v0
863; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
864; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
865; GCN-IR-NEXT:    s_endpgm
866  %1 = ashr i64 %x, 32
867  %2 = ashr i64 %y, 32
868  %result = srem i64 %1, %2
869  store i64 %result, i64 addrspace(1)* %out
870  ret void
871}
872
873; 33 known sign bits
874define amdgpu_kernel void @s_test_srem33_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
875; GCN-LABEL: s_test_srem33_64:
876; GCN:       ; %bb.0:
877; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
878; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
879; GCN-NEXT:    v_mov_b32_e32 v7, 0
880; GCN-NEXT:    s_mov_b32 s7, 0xf000
881; GCN-NEXT:    s_mov_b32 s6, -1
882; GCN-NEXT:    s_waitcnt lgkmcnt(0)
883; GCN-NEXT:    s_ashr_i64 s[2:3], s[10:11], 31
884; GCN-NEXT:    s_ashr_i64 s[4:5], s[0:1], 31
885; GCN-NEXT:    s_ashr_i32 s0, s1, 31
886; GCN-NEXT:    s_add_u32 s4, s4, s0
887; GCN-NEXT:    s_mov_b32 s1, s0
888; GCN-NEXT:    s_addc_u32 s5, s5, s0
889; GCN-NEXT:    s_xor_b64 s[12:13], s[4:5], s[0:1]
890; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
891; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
892; GCN-NEXT:    s_sub_u32 s4, 0, s12
893; GCN-NEXT:    s_subb_u32 s5, 0, s13
894; GCN-NEXT:    s_ashr_i32 s10, s11, 31
895; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
896; GCN-NEXT:    v_rcp_f32_e32 v0, v0
897; GCN-NEXT:    v_mov_b32_e32 v1, 0
898; GCN-NEXT:    s_mov_b32 s11, s10
899; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
900; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
901; GCN-NEXT:    v_trunc_f32_e32 v2, v2
902; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
903; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
904; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
905; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
906; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
907; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
908; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
909; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
910; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
911; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
912; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
913; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
914; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
915; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
916; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
917; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v7, v8, vcc
918; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
919; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
920; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
921; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
922; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
923; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
924; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
925; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v3
926; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v2, v4, s[0:1]
927; GCN-NEXT:    v_mul_lo_u32 v5, s4, v3
928; GCN-NEXT:    v_mul_hi_u32 v6, s4, v0
929; GCN-NEXT:    v_mul_lo_u32 v8, s5, v0
930; GCN-NEXT:    s_mov_b32 s5, s9
931; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
932; GCN-NEXT:    v_mul_lo_u32 v6, s4, v0
933; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
934; GCN-NEXT:    v_mul_lo_u32 v10, v0, v5
935; GCN-NEXT:    v_mul_hi_u32 v11, v0, v6
936; GCN-NEXT:    v_mul_hi_u32 v12, v0, v5
937; GCN-NEXT:    v_mul_hi_u32 v9, v3, v6
938; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
939; GCN-NEXT:    v_mul_hi_u32 v8, v3, v5
940; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
941; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v7, v12, vcc
942; GCN-NEXT:    v_mul_lo_u32 v3, v3, v5
943; GCN-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
944; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
945; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v1, vcc
946; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
947; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v5, vcc
948; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
949; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v5, s[0:1]
950; GCN-NEXT:    s_add_u32 s0, s2, s10
951; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
952; GCN-NEXT:    s_addc_u32 s1, s3, s10
953; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
954; GCN-NEXT:    s_xor_b64 s[14:15], s[0:1], s[10:11]
955; GCN-NEXT:    v_mul_lo_u32 v3, s14, v2
956; GCN-NEXT:    v_mul_hi_u32 v4, s14, v0
957; GCN-NEXT:    v_mul_hi_u32 v5, s14, v2
958; GCN-NEXT:    v_mul_hi_u32 v6, s15, v2
959; GCN-NEXT:    v_mul_lo_u32 v2, s15, v2
960; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
961; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
962; GCN-NEXT:    v_mul_lo_u32 v5, s15, v0
963; GCN-NEXT:    v_mul_hi_u32 v0, s15, v0
964; GCN-NEXT:    s_mov_b32 s4, s8
965; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
966; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
967; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
968; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
969; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
970; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
971; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
972; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
973; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
974; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
975; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
976; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s15, v1
977; GCN-NEXT:    v_mov_b32_e32 v3, s13
978; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s14, v0
979; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
980; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
981; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
982; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
983; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
984; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
985; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
986; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
987; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
988; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
989; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
990; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
991; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
992; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
993; GCN-NEXT:    v_mov_b32_e32 v5, s15
994; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
995; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
996; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
997; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
998; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
999; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
1000; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
1001; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
1002; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1003; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
1004; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1005; GCN-NEXT:    v_xor_b32_e32 v0, s10, v0
1006; GCN-NEXT:    v_xor_b32_e32 v1, s10, v1
1007; GCN-NEXT:    v_mov_b32_e32 v2, s10
1008; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s10, v0
1009; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1010; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1011; GCN-NEXT:    s_endpgm
1012;
1013; GCN-IR-LABEL: s_test_srem33_64:
1014; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1015; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1016; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
1017; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1018; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[6:7], 31
1019; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 31
1020; GCN-IR-NEXT:    s_ashr_i32 s0, s7, 31
1021; GCN-IR-NEXT:    s_ashr_i32 s6, s1, 31
1022; GCN-IR-NEXT:    s_mov_b32 s1, s0
1023; GCN-IR-NEXT:    s_mov_b32 s7, s6
1024; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[2:3], s[0:1]
1025; GCN-IR-NEXT:    s_xor_b64 s[8:9], s[8:9], s[6:7]
1026; GCN-IR-NEXT:    s_sub_u32 s2, s2, s0
1027; GCN-IR-NEXT:    s_subb_u32 s3, s3, s0
1028; GCN-IR-NEXT:    s_sub_u32 s8, s8, s6
1029; GCN-IR-NEXT:    s_subb_u32 s9, s9, s6
1030; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[8:9], 0
1031; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[2:3], 0
1032; GCN-IR-NEXT:    s_mov_b64 s[6:7], 0
1033; GCN-IR-NEXT:    s_or_b64 s[16:17], s[10:11], s[12:13]
1034; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s8
1035; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s2
1036; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
1037; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s9
1038; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
1039; GCN-IR-NEXT:    s_flbit_i32_b32 s13, s3
1040; GCN-IR-NEXT:    s_min_u32 s10, s10, s11
1041; GCN-IR-NEXT:    s_min_u32 s14, s12, s13
1042; GCN-IR-NEXT:    s_sub_u32 s12, s10, s14
1043; GCN-IR-NEXT:    s_subb_u32 s13, 0, 0
1044; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[18:19], s[12:13], 63
1045; GCN-IR-NEXT:    s_mov_b32 s11, 0
1046; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[18:19]
1047; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[18:19], s[12:13], 63
1048; GCN-IR-NEXT:    s_xor_b64 s[20:21], s[16:17], -1
1049; GCN-IR-NEXT:    s_and_b64 s[18:19], s[20:21], s[18:19]
1050; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[18:19]
1051; GCN-IR-NEXT:    s_cbranch_vccz BB8_5
1052; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1053; GCN-IR-NEXT:    s_add_u32 s16, s12, 1
1054; GCN-IR-NEXT:    v_mov_b32_e32 v0, s12
1055; GCN-IR-NEXT:    s_addc_u32 s17, s13, 0
1056; GCN-IR-NEXT:    v_mov_b32_e32 v1, s13
1057; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[16:17], v[0:1]
1058; GCN-IR-NEXT:    s_sub_i32 s12, 63, s12
1059; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1060; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[2:3], s12
1061; GCN-IR-NEXT:    s_cbranch_vccz BB8_4
1062; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1063; GCN-IR-NEXT:    s_lshr_b64 s[16:17], s[2:3], s16
1064; GCN-IR-NEXT:    s_add_u32 s18, s8, -1
1065; GCN-IR-NEXT:    s_addc_u32 s19, s9, -1
1066; GCN-IR-NEXT:    s_not_b64 s[6:7], s[10:11]
1067; GCN-IR-NEXT:    s_mov_b32 s15, s11
1068; GCN-IR-NEXT:    s_add_u32 s10, s6, s14
1069; GCN-IR-NEXT:    s_addc_u32 s11, s7, s11
1070; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
1071; GCN-IR-NEXT:    s_mov_b32 s7, 0
1072; GCN-IR-NEXT:  BB8_3: ; %udiv-do-while
1073; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1074; GCN-IR-NEXT:    s_lshl_b64 s[16:17], s[16:17], 1
1075; GCN-IR-NEXT:    s_lshr_b32 s6, s13, 31
1076; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
1077; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[6:7]
1078; GCN-IR-NEXT:    s_or_b64 s[12:13], s[14:15], s[12:13]
1079; GCN-IR-NEXT:    s_sub_u32 s6, s18, s16
1080; GCN-IR-NEXT:    s_subb_u32 s6, s19, s17
1081; GCN-IR-NEXT:    s_ashr_i32 s14, s6, 31
1082; GCN-IR-NEXT:    s_mov_b32 s15, s14
1083; GCN-IR-NEXT:    s_and_b32 s6, s14, 1
1084; GCN-IR-NEXT:    s_and_b64 s[20:21], s[14:15], s[8:9]
1085; GCN-IR-NEXT:    s_sub_u32 s16, s16, s20
1086; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1087; GCN-IR-NEXT:    s_subb_u32 s17, s17, s21
1088; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
1089; GCN-IR-NEXT:    s_add_u32 s10, s10, 1
1090; GCN-IR-NEXT:    s_addc_u32 s11, s11, 0
1091; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
1092; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[6:7]
1093; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1094; GCN-IR-NEXT:    s_cbranch_vccz BB8_3
1095; GCN-IR-NEXT:  BB8_4: ; %Flow6
1096; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[12:13], 1
1097; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], s[10:11]
1098; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1099; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
1100; GCN-IR-NEXT:    s_branch BB8_6
1101; GCN-IR-NEXT:  BB8_5:
1102; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
1103; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[16:17]
1104; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1105; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[16:17]
1106; GCN-IR-NEXT:  BB8_6: ; %udiv-end
1107; GCN-IR-NEXT:    v_mul_lo_u32 v1, s8, v1
1108; GCN-IR-NEXT:    v_mul_hi_u32 v2, s8, v0
1109; GCN-IR-NEXT:    v_mul_lo_u32 v3, s9, v0
1110; GCN-IR-NEXT:    v_mul_lo_u32 v0, s8, v0
1111; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1112; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1113; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1114; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
1115; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1116; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
1117; GCN-IR-NEXT:    v_xor_b32_e32 v0, s0, v0
1118; GCN-IR-NEXT:    v_xor_b32_e32 v1, s1, v1
1119; GCN-IR-NEXT:    v_mov_b32_e32 v2, s1
1120; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
1121; GCN-IR-NEXT:    s_mov_b32 s6, -1
1122; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1123; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1124; GCN-IR-NEXT:    s_endpgm
1125  %1 = ashr i64 %x, 31
1126  %2 = ashr i64 %y, 31
1127  %result = srem i64 %1, %2
1128  store i64 %result, i64 addrspace(1)* %out
1129  ret void
1130}
1131
1132define amdgpu_kernel void @s_test_srem24_48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
1133; GCN-LABEL: s_test_srem24_48:
1134; GCN:       ; %bb.0:
1135; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
1136; GCN-NEXT:    s_load_dword s2, s[0:1], 0xb
1137; GCN-NEXT:    s_load_dword s3, s[0:1], 0xc
1138; GCN-NEXT:    s_load_dword s6, s[0:1], 0xd
1139; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
1140; GCN-NEXT:    s_mov_b32 s7, 0xf000
1141; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1142; GCN-NEXT:    v_mov_b32_e32 v2, s2
1143; GCN-NEXT:    s_sext_i32_i16 s1, s3
1144; GCN-NEXT:    v_mov_b32_e32 v0, s6
1145; GCN-NEXT:    s_sext_i32_i16 s0, s0
1146; GCN-NEXT:    v_alignbit_b32 v0, s0, v0, 24
1147; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
1148; GCN-NEXT:    v_alignbit_b32 v2, s1, v2, 24
1149; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
1150; GCN-NEXT:    v_xor_b32_e32 v5, v2, v0
1151; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v1
1152; GCN-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
1153; GCN-NEXT:    v_or_b32_e32 v5, 1, v5
1154; GCN-NEXT:    s_mov_b32 s6, -1
1155; GCN-NEXT:    v_mul_f32_e32 v4, v3, v4
1156; GCN-NEXT:    v_trunc_f32_e32 v4, v4
1157; GCN-NEXT:    v_mad_f32 v3, -v4, v1, v3
1158; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
1159; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1160; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
1161; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
1162; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
1163; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v2, v0
1164; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1165; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1166; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
1167; GCN-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
1168; GCN-NEXT:    s_endpgm
1169;
1170; GCN-IR-LABEL: s_test_srem24_48:
1171; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1172; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
1173; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xb
1174; GCN-IR-NEXT:    s_load_dword s3, s[0:1], 0xc
1175; GCN-IR-NEXT:    s_load_dword s6, s[0:1], 0xd
1176; GCN-IR-NEXT:    s_load_dword s0, s[0:1], 0xe
1177; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1178; GCN-IR-NEXT:    s_sext_i32_i16 s3, s3
1179; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[2:3], 24
1180; GCN-IR-NEXT:    s_sext_i32_i16 s7, s0
1181; GCN-IR-NEXT:    s_ashr_i32 s0, s3, 31
1182; GCN-IR-NEXT:    s_ashr_i32 s12, s7, 31
1183; GCN-IR-NEXT:    s_ashr_i64 s[10:11], s[6:7], 24
1184; GCN-IR-NEXT:    s_mov_b32 s1, s0
1185; GCN-IR-NEXT:    s_mov_b32 s13, s12
1186; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[8:9], s[0:1]
1187; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[10:11], s[12:13]
1188; GCN-IR-NEXT:    s_sub_u32 s2, s2, s0
1189; GCN-IR-NEXT:    s_subb_u32 s3, s3, s0
1190; GCN-IR-NEXT:    s_sub_u32 s6, s6, s12
1191; GCN-IR-NEXT:    s_subb_u32 s7, s7, s12
1192; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
1193; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[2:3], 0
1194; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1195; GCN-IR-NEXT:    s_or_b64 s[16:17], s[10:11], s[12:13]
1196; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s6
1197; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s2
1198; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
1199; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s7
1200; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
1201; GCN-IR-NEXT:    s_flbit_i32_b32 s13, s3
1202; GCN-IR-NEXT:    s_min_u32 s10, s10, s11
1203; GCN-IR-NEXT:    s_min_u32 s14, s12, s13
1204; GCN-IR-NEXT:    s_sub_u32 s12, s10, s14
1205; GCN-IR-NEXT:    s_subb_u32 s13, 0, 0
1206; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[18:19], s[12:13], 63
1207; GCN-IR-NEXT:    s_mov_b32 s11, 0
1208; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[18:19]
1209; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[18:19], s[12:13], 63
1210; GCN-IR-NEXT:    s_xor_b64 s[20:21], s[16:17], -1
1211; GCN-IR-NEXT:    s_and_b64 s[18:19], s[20:21], s[18:19]
1212; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[18:19]
1213; GCN-IR-NEXT:    s_cbranch_vccz BB9_5
1214; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1215; GCN-IR-NEXT:    s_add_u32 s16, s12, 1
1216; GCN-IR-NEXT:    v_mov_b32_e32 v0, s12
1217; GCN-IR-NEXT:    s_addc_u32 s17, s13, 0
1218; GCN-IR-NEXT:    v_mov_b32_e32 v1, s13
1219; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[16:17], v[0:1]
1220; GCN-IR-NEXT:    s_sub_i32 s12, 63, s12
1221; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1222; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[2:3], s12
1223; GCN-IR-NEXT:    s_cbranch_vccz BB9_4
1224; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1225; GCN-IR-NEXT:    s_lshr_b64 s[16:17], s[2:3], s16
1226; GCN-IR-NEXT:    s_add_u32 s18, s6, -1
1227; GCN-IR-NEXT:    s_addc_u32 s19, s7, -1
1228; GCN-IR-NEXT:    s_not_b64 s[8:9], s[10:11]
1229; GCN-IR-NEXT:    s_mov_b32 s15, s11
1230; GCN-IR-NEXT:    s_add_u32 s10, s8, s14
1231; GCN-IR-NEXT:    s_addc_u32 s11, s9, s11
1232; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
1233; GCN-IR-NEXT:    s_mov_b32 s9, 0
1234; GCN-IR-NEXT:  BB9_3: ; %udiv-do-while
1235; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1236; GCN-IR-NEXT:    s_lshl_b64 s[16:17], s[16:17], 1
1237; GCN-IR-NEXT:    s_lshr_b32 s8, s13, 31
1238; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
1239; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[8:9]
1240; GCN-IR-NEXT:    s_or_b64 s[12:13], s[14:15], s[12:13]
1241; GCN-IR-NEXT:    s_sub_u32 s8, s18, s16
1242; GCN-IR-NEXT:    s_subb_u32 s8, s19, s17
1243; GCN-IR-NEXT:    s_ashr_i32 s14, s8, 31
1244; GCN-IR-NEXT:    s_mov_b32 s15, s14
1245; GCN-IR-NEXT:    s_and_b32 s8, s14, 1
1246; GCN-IR-NEXT:    s_and_b64 s[20:21], s[14:15], s[6:7]
1247; GCN-IR-NEXT:    s_sub_u32 s16, s16, s20
1248; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1249; GCN-IR-NEXT:    s_subb_u32 s17, s17, s21
1250; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
1251; GCN-IR-NEXT:    s_add_u32 s10, s10, 1
1252; GCN-IR-NEXT:    s_addc_u32 s11, s11, 0
1253; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
1254; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[8:9]
1255; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1256; GCN-IR-NEXT:    s_cbranch_vccz BB9_3
1257; GCN-IR-NEXT:  BB9_4: ; %Flow3
1258; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[12:13], 1
1259; GCN-IR-NEXT:    s_or_b64 s[8:9], s[8:9], s[10:11]
1260; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
1261; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
1262; GCN-IR-NEXT:    s_branch BB9_6
1263; GCN-IR-NEXT:  BB9_5:
1264; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
1265; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[16:17]
1266; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1267; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[16:17]
1268; GCN-IR-NEXT:  BB9_6: ; %udiv-end
1269; GCN-IR-NEXT:    v_mul_lo_u32 v1, s6, v1
1270; GCN-IR-NEXT:    v_mul_hi_u32 v2, s6, v0
1271; GCN-IR-NEXT:    v_mul_lo_u32 v3, s7, v0
1272; GCN-IR-NEXT:    v_mul_lo_u32 v0, s6, v0
1273; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1274; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1275; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1276; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
1277; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1278; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
1279; GCN-IR-NEXT:    v_xor_b32_e32 v0, s0, v0
1280; GCN-IR-NEXT:    v_xor_b32_e32 v1, s1, v1
1281; GCN-IR-NEXT:    v_mov_b32_e32 v2, s1
1282; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
1283; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1284; GCN-IR-NEXT:    s_mov_b32 s6, -1
1285; GCN-IR-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
1286; GCN-IR-NEXT:    buffer_store_dword v0, off, s[4:7], 0
1287; GCN-IR-NEXT:    s_endpgm
1288  %1 = ashr i48 %x, 24
1289  %2 = ashr i48 %y, 24
1290  %result = srem i48 %1, %2
1291  store i48 %result, i48 addrspace(1)* %out
1292  ret void
1293}
1294
1295define amdgpu_kernel void @s_test_srem_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1296; GCN-LABEL: s_test_srem_k_num_i64:
1297; GCN:       ; %bb.0:
1298; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1299; GCN-NEXT:    v_mov_b32_e32 v2, 0
1300; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1301; GCN-NEXT:    s_ashr_i32 s0, s7, 31
1302; GCN-NEXT:    s_add_u32 s2, s6, s0
1303; GCN-NEXT:    s_mov_b32 s1, s0
1304; GCN-NEXT:    s_addc_u32 s3, s7, s0
1305; GCN-NEXT:    s_xor_b64 s[8:9], s[2:3], s[0:1]
1306; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
1307; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s9
1308; GCN-NEXT:    s_sub_u32 s2, 0, s8
1309; GCN-NEXT:    s_subb_u32 s3, 0, s9
1310; GCN-NEXT:    s_mov_b32 s7, 0xf000
1311; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
1312; GCN-NEXT:    v_rcp_f32_e32 v0, v0
1313; GCN-NEXT:    v_mov_b32_e32 v1, 0
1314; GCN-NEXT:    s_mov_b32 s6, -1
1315; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
1316; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
1317; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1318; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
1319; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1320; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
1321; GCN-NEXT:    v_mul_lo_u32 v4, s2, v3
1322; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
1323; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
1324; GCN-NEXT:    v_mul_lo_u32 v6, s2, v0
1325; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1326; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
1327; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
1328; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
1329; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
1330; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
1331; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
1332; GCN-NEXT:    v_mul_hi_u32 v10, v3, v4
1333; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
1334; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
1335; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1336; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
1337; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
1338; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
1339; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1340; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
1341; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
1342; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
1343; GCN-NEXT:    v_mul_lo_u32 v6, s2, v4
1344; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
1345; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
1346; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1347; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
1348; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
1349; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
1350; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
1351; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
1352; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
1353; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
1354; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
1355; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
1356; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
1357; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
1358; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
1359; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
1360; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v8, v1, vcc
1361; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
1362; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
1363; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1364; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v3, v1, s[0:1]
1365; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
1366; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1367; GCN-NEXT:    v_mul_lo_u32 v3, v1, 24
1368; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
1369; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
1370; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
1371; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v2, v1, vcc
1372; GCN-NEXT:    v_mul_lo_u32 v1, s9, v0
1373; GCN-NEXT:    v_mul_hi_u32 v2, s8, v0
1374; GCN-NEXT:    v_mul_lo_u32 v0, s8, v0
1375; GCN-NEXT:    v_mov_b32_e32 v3, s9
1376; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1377; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
1378; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1379; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
1380; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s8, v0
1381; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
1382; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s9, v5
1383; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
1384; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s8, v4
1385; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
1386; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
1387; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s9, v5
1388; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s8, v4
1389; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
1390; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
1391; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1392; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
1393; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
1394; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
1395; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
1396; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
1397; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1398; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v1
1399; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
1400; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
1401; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1402; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
1403; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1404; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1405; GCN-NEXT:    s_endpgm
1406;
1407; GCN-IR-LABEL: s_test_srem_k_num_i64:
1408; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1409; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1410; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1411; GCN-IR-NEXT:    s_ashr_i32 s6, s3, 31
1412; GCN-IR-NEXT:    s_mov_b32 s7, s6
1413; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[2:3], s[6:7]
1414; GCN-IR-NEXT:    s_sub_u32 s4, s2, s6
1415; GCN-IR-NEXT:    s_subb_u32 s5, s3, s6
1416; GCN-IR-NEXT:    s_flbit_i32_b32 s2, s4
1417; GCN-IR-NEXT:    s_add_i32 s2, s2, 32
1418; GCN-IR-NEXT:    s_flbit_i32_b32 s3, s5
1419; GCN-IR-NEXT:    s_min_u32 s6, s2, s3
1420; GCN-IR-NEXT:    s_add_u32 s8, s6, 0xffffffc5
1421; GCN-IR-NEXT:    s_addc_u32 s9, 0, -1
1422; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[4:5], 0
1423; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[12:13], s[8:9], 63
1424; GCN-IR-NEXT:    s_mov_b64 s[2:3], 0
1425; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
1426; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[12:13], s[8:9], 63
1427; GCN-IR-NEXT:    s_xor_b64 s[14:15], s[10:11], -1
1428; GCN-IR-NEXT:    s_and_b64 s[12:13], s[14:15], s[12:13]
1429; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
1430; GCN-IR-NEXT:    s_cbranch_vccz BB10_5
1431; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1432; GCN-IR-NEXT:    s_add_u32 s10, s8, 1
1433; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
1434; GCN-IR-NEXT:    s_addc_u32 s11, s9, 0
1435; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
1436; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
1437; GCN-IR-NEXT:    s_sub_i32 s7, 63, s8
1438; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1439; GCN-IR-NEXT:    s_lshl_b64 s[8:9], 24, s7
1440; GCN-IR-NEXT:    s_cbranch_vccz BB10_4
1441; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1442; GCN-IR-NEXT:    s_lshr_b64 s[12:13], 24, s10
1443; GCN-IR-NEXT:    s_add_u32 s14, s4, -1
1444; GCN-IR-NEXT:    s_addc_u32 s15, s5, -1
1445; GCN-IR-NEXT:    s_sub_u32 s6, 58, s6
1446; GCN-IR-NEXT:    s_subb_u32 s7, 0, 0
1447; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1448; GCN-IR-NEXT:    s_mov_b32 s3, 0
1449; GCN-IR-NEXT:  BB10_3: ; %udiv-do-while
1450; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1451; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
1452; GCN-IR-NEXT:    s_lshr_b32 s2, s9, 31
1453; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
1454; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[2:3]
1455; GCN-IR-NEXT:    s_or_b64 s[8:9], s[10:11], s[8:9]
1456; GCN-IR-NEXT:    s_sub_u32 s2, s14, s12
1457; GCN-IR-NEXT:    s_subb_u32 s2, s15, s13
1458; GCN-IR-NEXT:    s_ashr_i32 s10, s2, 31
1459; GCN-IR-NEXT:    s_mov_b32 s11, s10
1460; GCN-IR-NEXT:    s_and_b32 s2, s10, 1
1461; GCN-IR-NEXT:    s_and_b64 s[16:17], s[10:11], s[4:5]
1462; GCN-IR-NEXT:    s_sub_u32 s12, s12, s16
1463; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1464; GCN-IR-NEXT:    s_subb_u32 s13, s13, s17
1465; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
1466; GCN-IR-NEXT:    s_add_u32 s6, s6, 1
1467; GCN-IR-NEXT:    s_addc_u32 s7, s7, 0
1468; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1]
1469; GCN-IR-NEXT:    s_mov_b64 s[10:11], s[2:3]
1470; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1471; GCN-IR-NEXT:    s_cbranch_vccz BB10_3
1472; GCN-IR-NEXT:  BB10_4: ; %Flow5
1473; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[8:9], 1
1474; GCN-IR-NEXT:    s_or_b64 s[2:3], s[2:3], s[6:7]
1475; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1476; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
1477; GCN-IR-NEXT:    s_branch BB10_6
1478; GCN-IR-NEXT:  BB10_5:
1479; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1480; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, 24, 0, s[10:11]
1481; GCN-IR-NEXT:  BB10_6: ; %udiv-end
1482; GCN-IR-NEXT:    v_mul_lo_u32 v1, s4, v1
1483; GCN-IR-NEXT:    v_mul_hi_u32 v2, s4, v0
1484; GCN-IR-NEXT:    v_mul_lo_u32 v3, s5, v0
1485; GCN-IR-NEXT:    v_mul_lo_u32 v0, s4, v0
1486; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1487; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1488; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1489; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1490; GCN-IR-NEXT:    s_mov_b32 s2, -1
1491; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1492; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1493; GCN-IR-NEXT:    s_endpgm
1494  %result = srem i64 24, %x
1495  store i64 %result, i64 addrspace(1)* %out
1496  ret void
1497}
1498
1499define i64 @v_test_srem_k_num_i64(i64 %x) {
1500; GCN-LABEL: v_test_srem_k_num_i64:
1501; GCN:       ; %bb.0:
1502; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1503; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1504; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1505; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1506; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1507; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1508; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1509; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1510; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1511; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1512; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
1513; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1514; GCN-NEXT:    v_mov_b32_e32 v12, 0
1515; GCN-NEXT:    v_mov_b32_e32 v11, 0
1516; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1517; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1518; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1519; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1520; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1521; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1522; GCN-NEXT:    v_mul_hi_u32 v6, v4, v2
1523; GCN-NEXT:    v_mul_lo_u32 v7, v4, v3
1524; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1525; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
1526; GCN-NEXT:    v_mul_lo_u32 v7, v4, v2
1527; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1528; GCN-NEXT:    v_mul_lo_u32 v9, v2, v6
1529; GCN-NEXT:    v_mul_hi_u32 v10, v2, v7
1530; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
1531; GCN-NEXT:    v_mul_hi_u32 v13, v3, v6
1532; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1533; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1534; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
1535; GCN-NEXT:    v_mul_hi_u32 v7, v3, v7
1536; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v8, vcc
1537; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
1538; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v7, vcc
1539; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v11, vcc
1540; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1541; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v8, vcc
1542; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v6
1543; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v3, v7, s[4:5]
1544; GCN-NEXT:    v_mul_lo_u32 v8, v4, v6
1545; GCN-NEXT:    v_mul_hi_u32 v9, v4, v2
1546; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1547; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1548; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1549; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
1550; GCN-NEXT:    v_mul_lo_u32 v10, v2, v5
1551; GCN-NEXT:    v_mul_hi_u32 v13, v2, v4
1552; GCN-NEXT:    v_mul_hi_u32 v14, v2, v5
1553; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
1554; GCN-NEXT:    v_mul_lo_u32 v4, v6, v4
1555; GCN-NEXT:    v_mul_hi_u32 v8, v6, v5
1556; GCN-NEXT:    v_add_i32_e32 v10, vcc, v13, v10
1557; GCN-NEXT:    v_addc_u32_e32 v13, vcc, v12, v14, vcc
1558; GCN-NEXT:    v_mul_lo_u32 v5, v6, v5
1559; GCN-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
1560; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v13, v9, vcc
1561; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v11, vcc
1562; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1563; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
1564; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
1565; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
1566; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1567; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1568; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
1569; GCN-NEXT:    v_mul_hi_u32 v2, v2, 24
1570; GCN-NEXT:    v_mul_hi_u32 v3, v3, 24
1571; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1572; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v12, v3, vcc
1573; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
1574; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1575; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
1576; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1577; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
1578; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 24, v2
1579; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
1580; GCN-NEXT:    v_sub_i32_e64 v5, s[4:5], v2, v0
1581; GCN-NEXT:    v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
1582; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v1
1583; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[6:7]
1584; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v5, v0
1585; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
1586; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v6, v1
1587; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
1588; GCN-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[6:7]
1589; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v5, v0
1590; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1591; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
1592; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1593; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1594; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
1595; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v0
1596; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1597; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1598; GCN-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
1599; GCN-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[4:5]
1600; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1601; GCN-NEXT:    v_cndmask_b32_e64 v1, v6, v4, s[4:5]
1602; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1603; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1604; GCN-NEXT:    s_setpc_b64 s[30:31]
1605;
1606; GCN-IR-LABEL: v_test_srem_k_num_i64:
1607; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1608; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1609; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1610; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1611; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
1612; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1613; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1614; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1615; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1616; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1617; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1618; GCN-IR-NEXT:    s_movk_i32 s6, 0xffc5
1619; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, s6, v6
1620; GCN-IR-NEXT:    v_addc_u32_e64 v4, s[6:7], 0, -1, vcc
1621; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1622; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[3:4]
1623; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1624; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1625; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[3:4]
1626; GCN-IR-NEXT:    v_cndmask_b32_e64 v2, 24, 0, s[4:5]
1627; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1628; GCN-IR-NEXT:    v_mov_b32_e32 v5, v7
1629; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1630; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1631; GCN-IR-NEXT:    s_cbranch_execz BB11_6
1632; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1633; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v3
1634; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v4, vcc
1635; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v3
1636; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[8:9], v[3:4]
1637; GCN-IR-NEXT:    v_lshl_b64 v[2:3], 24, v2
1638; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1639; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1640; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1641; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1642; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1643; GCN-IR-NEXT:    s_cbranch_execz BB11_5
1644; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1645; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, -1, v0
1646; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, -1, v1, vcc
1647; GCN-IR-NEXT:    v_lshr_b64 v[8:9], 24, v8
1648; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, 58, v6
1649; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1650; GCN-IR-NEXT:    v_subb_u32_e32 v7, vcc, 0, v7, vcc
1651; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1652; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1653; GCN-IR-NEXT:  BB11_3: ; %udiv-do-while
1654; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1655; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1656; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1657; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1658; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1659; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, v12, v8
1660; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, v13, v9, vcc
1661; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1662; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1663; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1664; GCN-IR-NEXT:    v_and_b32_e32 v14, v10, v1
1665; GCN-IR-NEXT:    v_and_b32_e32 v15, v10, v0
1666; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v6
1667; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1668; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v7, vcc
1669; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7]
1670; GCN-IR-NEXT:    v_mov_b32_e32 v6, v10
1671; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v15
1672; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1673; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1674; GCN-IR-NEXT:    v_subb_u32_e64 v9, s[4:5], v9, v14, s[4:5]
1675; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1676; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1677; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1678; GCN-IR-NEXT:    s_cbranch_execnz BB11_3
1679; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1680; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1681; GCN-IR-NEXT:  BB11_5: ; %Flow3
1682; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1683; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1684; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1685; GCN-IR-NEXT:    v_or_b32_e32 v2, v4, v2
1686; GCN-IR-NEXT:  BB11_6: ; %Flow4
1687; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1688; GCN-IR-NEXT:    v_mul_lo_u32 v3, v0, v5
1689; GCN-IR-NEXT:    v_mul_hi_u32 v4, v0, v2
1690; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v2
1691; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, v2
1692; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1693; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
1694; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1695; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1696; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1697  %result = srem i64 24, %x
1698  ret i64 %result
1699}
1700
1701define i64 @v_test_srem_pow2_k_num_i64(i64 %x) {
1702; GCN-LABEL: v_test_srem_pow2_k_num_i64:
1703; GCN:       ; %bb.0:
1704; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1705; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1706; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1707; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1708; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1709; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1710; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1711; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1712; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1713; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1714; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
1715; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1716; GCN-NEXT:    v_mov_b32_e32 v12, 0
1717; GCN-NEXT:    v_mov_b32_e32 v11, 0
1718; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1719; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1720; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1721; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1722; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1723; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1724; GCN-NEXT:    v_mul_hi_u32 v6, v4, v2
1725; GCN-NEXT:    v_mul_lo_u32 v7, v4, v3
1726; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1727; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
1728; GCN-NEXT:    v_mul_lo_u32 v7, v4, v2
1729; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1730; GCN-NEXT:    v_mul_lo_u32 v9, v2, v6
1731; GCN-NEXT:    v_mul_hi_u32 v10, v2, v7
1732; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
1733; GCN-NEXT:    v_mul_hi_u32 v13, v3, v6
1734; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1735; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1736; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
1737; GCN-NEXT:    v_mul_hi_u32 v7, v3, v7
1738; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v8, vcc
1739; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
1740; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v7, vcc
1741; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v11, vcc
1742; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1743; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v8, vcc
1744; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v6
1745; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v3, v7, s[4:5]
1746; GCN-NEXT:    v_mul_lo_u32 v8, v4, v6
1747; GCN-NEXT:    v_mul_hi_u32 v9, v4, v2
1748; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1749; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1750; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1751; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
1752; GCN-NEXT:    v_mul_lo_u32 v10, v2, v5
1753; GCN-NEXT:    v_mul_hi_u32 v13, v2, v4
1754; GCN-NEXT:    v_mul_hi_u32 v14, v2, v5
1755; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
1756; GCN-NEXT:    v_mul_lo_u32 v4, v6, v4
1757; GCN-NEXT:    v_mul_hi_u32 v8, v6, v5
1758; GCN-NEXT:    v_add_i32_e32 v10, vcc, v13, v10
1759; GCN-NEXT:    v_addc_u32_e32 v13, vcc, v12, v14, vcc
1760; GCN-NEXT:    v_mul_lo_u32 v5, v6, v5
1761; GCN-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
1762; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v13, v9, vcc
1763; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v11, vcc
1764; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1765; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
1766; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
1767; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
1768; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1769; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1770; GCN-NEXT:    v_lshrrev_b32_e32 v4, 17, v3
1771; GCN-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
1772; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1773; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
1774; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v12, v4, vcc
1775; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
1776; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1777; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
1778; GCN-NEXT:    s_mov_b32 s4, 0x8000
1779; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1780; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
1781; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s4, v2
1782; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
1783; GCN-NEXT:    v_sub_i32_e64 v5, s[4:5], v2, v0
1784; GCN-NEXT:    v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
1785; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v1
1786; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[6:7]
1787; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v5, v0
1788; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
1789; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v6, v1
1790; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
1791; GCN-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[6:7]
1792; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v5, v0
1793; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1794; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
1795; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1796; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1797; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
1798; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v0
1799; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1800; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1801; GCN-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
1802; GCN-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[4:5]
1803; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1804; GCN-NEXT:    v_cndmask_b32_e64 v1, v6, v4, s[4:5]
1805; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1806; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1807; GCN-NEXT:    s_setpc_b64 s[30:31]
1808;
1809; GCN-IR-LABEL: v_test_srem_pow2_k_num_i64:
1810; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1811; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1812; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1813; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1814; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
1815; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1816; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1817; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1818; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1819; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1820; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1821; GCN-IR-NEXT:    s_movk_i32 s6, 0xffd0
1822; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, s6, v6
1823; GCN-IR-NEXT:    v_addc_u32_e64 v3, s[6:7], 0, -1, vcc
1824; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1825; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[2:3]
1826; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0x8000
1827; GCN-IR-NEXT:    v_mov_b32_e32 v4, s8
1828; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1829; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[2:3]
1830; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1831; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v4, 0, s[4:5]
1832; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1833; GCN-IR-NEXT:    v_mov_b32_e32 v5, v7
1834; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1835; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1836; GCN-IR-NEXT:    s_cbranch_execz BB12_6
1837; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1838; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v2
1839; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v3, vcc
1840; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[8:9], v[2:3]
1841; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v2
1842; GCN-IR-NEXT:    v_lshl_b64 v[2:3], s[8:9], v2
1843; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1844; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1845; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1846; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1847; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1848; GCN-IR-NEXT:    s_cbranch_execz BB12_5
1849; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1850; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, -1, v0
1851; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0x8000
1852; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, -1, v1, vcc
1853; GCN-IR-NEXT:    v_lshr_b64 v[8:9], s[4:5], v8
1854; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, 47, v6
1855; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1856; GCN-IR-NEXT:    v_subb_u32_e32 v7, vcc, 0, v7, vcc
1857; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1858; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1859; GCN-IR-NEXT:  BB12_3: ; %udiv-do-while
1860; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1861; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1862; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1863; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1864; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1865; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, v12, v8
1866; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, v13, v9, vcc
1867; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1868; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1869; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1870; GCN-IR-NEXT:    v_and_b32_e32 v14, v10, v1
1871; GCN-IR-NEXT:    v_and_b32_e32 v15, v10, v0
1872; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v6
1873; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1874; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v7, vcc
1875; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7]
1876; GCN-IR-NEXT:    v_mov_b32_e32 v6, v10
1877; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v15
1878; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1879; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1880; GCN-IR-NEXT:    v_subb_u32_e64 v9, s[4:5], v9, v14, s[4:5]
1881; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1882; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1883; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1884; GCN-IR-NEXT:    s_cbranch_execnz BB12_3
1885; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1886; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1887; GCN-IR-NEXT:  BB12_5: ; %Flow3
1888; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1889; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1890; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1891; GCN-IR-NEXT:    v_or_b32_e32 v4, v4, v2
1892; GCN-IR-NEXT:  BB12_6: ; %Flow4
1893; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1894; GCN-IR-NEXT:    v_mul_lo_u32 v2, v0, v5
1895; GCN-IR-NEXT:    v_mul_hi_u32 v3, v0, v4
1896; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v4
1897; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, v4
1898; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1899; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1900; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1901; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1902; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1903  %result = srem i64 32768, %x
1904  ret i64 %result
1905}
1906
1907define i64 @v_test_srem_pow2_k_den_i64(i64 %x) {
1908; GCN-LABEL: v_test_srem_pow2_k_den_i64:
1909; GCN:       ; %bb.0:
1910; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1911; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1912; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1913; GCN-NEXT:    v_add_i32_e32 v2, vcc, v0, v2
1914; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
1915; GCN-NEXT:    v_and_b32_e32 v2, 0xffff8000, v2
1916; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1917; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1918; GCN-NEXT:    s_setpc_b64 s[30:31]
1919;
1920; GCN-IR-LABEL: v_test_srem_pow2_k_den_i64:
1921; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1922; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1923; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1924; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1925; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
1926; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1927; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1928; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v0
1929; GCN-IR-NEXT:    v_add_i32_e64 v3, s[4:5], 32, v3
1930; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v1
1931; GCN-IR-NEXT:    v_min_u32_e32 v8, v3, v4
1932; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 48, v8
1933; GCN-IR-NEXT:    v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5]
1934; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1935; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
1936; GCN-IR-NEXT:    v_mov_b32_e32 v3, v2
1937; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1938; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1939; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1940; GCN-IR-NEXT:    v_cndmask_b32_e64 v7, v1, 0, s[4:5]
1941; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v0, 0, s[4:5]
1942; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1943; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1944; GCN-IR-NEXT:    s_cbranch_execz BB13_6
1945; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1946; GCN-IR-NEXT:    v_add_i32_e32 v9, vcc, 1, v4
1947; GCN-IR-NEXT:    v_addc_u32_e32 v10, vcc, 0, v5, vcc
1948; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[9:10], v[4:5]
1949; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v4
1950; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[0:1], v4
1951; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1952; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1953; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1954; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1955; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1956; GCN-IR-NEXT:    s_cbranch_execz BB13_5
1957; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1958; GCN-IR-NEXT:    v_lshr_b64 v[10:11], v[0:1], v9
1959; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 0xffffffcf, v8
1960; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1961; GCN-IR-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, -1, vcc
1962; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1963; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1964; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
1965; GCN-IR-NEXT:  BB13_3: ; %udiv-do-while
1966; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1967; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
1968; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
1969; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v6
1970; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
1971; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, s12, v10
1972; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, 0, v11, vcc
1973; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
1974; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v6
1975; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v12
1976; GCN-IR-NEXT:    v_and_b32_e32 v15, 0x8000, v12
1977; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
1978; GCN-IR-NEXT:    v_or_b32_e32 v5, v13, v5
1979; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
1980; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
1981; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
1982; GCN-IR-NEXT:    v_mov_b32_e32 v14, 0
1983; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v15
1984; GCN-IR-NEXT:    v_mov_b32_e32 v9, v13
1985; GCN-IR-NEXT:    v_mov_b32_e32 v13, v7
1986; GCN-IR-NEXT:    v_subb_u32_e64 v11, s[4:5], v11, v14, s[4:5]
1987; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1988; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
1989; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1990; GCN-IR-NEXT:    s_cbranch_execnz BB13_3
1991; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1992; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1993; GCN-IR-NEXT:  BB13_5: ; %Flow3
1994; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1995; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
1996; GCN-IR-NEXT:    v_or_b32_e32 v7, v7, v5
1997; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v4
1998; GCN-IR-NEXT:  BB13_6: ; %Flow4
1999; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
2000; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[6:7], 15
2001; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
2002; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
2003; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
2004; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v3
2005; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
2006; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
2007; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2008  %result = srem i64 %x, 32768
2009  ret i64 %result
2010}
2011
2012define amdgpu_kernel void @s_test_srem24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
2013; GCN-LABEL: s_test_srem24_k_num_i64:
2014; GCN:       ; %bb.0:
2015; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
2016; GCN-NEXT:    s_mov_b32 s6, 0x41c00000
2017; GCN-NEXT:    s_waitcnt lgkmcnt(0)
2018; GCN-NEXT:    s_ashr_i64 s[4:5], s[2:3], 40
2019; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
2020; GCN-NEXT:    s_ashr_i32 s5, s4, 30
2021; GCN-NEXT:    s_or_b32 s5, s5, 1
2022; GCN-NEXT:    v_mov_b32_e32 v3, s5
2023; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
2024; GCN-NEXT:    s_mov_b32 s3, 0xf000
2025; GCN-NEXT:    s_mov_b32 s2, -1
2026; GCN-NEXT:    v_mul_f32_e32 v1, s6, v1
2027; GCN-NEXT:    v_trunc_f32_e32 v1, v1
2028; GCN-NEXT:    v_mad_f32 v2, -v1, v0, s6
2029; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
2030; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
2031; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
2032; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
2033; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
2034; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2035; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2036; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2037; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2038; GCN-NEXT:    s_endpgm
2039;
2040; GCN-IR-LABEL: s_test_srem24_k_num_i64:
2041; GCN-IR:       ; %bb.0:
2042; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
2043; GCN-IR-NEXT:    s_mov_b32 s6, 0x41c00000
2044; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
2045; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[2:3], 40
2046; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
2047; GCN-IR-NEXT:    s_ashr_i32 s5, s4, 30
2048; GCN-IR-NEXT:    s_or_b32 s5, s5, 1
2049; GCN-IR-NEXT:    v_mov_b32_e32 v3, s5
2050; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
2051; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
2052; GCN-IR-NEXT:    s_mov_b32 s2, -1
2053; GCN-IR-NEXT:    v_mul_f32_e32 v1, s6, v1
2054; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
2055; GCN-IR-NEXT:    v_mad_f32 v2, -v1, v0, s6
2056; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
2057; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
2058; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
2059; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
2060; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
2061; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2062; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2063; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2064; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2065; GCN-IR-NEXT:    s_endpgm
2066  %x.shr = ashr i64 %x, 40
2067  %result = srem i64 24, %x.shr
2068  store i64 %result, i64 addrspace(1)* %out
2069  ret void
2070}
2071
2072define amdgpu_kernel void @s_test_srem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
2073; GCN-LABEL: s_test_srem24_k_den_i64:
2074; GCN:       ; %bb.0:
2075; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
2076; GCN-NEXT:    s_mov_b32 s1, 0x46b6fe00
2077; GCN-NEXT:    s_mov_b32 s3, 0xf000
2078; GCN-NEXT:    s_mov_b32 s2, -1
2079; GCN-NEXT:    s_waitcnt lgkmcnt(0)
2080; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
2081; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s6
2082; GCN-NEXT:    s_ashr_i32 s0, s6, 30
2083; GCN-NEXT:    s_or_b32 s0, s0, 1
2084; GCN-NEXT:    v_mov_b32_e32 v1, s0
2085; GCN-NEXT:    v_mul_f32_e32 v2, 0x38331158, v0
2086; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2087; GCN-NEXT:    v_mad_f32 v0, -v2, s1, v0
2088; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2089; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s1
2090; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
2091; GCN-NEXT:    s_movk_i32 s0, 0x5b7f
2092; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
2093; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
2094; GCN-NEXT:    s_mov_b32 s0, s4
2095; GCN-NEXT:    s_mov_b32 s1, s5
2096; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
2097; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2098; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2099; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2100; GCN-NEXT:    s_endpgm
2101;
2102; GCN-IR-LABEL: s_test_srem24_k_den_i64:
2103; GCN-IR:       ; %bb.0:
2104; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
2105; GCN-IR-NEXT:    s_mov_b32 s1, 0x46b6fe00
2106; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
2107; GCN-IR-NEXT:    s_mov_b32 s2, -1
2108; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
2109; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
2110; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s6
2111; GCN-IR-NEXT:    s_ashr_i32 s0, s6, 30
2112; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
2113; GCN-IR-NEXT:    v_mov_b32_e32 v1, s0
2114; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x38331158, v0
2115; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2116; GCN-IR-NEXT:    v_mad_f32 v0, -v2, s1, v0
2117; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2118; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s1
2119; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
2120; GCN-IR-NEXT:    s_movk_i32 s0, 0x5b7f
2121; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
2122; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
2123; GCN-IR-NEXT:    s_mov_b32 s0, s4
2124; GCN-IR-NEXT:    s_mov_b32 s1, s5
2125; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
2126; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2127; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2128; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2129; GCN-IR-NEXT:    s_endpgm
2130  %x.shr = ashr i64 %x, 40
2131  %result = srem i64 %x.shr, 23423
2132  store i64 %result, i64 addrspace(1)* %out
2133  ret void
2134}
2135
2136define i64 @v_test_srem24_k_num_i64(i64 %x) {
2137; GCN-LABEL: v_test_srem24_k_num_i64:
2138; GCN:       ; %bb.0:
2139; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2140; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2141; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
2142; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
2143; GCN-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2144; GCN-NEXT:    v_or_b32_e32 v3, 1, v3
2145; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2146; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
2147; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2148; GCN-NEXT:    v_mad_f32 v4, -v2, v1, s4
2149; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2150; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2151; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2152; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2153; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
2154; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2155; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2156; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2157; GCN-NEXT:    s_setpc_b64 s[30:31]
2158;
2159; GCN-IR-LABEL: v_test_srem24_k_num_i64:
2160; GCN-IR:       ; %bb.0:
2161; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2162; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2163; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
2164; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2165; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2166; GCN-IR-NEXT:    v_or_b32_e32 v3, 1, v3
2167; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2168; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
2169; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2170; GCN-IR-NEXT:    v_mad_f32 v4, -v2, v1, s4
2171; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2172; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2173; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2174; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2175; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
2176; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2177; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2178; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2179; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2180  %x.shr = ashr i64 %x, 40
2181  %result = srem i64 24, %x.shr
2182  ret i64 %result
2183}
2184
2185define i64 @v_test_srem24_pow2_k_num_i64(i64 %x) {
2186; GCN-LABEL: v_test_srem24_pow2_k_num_i64:
2187; GCN:       ; %bb.0:
2188; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2189; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2190; GCN-NEXT:    s_mov_b32 s4, 0x47000000
2191; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
2192; GCN-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2193; GCN-NEXT:    v_or_b32_e32 v3, 1, v3
2194; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2195; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
2196; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2197; GCN-NEXT:    v_mad_f32 v4, -v2, v1, s4
2198; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2199; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2200; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2201; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2202; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
2203; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
2204; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2205; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2206; GCN-NEXT:    s_setpc_b64 s[30:31]
2207;
2208; GCN-IR-LABEL: v_test_srem24_pow2_k_num_i64:
2209; GCN-IR:       ; %bb.0:
2210; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2211; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2212; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2213; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2214; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2215; GCN-IR-NEXT:    v_or_b32_e32 v3, 1, v3
2216; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2217; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
2218; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2219; GCN-IR-NEXT:    v_mad_f32 v4, -v2, v1, s4
2220; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2221; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2222; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2223; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2224; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
2225; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
2226; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2227; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2228; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2229  %x.shr = ashr i64 %x, 40
2230  %result = srem i64 32768, %x.shr
2231  ret i64 %result
2232}
2233
2234define i64 @v_test_srem24_pow2_k_den_i64(i64 %x) {
2235; GCN-LABEL: v_test_srem24_pow2_k_den_i64:
2236; GCN:       ; %bb.0:
2237; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2238; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2239; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v1
2240; GCN-NEXT:    v_add_i32_e32 v2, vcc, v0, v2
2241; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
2242; GCN-NEXT:    v_and_b32_e32 v2, 0xffff8000, v2
2243; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
2244; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
2245; GCN-NEXT:    s_setpc_b64 s[30:31]
2246;
2247; GCN-IR-LABEL: v_test_srem24_pow2_k_den_i64:
2248; GCN-IR:       ; %bb.0:
2249; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2250; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2251; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2252; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2253; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 30, v0
2254; GCN-IR-NEXT:    v_or_b32_e32 v2, 1, v2
2255; GCN-IR-NEXT:    v_mul_f32_e32 v3, 0x38000000, v1
2256; GCN-IR-NEXT:    v_trunc_f32_e32 v3, v3
2257; GCN-IR-NEXT:    v_mad_f32 v1, -v3, s4, v1
2258; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v3
2259; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
2260; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
2261; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
2262; GCN-IR-NEXT:    v_lshlrev_b32_e32 v1, 15, v1
2263; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
2264; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2265; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2266; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2267  %x.shr = ashr i64 %x, 40
2268  %result = srem i64 %x.shr, 32768
2269  ret i64 %result
2270}
2271