1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_srem(i64 addrspace(1)* %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_srem:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
9; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
10; GCN-NEXT:    s_mov_b32 s7, 0xf000
11; GCN-NEXT:    s_mov_b32 s6, -1
12; GCN-NEXT:    s_waitcnt lgkmcnt(0)
13; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
14; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
15; GCN-NEXT:    s_sub_u32 s0, 0, s12
16; GCN-NEXT:    s_subb_u32 s1, 0, s13
17; GCN-NEXT:    s_mov_b32 s4, s8
18; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
19; GCN-NEXT:    v_rcp_f32_e32 v0, v0
20; GCN-NEXT:    v_mov_b32_e32 v1, 0
21; GCN-NEXT:    s_mov_b32 s5, s9
22; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
23; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
24; GCN-NEXT:    v_trunc_f32_e32 v2, v2
25; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
26; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
27; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
28; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
29; GCN-NEXT:    v_mul_hi_u32 v4, s0, v0
30; GCN-NEXT:    v_mul_lo_u32 v6, s1, v0
31; GCN-NEXT:    v_mul_lo_u32 v5, s0, v0
32; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
33; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
34; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
35; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
36; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
37; GCN-NEXT:    v_mul_lo_u32 v7, v2, v5
38; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
39; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
40; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
41; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
42; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
43; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
44; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
45; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
46; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
47; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
48; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
49; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
50; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
51; GCN-NEXT:    v_mul_hi_u32 v4, s0, v0
52; GCN-NEXT:    v_mul_lo_u32 v5, s1, v0
53; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
54; GCN-NEXT:    v_mul_lo_u32 v4, s0, v0
55; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
56; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
57; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
58; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
59; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
60; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
61; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
62; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
63; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
64; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
65; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
66; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
67; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v1, vcc
68; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
69; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
70; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
71; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
72; GCN-NEXT:    v_mul_lo_u32 v3, s10, v2
73; GCN-NEXT:    v_mul_hi_u32 v4, s10, v0
74; GCN-NEXT:    v_mul_hi_u32 v5, s10, v2
75; GCN-NEXT:    v_mul_hi_u32 v6, s11, v2
76; GCN-NEXT:    v_mul_lo_u32 v2, s11, v2
77; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
78; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
79; GCN-NEXT:    v_mul_lo_u32 v5, s11, v0
80; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
81; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
82; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
83; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
84; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
85; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
86; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
87; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
88; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
89; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
90; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
91; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
92; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s11, v1
93; GCN-NEXT:    v_mov_b32_e32 v3, s13
94; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s10, v0
95; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
96; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
97; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
98; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
99; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
100; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
101; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
102; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
103; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
104; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
105; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
106; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
107; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
108; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
109; GCN-NEXT:    v_mov_b32_e32 v5, s11
110; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
111; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
112; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
113; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
114; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
115; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
116; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
117; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
118; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
119; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
120; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
121; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
122; GCN-NEXT:    s_endpgm
123;
124; GCN-IR-LABEL: s_test_srem:
125; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
126; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
127; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
128; GCN-IR-NEXT:    s_mov_b64 s[6:7], 0
129; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
130; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[4:5], 0
131; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
132; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s4
133; GCN-IR-NEXT:    s_or_b64 s[14:15], s[8:9], s[10:11]
134; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s2
135; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
136; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s5
137; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
138; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s3
139; GCN-IR-NEXT:    s_min_u32 s8, s12, s8
140; GCN-IR-NEXT:    s_min_u32 s12, s10, s11
141; GCN-IR-NEXT:    s_sub_u32 s10, s8, s12
142; GCN-IR-NEXT:    s_subb_u32 s11, 0, 0
143; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[16:17], s[10:11], 63
144; GCN-IR-NEXT:    s_mov_b32 s9, 0
145; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[16:17]
146; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[16:17], s[10:11], 63
147; GCN-IR-NEXT:    s_xor_b64 s[18:19], s[14:15], -1
148; GCN-IR-NEXT:    s_and_b64 s[16:17], s[18:19], s[16:17]
149; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[16:17]
150; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_5
151; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
152; GCN-IR-NEXT:    s_add_u32 s14, s10, 1
153; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
154; GCN-IR-NEXT:    s_addc_u32 s15, s11, 0
155; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
156; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[14:15], v[0:1]
157; GCN-IR-NEXT:    s_sub_i32 s10, 63, s10
158; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
159; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[2:3], s10
160; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_4
161; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
162; GCN-IR-NEXT:    s_lshr_b64 s[14:15], s[2:3], s14
163; GCN-IR-NEXT:    s_add_u32 s16, s4, -1
164; GCN-IR-NEXT:    s_addc_u32 s17, s5, -1
165; GCN-IR-NEXT:    s_not_b64 s[6:7], s[8:9]
166; GCN-IR-NEXT:    s_mov_b32 s13, s9
167; GCN-IR-NEXT:    s_add_u32 s8, s6, s12
168; GCN-IR-NEXT:    s_addc_u32 s9, s7, s9
169; GCN-IR-NEXT:    s_mov_b64 s[12:13], 0
170; GCN-IR-NEXT:    s_mov_b32 s7, 0
171; GCN-IR-NEXT:  .LBB0_3: ; %udiv-do-while
172; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
173; GCN-IR-NEXT:    s_lshl_b64 s[14:15], s[14:15], 1
174; GCN-IR-NEXT:    s_lshr_b32 s6, s11, 31
175; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
176; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[6:7]
177; GCN-IR-NEXT:    s_or_b64 s[10:11], s[12:13], s[10:11]
178; GCN-IR-NEXT:    s_sub_u32 s6, s16, s14
179; GCN-IR-NEXT:    s_subb_u32 s6, s17, s15
180; GCN-IR-NEXT:    s_ashr_i32 s12, s6, 31
181; GCN-IR-NEXT:    s_mov_b32 s13, s12
182; GCN-IR-NEXT:    s_and_b32 s6, s12, 1
183; GCN-IR-NEXT:    s_and_b64 s[18:19], s[12:13], s[4:5]
184; GCN-IR-NEXT:    s_sub_u32 s14, s14, s18
185; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
186; GCN-IR-NEXT:    s_subb_u32 s15, s15, s19
187; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
188; GCN-IR-NEXT:    s_add_u32 s8, s8, 1
189; GCN-IR-NEXT:    s_addc_u32 s9, s9, 0
190; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
191; GCN-IR-NEXT:    s_mov_b64 s[12:13], s[6:7]
192; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
193; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_3
194; GCN-IR-NEXT:  .LBB0_4: ; %Flow6
195; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[10:11], 1
196; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], s[8:9]
197; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
198; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
199; GCN-IR-NEXT:    s_branch .LBB0_6
200; GCN-IR-NEXT:  .LBB0_5:
201; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
202; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[14:15]
203; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
204; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[14:15]
205; GCN-IR-NEXT:  .LBB0_6: ; %udiv-end
206; GCN-IR-NEXT:    v_mul_lo_u32 v1, s4, v1
207; GCN-IR-NEXT:    v_mul_hi_u32 v2, s4, v0
208; GCN-IR-NEXT:    v_mul_lo_u32 v3, s5, v0
209; GCN-IR-NEXT:    v_mul_lo_u32 v0, s4, v0
210; GCN-IR-NEXT:    s_mov_b32 s11, 0xf000
211; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
212; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
213; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
214; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
215; GCN-IR-NEXT:    s_mov_b32 s10, -1
216; GCN-IR-NEXT:    s_mov_b32 s8, s0
217; GCN-IR-NEXT:    s_mov_b32 s9, s1
218; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
219; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
220; GCN-IR-NEXT:    s_endpgm
221  %result = urem i64 %x, %y
222  store i64 %result, i64 addrspace(1)* %out
223  ret void
224}
225
226define i64 @v_test_srem(i64 %x, i64 %y) {
227; GCN-LABEL: v_test_srem:
228; GCN:       ; %bb.0:
229; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
230; GCN-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
231; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
232; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
233; GCN-NEXT:    v_xor_b32_e32 v3, v3, v4
234; GCN-NEXT:    v_xor_b32_e32 v2, v2, v4
235; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v2
236; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v3
237; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v2
238; GCN-NEXT:    v_subb_u32_e32 v7, vcc, 0, v3, vcc
239; GCN-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
240; GCN-NEXT:    v_rcp_f32_e32 v4, v4
241; GCN-NEXT:    v_mov_b32_e32 v13, 0
242; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
243; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
244; GCN-NEXT:    v_trunc_f32_e32 v5, v5
245; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
246; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
247; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
248; GCN-NEXT:    v_mul_hi_u32 v8, v6, v4
249; GCN-NEXT:    v_mul_lo_u32 v9, v6, v5
250; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
251; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
252; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
253; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
254; GCN-NEXT:    v_mul_lo_u32 v10, v4, v8
255; GCN-NEXT:    v_mul_hi_u32 v11, v4, v9
256; GCN-NEXT:    v_mul_hi_u32 v12, v4, v8
257; GCN-NEXT:    v_mul_hi_u32 v14, v5, v8
258; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
259; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
260; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
261; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
262; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
263; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
264; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v11, v9, vcc
265; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v13, vcc
266; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
267; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
268; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
269; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v9, vcc
270; GCN-NEXT:    v_mul_lo_u32 v8, v6, v5
271; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
272; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
273; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
274; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
275; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
276; GCN-NEXT:    v_mul_lo_u32 v10, v4, v7
277; GCN-NEXT:    v_mul_hi_u32 v11, v4, v6
278; GCN-NEXT:    v_mul_hi_u32 v12, v4, v7
279; GCN-NEXT:    v_mul_hi_u32 v9, v5, v6
280; GCN-NEXT:    v_mul_lo_u32 v6, v5, v6
281; GCN-NEXT:    v_mul_hi_u32 v8, v5, v7
282; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
283; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
284; GCN-NEXT:    v_mul_lo_u32 v7, v5, v7
285; GCN-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
286; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
287; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v8, v13, vcc
288; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
289; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
290; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
291; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
292; GCN-NEXT:    v_ashrrev_i32_e32 v6, 31, v1
293; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
294; GCN-NEXT:    v_xor_b32_e32 v0, v0, v6
295; GCN-NEXT:    v_mul_lo_u32 v7, v0, v5
296; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
297; GCN-NEXT:    v_mul_hi_u32 v9, v0, v5
298; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v6, vcc
299; GCN-NEXT:    v_xor_b32_e32 v1, v1, v6
300; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
301; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
302; GCN-NEXT:    v_mul_lo_u32 v9, v1, v4
303; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
304; GCN-NEXT:    v_mul_hi_u32 v10, v1, v5
305; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
306; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
307; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
308; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v10, v13, vcc
309; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
310; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
311; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
312; GCN-NEXT:    v_mul_hi_u32 v7, v2, v4
313; GCN-NEXT:    v_mul_lo_u32 v8, v3, v4
314; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
315; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
316; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
317; GCN-NEXT:    v_sub_i32_e32 v7, vcc, v1, v5
318; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
319; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v7, v3, vcc
320; GCN-NEXT:    v_sub_i32_e64 v7, s[4:5], v0, v2
321; GCN-NEXT:    v_subbrev_u32_e64 v8, s[6:7], 0, v4, s[4:5]
322; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v8, v3
323; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[6:7]
324; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v7, v2
325; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
326; GCN-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[6:7]
327; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v8, v3
328; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v3, s[4:5]
329; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
330; GCN-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[6:7]
331; GCN-NEXT:    v_sub_i32_e64 v10, s[4:5], v7, v2
332; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
333; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
334; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
335; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
336; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
337; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v9
338; GCN-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
339; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
340; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v10, s[4:5]
341; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v4, s[4:5]
342; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
343; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
344; GCN-NEXT:    v_xor_b32_e32 v0, v0, v6
345; GCN-NEXT:    v_xor_b32_e32 v1, v1, v6
346; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
347; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
348; GCN-NEXT:    s_setpc_b64 s[30:31]
349;
350; GCN-IR-LABEL: v_test_srem:
351; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
352; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
353; GCN-IR-NEXT:    v_ashrrev_i32_e32 v4, 31, v1
354; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v4
355; GCN-IR-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
356; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v4
357; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
358; GCN-IR-NEXT:    v_xor_b32_e32 v2, v2, v6
359; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc
360; GCN-IR-NEXT:    v_xor_b32_e32 v3, v3, v6
361; GCN-IR-NEXT:    v_sub_i32_e32 v5, vcc, v2, v6
362; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v3, v6, vcc
363; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[5:6]
364; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
365; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v5
366; GCN-IR-NEXT:    s_or_b64 s[6:7], vcc, s[4:5]
367; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, 32, v3
368; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v6
369; GCN-IR-NEXT:    v_min_u32_e32 v3, v3, v7
370; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v0
371; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 32, v7
372; GCN-IR-NEXT:    v_ffbh_u32_e32 v8, v1
373; GCN-IR-NEXT:    v_min_u32_e32 v12, v7, v8
374; GCN-IR-NEXT:    v_sub_i32_e32 v7, vcc, v3, v12
375; GCN-IR-NEXT:    v_subb_u32_e64 v8, s[4:5], 0, 0, vcc
376; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[7:8]
377; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[4:5], 63, v[7:8]
378; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], vcc
379; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
380; GCN-IR-NEXT:    s_xor_b64 s[8:9], s[6:7], -1
381; GCN-IR-NEXT:    v_mov_b32_e32 v2, v4
382; GCN-IR-NEXT:    v_mov_b32_e32 v13, v11
383; GCN-IR-NEXT:    v_cndmask_b32_e64 v10, v1, 0, s[6:7]
384; GCN-IR-NEXT:    s_and_b64 s[4:5], s[8:9], s[4:5]
385; GCN-IR-NEXT:    v_cndmask_b32_e64 v9, v0, 0, s[6:7]
386; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
387; GCN-IR-NEXT:    s_cbranch_execz .LBB1_6
388; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
389; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, 1, v7
390; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, 0, v8, vcc
391; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[14:15], v[7:8]
392; GCN-IR-NEXT:    v_sub_i32_e64 v7, s[4:5], 63, v7
393; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[0:1], v7
394; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
395; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
396; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
397; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
398; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
399; GCN-IR-NEXT:    s_cbranch_execz .LBB1_5
400; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
401; GCN-IR-NEXT:    v_add_i32_e32 v18, vcc, -1, v5
402; GCN-IR-NEXT:    v_addc_u32_e32 v19, vcc, -1, v6, vcc
403; GCN-IR-NEXT:    v_not_b32_e32 v3, v3
404; GCN-IR-NEXT:    v_lshr_b64 v[14:15], v[0:1], v14
405; GCN-IR-NEXT:    v_not_b32_e32 v9, v11
406; GCN-IR-NEXT:    v_add_i32_e32 v11, vcc, v3, v12
407; GCN-IR-NEXT:    v_mov_b32_e32 v16, 0
408; GCN-IR-NEXT:    v_addc_u32_e32 v12, vcc, v9, v13, vcc
409; GCN-IR-NEXT:    v_mov_b32_e32 v17, 0
410; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
411; GCN-IR-NEXT:  .LBB1_3: ; %udiv-do-while
412; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
413; GCN-IR-NEXT:    v_lshl_b64 v[14:15], v[14:15], 1
414; GCN-IR-NEXT:    v_lshrrev_b32_e32 v3, 31, v8
415; GCN-IR-NEXT:    v_or_b32_e32 v3, v14, v3
416; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
417; GCN-IR-NEXT:    v_sub_i32_e32 v9, vcc, v18, v3
418; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, v19, v15, vcc
419; GCN-IR-NEXT:    v_or_b32_e32 v7, v16, v7
420; GCN-IR-NEXT:    v_add_i32_e32 v16, vcc, 1, v11
421; GCN-IR-NEXT:    v_or_b32_e32 v8, v17, v8
422; GCN-IR-NEXT:    v_ashrrev_i32_e32 v13, 31, v9
423; GCN-IR-NEXT:    v_addc_u32_e32 v17, vcc, 0, v12, vcc
424; GCN-IR-NEXT:    v_and_b32_e32 v9, 1, v13
425; GCN-IR-NEXT:    v_and_b32_e32 v20, v13, v6
426; GCN-IR-NEXT:    v_and_b32_e32 v13, v13, v5
427; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[16:17], v[11:12]
428; GCN-IR-NEXT:    v_mov_b32_e32 v11, v16
429; GCN-IR-NEXT:    v_sub_i32_e64 v14, s[4:5], v3, v13
430; GCN-IR-NEXT:    v_mov_b32_e32 v12, v17
431; GCN-IR-NEXT:    v_mov_b32_e32 v17, v10
432; GCN-IR-NEXT:    v_subb_u32_e64 v15, s[4:5], v15, v20, s[4:5]
433; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
434; GCN-IR-NEXT:    v_mov_b32_e32 v16, v9
435; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
436; GCN-IR-NEXT:    s_cbranch_execnz .LBB1_3
437; GCN-IR-NEXT:  ; %bb.4: ; %Flow
438; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
439; GCN-IR-NEXT:  .LBB1_5: ; %Flow3
440; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
441; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
442; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v8
443; GCN-IR-NEXT:    v_or_b32_e32 v9, v9, v7
444; GCN-IR-NEXT:  .LBB1_6: ; %Flow4
445; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
446; GCN-IR-NEXT:    v_mul_lo_u32 v3, v5, v10
447; GCN-IR-NEXT:    v_mul_hi_u32 v7, v5, v9
448; GCN-IR-NEXT:    v_mul_lo_u32 v6, v6, v9
449; GCN-IR-NEXT:    v_mul_lo_u32 v5, v5, v9
450; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
451; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
452; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v5
453; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
454; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v4
455; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
456; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
457; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
458; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
459  %result = srem i64 %x, %y
460  ret i64 %result
461}
462
463define amdgpu_kernel void @s_test_srem23_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
464; GCN-LABEL: s_test_srem23_64:
465; GCN:       ; %bb.0:
466; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
467; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
468; GCN-NEXT:    s_mov_b32 s7, 0xf000
469; GCN-NEXT:    s_mov_b32 s6, -1
470; GCN-NEXT:    s_waitcnt lgkmcnt(0)
471; GCN-NEXT:    s_ashr_i64 s[4:5], s[4:5], 41
472; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
473; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 41
474; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s2
475; GCN-NEXT:    s_xor_b32 s3, s2, s4
476; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
477; GCN-NEXT:    s_ashr_i32 s3, s3, 30
478; GCN-NEXT:    s_or_b32 s3, s3, 1
479; GCN-NEXT:    v_mov_b32_e32 v3, s3
480; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
481; GCN-NEXT:    v_trunc_f32_e32 v2, v2
482; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
483; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
484; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
485; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
486; GCN-NEXT:    s_mov_b32 s5, s1
487; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
488; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
489; GCN-NEXT:    s_mov_b32 s4, s0
490; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
491; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 23
492; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
493; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
494; GCN-NEXT:    s_endpgm
495;
496; GCN-IR-LABEL: s_test_srem23_64:
497; GCN-IR:       ; %bb.0:
498; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
499; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
500; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
501; GCN-IR-NEXT:    s_mov_b32 s6, -1
502; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
503; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[4:5], 41
504; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
505; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 41
506; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s2
507; GCN-IR-NEXT:    s_xor_b32 s3, s2, s4
508; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
509; GCN-IR-NEXT:    s_ashr_i32 s3, s3, 30
510; GCN-IR-NEXT:    s_or_b32 s3, s3, 1
511; GCN-IR-NEXT:    v_mov_b32_e32 v3, s3
512; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
513; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
514; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
515; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
516; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
517; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
518; GCN-IR-NEXT:    s_mov_b32 s5, s1
519; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
520; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
521; GCN-IR-NEXT:    s_mov_b32 s4, s0
522; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
523; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 23
524; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
525; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
526; GCN-IR-NEXT:    s_endpgm
527  %1 = ashr i64 %x, 41
528  %2 = ashr i64 %y, 41
529  %result = srem i64 %1, %2
530  store i64 %result, i64 addrspace(1)* %out
531  ret void
532}
533
534define amdgpu_kernel void @s_test_srem24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
535; GCN-LABEL: s_test_srem24_64:
536; GCN:       ; %bb.0:
537; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
538; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
539; GCN-NEXT:    s_mov_b32 s7, 0xf000
540; GCN-NEXT:    s_mov_b32 s6, -1
541; GCN-NEXT:    s_waitcnt lgkmcnt(0)
542; GCN-NEXT:    s_ashr_i64 s[4:5], s[4:5], 40
543; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
544; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
545; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s2
546; GCN-NEXT:    s_xor_b32 s3, s2, s4
547; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
548; GCN-NEXT:    s_ashr_i32 s3, s3, 30
549; GCN-NEXT:    s_or_b32 s3, s3, 1
550; GCN-NEXT:    v_mov_b32_e32 v3, s3
551; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
552; GCN-NEXT:    v_trunc_f32_e32 v2, v2
553; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
554; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
555; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
556; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
557; GCN-NEXT:    s_mov_b32 s5, s1
558; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
559; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
560; GCN-NEXT:    s_mov_b32 s4, s0
561; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
562; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
563; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
564; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
565; GCN-NEXT:    s_endpgm
566;
567; GCN-IR-LABEL: s_test_srem24_64:
568; GCN-IR:       ; %bb.0:
569; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
570; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
571; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
572; GCN-IR-NEXT:    s_mov_b32 s6, -1
573; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
574; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[4:5], 40
575; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
576; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
577; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s2
578; GCN-IR-NEXT:    s_xor_b32 s3, s2, s4
579; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
580; GCN-IR-NEXT:    s_ashr_i32 s3, s3, 30
581; GCN-IR-NEXT:    s_or_b32 s3, s3, 1
582; GCN-IR-NEXT:    v_mov_b32_e32 v3, s3
583; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
584; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
585; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
586; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
587; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
588; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
589; GCN-IR-NEXT:    s_mov_b32 s5, s1
590; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
591; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
592; GCN-IR-NEXT:    s_mov_b32 s4, s0
593; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
594; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
595; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
596; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
597; GCN-IR-NEXT:    s_endpgm
598  %1 = ashr i64 %x, 40
599  %2 = ashr i64 %y, 40
600  %result = srem i64 %1, %2
601  store i64 %result, i64 addrspace(1)* %out
602  ret void
603}
604
605define i64 @v_test_srem24_64(i64 %x, i64 %y) {
606; GCN-LABEL: v_test_srem24_64:
607; GCN:       ; %bb.0:
608; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
609; GCN-NEXT:    v_ashr_i64 v[2:3], v[2:3], 40
610; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
611; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
612; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
613; GCN-NEXT:    v_xor_b32_e32 v5, v0, v2
614; GCN-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
615; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v3
616; GCN-NEXT:    v_or_b32_e32 v5, 1, v5
617; GCN-NEXT:    v_mul_f32_e32 v4, v1, v4
618; GCN-NEXT:    v_trunc_f32_e32 v4, v4
619; GCN-NEXT:    v_mad_f32 v1, -v4, v3, v1
620; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
621; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
622; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
623; GCN-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
624; GCN-NEXT:    v_mul_lo_u32 v1, v1, v2
625; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
626; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
627; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
628; GCN-NEXT:    s_setpc_b64 s[30:31]
629;
630; GCN-IR-LABEL: v_test_srem24_64:
631; GCN-IR:       ; %bb.0:
632; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
633; GCN-IR-NEXT:    v_ashr_i64 v[2:3], v[2:3], 40
634; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
635; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v3, v2
636; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
637; GCN-IR-NEXT:    v_xor_b32_e32 v5, v0, v2
638; GCN-IR-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
639; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v4, v3
640; GCN-IR-NEXT:    v_or_b32_e32 v5, 1, v5
641; GCN-IR-NEXT:    v_mul_f32_e32 v4, v1, v4
642; GCN-IR-NEXT:    v_trunc_f32_e32 v4, v4
643; GCN-IR-NEXT:    v_mad_f32 v1, -v4, v3, v1
644; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v4, v4
645; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
646; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
647; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
648; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v2
649; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
650; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
651; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
652; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
653  %1 = ashr i64 %x, 40
654  %2 = ashr i64 %y, 40
655  %result = srem i64 %1, %2
656  ret i64 %result
657}
658
659define amdgpu_kernel void @s_test_srem25_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
660; GCN-LABEL: s_test_srem25_64:
661; GCN:       ; %bb.0:
662; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
663; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
664; GCN-NEXT:    s_mov_b32 s7, 0xf000
665; GCN-NEXT:    s_mov_b32 s6, -1
666; GCN-NEXT:    s_waitcnt lgkmcnt(0)
667; GCN-NEXT:    s_ashr_i64 s[4:5], s[4:5], 39
668; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
669; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 39
670; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s2
671; GCN-NEXT:    s_xor_b32 s3, s2, s4
672; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
673; GCN-NEXT:    s_ashr_i32 s3, s3, 30
674; GCN-NEXT:    s_or_b32 s3, s3, 1
675; GCN-NEXT:    v_mov_b32_e32 v3, s3
676; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
677; GCN-NEXT:    v_trunc_f32_e32 v2, v2
678; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
679; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
680; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
681; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
682; GCN-NEXT:    s_mov_b32 s5, s1
683; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
684; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
685; GCN-NEXT:    s_mov_b32 s4, s0
686; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
687; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 25
688; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
689; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
690; GCN-NEXT:    s_endpgm
691;
692; GCN-IR-LABEL: s_test_srem25_64:
693; GCN-IR:       ; %bb.0:
694; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
695; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
696; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
697; GCN-IR-NEXT:    s_mov_b32 s6, -1
698; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
699; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[4:5], 39
700; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
701; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 39
702; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s2
703; GCN-IR-NEXT:    s_xor_b32 s3, s2, s4
704; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
705; GCN-IR-NEXT:    s_ashr_i32 s3, s3, 30
706; GCN-IR-NEXT:    s_or_b32 s3, s3, 1
707; GCN-IR-NEXT:    v_mov_b32_e32 v3, s3
708; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
709; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
710; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
711; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
712; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
713; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
714; GCN-IR-NEXT:    s_mov_b32 s5, s1
715; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
716; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
717; GCN-IR-NEXT:    s_mov_b32 s4, s0
718; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
719; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 25
720; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
721; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
722; GCN-IR-NEXT:    s_endpgm
723  %1 = ashr i64 %x, 39
724  %2 = ashr i64 %y, 39
725  %result = srem i64 %1, %2
726  store i64 %result, i64 addrspace(1)* %out
727  ret void
728}
729
730define amdgpu_kernel void @s_test_srem31_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
731; GCN-LABEL: s_test_srem31_64:
732; GCN:       ; %bb.0:
733; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
734; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
735; GCN-NEXT:    s_mov_b32 s7, 0xf000
736; GCN-NEXT:    s_mov_b32 s6, -1
737; GCN-NEXT:    s_waitcnt lgkmcnt(0)
738; GCN-NEXT:    s_ashr_i64 s[4:5], s[4:5], 33
739; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
740; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 33
741; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s2
742; GCN-NEXT:    s_xor_b32 s3, s2, s4
743; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
744; GCN-NEXT:    s_ashr_i32 s3, s3, 30
745; GCN-NEXT:    s_or_b32 s3, s3, 1
746; GCN-NEXT:    v_mov_b32_e32 v3, s3
747; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
748; GCN-NEXT:    v_trunc_f32_e32 v2, v2
749; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
750; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
751; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
752; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
753; GCN-NEXT:    s_mov_b32 s5, s1
754; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
755; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
756; GCN-NEXT:    s_mov_b32 s4, s0
757; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
758; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 31
759; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
760; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
761; GCN-NEXT:    s_endpgm
762;
763; GCN-IR-LABEL: s_test_srem31_64:
764; GCN-IR:       ; %bb.0:
765; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
766; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
767; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
768; GCN-IR-NEXT:    s_mov_b32 s6, -1
769; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
770; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[4:5], 33
771; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
772; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 33
773; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s2
774; GCN-IR-NEXT:    s_xor_b32 s3, s2, s4
775; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
776; GCN-IR-NEXT:    s_ashr_i32 s3, s3, 30
777; GCN-IR-NEXT:    s_or_b32 s3, s3, 1
778; GCN-IR-NEXT:    v_mov_b32_e32 v3, s3
779; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
780; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
781; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
782; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
783; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
784; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
785; GCN-IR-NEXT:    s_mov_b32 s5, s1
786; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
787; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
788; GCN-IR-NEXT:    s_mov_b32 s4, s0
789; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
790; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 31
791; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
792; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
793; GCN-IR-NEXT:    s_endpgm
794  %1 = ashr i64 %x, 33
795  %2 = ashr i64 %y, 33
796  %result = srem i64 %1, %2
797  store i64 %result, i64 addrspace(1)* %out
798  ret void
799}
800
801; 32 known sign bits
802define amdgpu_kernel void @s_test_srem32_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
803; GCN-LABEL: s_test_srem32_64:
804; GCN:       ; %bb.0:
805; GCN-NEXT:    s_load_dword s4, s[0:1], 0xe
806; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
807; GCN-NEXT:    s_mov_b32 s7, 0xf000
808; GCN-NEXT:    s_mov_b32 s6, -1
809; GCN-NEXT:    s_waitcnt lgkmcnt(0)
810; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
811; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s3
812; GCN-NEXT:    s_xor_b32 s2, s3, s4
813; GCN-NEXT:    s_ashr_i32 s2, s2, 30
814; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
815; GCN-NEXT:    s_or_b32 s2, s2, 1
816; GCN-NEXT:    v_mov_b32_e32 v3, s2
817; GCN-NEXT:    s_mov_b32 s5, s1
818; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
819; GCN-NEXT:    v_trunc_f32_e32 v2, v2
820; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
821; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
822; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
823; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
824; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
825; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
826; GCN-NEXT:    s_mov_b32 s4, s0
827; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s3, v0
828; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
829; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
830; GCN-NEXT:    s_endpgm
831;
832; GCN-IR-LABEL: s_test_srem32_64:
833; GCN-IR:       ; %bb.0:
834; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xe
835; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
836; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
837; GCN-IR-NEXT:    s_mov_b32 s6, -1
838; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
839; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
840; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s3
841; GCN-IR-NEXT:    s_xor_b32 s2, s3, s4
842; GCN-IR-NEXT:    s_ashr_i32 s2, s2, 30
843; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
844; GCN-IR-NEXT:    s_or_b32 s2, s2, 1
845; GCN-IR-NEXT:    v_mov_b32_e32 v3, s2
846; GCN-IR-NEXT:    s_mov_b32 s5, s1
847; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
848; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
849; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
850; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
851; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
852; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
853; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
854; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
855; GCN-IR-NEXT:    s_mov_b32 s4, s0
856; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s3, v0
857; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
858; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
859; GCN-IR-NEXT:    s_endpgm
860  %1 = ashr i64 %x, 32
861  %2 = ashr i64 %y, 32
862  %result = srem i64 %1, %2
863  store i64 %result, i64 addrspace(1)* %out
864  ret void
865}
866
867; 33 known sign bits
868define amdgpu_kernel void @s_test_srem33_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
869; GCN-LABEL: s_test_srem33_64:
870; GCN:       ; %bb.0:
871; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
872; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
873; GCN-NEXT:    v_mov_b32_e32 v6, 0
874; GCN-NEXT:    s_mov_b32 s7, 0xf000
875; GCN-NEXT:    s_mov_b32 s6, -1
876; GCN-NEXT:    s_waitcnt lgkmcnt(0)
877; GCN-NEXT:    s_ashr_i64 s[2:3], s[10:11], 31
878; GCN-NEXT:    s_ashr_i64 s[4:5], s[0:1], 31
879; GCN-NEXT:    s_ashr_i32 s0, s1, 31
880; GCN-NEXT:    s_add_u32 s4, s4, s0
881; GCN-NEXT:    s_mov_b32 s1, s0
882; GCN-NEXT:    s_addc_u32 s5, s5, s0
883; GCN-NEXT:    s_xor_b64 s[12:13], s[4:5], s[0:1]
884; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
885; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
886; GCN-NEXT:    s_sub_u32 s0, 0, s12
887; GCN-NEXT:    s_subb_u32 s1, 0, s13
888; GCN-NEXT:    s_ashr_i32 s10, s11, 31
889; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
890; GCN-NEXT:    v_rcp_f32_e32 v0, v0
891; GCN-NEXT:    s_mov_b32 s11, s10
892; GCN-NEXT:    s_mov_b32 s4, s8
893; GCN-NEXT:    s_mov_b32 s5, s9
894; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
895; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
896; GCN-NEXT:    v_trunc_f32_e32 v1, v1
897; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
898; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
899; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
900; GCN-NEXT:    v_mul_lo_u32 v2, s0, v1
901; GCN-NEXT:    v_mul_hi_u32 v3, s0, v0
902; GCN-NEXT:    v_mul_lo_u32 v5, s1, v0
903; GCN-NEXT:    v_mul_lo_u32 v4, s0, v0
904; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
905; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
906; GCN-NEXT:    v_mul_hi_u32 v3, v0, v4
907; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
908; GCN-NEXT:    v_mul_hi_u32 v7, v0, v2
909; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
910; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
911; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
912; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
913; GCN-NEXT:    v_mul_lo_u32 v7, v1, v4
914; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
915; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
916; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
917; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
918; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
919; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
920; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
921; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
922; GCN-NEXT:    v_mul_lo_u32 v2, s0, v1
923; GCN-NEXT:    v_mul_hi_u32 v3, s0, v0
924; GCN-NEXT:    v_mul_lo_u32 v4, s1, v0
925; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
926; GCN-NEXT:    v_mul_lo_u32 v3, s0, v0
927; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
928; GCN-NEXT:    v_mul_lo_u32 v7, v0, v2
929; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
930; GCN-NEXT:    v_mul_hi_u32 v9, v0, v2
931; GCN-NEXT:    v_mul_hi_u32 v5, v1, v3
932; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
933; GCN-NEXT:    v_mul_hi_u32 v4, v1, v2
934; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
935; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
936; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
937; GCN-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
938; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v5, vcc
939; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
940; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
941; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
942; GCN-NEXT:    s_add_u32 s0, s2, s10
943; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
944; GCN-NEXT:    s_addc_u32 s1, s3, s10
945; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
946; GCN-NEXT:    s_xor_b64 s[14:15], s[0:1], s[10:11]
947; GCN-NEXT:    v_mul_lo_u32 v2, s14, v1
948; GCN-NEXT:    v_mul_hi_u32 v3, s14, v0
949; GCN-NEXT:    v_mul_hi_u32 v4, s14, v1
950; GCN-NEXT:    v_mul_hi_u32 v5, s15, v1
951; GCN-NEXT:    v_mul_lo_u32 v1, s15, v1
952; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
953; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
954; GCN-NEXT:    v_mul_lo_u32 v4, s15, v0
955; GCN-NEXT:    v_mul_hi_u32 v0, s15, v0
956; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
957; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
958; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v6, vcc
959; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
960; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
961; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
962; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
963; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
964; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
965; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
966; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
967; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s15, v1
968; GCN-NEXT:    v_mov_b32_e32 v3, s13
969; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s14, v0
970; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
971; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
972; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
973; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
974; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
975; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
976; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
977; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
978; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
979; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
980; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
981; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
982; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
983; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
984; GCN-NEXT:    v_mov_b32_e32 v5, s15
985; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
986; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
987; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
988; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
989; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
990; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
991; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
992; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
993; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
994; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
995; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
996; GCN-NEXT:    v_xor_b32_e32 v0, s10, v0
997; GCN-NEXT:    v_xor_b32_e32 v1, s10, v1
998; GCN-NEXT:    v_mov_b32_e32 v2, s10
999; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s10, v0
1000; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1001; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1002; GCN-NEXT:    s_endpgm
1003;
1004; GCN-IR-LABEL: s_test_srem33_64:
1005; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1006; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1007; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
1008; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1009; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[6:7], 31
1010; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 31
1011; GCN-IR-NEXT:    s_ashr_i32 s0, s7, 31
1012; GCN-IR-NEXT:    s_ashr_i32 s6, s1, 31
1013; GCN-IR-NEXT:    s_mov_b32 s1, s0
1014; GCN-IR-NEXT:    s_mov_b32 s7, s6
1015; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[2:3], s[0:1]
1016; GCN-IR-NEXT:    s_xor_b64 s[8:9], s[8:9], s[6:7]
1017; GCN-IR-NEXT:    s_sub_u32 s2, s2, s0
1018; GCN-IR-NEXT:    s_subb_u32 s3, s3, s0
1019; GCN-IR-NEXT:    s_sub_u32 s8, s8, s6
1020; GCN-IR-NEXT:    s_subb_u32 s9, s9, s6
1021; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[8:9], 0
1022; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[2:3], 0
1023; GCN-IR-NEXT:    s_mov_b64 s[6:7], 0
1024; GCN-IR-NEXT:    s_or_b64 s[16:17], s[10:11], s[12:13]
1025; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s8
1026; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s2
1027; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
1028; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s9
1029; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
1030; GCN-IR-NEXT:    s_flbit_i32_b32 s13, s3
1031; GCN-IR-NEXT:    s_min_u32 s10, s10, s11
1032; GCN-IR-NEXT:    s_min_u32 s14, s12, s13
1033; GCN-IR-NEXT:    s_sub_u32 s12, s10, s14
1034; GCN-IR-NEXT:    s_subb_u32 s13, 0, 0
1035; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[18:19], s[12:13], 63
1036; GCN-IR-NEXT:    s_mov_b32 s11, 0
1037; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[18:19]
1038; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[18:19], s[12:13], 63
1039; GCN-IR-NEXT:    s_xor_b64 s[20:21], s[16:17], -1
1040; GCN-IR-NEXT:    s_and_b64 s[18:19], s[20:21], s[18:19]
1041; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[18:19]
1042; GCN-IR-NEXT:    s_cbranch_vccz .LBB8_5
1043; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1044; GCN-IR-NEXT:    s_add_u32 s16, s12, 1
1045; GCN-IR-NEXT:    v_mov_b32_e32 v0, s12
1046; GCN-IR-NEXT:    s_addc_u32 s17, s13, 0
1047; GCN-IR-NEXT:    v_mov_b32_e32 v1, s13
1048; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[16:17], v[0:1]
1049; GCN-IR-NEXT:    s_sub_i32 s12, 63, s12
1050; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1051; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[2:3], s12
1052; GCN-IR-NEXT:    s_cbranch_vccz .LBB8_4
1053; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1054; GCN-IR-NEXT:    s_lshr_b64 s[16:17], s[2:3], s16
1055; GCN-IR-NEXT:    s_add_u32 s18, s8, -1
1056; GCN-IR-NEXT:    s_addc_u32 s19, s9, -1
1057; GCN-IR-NEXT:    s_not_b64 s[6:7], s[10:11]
1058; GCN-IR-NEXT:    s_mov_b32 s15, s11
1059; GCN-IR-NEXT:    s_add_u32 s10, s6, s14
1060; GCN-IR-NEXT:    s_addc_u32 s11, s7, s11
1061; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
1062; GCN-IR-NEXT:    s_mov_b32 s7, 0
1063; GCN-IR-NEXT:  .LBB8_3: ; %udiv-do-while
1064; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1065; GCN-IR-NEXT:    s_lshl_b64 s[16:17], s[16:17], 1
1066; GCN-IR-NEXT:    s_lshr_b32 s6, s13, 31
1067; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
1068; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[6:7]
1069; GCN-IR-NEXT:    s_or_b64 s[12:13], s[14:15], s[12:13]
1070; GCN-IR-NEXT:    s_sub_u32 s6, s18, s16
1071; GCN-IR-NEXT:    s_subb_u32 s6, s19, s17
1072; GCN-IR-NEXT:    s_ashr_i32 s14, s6, 31
1073; GCN-IR-NEXT:    s_mov_b32 s15, s14
1074; GCN-IR-NEXT:    s_and_b32 s6, s14, 1
1075; GCN-IR-NEXT:    s_and_b64 s[20:21], s[14:15], s[8:9]
1076; GCN-IR-NEXT:    s_sub_u32 s16, s16, s20
1077; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1078; GCN-IR-NEXT:    s_subb_u32 s17, s17, s21
1079; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
1080; GCN-IR-NEXT:    s_add_u32 s10, s10, 1
1081; GCN-IR-NEXT:    s_addc_u32 s11, s11, 0
1082; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
1083; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[6:7]
1084; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1085; GCN-IR-NEXT:    s_cbranch_vccz .LBB8_3
1086; GCN-IR-NEXT:  .LBB8_4: ; %Flow6
1087; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[12:13], 1
1088; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], s[10:11]
1089; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1090; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
1091; GCN-IR-NEXT:    s_branch .LBB8_6
1092; GCN-IR-NEXT:  .LBB8_5:
1093; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
1094; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[16:17]
1095; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1096; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[16:17]
1097; GCN-IR-NEXT:  .LBB8_6: ; %udiv-end
1098; GCN-IR-NEXT:    v_mul_lo_u32 v1, s8, v1
1099; GCN-IR-NEXT:    v_mul_hi_u32 v2, s8, v0
1100; GCN-IR-NEXT:    v_mul_lo_u32 v3, s9, v0
1101; GCN-IR-NEXT:    v_mul_lo_u32 v0, s8, v0
1102; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1103; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1104; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1105; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
1106; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1107; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
1108; GCN-IR-NEXT:    v_xor_b32_e32 v0, s0, v0
1109; GCN-IR-NEXT:    v_xor_b32_e32 v1, s1, v1
1110; GCN-IR-NEXT:    v_mov_b32_e32 v2, s1
1111; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
1112; GCN-IR-NEXT:    s_mov_b32 s6, -1
1113; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1114; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1115; GCN-IR-NEXT:    s_endpgm
1116  %1 = ashr i64 %x, 31
1117  %2 = ashr i64 %y, 31
1118  %result = srem i64 %1, %2
1119  store i64 %result, i64 addrspace(1)* %out
1120  ret void
1121}
1122
1123define amdgpu_kernel void @s_test_srem24_48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
1124; GCN-LABEL: s_test_srem24_48:
1125; GCN:       ; %bb.0:
1126; GCN-NEXT:    s_load_dword s2, s[0:1], 0xc
1127; GCN-NEXT:    s_load_dword s3, s[0:1], 0xe
1128; GCN-NEXT:    s_load_dword s6, s[0:1], 0xd
1129; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
1130; GCN-NEXT:    s_load_dword s0, s[0:1], 0xb
1131; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1132; GCN-NEXT:    s_sext_i32_i16 s1, s2
1133; GCN-NEXT:    s_sext_i32_i16 s2, s3
1134; GCN-NEXT:    v_mov_b32_e32 v0, s6
1135; GCN-NEXT:    v_alignbit_b32 v0, s2, v0, 24
1136; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
1137; GCN-NEXT:    v_mov_b32_e32 v2, s0
1138; GCN-NEXT:    v_alignbit_b32 v2, s1, v2, 24
1139; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
1140; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v1
1141; GCN-NEXT:    v_xor_b32_e32 v5, v2, v0
1142; GCN-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
1143; GCN-NEXT:    v_or_b32_e32 v5, 1, v5
1144; GCN-NEXT:    v_mul_f32_e32 v4, v3, v4
1145; GCN-NEXT:    v_trunc_f32_e32 v4, v4
1146; GCN-NEXT:    v_mad_f32 v3, -v4, v1, v3
1147; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
1148; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1149; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
1150; GCN-NEXT:    s_mov_b32 s7, 0xf000
1151; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
1152; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
1153; GCN-NEXT:    s_mov_b32 s6, -1
1154; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v2, v0
1155; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1156; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1157; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
1158; GCN-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
1159; GCN-NEXT:    s_endpgm
1160;
1161; GCN-IR-LABEL: s_test_srem24_48:
1162; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1163; GCN-IR-NEXT:    s_load_dword s3, s[0:1], 0xc
1164; GCN-IR-NEXT:    s_load_dword s5, s[0:1], 0xe
1165; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xb
1166; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xd
1167; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
1168; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1169; GCN-IR-NEXT:    s_sext_i32_i16 s3, s3
1170; GCN-IR-NEXT:    s_sext_i32_i16 s5, s5
1171; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[2:3], 24
1172; GCN-IR-NEXT:    s_ashr_i32 s2, s3, 31
1173; GCN-IR-NEXT:    s_ashr_i32 s10, s5, 31
1174; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[4:5], 24
1175; GCN-IR-NEXT:    s_mov_b32 s3, s2
1176; GCN-IR-NEXT:    s_mov_b32 s11, s10
1177; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[6:7], s[2:3]
1178; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[8:9], s[10:11]
1179; GCN-IR-NEXT:    s_sub_u32 s4, s4, s2
1180; GCN-IR-NEXT:    s_subb_u32 s5, s5, s2
1181; GCN-IR-NEXT:    s_sub_u32 s6, s6, s10
1182; GCN-IR-NEXT:    s_subb_u32 s7, s7, s10
1183; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
1184; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[4:5], 0
1185; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1186; GCN-IR-NEXT:    s_or_b64 s[16:17], s[10:11], s[12:13]
1187; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s6
1188; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s4
1189; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
1190; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s7
1191; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
1192; GCN-IR-NEXT:    s_flbit_i32_b32 s13, s5
1193; GCN-IR-NEXT:    s_min_u32 s10, s10, s11
1194; GCN-IR-NEXT:    s_min_u32 s14, s12, s13
1195; GCN-IR-NEXT:    s_sub_u32 s12, s10, s14
1196; GCN-IR-NEXT:    s_subb_u32 s13, 0, 0
1197; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[18:19], s[12:13], 63
1198; GCN-IR-NEXT:    s_mov_b32 s11, 0
1199; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[18:19]
1200; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[18:19], s[12:13], 63
1201; GCN-IR-NEXT:    s_xor_b64 s[20:21], s[16:17], -1
1202; GCN-IR-NEXT:    s_and_b64 s[18:19], s[20:21], s[18:19]
1203; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[18:19]
1204; GCN-IR-NEXT:    s_cbranch_vccz .LBB9_5
1205; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1206; GCN-IR-NEXT:    s_add_u32 s16, s12, 1
1207; GCN-IR-NEXT:    v_mov_b32_e32 v0, s12
1208; GCN-IR-NEXT:    s_addc_u32 s17, s13, 0
1209; GCN-IR-NEXT:    v_mov_b32_e32 v1, s13
1210; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[16:17], v[0:1]
1211; GCN-IR-NEXT:    s_sub_i32 s12, 63, s12
1212; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1213; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[4:5], s12
1214; GCN-IR-NEXT:    s_cbranch_vccz .LBB9_4
1215; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1216; GCN-IR-NEXT:    s_lshr_b64 s[16:17], s[4:5], s16
1217; GCN-IR-NEXT:    s_add_u32 s18, s6, -1
1218; GCN-IR-NEXT:    s_addc_u32 s19, s7, -1
1219; GCN-IR-NEXT:    s_not_b64 s[8:9], s[10:11]
1220; GCN-IR-NEXT:    s_mov_b32 s15, s11
1221; GCN-IR-NEXT:    s_add_u32 s10, s8, s14
1222; GCN-IR-NEXT:    s_addc_u32 s11, s9, s11
1223; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
1224; GCN-IR-NEXT:    s_mov_b32 s9, 0
1225; GCN-IR-NEXT:  .LBB9_3: ; %udiv-do-while
1226; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1227; GCN-IR-NEXT:    s_lshl_b64 s[16:17], s[16:17], 1
1228; GCN-IR-NEXT:    s_lshr_b32 s8, s13, 31
1229; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
1230; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[8:9]
1231; GCN-IR-NEXT:    s_or_b64 s[12:13], s[14:15], s[12:13]
1232; GCN-IR-NEXT:    s_sub_u32 s8, s18, s16
1233; GCN-IR-NEXT:    s_subb_u32 s8, s19, s17
1234; GCN-IR-NEXT:    s_ashr_i32 s14, s8, 31
1235; GCN-IR-NEXT:    s_mov_b32 s15, s14
1236; GCN-IR-NEXT:    s_and_b32 s8, s14, 1
1237; GCN-IR-NEXT:    s_and_b64 s[20:21], s[14:15], s[6:7]
1238; GCN-IR-NEXT:    s_sub_u32 s16, s16, s20
1239; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1240; GCN-IR-NEXT:    s_subb_u32 s17, s17, s21
1241; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
1242; GCN-IR-NEXT:    s_add_u32 s10, s10, 1
1243; GCN-IR-NEXT:    s_addc_u32 s11, s11, 0
1244; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
1245; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[8:9]
1246; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1247; GCN-IR-NEXT:    s_cbranch_vccz .LBB9_3
1248; GCN-IR-NEXT:  .LBB9_4: ; %Flow3
1249; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[12:13], 1
1250; GCN-IR-NEXT:    s_or_b64 s[8:9], s[8:9], s[10:11]
1251; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
1252; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
1253; GCN-IR-NEXT:    s_branch .LBB9_6
1254; GCN-IR-NEXT:  .LBB9_5:
1255; GCN-IR-NEXT:    v_mov_b32_e32 v0, s5
1256; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[16:17]
1257; GCN-IR-NEXT:    v_mov_b32_e32 v0, s4
1258; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[16:17]
1259; GCN-IR-NEXT:  .LBB9_6: ; %udiv-end
1260; GCN-IR-NEXT:    v_mul_lo_u32 v1, s6, v1
1261; GCN-IR-NEXT:    v_mul_hi_u32 v2, s6, v0
1262; GCN-IR-NEXT:    v_mul_lo_u32 v3, s7, v0
1263; GCN-IR-NEXT:    v_mul_lo_u32 v0, s6, v0
1264; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1265; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1266; GCN-IR-NEXT:    v_mov_b32_e32 v2, s5
1267; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
1268; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
1269; GCN-IR-NEXT:    v_xor_b32_e32 v0, s2, v0
1270; GCN-IR-NEXT:    v_xor_b32_e32 v1, s3, v1
1271; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
1272; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
1273; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1274; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1275; GCN-IR-NEXT:    s_mov_b32 s2, -1
1276; GCN-IR-NEXT:    buffer_store_short v1, off, s[0:3], 0 offset:4
1277; GCN-IR-NEXT:    buffer_store_dword v0, off, s[0:3], 0
1278; GCN-IR-NEXT:    s_endpgm
1279  %1 = ashr i48 %x, 24
1280  %2 = ashr i48 %y, 24
1281  %result = srem i48 %1, %2
1282  store i48 %result, i48 addrspace(1)* %out
1283  ret void
1284}
1285
1286define amdgpu_kernel void @s_test_srem_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1287; GCN-LABEL: s_test_srem_k_num_i64:
1288; GCN:       ; %bb.0:
1289; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1290; GCN-NEXT:    s_mov_b32 s7, 0xf000
1291; GCN-NEXT:    s_mov_b32 s6, -1
1292; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1293; GCN-NEXT:    s_ashr_i32 s4, s3, 31
1294; GCN-NEXT:    s_add_u32 s2, s2, s4
1295; GCN-NEXT:    s_mov_b32 s5, s4
1296; GCN-NEXT:    s_addc_u32 s3, s3, s4
1297; GCN-NEXT:    s_xor_b64 s[8:9], s[2:3], s[4:5]
1298; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
1299; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s9
1300; GCN-NEXT:    s_sub_u32 s2, 0, s8
1301; GCN-NEXT:    s_subb_u32 s3, 0, s9
1302; GCN-NEXT:    s_mov_b32 s4, s0
1303; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
1304; GCN-NEXT:    v_rcp_f32_e32 v0, v0
1305; GCN-NEXT:    v_mov_b32_e32 v1, 0
1306; GCN-NEXT:    s_mov_b32 s5, s1
1307; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
1308; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
1309; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1310; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
1311; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1312; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
1313; GCN-NEXT:    v_mul_lo_u32 v3, s2, v2
1314; GCN-NEXT:    v_mul_hi_u32 v4, s2, v0
1315; GCN-NEXT:    v_mul_lo_u32 v6, s3, v0
1316; GCN-NEXT:    v_mul_lo_u32 v5, s2, v0
1317; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1318; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
1319; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
1320; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
1321; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
1322; GCN-NEXT:    v_mul_hi_u32 v7, v2, v5
1323; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
1324; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
1325; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
1326; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
1327; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
1328; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1329; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v7, vcc
1330; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
1331; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1332; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
1333; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
1334; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
1335; GCN-NEXT:    v_mul_lo_u32 v3, s2, v2
1336; GCN-NEXT:    v_mul_hi_u32 v4, s2, v0
1337; GCN-NEXT:    v_mul_lo_u32 v5, s3, v0
1338; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1339; GCN-NEXT:    v_mul_lo_u32 v4, s2, v0
1340; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
1341; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
1342; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
1343; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
1344; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
1345; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
1346; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
1347; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1348; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
1349; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
1350; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
1351; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
1352; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v5, v1, vcc
1353; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1354; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1355; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
1356; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
1357; GCN-NEXT:    v_mul_lo_u32 v2, v1, 24
1358; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
1359; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
1360; GCN-NEXT:    v_mov_b32_e32 v3, s9
1361; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1362; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v1, vcc
1363; GCN-NEXT:    v_mul_lo_u32 v1, s9, v0
1364; GCN-NEXT:    v_mul_hi_u32 v2, s8, v0
1365; GCN-NEXT:    v_mul_lo_u32 v0, s8, v0
1366; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1367; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
1368; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1369; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
1370; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s8, v0
1371; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
1372; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s9, v5
1373; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
1374; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s8, v4
1375; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
1376; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
1377; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s9, v5
1378; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s8, v4
1379; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
1380; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
1381; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1382; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
1383; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
1384; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
1385; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
1386; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
1387; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1388; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v1
1389; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
1390; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
1391; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1392; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
1393; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1394; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1395; GCN-NEXT:    s_endpgm
1396;
1397; GCN-IR-LABEL: s_test_srem_k_num_i64:
1398; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1399; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1400; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1401; GCN-IR-NEXT:    s_ashr_i32 s6, s3, 31
1402; GCN-IR-NEXT:    s_mov_b32 s7, s6
1403; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[2:3], s[6:7]
1404; GCN-IR-NEXT:    s_sub_u32 s4, s2, s6
1405; GCN-IR-NEXT:    s_subb_u32 s5, s3, s6
1406; GCN-IR-NEXT:    s_flbit_i32_b32 s2, s4
1407; GCN-IR-NEXT:    s_add_i32 s2, s2, 32
1408; GCN-IR-NEXT:    s_flbit_i32_b32 s3, s5
1409; GCN-IR-NEXT:    s_min_u32 s6, s2, s3
1410; GCN-IR-NEXT:    s_add_u32 s8, s6, 0xffffffc5
1411; GCN-IR-NEXT:    s_addc_u32 s9, 0, -1
1412; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[4:5], 0
1413; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[12:13], s[8:9], 63
1414; GCN-IR-NEXT:    s_mov_b64 s[2:3], 0
1415; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
1416; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[12:13], s[8:9], 63
1417; GCN-IR-NEXT:    s_xor_b64 s[14:15], s[10:11], -1
1418; GCN-IR-NEXT:    s_and_b64 s[12:13], s[14:15], s[12:13]
1419; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
1420; GCN-IR-NEXT:    s_cbranch_vccz .LBB10_5
1421; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1422; GCN-IR-NEXT:    s_add_u32 s10, s8, 1
1423; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
1424; GCN-IR-NEXT:    s_addc_u32 s11, s9, 0
1425; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
1426; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
1427; GCN-IR-NEXT:    s_sub_i32 s7, 63, s8
1428; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1429; GCN-IR-NEXT:    s_lshl_b64 s[8:9], 24, s7
1430; GCN-IR-NEXT:    s_cbranch_vccz .LBB10_4
1431; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1432; GCN-IR-NEXT:    s_lshr_b64 s[12:13], 24, s10
1433; GCN-IR-NEXT:    s_add_u32 s14, s4, -1
1434; GCN-IR-NEXT:    s_addc_u32 s15, s5, -1
1435; GCN-IR-NEXT:    s_sub_u32 s6, 58, s6
1436; GCN-IR-NEXT:    s_subb_u32 s7, 0, 0
1437; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1438; GCN-IR-NEXT:    s_mov_b32 s3, 0
1439; GCN-IR-NEXT:  .LBB10_3: ; %udiv-do-while
1440; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1441; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
1442; GCN-IR-NEXT:    s_lshr_b32 s2, s9, 31
1443; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
1444; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[2:3]
1445; GCN-IR-NEXT:    s_or_b64 s[8:9], s[10:11], s[8:9]
1446; GCN-IR-NEXT:    s_sub_u32 s2, s14, s12
1447; GCN-IR-NEXT:    s_subb_u32 s2, s15, s13
1448; GCN-IR-NEXT:    s_ashr_i32 s10, s2, 31
1449; GCN-IR-NEXT:    s_mov_b32 s11, s10
1450; GCN-IR-NEXT:    s_and_b32 s2, s10, 1
1451; GCN-IR-NEXT:    s_and_b64 s[16:17], s[10:11], s[4:5]
1452; GCN-IR-NEXT:    s_sub_u32 s12, s12, s16
1453; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1454; GCN-IR-NEXT:    s_subb_u32 s13, s13, s17
1455; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
1456; GCN-IR-NEXT:    s_add_u32 s6, s6, 1
1457; GCN-IR-NEXT:    s_addc_u32 s7, s7, 0
1458; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1]
1459; GCN-IR-NEXT:    s_mov_b64 s[10:11], s[2:3]
1460; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1461; GCN-IR-NEXT:    s_cbranch_vccz .LBB10_3
1462; GCN-IR-NEXT:  .LBB10_4: ; %Flow5
1463; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[8:9], 1
1464; GCN-IR-NEXT:    s_or_b64 s[2:3], s[2:3], s[6:7]
1465; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1466; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
1467; GCN-IR-NEXT:    s_branch .LBB10_6
1468; GCN-IR-NEXT:  .LBB10_5:
1469; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1470; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, 24, 0, s[10:11]
1471; GCN-IR-NEXT:  .LBB10_6: ; %udiv-end
1472; GCN-IR-NEXT:    v_mul_lo_u32 v1, s4, v1
1473; GCN-IR-NEXT:    v_mul_hi_u32 v2, s4, v0
1474; GCN-IR-NEXT:    v_mul_lo_u32 v3, s5, v0
1475; GCN-IR-NEXT:    v_mul_lo_u32 v0, s4, v0
1476; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1477; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1478; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1479; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1480; GCN-IR-NEXT:    s_mov_b32 s2, -1
1481; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1482; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1483; GCN-IR-NEXT:    s_endpgm
1484  %result = srem i64 24, %x
1485  store i64 %result, i64 addrspace(1)* %out
1486  ret void
1487}
1488
1489define i64 @v_test_srem_k_num_i64(i64 %x) {
1490; GCN-LABEL: v_test_srem_k_num_i64:
1491; GCN:       ; %bb.0:
1492; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1493; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1494; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1495; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1496; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1497; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1498; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1499; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1500; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1501; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1502; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
1503; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1504; GCN-NEXT:    v_mov_b32_e32 v11, 0
1505; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1506; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1507; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1508; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1509; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1510; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1511; GCN-NEXT:    v_mul_hi_u32 v6, v4, v2
1512; GCN-NEXT:    v_mul_lo_u32 v7, v4, v3
1513; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1514; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
1515; GCN-NEXT:    v_mul_lo_u32 v7, v4, v2
1516; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1517; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
1518; GCN-NEXT:    v_mul_hi_u32 v9, v2, v7
1519; GCN-NEXT:    v_mul_hi_u32 v10, v2, v6
1520; GCN-NEXT:    v_mul_hi_u32 v12, v3, v6
1521; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1522; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1523; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
1524; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
1525; GCN-NEXT:    v_mul_hi_u32 v7, v3, v7
1526; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
1527; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v7, vcc
1528; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v11, vcc
1529; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1530; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
1531; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
1532; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v7, vcc
1533; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1534; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1535; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1536; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1537; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1538; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
1539; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
1540; GCN-NEXT:    v_mul_hi_u32 v9, v2, v4
1541; GCN-NEXT:    v_mul_hi_u32 v10, v2, v5
1542; GCN-NEXT:    v_mul_hi_u32 v7, v3, v4
1543; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1544; GCN-NEXT:    v_mul_hi_u32 v6, v3, v5
1545; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1546; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
1547; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
1548; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
1549; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
1550; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v11, vcc
1551; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1552; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
1553; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1554; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
1555; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
1556; GCN-NEXT:    v_mul_hi_u32 v2, v2, 24
1557; GCN-NEXT:    v_mul_hi_u32 v3, v3, 24
1558; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1559; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
1560; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
1561; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1562; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
1563; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1564; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
1565; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 24, v2
1566; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
1567; GCN-NEXT:    v_sub_i32_e64 v5, s[4:5], v2, v0
1568; GCN-NEXT:    v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
1569; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v1
1570; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[6:7]
1571; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v5, v0
1572; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
1573; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v6, v1
1574; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
1575; GCN-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[6:7]
1576; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v5, v0
1577; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1578; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
1579; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1580; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1581; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
1582; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v0
1583; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1584; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1585; GCN-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
1586; GCN-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[4:5]
1587; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1588; GCN-NEXT:    v_cndmask_b32_e64 v1, v6, v4, s[4:5]
1589; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1590; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1591; GCN-NEXT:    s_setpc_b64 s[30:31]
1592;
1593; GCN-IR-LABEL: v_test_srem_k_num_i64:
1594; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1595; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1596; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1597; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1598; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
1599; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1600; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1601; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1602; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1603; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1604; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1605; GCN-IR-NEXT:    s_movk_i32 s6, 0xffc5
1606; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, s6, v6
1607; GCN-IR-NEXT:    v_addc_u32_e64 v4, s[6:7], 0, -1, vcc
1608; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1609; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[3:4]
1610; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1611; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1612; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[3:4]
1613; GCN-IR-NEXT:    v_cndmask_b32_e64 v2, 24, 0, s[4:5]
1614; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1615; GCN-IR-NEXT:    v_mov_b32_e32 v5, v7
1616; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1617; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1618; GCN-IR-NEXT:    s_cbranch_execz .LBB11_6
1619; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1620; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v3
1621; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v4, vcc
1622; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v3
1623; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[8:9], v[3:4]
1624; GCN-IR-NEXT:    v_lshl_b64 v[2:3], 24, v2
1625; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1626; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1627; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1628; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1629; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1630; GCN-IR-NEXT:    s_cbranch_execz .LBB11_5
1631; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1632; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, -1, v0
1633; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, -1, v1, vcc
1634; GCN-IR-NEXT:    v_lshr_b64 v[8:9], 24, v8
1635; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, 58, v6
1636; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1637; GCN-IR-NEXT:    v_subb_u32_e32 v7, vcc, 0, v7, vcc
1638; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1639; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1640; GCN-IR-NEXT:  .LBB11_3: ; %udiv-do-while
1641; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1642; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1643; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1644; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1645; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1646; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, v12, v8
1647; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, v13, v9, vcc
1648; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1649; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1650; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1651; GCN-IR-NEXT:    v_and_b32_e32 v14, v10, v1
1652; GCN-IR-NEXT:    v_and_b32_e32 v15, v10, v0
1653; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v6
1654; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1655; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v7, vcc
1656; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7]
1657; GCN-IR-NEXT:    v_mov_b32_e32 v6, v10
1658; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v15
1659; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1660; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1661; GCN-IR-NEXT:    v_subb_u32_e64 v9, s[4:5], v9, v14, s[4:5]
1662; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1663; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1664; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1665; GCN-IR-NEXT:    s_cbranch_execnz .LBB11_3
1666; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1667; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1668; GCN-IR-NEXT:  .LBB11_5: ; %Flow3
1669; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1670; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1671; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1672; GCN-IR-NEXT:    v_or_b32_e32 v2, v4, v2
1673; GCN-IR-NEXT:  .LBB11_6: ; %Flow4
1674; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1675; GCN-IR-NEXT:    v_mul_lo_u32 v3, v0, v5
1676; GCN-IR-NEXT:    v_mul_hi_u32 v4, v0, v2
1677; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v2
1678; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, v2
1679; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1680; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
1681; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1682; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1683; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1684  %result = srem i64 24, %x
1685  ret i64 %result
1686}
1687
1688define i64 @v_test_srem_pow2_k_num_i64(i64 %x) {
1689; GCN-LABEL: v_test_srem_pow2_k_num_i64:
1690; GCN:       ; %bb.0:
1691; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1692; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1693; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1694; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1695; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1696; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1697; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1698; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1699; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1700; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1701; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
1702; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1703; GCN-NEXT:    v_mov_b32_e32 v11, 0
1704; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1705; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1706; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1707; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1708; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1709; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1710; GCN-NEXT:    v_mul_hi_u32 v6, v4, v2
1711; GCN-NEXT:    v_mul_lo_u32 v7, v4, v3
1712; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1713; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
1714; GCN-NEXT:    v_mul_lo_u32 v7, v4, v2
1715; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1716; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
1717; GCN-NEXT:    v_mul_hi_u32 v9, v2, v7
1718; GCN-NEXT:    v_mul_hi_u32 v10, v2, v6
1719; GCN-NEXT:    v_mul_hi_u32 v12, v3, v6
1720; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1721; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1722; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
1723; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
1724; GCN-NEXT:    v_mul_hi_u32 v7, v3, v7
1725; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
1726; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v7, vcc
1727; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v11, vcc
1728; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1729; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
1730; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
1731; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v7, vcc
1732; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1733; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1734; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1735; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1736; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1737; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
1738; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
1739; GCN-NEXT:    v_mul_hi_u32 v9, v2, v4
1740; GCN-NEXT:    v_mul_hi_u32 v10, v2, v5
1741; GCN-NEXT:    v_mul_hi_u32 v7, v3, v4
1742; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1743; GCN-NEXT:    v_mul_hi_u32 v6, v3, v5
1744; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1745; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
1746; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
1747; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
1748; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
1749; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v11, vcc
1750; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1751; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
1752; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1753; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v3, v5, vcc
1754; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1755; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
1756; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1757; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
1758; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1759; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
1760; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0x8000, v2
1761; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
1762; GCN-NEXT:    v_sub_i32_e64 v5, s[4:5], v2, v0
1763; GCN-NEXT:    v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
1764; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v1
1765; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[6:7]
1766; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v5, v0
1767; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
1768; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v6, v1
1769; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
1770; GCN-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[6:7]
1771; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v5, v0
1772; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1773; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
1774; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1775; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1776; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
1777; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v0
1778; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1779; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1780; GCN-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
1781; GCN-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[4:5]
1782; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1783; GCN-NEXT:    v_cndmask_b32_e64 v1, v6, v4, s[4:5]
1784; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1785; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1786; GCN-NEXT:    s_setpc_b64 s[30:31]
1787;
1788; GCN-IR-LABEL: v_test_srem_pow2_k_num_i64:
1789; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1790; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1791; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1792; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1793; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
1794; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1795; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1796; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1797; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1798; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1799; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1800; GCN-IR-NEXT:    s_movk_i32 s6, 0xffd0
1801; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, s6, v6
1802; GCN-IR-NEXT:    v_addc_u32_e64 v3, s[6:7], 0, -1, vcc
1803; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1804; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[2:3]
1805; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0x8000
1806; GCN-IR-NEXT:    v_mov_b32_e32 v4, s8
1807; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1808; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[2:3]
1809; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1810; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v4, 0, s[4:5]
1811; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1812; GCN-IR-NEXT:    v_mov_b32_e32 v5, v7
1813; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1814; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1815; GCN-IR-NEXT:    s_cbranch_execz .LBB12_6
1816; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1817; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v2
1818; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v3, vcc
1819; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[8:9], v[2:3]
1820; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v2
1821; GCN-IR-NEXT:    v_lshl_b64 v[2:3], s[8:9], v2
1822; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1823; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1824; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1825; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1826; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1827; GCN-IR-NEXT:    s_cbranch_execz .LBB12_5
1828; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1829; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, -1, v0
1830; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0x8000
1831; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, -1, v1, vcc
1832; GCN-IR-NEXT:    v_lshr_b64 v[8:9], s[4:5], v8
1833; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, 47, v6
1834; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1835; GCN-IR-NEXT:    v_subb_u32_e32 v7, vcc, 0, v7, vcc
1836; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1837; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1838; GCN-IR-NEXT:  .LBB12_3: ; %udiv-do-while
1839; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1840; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1841; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1842; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1843; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1844; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, v12, v8
1845; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, v13, v9, vcc
1846; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1847; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1848; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1849; GCN-IR-NEXT:    v_and_b32_e32 v14, v10, v1
1850; GCN-IR-NEXT:    v_and_b32_e32 v15, v10, v0
1851; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v6
1852; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1853; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v7, vcc
1854; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7]
1855; GCN-IR-NEXT:    v_mov_b32_e32 v6, v10
1856; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v15
1857; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1858; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1859; GCN-IR-NEXT:    v_subb_u32_e64 v9, s[4:5], v9, v14, s[4:5]
1860; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1861; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1862; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1863; GCN-IR-NEXT:    s_cbranch_execnz .LBB12_3
1864; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1865; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1866; GCN-IR-NEXT:  .LBB12_5: ; %Flow3
1867; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1868; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1869; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1870; GCN-IR-NEXT:    v_or_b32_e32 v4, v4, v2
1871; GCN-IR-NEXT:  .LBB12_6: ; %Flow4
1872; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1873; GCN-IR-NEXT:    v_mul_lo_u32 v2, v0, v5
1874; GCN-IR-NEXT:    v_mul_hi_u32 v3, v0, v4
1875; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v4
1876; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, v4
1877; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1878; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1879; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1880; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1881; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1882  %result = srem i64 32768, %x
1883  ret i64 %result
1884}
1885
1886define i64 @v_test_srem_pow2_k_den_i64(i64 %x) {
1887; GCN-LABEL: v_test_srem_pow2_k_den_i64:
1888; GCN:       ; %bb.0:
1889; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1890; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1891; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1892; GCN-NEXT:    v_add_i32_e32 v2, vcc, v0, v2
1893; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
1894; GCN-NEXT:    v_and_b32_e32 v2, 0xffff8000, v2
1895; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1896; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1897; GCN-NEXT:    s_setpc_b64 s[30:31]
1898;
1899; GCN-IR-LABEL: v_test_srem_pow2_k_den_i64:
1900; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1901; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1902; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1903; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1904; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
1905; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1906; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1907; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v0
1908; GCN-IR-NEXT:    v_add_i32_e64 v3, s[4:5], 32, v3
1909; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v1
1910; GCN-IR-NEXT:    v_min_u32_e32 v8, v3, v4
1911; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 48, v8
1912; GCN-IR-NEXT:    v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5]
1913; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1914; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
1915; GCN-IR-NEXT:    v_mov_b32_e32 v3, v2
1916; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1917; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1918; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1919; GCN-IR-NEXT:    v_cndmask_b32_e64 v7, v1, 0, s[4:5]
1920; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v0, 0, s[4:5]
1921; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1922; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1923; GCN-IR-NEXT:    s_cbranch_execz .LBB13_6
1924; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1925; GCN-IR-NEXT:    v_add_i32_e32 v9, vcc, 1, v4
1926; GCN-IR-NEXT:    v_addc_u32_e32 v10, vcc, 0, v5, vcc
1927; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[9:10], v[4:5]
1928; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v4
1929; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[0:1], v4
1930; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1931; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1932; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1933; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1934; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1935; GCN-IR-NEXT:    s_cbranch_execz .LBB13_5
1936; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1937; GCN-IR-NEXT:    v_lshr_b64 v[10:11], v[0:1], v9
1938; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 0xffffffcf, v8
1939; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1940; GCN-IR-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, -1, vcc
1941; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1942; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1943; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
1944; GCN-IR-NEXT:  .LBB13_3: ; %udiv-do-while
1945; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1946; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
1947; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
1948; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v6
1949; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
1950; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, s12, v10
1951; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, 0, v11, vcc
1952; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
1953; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v6
1954; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v12
1955; GCN-IR-NEXT:    v_and_b32_e32 v14, 0x8000, v12
1956; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
1957; GCN-IR-NEXT:    v_or_b32_e32 v5, v13, v5
1958; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
1959; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
1960; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
1961; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v14
1962; GCN-IR-NEXT:    v_mov_b32_e32 v9, v13
1963; GCN-IR-NEXT:    v_mov_b32_e32 v13, v7
1964; GCN-IR-NEXT:    v_subbrev_u32_e64 v11, s[4:5], 0, v11, s[4:5]
1965; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1966; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
1967; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1968; GCN-IR-NEXT:    s_cbranch_execnz .LBB13_3
1969; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1970; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1971; GCN-IR-NEXT:  .LBB13_5: ; %Flow3
1972; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1973; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
1974; GCN-IR-NEXT:    v_or_b32_e32 v7, v7, v5
1975; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v4
1976; GCN-IR-NEXT:  .LBB13_6: ; %Flow4
1977; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1978; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[6:7], 15
1979; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
1980; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
1981; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1982; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v3
1983; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1984; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1985; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1986  %result = srem i64 %x, 32768
1987  ret i64 %result
1988}
1989
1990define amdgpu_kernel void @s_test_srem24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1991; GCN-LABEL: s_test_srem24_k_num_i64:
1992; GCN:       ; %bb.0:
1993; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1994; GCN-NEXT:    s_mov_b32 s6, 0x41c00000
1995; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1996; GCN-NEXT:    s_ashr_i64 s[4:5], s[2:3], 40
1997; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
1998; GCN-NEXT:    s_ashr_i32 s5, s4, 30
1999; GCN-NEXT:    s_or_b32 s5, s5, 1
2000; GCN-NEXT:    v_mov_b32_e32 v3, s5
2001; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
2002; GCN-NEXT:    s_mov_b32 s3, 0xf000
2003; GCN-NEXT:    s_mov_b32 s2, -1
2004; GCN-NEXT:    v_mul_f32_e32 v1, s6, v1
2005; GCN-NEXT:    v_trunc_f32_e32 v1, v1
2006; GCN-NEXT:    v_mad_f32 v2, -v1, v0, s6
2007; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
2008; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
2009; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
2010; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
2011; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
2012; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2013; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2014; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2015; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2016; GCN-NEXT:    s_endpgm
2017;
2018; GCN-IR-LABEL: s_test_srem24_k_num_i64:
2019; GCN-IR:       ; %bb.0:
2020; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
2021; GCN-IR-NEXT:    s_mov_b32 s6, 0x41c00000
2022; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
2023; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[2:3], 40
2024; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
2025; GCN-IR-NEXT:    s_ashr_i32 s5, s4, 30
2026; GCN-IR-NEXT:    s_or_b32 s5, s5, 1
2027; GCN-IR-NEXT:    v_mov_b32_e32 v3, s5
2028; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
2029; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
2030; GCN-IR-NEXT:    s_mov_b32 s2, -1
2031; GCN-IR-NEXT:    v_mul_f32_e32 v1, s6, v1
2032; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
2033; GCN-IR-NEXT:    v_mad_f32 v2, -v1, v0, s6
2034; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
2035; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
2036; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
2037; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
2038; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
2039; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2040; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2041; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2042; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2043; GCN-IR-NEXT:    s_endpgm
2044  %x.shr = ashr i64 %x, 40
2045  %result = srem i64 24, %x.shr
2046  store i64 %result, i64 addrspace(1)* %out
2047  ret void
2048}
2049
2050define amdgpu_kernel void @s_test_srem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
2051; GCN-LABEL: s_test_srem24_k_den_i64:
2052; GCN:       ; %bb.0:
2053; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
2054; GCN-NEXT:    s_mov_b32 s4, 0x46b6fe00
2055; GCN-NEXT:    s_mov_b32 s7, 0xf000
2056; GCN-NEXT:    s_mov_b32 s6, -1
2057; GCN-NEXT:    s_waitcnt lgkmcnt(0)
2058; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
2059; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s2
2060; GCN-NEXT:    s_ashr_i32 s3, s2, 30
2061; GCN-NEXT:    s_or_b32 s3, s3, 1
2062; GCN-NEXT:    v_mov_b32_e32 v1, s3
2063; GCN-NEXT:    v_mul_f32_e32 v2, 0x38331158, v0
2064; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2065; GCN-NEXT:    v_mad_f32 v0, -v2, s4, v0
2066; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2067; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
2068; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
2069; GCN-NEXT:    s_movk_i32 s3, 0x5b7f
2070; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
2071; GCN-NEXT:    v_mul_lo_u32 v0, v0, s3
2072; GCN-NEXT:    s_mov_b32 s4, s0
2073; GCN-NEXT:    s_mov_b32 s5, s1
2074; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
2075; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2076; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2077; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
2078; GCN-NEXT:    s_endpgm
2079;
2080; GCN-IR-LABEL: s_test_srem24_k_den_i64:
2081; GCN-IR:       ; %bb.0:
2082; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
2083; GCN-IR-NEXT:    s_mov_b32 s4, 0x46b6fe00
2084; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
2085; GCN-IR-NEXT:    s_mov_b32 s6, -1
2086; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
2087; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
2088; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s2
2089; GCN-IR-NEXT:    s_ashr_i32 s3, s2, 30
2090; GCN-IR-NEXT:    s_or_b32 s3, s3, 1
2091; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
2092; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x38331158, v0
2093; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2094; GCN-IR-NEXT:    v_mad_f32 v0, -v2, s4, v0
2095; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2096; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
2097; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
2098; GCN-IR-NEXT:    s_movk_i32 s3, 0x5b7f
2099; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
2100; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s3
2101; GCN-IR-NEXT:    s_mov_b32 s4, s0
2102; GCN-IR-NEXT:    s_mov_b32 s5, s1
2103; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
2104; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2105; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2106; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
2107; GCN-IR-NEXT:    s_endpgm
2108  %x.shr = ashr i64 %x, 40
2109  %result = srem i64 %x.shr, 23423
2110  store i64 %result, i64 addrspace(1)* %out
2111  ret void
2112}
2113
2114define i64 @v_test_srem24_k_num_i64(i64 %x) {
2115; GCN-LABEL: v_test_srem24_k_num_i64:
2116; GCN:       ; %bb.0:
2117; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2118; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2119; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
2120; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
2121; GCN-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2122; GCN-NEXT:    v_or_b32_e32 v3, 1, v3
2123; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2124; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
2125; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2126; GCN-NEXT:    v_mad_f32 v4, -v2, v1, s4
2127; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2128; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2129; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2130; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2131; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
2132; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2133; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2134; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2135; GCN-NEXT:    s_setpc_b64 s[30:31]
2136;
2137; GCN-IR-LABEL: v_test_srem24_k_num_i64:
2138; GCN-IR:       ; %bb.0:
2139; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2140; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2141; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
2142; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2143; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2144; GCN-IR-NEXT:    v_or_b32_e32 v3, 1, v3
2145; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2146; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
2147; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2148; GCN-IR-NEXT:    v_mad_f32 v4, -v2, v1, s4
2149; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2150; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2151; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2152; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2153; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
2154; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2155; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2156; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2157; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2158  %x.shr = ashr i64 %x, 40
2159  %result = srem i64 24, %x.shr
2160  ret i64 %result
2161}
2162
2163define i64 @v_test_srem24_pow2_k_num_i64(i64 %x) {
2164; GCN-LABEL: v_test_srem24_pow2_k_num_i64:
2165; GCN:       ; %bb.0:
2166; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2167; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2168; GCN-NEXT:    s_mov_b32 s4, 0x47000000
2169; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
2170; GCN-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2171; GCN-NEXT:    v_or_b32_e32 v3, 1, v3
2172; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2173; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
2174; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2175; GCN-NEXT:    v_mad_f32 v4, -v2, v1, s4
2176; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2177; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2178; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2179; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2180; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
2181; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
2182; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2183; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2184; GCN-NEXT:    s_setpc_b64 s[30:31]
2185;
2186; GCN-IR-LABEL: v_test_srem24_pow2_k_num_i64:
2187; GCN-IR:       ; %bb.0:
2188; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2189; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2190; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2191; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2192; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2193; GCN-IR-NEXT:    v_or_b32_e32 v3, 1, v3
2194; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2195; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
2196; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2197; GCN-IR-NEXT:    v_mad_f32 v4, -v2, v1, s4
2198; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2199; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2200; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2201; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2202; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
2203; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
2204; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2205; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2206; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2207  %x.shr = ashr i64 %x, 40
2208  %result = srem i64 32768, %x.shr
2209  ret i64 %result
2210}
2211
2212define i64 @v_test_srem24_pow2_k_den_i64(i64 %x) {
2213; GCN-LABEL: v_test_srem24_pow2_k_den_i64:
2214; GCN:       ; %bb.0:
2215; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2216; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2217; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v1
2218; GCN-NEXT:    v_add_i32_e32 v2, vcc, v0, v2
2219; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
2220; GCN-NEXT:    v_and_b32_e32 v2, 0xffff8000, v2
2221; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
2222; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
2223; GCN-NEXT:    s_setpc_b64 s[30:31]
2224;
2225; GCN-IR-LABEL: v_test_srem24_pow2_k_den_i64:
2226; GCN-IR:       ; %bb.0:
2227; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2228; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2229; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2230; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2231; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 30, v0
2232; GCN-IR-NEXT:    v_or_b32_e32 v2, 1, v2
2233; GCN-IR-NEXT:    v_mul_f32_e32 v3, 0x38000000, v1
2234; GCN-IR-NEXT:    v_trunc_f32_e32 v3, v3
2235; GCN-IR-NEXT:    v_mad_f32 v1, -v3, s4, v1
2236; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v3
2237; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
2238; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
2239; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
2240; GCN-IR-NEXT:    v_lshlrev_b32_e32 v1, 15, v1
2241; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
2242; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2243; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2244; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2245  %x.shr = ashr i64 %x, 40
2246  %result = srem i64 %x.shr, 32768
2247  ret i64 %result
2248}
2249