1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_srem(i64 addrspace(1)* %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_srem:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
9; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
10; GCN-NEXT:    s_mov_b32 s7, 0xf000
11; GCN-NEXT:    s_mov_b32 s6, -1
12; GCN-NEXT:    s_waitcnt lgkmcnt(0)
13; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
14; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
15; GCN-NEXT:    s_sub_u32 s2, 0, s12
16; GCN-NEXT:    s_subb_u32 s3, 0, s13
17; GCN-NEXT:    s_mov_b32 s4, s8
18; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
19; GCN-NEXT:    v_rcp_f32_e32 v0, v0
20; GCN-NEXT:    s_mov_b32 s5, s9
21; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
22; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
23; GCN-NEXT:    v_trunc_f32_e32 v1, v1
24; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
25; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
26; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
27; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
28; GCN-NEXT:    v_mul_lo_u32 v2, s2, v1
29; GCN-NEXT:    v_mul_lo_u32 v5, s3, v0
30; GCN-NEXT:    v_mul_lo_u32 v4, s2, v0
31; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
32; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
33; GCN-NEXT:    v_mul_hi_u32 v3, v0, v4
34; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
35; GCN-NEXT:    v_mul_hi_u32 v7, v0, v2
36; GCN-NEXT:    v_mul_hi_u32 v6, v1, v4
37; GCN-NEXT:    v_mul_lo_u32 v4, v1, v4
38; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
39; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
40; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
41; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
42; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
43; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v6, vcc
44; GCN-NEXT:    v_mov_b32_e32 v4, 0
45; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v4, vcc
46; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
47; GCN-NEXT:    v_mov_b32_e32 v6, 0
48; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
49; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v6, v5, vcc
50; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
51; GCN-NEXT:    v_mul_lo_u32 v5, s2, v2
52; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
53; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
54; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
55; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
56; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
57; GCN-NEXT:    v_mul_lo_u32 v10, v0, v5
58; GCN-NEXT:    v_mul_hi_u32 v12, v0, v5
59; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
60; GCN-NEXT:    v_mul_hi_u32 v9, v2, v7
61; GCN-NEXT:    v_mul_lo_u32 v7, v2, v7
62; GCN-NEXT:    v_mul_hi_u32 v8, v2, v5
63; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
64; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
65; GCN-NEXT:    v_mul_lo_u32 v2, v2, v5
66; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
67; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
68; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v4, vcc
69; GCN-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
70; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v6, v5, vcc
71; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
72; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[0:1]
73; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
74; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
75; GCN-NEXT:    v_mul_lo_u32 v2, s10, v1
76; GCN-NEXT:    v_mul_hi_u32 v3, s10, v0
77; GCN-NEXT:    v_mul_hi_u32 v5, s10, v1
78; GCN-NEXT:    v_mul_hi_u32 v7, s11, v1
79; GCN-NEXT:    v_mul_lo_u32 v1, s11, v1
80; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
81; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
82; GCN-NEXT:    v_mul_lo_u32 v5, s11, v0
83; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
84; GCN-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
85; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
86; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v7, v4, vcc
87; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
88; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
89; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
90; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
91; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
92; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
93; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
94; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
95; GCN-NEXT:    v_sub_i32_e64 v0, s[0:1], s10, v0
96; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s11, v1
97; GCN-NEXT:    v_mov_b32_e32 v3, s13
98; GCN-NEXT:    v_subb_u32_e64 v2, vcc, v2, v3, s[0:1]
99; GCN-NEXT:    v_subrev_i32_e64 v4, s[2:3], s12, v0
100; GCN-NEXT:    v_subbrev_u32_e64 v5, vcc, 0, v2, s[2:3]
101; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v5
102; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
103; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v4
104; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
105; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v5
106; GCN-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc
107; GCN-NEXT:    v_subb_u32_e64 v2, vcc, v2, v3, s[2:3]
108; GCN-NEXT:    v_subrev_i32_e32 v3, vcc, s12, v4
109; GCN-NEXT:    v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
110; GCN-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v6
111; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[2:3]
112; GCN-NEXT:    v_mov_b32_e32 v5, s11
113; GCN-NEXT:    v_subb_u32_e64 v1, vcc, v5, v1, s[0:1]
114; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
115; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
116; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
117; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
118; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
119; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
120; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
121; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
122; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[2:3]
123; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
124; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
125; GCN-NEXT:    s_endpgm
126;
127; GCN-IR-LABEL: s_test_srem:
128; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
129; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
130; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
131; GCN-IR-NEXT:    s_mov_b64 s[2:3], 0
132; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
133; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
134; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[0:1], 0
135; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s0
136; GCN-IR-NEXT:    s_add_i32 s14, s12, 32
137; GCN-IR-NEXT:    s_or_b64 s[12:13], s[8:9], s[10:11]
138; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s1
139; GCN-IR-NEXT:    s_cmp_eq_u32 s1, 0
140; GCN-IR-NEXT:    s_cselect_b32 s10, s14, s8
141; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s6
142; GCN-IR-NEXT:    s_add_i32 s8, s8, 32
143; GCN-IR-NEXT:    s_flbit_i32_b32 s9, s7
144; GCN-IR-NEXT:    s_cmp_eq_u32 s7, 0
145; GCN-IR-NEXT:    s_cselect_b32 s14, s8, s9
146; GCN-IR-NEXT:    s_sub_u32 s8, s10, s14
147; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
148; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[16:17], s[8:9], 63
149; GCN-IR-NEXT:    s_mov_b32 s11, 0
150; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[16:17]
151; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[16:17], s[8:9], 63
152; GCN-IR-NEXT:    s_xor_b64 s[18:19], s[12:13], -1
153; GCN-IR-NEXT:    s_and_b64 s[16:17], s[18:19], s[16:17]
154; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[16:17]
155; GCN-IR-NEXT:    s_cbranch_vccz BB0_5
156; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
157; GCN-IR-NEXT:    s_add_u32 s16, s8, 1
158; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
159; GCN-IR-NEXT:    s_addc_u32 s17, s9, 0
160; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
161; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[16:17], v[0:1]
162; GCN-IR-NEXT:    s_sub_i32 s8, 63, s8
163; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
164; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[6:7], s8
165; GCN-IR-NEXT:    s_cbranch_vccz BB0_4
166; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
167; GCN-IR-NEXT:    s_lshr_b64 s[16:17], s[6:7], s16
168; GCN-IR-NEXT:    s_add_u32 s8, s0, -1
169; GCN-IR-NEXT:    s_addc_u32 s9, s1, -1
170; GCN-IR-NEXT:    s_not_b64 s[2:3], s[10:11]
171; GCN-IR-NEXT:    s_mov_b32 s15, s11
172; GCN-IR-NEXT:    s_add_u32 s10, s2, s14
173; GCN-IR-NEXT:    s_addc_u32 s11, s3, s11
174; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
175; GCN-IR-NEXT:    s_mov_b32 s3, 0
176; GCN-IR-NEXT:  BB0_3: ; %udiv-do-while
177; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
178; GCN-IR-NEXT:    s_lshr_b32 s2, s13, 31
179; GCN-IR-NEXT:    s_lshl_b64 s[16:17], s[16:17], 1
180; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
181; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[2:3]
182; GCN-IR-NEXT:    s_or_b64 s[12:13], s[14:15], s[12:13]
183; GCN-IR-NEXT:    s_sub_u32 s2, s8, s16
184; GCN-IR-NEXT:    s_subb_u32 s2, s9, s17
185; GCN-IR-NEXT:    s_ashr_i32 s14, s2, 31
186; GCN-IR-NEXT:    s_mov_b32 s15, s14
187; GCN-IR-NEXT:    s_and_b32 s2, s14, 1
188; GCN-IR-NEXT:    s_and_b64 s[18:19], s[14:15], s[0:1]
189; GCN-IR-NEXT:    s_sub_u32 s16, s16, s18
190; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
191; GCN-IR-NEXT:    s_subb_u32 s17, s17, s19
192; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
193; GCN-IR-NEXT:    s_add_u32 s10, s10, 1
194; GCN-IR-NEXT:    s_addc_u32 s11, s11, 0
195; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
196; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[2:3]
197; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
198; GCN-IR-NEXT:    s_cbranch_vccz BB0_3
199; GCN-IR-NEXT:  BB0_4: ; %Flow6
200; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[12:13], 1
201; GCN-IR-NEXT:    s_or_b64 s[2:3], s[2:3], s[8:9]
202; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
203; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
204; GCN-IR-NEXT:    s_branch BB0_6
205; GCN-IR-NEXT:  BB0_5:
206; GCN-IR-NEXT:    v_mov_b32_e32 v0, s7
207; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[12:13]
208; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
209; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[12:13]
210; GCN-IR-NEXT:  BB0_6: ; %udiv-end
211; GCN-IR-NEXT:    v_mul_lo_u32 v1, s0, v1
212; GCN-IR-NEXT:    v_mul_hi_u32 v2, s0, v0
213; GCN-IR-NEXT:    v_mul_lo_u32 v3, s1, v0
214; GCN-IR-NEXT:    v_mul_lo_u32 v0, s0, v0
215; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
216; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
217; GCN-IR-NEXT:    v_mov_b32_e32 v2, s7
218; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
219; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
220; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
221; GCN-IR-NEXT:    s_mov_b32 s6, -1
222; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
223; GCN-IR-NEXT:    s_endpgm
224  %result = urem i64 %x, %y
225  store i64 %result, i64 addrspace(1)* %out
226  ret void
227}
228
229define i64 @v_test_srem(i64 %x, i64 %y) {
230; GCN-LABEL: v_test_srem:
231; GCN:       ; %bb.0:
232; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
233; GCN-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
234; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
235; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
236; GCN-NEXT:    v_xor_b32_e32 v3, v3, v4
237; GCN-NEXT:    v_xor_b32_e32 v2, v2, v4
238; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v2
239; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v3
240; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v2
241; GCN-NEXT:    v_subb_u32_e32 v7, vcc, 0, v3, vcc
242; GCN-NEXT:    v_mov_b32_e32 v14, 0
243; GCN-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
244; GCN-NEXT:    v_rcp_f32_e32 v4, v4
245; GCN-NEXT:    v_mov_b32_e32 v13, 0
246; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
247; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
248; GCN-NEXT:    v_trunc_f32_e32 v5, v5
249; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
250; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
251; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
252; GCN-NEXT:    v_mul_hi_u32 v8, v6, v4
253; GCN-NEXT:    v_mul_lo_u32 v9, v6, v5
254; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
255; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
256; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
257; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
258; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
259; GCN-NEXT:    v_mul_hi_u32 v10, v4, v8
260; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
261; GCN-NEXT:    v_mul_hi_u32 v15, v5, v8
262; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
263; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
264; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
265; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
266; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v10, vcc
267; GCN-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
268; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v10, v9, vcc
269; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v15, v13, vcc
270; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
271; GCN-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v8
272; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v10, vcc
273; GCN-NEXT:    v_addc_u32_e64 v8, vcc, v5, v9, s[4:5]
274; GCN-NEXT:    v_mul_lo_u32 v10, v6, v8
275; GCN-NEXT:    v_mul_hi_u32 v11, v6, v4
276; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
277; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
278; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
279; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
280; GCN-NEXT:    v_mul_lo_u32 v12, v4, v7
281; GCN-NEXT:    v_mul_hi_u32 v15, v4, v6
282; GCN-NEXT:    v_mul_hi_u32 v16, v4, v7
283; GCN-NEXT:    v_mul_hi_u32 v11, v8, v6
284; GCN-NEXT:    v_mul_lo_u32 v6, v8, v6
285; GCN-NEXT:    v_add_i32_e32 v12, vcc, v15, v12
286; GCN-NEXT:    v_mul_hi_u32 v10, v8, v7
287; GCN-NEXT:    v_addc_u32_e32 v15, vcc, v14, v16, vcc
288; GCN-NEXT:    v_mul_lo_u32 v7, v8, v7
289; GCN-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
290; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v15, v11, vcc
291; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v13, vcc
292; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
293; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v14, v8, vcc
294; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
295; GCN-NEXT:    v_addc_u32_e64 v5, vcc, v5, v7, s[4:5]
296; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
297; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
298; GCN-NEXT:    v_ashrrev_i32_e32 v6, 31, v1
299; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
300; GCN-NEXT:    v_xor_b32_e32 v0, v0, v6
301; GCN-NEXT:    v_mul_lo_u32 v7, v0, v5
302; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
303; GCN-NEXT:    v_mul_hi_u32 v9, v0, v5
304; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v6, vcc
305; GCN-NEXT:    v_xor_b32_e32 v1, v1, v6
306; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
307; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v14, v9, vcc
308; GCN-NEXT:    v_mul_lo_u32 v9, v1, v4
309; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
310; GCN-NEXT:    v_mul_hi_u32 v10, v1, v5
311; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
312; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
313; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
314; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v10, v13, vcc
315; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
316; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v14, v7, vcc
317; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
318; GCN-NEXT:    v_mul_hi_u32 v7, v2, v4
319; GCN-NEXT:    v_mul_lo_u32 v8, v3, v4
320; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
321; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
322; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
323; GCN-NEXT:    v_sub_i32_e32 v7, vcc, v1, v5
324; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
325; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v7, v3, vcc
326; GCN-NEXT:    v_sub_i32_e64 v7, s[4:5], v0, v2
327; GCN-NEXT:    v_subbrev_u32_e64 v8, s[6:7], 0, v4, s[4:5]
328; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v8, v3
329; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
330; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[6:7]
331; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v7, v2
332; GCN-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[6:7]
333; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v8, v3
334; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
335; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v3, s[4:5]
336; GCN-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[6:7]
337; GCN-NEXT:    v_sub_i32_e64 v10, s[4:5], v7, v2
338; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
339; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
340; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
341; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
342; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
343; GCN-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
344; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v9
345; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
346; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v10, s[4:5]
347; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
348; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v4, s[4:5]
349; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
350; GCN-NEXT:    v_xor_b32_e32 v0, v0, v6
351; GCN-NEXT:    v_xor_b32_e32 v1, v1, v6
352; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
353; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
354; GCN-NEXT:    s_setpc_b64 s[30:31]
355;
356; GCN-IR-LABEL: v_test_srem:
357; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
358; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
359; GCN-IR-NEXT:    v_ashrrev_i32_e32 v4, 31, v1
360; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v4
361; GCN-IR-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
362; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v4
363; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
364; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc
365; GCN-IR-NEXT:    v_xor_b32_e32 v2, v2, v6
366; GCN-IR-NEXT:    v_sub_i32_e32 v5, vcc, v2, v6
367; GCN-IR-NEXT:    v_xor_b32_e32 v3, v3, v6
368; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v3, v6, vcc
369; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[5:6]
370; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
371; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v5
372; GCN-IR-NEXT:    s_or_b64 s[6:7], vcc, s[4:5]
373; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, 32, v3
374; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v6
375; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v6
376; GCN-IR-NEXT:    v_cndmask_b32_e32 v12, v7, v3, vcc
377; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v0
378; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, 32, v3
379; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v1
380; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
381; GCN-IR-NEXT:    v_cndmask_b32_e32 v14, v7, v3, vcc
382; GCN-IR-NEXT:    v_sub_i32_e32 v7, vcc, v12, v14
383; GCN-IR-NEXT:    v_subb_u32_e64 v8, s[4:5], 0, 0, vcc
384; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[7:8]
385; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[4:5], 63, v[7:8]
386; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], vcc
387; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
388; GCN-IR-NEXT:    s_xor_b64 s[8:9], s[6:7], -1
389; GCN-IR-NEXT:    v_mov_b32_e32 v2, v4
390; GCN-IR-NEXT:    v_mov_b32_e32 v15, v13
391; GCN-IR-NEXT:    v_cndmask_b32_e64 v3, v1, 0, s[6:7]
392; GCN-IR-NEXT:    s_and_b64 s[4:5], s[8:9], s[4:5]
393; GCN-IR-NEXT:    v_cndmask_b32_e64 v9, v0, 0, s[6:7]
394; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
395; GCN-IR-NEXT:    s_cbranch_execz BB1_6
396; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
397; GCN-IR-NEXT:    v_add_i32_e32 v9, vcc, 1, v7
398; GCN-IR-NEXT:    v_addc_u32_e32 v10, vcc, 0, v8, vcc
399; GCN-IR-NEXT:    v_sub_i32_e64 v3, s[4:5], 63, v7
400; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[9:10], v[7:8]
401; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
402; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[0:1], v3
403; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
404; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
405; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
406; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
407; GCN-IR-NEXT:    s_cbranch_execz BB1_5
408; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
409; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, -1, v5
410; GCN-IR-NEXT:    v_lshr_b64 v[16:17], v[0:1], v9
411; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, -1, v6, vcc
412; GCN-IR-NEXT:    v_not_b32_e32 v10, v12
413; GCN-IR-NEXT:    v_not_b32_e32 v11, v13
414; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, v10, v14
415; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, v11, v15, vcc
416; GCN-IR-NEXT:    v_mov_b32_e32 v14, 0
417; GCN-IR-NEXT:    v_mov_b32_e32 v15, 0
418; GCN-IR-NEXT:  BB1_3: ; %udiv-do-while
419; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
420; GCN-IR-NEXT:    v_lshl_b64 v[16:17], v[16:17], 1
421; GCN-IR-NEXT:    v_lshrrev_b32_e32 v10, 31, v8
422; GCN-IR-NEXT:    v_or_b32_e32 v16, v16, v10
423; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
424; GCN-IR-NEXT:    v_sub_i32_e32 v10, vcc, v3, v16
425; GCN-IR-NEXT:    v_subb_u32_e32 v10, vcc, v9, v17, vcc
426; GCN-IR-NEXT:    v_or_b32_e32 v7, v14, v7
427; GCN-IR-NEXT:    v_ashrrev_i32_e32 v14, 31, v10
428; GCN-IR-NEXT:    v_and_b32_e32 v19, v14, v5
429; GCN-IR-NEXT:    v_and_b32_e32 v10, 1, v14
430; GCN-IR-NEXT:    v_and_b32_e32 v18, v14, v6
431; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, 1, v12
432; GCN-IR-NEXT:    v_or_b32_e32 v8, v15, v8
433; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, 0, v13, vcc
434; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[14:15], v[12:13]
435; GCN-IR-NEXT:    v_mov_b32_e32 v12, v14
436; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
437; GCN-IR-NEXT:    v_sub_i32_e64 v16, s[4:5], v16, v19
438; GCN-IR-NEXT:    v_mov_b32_e32 v13, v15
439; GCN-IR-NEXT:    v_mov_b32_e32 v15, v11
440; GCN-IR-NEXT:    v_subb_u32_e64 v17, s[4:5], v17, v18, s[4:5]
441; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
442; GCN-IR-NEXT:    v_mov_b32_e32 v14, v10
443; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
444; GCN-IR-NEXT:    s_cbranch_execnz BB1_3
445; GCN-IR-NEXT:  ; %bb.4: ; %Flow
446; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
447; GCN-IR-NEXT:  BB1_5: ; %Flow3
448; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
449; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
450; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v8
451; GCN-IR-NEXT:    v_or_b32_e32 v9, v10, v7
452; GCN-IR-NEXT:  BB1_6: ; %Flow4
453; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
454; GCN-IR-NEXT:    v_mul_lo_u32 v3, v5, v3
455; GCN-IR-NEXT:    v_mul_hi_u32 v7, v5, v9
456; GCN-IR-NEXT:    v_mul_lo_u32 v6, v6, v9
457; GCN-IR-NEXT:    v_mul_lo_u32 v5, v5, v9
458; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
459; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
460; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v5
461; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
462; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v4
463; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
464; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
465; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
466; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
467  %result = srem i64 %x, %y
468  ret i64 %result
469}
470
471define amdgpu_kernel void @s_test_srem23_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
472; GCN-LABEL: s_test_srem23_64:
473; GCN:       ; %bb.0:
474; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
475; GCN-NEXT:    s_load_dword s1, s[0:1], 0xe
476; GCN-NEXT:    s_mov_b32 s3, 0xf000
477; GCN-NEXT:    s_mov_b32 s2, -1
478; GCN-NEXT:    s_waitcnt lgkmcnt(0)
479; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 41
480; GCN-NEXT:    s_ashr_i64 s[0:1], s[0:1], 41
481; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
482; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s6
483; GCN-NEXT:    s_xor_b32 s1, s6, s0
484; GCN-NEXT:    s_ashr_i32 s1, s1, 30
485; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
486; GCN-NEXT:    s_or_b32 s1, s1, 1
487; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
488; GCN-NEXT:    v_trunc_f32_e32 v2, v2
489; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
490; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
491; GCN-NEXT:    v_cmp_ge_f32_e64 s[8:9], |v1|, |v0|
492; GCN-NEXT:    s_cmp_lg_u32 s8, 0
493; GCN-NEXT:    s_cselect_b32 s1, s1, 0
494; GCN-NEXT:    v_add_i32_e32 v0, vcc, s1, v2
495; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
496; GCN-NEXT:    s_mov_b32 s0, s4
497; GCN-NEXT:    s_mov_b32 s1, s5
498; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
499; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 23
500; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
501; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
502; GCN-NEXT:    s_endpgm
503;
504; GCN-IR-LABEL: s_test_srem23_64:
505; GCN-IR:       ; %bb.0:
506; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
507; GCN-IR-NEXT:    s_load_dword s1, s[0:1], 0xe
508; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
509; GCN-IR-NEXT:    s_mov_b32 s2, -1
510; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
511; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 41
512; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[0:1], 41
513; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
514; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s6
515; GCN-IR-NEXT:    s_xor_b32 s1, s6, s0
516; GCN-IR-NEXT:    s_ashr_i32 s1, s1, 30
517; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
518; GCN-IR-NEXT:    s_or_b32 s1, s1, 1
519; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
520; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
521; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
522; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
523; GCN-IR-NEXT:    v_cmp_ge_f32_e64 s[8:9], |v1|, |v0|
524; GCN-IR-NEXT:    s_cmp_lg_u32 s8, 0
525; GCN-IR-NEXT:    s_cselect_b32 s1, s1, 0
526; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, s1, v2
527; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
528; GCN-IR-NEXT:    s_mov_b32 s0, s4
529; GCN-IR-NEXT:    s_mov_b32 s1, s5
530; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
531; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 23
532; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
533; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
534; GCN-IR-NEXT:    s_endpgm
535  %1 = ashr i64 %x, 41
536  %2 = ashr i64 %y, 41
537  %result = srem i64 %1, %2
538  store i64 %result, i64 addrspace(1)* %out
539  ret void
540}
541
542define amdgpu_kernel void @s_test_srem24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
543; GCN-LABEL: s_test_srem24_64:
544; GCN:       ; %bb.0:
545; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
546; GCN-NEXT:    s_load_dword s1, s[0:1], 0xe
547; GCN-NEXT:    s_mov_b32 s3, 0xf000
548; GCN-NEXT:    s_mov_b32 s2, -1
549; GCN-NEXT:    s_waitcnt lgkmcnt(0)
550; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
551; GCN-NEXT:    s_ashr_i64 s[0:1], s[0:1], 40
552; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
553; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s6
554; GCN-NEXT:    s_xor_b32 s1, s6, s0
555; GCN-NEXT:    s_ashr_i32 s1, s1, 30
556; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
557; GCN-NEXT:    s_or_b32 s1, s1, 1
558; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
559; GCN-NEXT:    v_trunc_f32_e32 v2, v2
560; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
561; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
562; GCN-NEXT:    v_cmp_ge_f32_e64 s[8:9], |v1|, |v0|
563; GCN-NEXT:    s_cmp_lg_u32 s8, 0
564; GCN-NEXT:    s_cselect_b32 s1, s1, 0
565; GCN-NEXT:    v_add_i32_e32 v0, vcc, s1, v2
566; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
567; GCN-NEXT:    s_mov_b32 s0, s4
568; GCN-NEXT:    s_mov_b32 s1, s5
569; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
570; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
571; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
572; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
573; GCN-NEXT:    s_endpgm
574;
575; GCN-IR-LABEL: s_test_srem24_64:
576; GCN-IR:       ; %bb.0:
577; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
578; GCN-IR-NEXT:    s_load_dword s1, s[0:1], 0xe
579; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
580; GCN-IR-NEXT:    s_mov_b32 s2, -1
581; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
582; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
583; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[0:1], 40
584; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
585; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s6
586; GCN-IR-NEXT:    s_xor_b32 s1, s6, s0
587; GCN-IR-NEXT:    s_ashr_i32 s1, s1, 30
588; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
589; GCN-IR-NEXT:    s_or_b32 s1, s1, 1
590; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
591; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
592; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
593; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
594; GCN-IR-NEXT:    v_cmp_ge_f32_e64 s[8:9], |v1|, |v0|
595; GCN-IR-NEXT:    s_cmp_lg_u32 s8, 0
596; GCN-IR-NEXT:    s_cselect_b32 s1, s1, 0
597; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, s1, v2
598; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
599; GCN-IR-NEXT:    s_mov_b32 s0, s4
600; GCN-IR-NEXT:    s_mov_b32 s1, s5
601; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
602; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
603; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
604; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
605; GCN-IR-NEXT:    s_endpgm
606  %1 = ashr i64 %x, 40
607  %2 = ashr i64 %y, 40
608  %result = srem i64 %1, %2
609  store i64 %result, i64 addrspace(1)* %out
610  ret void
611}
612
613define i64 @v_test_srem24_64(i64 %x, i64 %y) {
614; GCN-LABEL: v_test_srem24_64:
615; GCN:       ; %bb.0:
616; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
617; GCN-NEXT:    v_ashr_i64 v[2:3], v[2:3], 40
618; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
619; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
620; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
621; GCN-NEXT:    v_xor_b32_e32 v5, v0, v2
622; GCN-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
623; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v3
624; GCN-NEXT:    v_or_b32_e32 v5, 1, v5
625; GCN-NEXT:    v_mul_f32_e32 v4, v1, v4
626; GCN-NEXT:    v_trunc_f32_e32 v4, v4
627; GCN-NEXT:    v_mad_f32 v1, -v4, v3, v1
628; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
629; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
630; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
631; GCN-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
632; GCN-NEXT:    v_mul_lo_u32 v1, v1, v2
633; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
634; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
635; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
636; GCN-NEXT:    s_setpc_b64 s[30:31]
637;
638; GCN-IR-LABEL: v_test_srem24_64:
639; GCN-IR:       ; %bb.0:
640; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
641; GCN-IR-NEXT:    v_ashr_i64 v[2:3], v[2:3], 40
642; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
643; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v3, v2
644; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
645; GCN-IR-NEXT:    v_xor_b32_e32 v5, v0, v2
646; GCN-IR-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
647; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v4, v3
648; GCN-IR-NEXT:    v_or_b32_e32 v5, 1, v5
649; GCN-IR-NEXT:    v_mul_f32_e32 v4, v1, v4
650; GCN-IR-NEXT:    v_trunc_f32_e32 v4, v4
651; GCN-IR-NEXT:    v_mad_f32 v1, -v4, v3, v1
652; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v4, v4
653; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
654; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
655; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
656; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v2
657; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
658; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
659; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
660; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
661  %1 = ashr i64 %x, 40
662  %2 = ashr i64 %y, 40
663  %result = srem i64 %1, %2
664  ret i64 %result
665}
666
667define amdgpu_kernel void @s_test_srem25_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
668; GCN-LABEL: s_test_srem25_64:
669; GCN:       ; %bb.0:
670; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
671; GCN-NEXT:    s_load_dword s1, s[0:1], 0xe
672; GCN-NEXT:    s_mov_b32 s3, 0xf000
673; GCN-NEXT:    s_mov_b32 s2, -1
674; GCN-NEXT:    s_waitcnt lgkmcnt(0)
675; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 39
676; GCN-NEXT:    s_ashr_i64 s[0:1], s[0:1], 39
677; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
678; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s6
679; GCN-NEXT:    s_xor_b32 s1, s6, s0
680; GCN-NEXT:    s_ashr_i32 s1, s1, 30
681; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
682; GCN-NEXT:    s_or_b32 s1, s1, 1
683; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
684; GCN-NEXT:    v_trunc_f32_e32 v2, v2
685; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
686; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
687; GCN-NEXT:    v_cmp_ge_f32_e64 s[8:9], |v1|, |v0|
688; GCN-NEXT:    s_cmp_lg_u32 s8, 0
689; GCN-NEXT:    s_cselect_b32 s1, s1, 0
690; GCN-NEXT:    v_add_i32_e32 v0, vcc, s1, v2
691; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
692; GCN-NEXT:    s_mov_b32 s0, s4
693; GCN-NEXT:    s_mov_b32 s1, s5
694; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
695; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 25
696; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
697; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
698; GCN-NEXT:    s_endpgm
699;
700; GCN-IR-LABEL: s_test_srem25_64:
701; GCN-IR:       ; %bb.0:
702; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
703; GCN-IR-NEXT:    s_load_dword s1, s[0:1], 0xe
704; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
705; GCN-IR-NEXT:    s_mov_b32 s2, -1
706; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
707; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 39
708; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[0:1], 39
709; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
710; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s6
711; GCN-IR-NEXT:    s_xor_b32 s1, s6, s0
712; GCN-IR-NEXT:    s_ashr_i32 s1, s1, 30
713; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
714; GCN-IR-NEXT:    s_or_b32 s1, s1, 1
715; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
716; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
717; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
718; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
719; GCN-IR-NEXT:    v_cmp_ge_f32_e64 s[8:9], |v1|, |v0|
720; GCN-IR-NEXT:    s_cmp_lg_u32 s8, 0
721; GCN-IR-NEXT:    s_cselect_b32 s1, s1, 0
722; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, s1, v2
723; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
724; GCN-IR-NEXT:    s_mov_b32 s0, s4
725; GCN-IR-NEXT:    s_mov_b32 s1, s5
726; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
727; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 25
728; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
729; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
730; GCN-IR-NEXT:    s_endpgm
731  %1 = ashr i64 %x, 39
732  %2 = ashr i64 %y, 39
733  %result = srem i64 %1, %2
734  store i64 %result, i64 addrspace(1)* %out
735  ret void
736}
737
738define amdgpu_kernel void @s_test_srem31_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
739; GCN-LABEL: s_test_srem31_64:
740; GCN:       ; %bb.0:
741; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
742; GCN-NEXT:    s_load_dword s1, s[0:1], 0xe
743; GCN-NEXT:    s_mov_b32 s3, 0xf000
744; GCN-NEXT:    s_mov_b32 s2, -1
745; GCN-NEXT:    s_waitcnt lgkmcnt(0)
746; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 33
747; GCN-NEXT:    s_ashr_i64 s[0:1], s[0:1], 33
748; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
749; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s6
750; GCN-NEXT:    s_xor_b32 s1, s6, s0
751; GCN-NEXT:    s_ashr_i32 s1, s1, 30
752; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
753; GCN-NEXT:    s_or_b32 s1, s1, 1
754; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
755; GCN-NEXT:    v_trunc_f32_e32 v2, v2
756; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
757; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
758; GCN-NEXT:    v_cmp_ge_f32_e64 s[8:9], |v1|, |v0|
759; GCN-NEXT:    s_cmp_lg_u32 s8, 0
760; GCN-NEXT:    s_cselect_b32 s1, s1, 0
761; GCN-NEXT:    v_add_i32_e32 v0, vcc, s1, v2
762; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
763; GCN-NEXT:    s_mov_b32 s0, s4
764; GCN-NEXT:    s_mov_b32 s1, s5
765; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
766; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 31
767; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
768; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
769; GCN-NEXT:    s_endpgm
770;
771; GCN-IR-LABEL: s_test_srem31_64:
772; GCN-IR:       ; %bb.0:
773; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
774; GCN-IR-NEXT:    s_load_dword s1, s[0:1], 0xe
775; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
776; GCN-IR-NEXT:    s_mov_b32 s2, -1
777; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
778; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 33
779; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[0:1], 33
780; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
781; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s6
782; GCN-IR-NEXT:    s_xor_b32 s1, s6, s0
783; GCN-IR-NEXT:    s_ashr_i32 s1, s1, 30
784; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
785; GCN-IR-NEXT:    s_or_b32 s1, s1, 1
786; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
787; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
788; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
789; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
790; GCN-IR-NEXT:    v_cmp_ge_f32_e64 s[8:9], |v1|, |v0|
791; GCN-IR-NEXT:    s_cmp_lg_u32 s8, 0
792; GCN-IR-NEXT:    s_cselect_b32 s1, s1, 0
793; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, s1, v2
794; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
795; GCN-IR-NEXT:    s_mov_b32 s0, s4
796; GCN-IR-NEXT:    s_mov_b32 s1, s5
797; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
798; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 31
799; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
800; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
801; GCN-IR-NEXT:    s_endpgm
802  %1 = ashr i64 %x, 33
803  %2 = ashr i64 %y, 33
804  %result = srem i64 %1, %2
805  store i64 %result, i64 addrspace(1)* %out
806  ret void
807}
808
809; 32 known sign bits
810define amdgpu_kernel void @s_test_srem32_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
811; GCN-LABEL: s_test_srem32_64:
812; GCN:       ; %bb.0:
813; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
814; GCN-NEXT:    s_waitcnt lgkmcnt(0)
815; GCN-NEXT:    s_load_dword s6, s[0:1], 0xe
816; GCN-NEXT:    s_mov_b32 s3, 0xf000
817; GCN-NEXT:    s_mov_b32 s2, -1
818; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s7
819; GCN-NEXT:    s_waitcnt lgkmcnt(0)
820; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s6
821; GCN-NEXT:    s_xor_b32 s0, s7, s6
822; GCN-NEXT:    s_ashr_i32 s0, s0, 30
823; GCN-NEXT:    s_or_b32 s8, s0, 1
824; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
825; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
826; GCN-NEXT:    v_trunc_f32_e32 v2, v2
827; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
828; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
829; GCN-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
830; GCN-NEXT:    s_cmp_lg_u32 s0, 0
831; GCN-NEXT:    s_cselect_b32 s0, s8, 0
832; GCN-NEXT:    v_add_i32_e32 v0, vcc, s0, v2
833; GCN-NEXT:    v_mul_lo_u32 v0, v0, s6
834; GCN-NEXT:    s_mov_b32 s0, s4
835; GCN-NEXT:    s_mov_b32 s1, s5
836; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s7, v0
837; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
838; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
839; GCN-NEXT:    s_endpgm
840;
841; GCN-IR-LABEL: s_test_srem32_64:
842; GCN-IR:       ; %bb.0:
843; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
844; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
845; GCN-IR-NEXT:    s_load_dword s6, s[0:1], 0xe
846; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
847; GCN-IR-NEXT:    s_mov_b32 s2, -1
848; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s7
849; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
850; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s6
851; GCN-IR-NEXT:    s_xor_b32 s0, s7, s6
852; GCN-IR-NEXT:    s_ashr_i32 s0, s0, 30
853; GCN-IR-NEXT:    s_or_b32 s8, s0, 1
854; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
855; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
856; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
857; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
858; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
859; GCN-IR-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
860; GCN-IR-NEXT:    s_cmp_lg_u32 s0, 0
861; GCN-IR-NEXT:    s_cselect_b32 s0, s8, 0
862; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, s0, v2
863; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s6
864; GCN-IR-NEXT:    s_mov_b32 s0, s4
865; GCN-IR-NEXT:    s_mov_b32 s1, s5
866; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s7, v0
867; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
868; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
869; GCN-IR-NEXT:    s_endpgm
870  %1 = ashr i64 %x, 32
871  %2 = ashr i64 %y, 32
872  %result = srem i64 %1, %2
873  store i64 %result, i64 addrspace(1)* %out
874  ret void
875}
876
877; 33 known sign bits
878define amdgpu_kernel void @s_test_srem33_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
879; GCN-LABEL: s_test_srem33_64:
880; GCN:       ; %bb.0:
881; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
882; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
883; GCN-NEXT:    s_mov_b32 s11, 0xf000
884; GCN-NEXT:    s_mov_b32 s10, -1
885; GCN-NEXT:    s_waitcnt lgkmcnt(0)
886; GCN-NEXT:    s_ashr_i64 s[2:3], s[6:7], 31
887; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 31
888; GCN-NEXT:    s_ashr_i32 s0, s1, 31
889; GCN-NEXT:    s_add_u32 s8, s8, s0
890; GCN-NEXT:    s_mov_b32 s1, s0
891; GCN-NEXT:    s_addc_u32 s9, s9, s0
892; GCN-NEXT:    s_xor_b64 s[12:13], s[8:9], s[0:1]
893; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
894; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
895; GCN-NEXT:    s_sub_u32 s6, 0, s12
896; GCN-NEXT:    s_subb_u32 s8, 0, s13
897; GCN-NEXT:    s_mov_b32 s9, s5
898; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
899; GCN-NEXT:    v_rcp_f32_e32 v0, v0
900; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
901; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
902; GCN-NEXT:    v_trunc_f32_e32 v1, v1
903; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
904; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
905; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
906; GCN-NEXT:    v_mul_hi_u32 v3, s6, v0
907; GCN-NEXT:    v_mul_lo_u32 v2, s6, v1
908; GCN-NEXT:    v_mul_lo_u32 v5, s8, v0
909; GCN-NEXT:    v_mul_lo_u32 v4, s6, v0
910; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
911; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
912; GCN-NEXT:    v_mul_hi_u32 v3, v0, v4
913; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
914; GCN-NEXT:    v_mul_hi_u32 v6, v0, v2
915; GCN-NEXT:    v_mul_hi_u32 v7, v1, v2
916; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
917; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
918; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
919; GCN-NEXT:    v_mul_lo_u32 v6, v1, v4
920; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
921; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
922; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
923; GCN-NEXT:    v_mov_b32_e32 v4, 0
924; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
925; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
926; GCN-NEXT:    v_mov_b32_e32 v6, 0
927; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
928; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v6, v5, vcc
929; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
930; GCN-NEXT:    v_mul_lo_u32 v5, s6, v2
931; GCN-NEXT:    v_mul_hi_u32 v7, s6, v0
932; GCN-NEXT:    v_mul_lo_u32 v8, s8, v0
933; GCN-NEXT:    s_mov_b32 s8, s4
934; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
935; GCN-NEXT:    v_mul_lo_u32 v7, s6, v0
936; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
937; GCN-NEXT:    v_mul_lo_u32 v10, v0, v5
938; GCN-NEXT:    v_mul_hi_u32 v12, v0, v5
939; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
940; GCN-NEXT:    v_mul_hi_u32 v9, v2, v7
941; GCN-NEXT:    v_mul_lo_u32 v7, v2, v7
942; GCN-NEXT:    v_mul_hi_u32 v8, v2, v5
943; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
944; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
945; GCN-NEXT:    v_mul_lo_u32 v2, v2, v5
946; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
947; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
948; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v4, vcc
949; GCN-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
950; GCN-NEXT:    s_ashr_i32 s6, s7, 31
951; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v6, v5, vcc
952; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
953; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[0:1]
954; GCN-NEXT:    s_add_u32 s0, s2, s6
955; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
956; GCN-NEXT:    s_mov_b32 s7, s6
957; GCN-NEXT:    s_addc_u32 s1, s3, s6
958; GCN-NEXT:    s_xor_b64 s[14:15], s[0:1], s[6:7]
959; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
960; GCN-NEXT:    v_mul_lo_u32 v2, s14, v1
961; GCN-NEXT:    v_mul_hi_u32 v3, s14, v0
962; GCN-NEXT:    v_mul_hi_u32 v5, s14, v1
963; GCN-NEXT:    v_mul_hi_u32 v7, s15, v1
964; GCN-NEXT:    v_mul_lo_u32 v1, s15, v1
965; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
966; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
967; GCN-NEXT:    v_mul_lo_u32 v5, s15, v0
968; GCN-NEXT:    v_mul_hi_u32 v0, s15, v0
969; GCN-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
970; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
971; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v7, v4, vcc
972; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
973; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
974; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
975; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
976; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
977; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
978; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
979; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
980; GCN-NEXT:    v_sub_i32_e64 v0, s[0:1], s14, v0
981; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s15, v1
982; GCN-NEXT:    v_mov_b32_e32 v3, s13
983; GCN-NEXT:    v_subb_u32_e64 v2, vcc, v2, v3, s[0:1]
984; GCN-NEXT:    v_subrev_i32_e64 v4, s[2:3], s12, v0
985; GCN-NEXT:    v_subbrev_u32_e64 v5, vcc, 0, v2, s[2:3]
986; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v5
987; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
988; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v4
989; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
990; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v5
991; GCN-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc
992; GCN-NEXT:    v_subb_u32_e64 v2, vcc, v2, v3, s[2:3]
993; GCN-NEXT:    v_subrev_i32_e32 v3, vcc, s12, v4
994; GCN-NEXT:    v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
995; GCN-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v6
996; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[2:3]
997; GCN-NEXT:    v_mov_b32_e32 v5, s15
998; GCN-NEXT:    v_subb_u32_e64 v1, vcc, v5, v1, s[0:1]
999; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
1000; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
1001; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
1002; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1003; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
1004; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
1005; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
1006; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1007; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[2:3]
1008; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1009; GCN-NEXT:    v_xor_b32_e32 v0, s6, v0
1010; GCN-NEXT:    v_xor_b32_e32 v1, s6, v1
1011; GCN-NEXT:    v_mov_b32_e32 v2, s6
1012; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s6, v0
1013; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1014; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
1015; GCN-NEXT:    s_endpgm
1016;
1017; GCN-IR-LABEL: s_test_srem33_64:
1018; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1019; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1020; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
1021; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1022; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[6:7], 31
1023; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 31
1024; GCN-IR-NEXT:    s_ashr_i32 s10, s1, 31
1025; GCN-IR-NEXT:    s_ashr_i32 s0, s7, 31
1026; GCN-IR-NEXT:    s_mov_b32 s1, s0
1027; GCN-IR-NEXT:    s_mov_b32 s11, s10
1028; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[8:9], s[10:11]
1029; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[2:3], s[0:1]
1030; GCN-IR-NEXT:    s_sub_u32 s2, s2, s0
1031; GCN-IR-NEXT:    s_subb_u32 s3, s3, s0
1032; GCN-IR-NEXT:    s_sub_u32 s6, s6, s10
1033; GCN-IR-NEXT:    s_subb_u32 s7, s7, s10
1034; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
1035; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[2:3], 0
1036; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1037; GCN-IR-NEXT:    s_or_b64 s[14:15], s[10:11], s[12:13]
1038; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s6
1039; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
1040; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s7
1041; GCN-IR-NEXT:    s_cmp_eq_u32 s7, 0
1042; GCN-IR-NEXT:    s_cselect_b32 s12, s10, s11
1043; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s2
1044; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
1045; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s3
1046; GCN-IR-NEXT:    s_cmp_eq_u32 s3, 0
1047; GCN-IR-NEXT:    s_cselect_b32 s16, s10, s11
1048; GCN-IR-NEXT:    s_sub_u32 s10, s12, s16
1049; GCN-IR-NEXT:    s_subb_u32 s11, 0, 0
1050; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[18:19], s[10:11], 63
1051; GCN-IR-NEXT:    s_mov_b32 s13, 0
1052; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[18:19]
1053; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[18:19], s[10:11], 63
1054; GCN-IR-NEXT:    s_xor_b64 s[20:21], s[14:15], -1
1055; GCN-IR-NEXT:    s_and_b64 s[18:19], s[20:21], s[18:19]
1056; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[18:19]
1057; GCN-IR-NEXT:    s_cbranch_vccz BB8_5
1058; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1059; GCN-IR-NEXT:    s_add_u32 s18, s10, 1
1060; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1061; GCN-IR-NEXT:    s_addc_u32 s19, s11, 0
1062; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
1063; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[18:19], v[0:1]
1064; GCN-IR-NEXT:    s_sub_i32 s10, 63, s10
1065; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1066; GCN-IR-NEXT:    s_lshl_b64 s[14:15], s[2:3], s10
1067; GCN-IR-NEXT:    s_cbranch_vccz BB8_4
1068; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1069; GCN-IR-NEXT:    s_lshr_b64 s[18:19], s[2:3], s18
1070; GCN-IR-NEXT:    s_add_u32 s10, s6, -1
1071; GCN-IR-NEXT:    s_addc_u32 s11, s7, -1
1072; GCN-IR-NEXT:    s_not_b64 s[8:9], s[12:13]
1073; GCN-IR-NEXT:    s_mov_b32 s17, s13
1074; GCN-IR-NEXT:    s_add_u32 s12, s8, s16
1075; GCN-IR-NEXT:    s_addc_u32 s13, s9, s13
1076; GCN-IR-NEXT:    s_mov_b64 s[16:17], 0
1077; GCN-IR-NEXT:    s_mov_b32 s9, 0
1078; GCN-IR-NEXT:  BB8_3: ; %udiv-do-while
1079; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1080; GCN-IR-NEXT:    s_lshr_b32 s8, s15, 31
1081; GCN-IR-NEXT:    s_lshl_b64 s[18:19], s[18:19], 1
1082; GCN-IR-NEXT:    s_lshl_b64 s[14:15], s[14:15], 1
1083; GCN-IR-NEXT:    s_or_b64 s[18:19], s[18:19], s[8:9]
1084; GCN-IR-NEXT:    s_or_b64 s[14:15], s[16:17], s[14:15]
1085; GCN-IR-NEXT:    s_sub_u32 s8, s10, s18
1086; GCN-IR-NEXT:    s_subb_u32 s8, s11, s19
1087; GCN-IR-NEXT:    s_ashr_i32 s16, s8, 31
1088; GCN-IR-NEXT:    s_mov_b32 s17, s16
1089; GCN-IR-NEXT:    s_and_b32 s8, s16, 1
1090; GCN-IR-NEXT:    s_and_b64 s[20:21], s[16:17], s[6:7]
1091; GCN-IR-NEXT:    s_sub_u32 s18, s18, s20
1092; GCN-IR-NEXT:    v_mov_b32_e32 v0, s12
1093; GCN-IR-NEXT:    s_subb_u32 s19, s19, s21
1094; GCN-IR-NEXT:    v_mov_b32_e32 v1, s13
1095; GCN-IR-NEXT:    s_add_u32 s12, s12, 1
1096; GCN-IR-NEXT:    s_addc_u32 s13, s13, 0
1097; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[12:13], v[0:1]
1098; GCN-IR-NEXT:    s_mov_b64 s[16:17], s[8:9]
1099; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1100; GCN-IR-NEXT:    s_cbranch_vccz BB8_3
1101; GCN-IR-NEXT:  BB8_4: ; %Flow6
1102; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[14:15], 1
1103; GCN-IR-NEXT:    s_or_b64 s[8:9], s[8:9], s[10:11]
1104; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
1105; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
1106; GCN-IR-NEXT:    s_branch BB8_6
1107; GCN-IR-NEXT:  BB8_5:
1108; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
1109; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[14:15]
1110; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1111; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[14:15]
1112; GCN-IR-NEXT:  BB8_6: ; %udiv-end
1113; GCN-IR-NEXT:    v_mul_lo_u32 v1, s6, v1
1114; GCN-IR-NEXT:    v_mul_hi_u32 v2, s6, v0
1115; GCN-IR-NEXT:    v_mul_lo_u32 v3, s7, v0
1116; GCN-IR-NEXT:    v_mul_lo_u32 v0, s6, v0
1117; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1118; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1119; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1120; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1121; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
1122; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
1123; GCN-IR-NEXT:    v_xor_b32_e32 v0, s0, v0
1124; GCN-IR-NEXT:    v_xor_b32_e32 v1, s1, v1
1125; GCN-IR-NEXT:    v_mov_b32_e32 v2, s1
1126; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
1127; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1128; GCN-IR-NEXT:    s_mov_b32 s6, -1
1129; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1130; GCN-IR-NEXT:    s_endpgm
1131  %1 = ashr i64 %x, 31
1132  %2 = ashr i64 %y, 31
1133  %result = srem i64 %1, %2
1134  store i64 %result, i64 addrspace(1)* %out
1135  ret void
1136}
1137
1138define amdgpu_kernel void @s_test_srem24_48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
1139; GCN-LABEL: s_test_srem24_48:
1140; GCN:       ; %bb.0:
1141; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
1142; GCN-NEXT:    s_load_dword s2, s[0:1], 0xb
1143; GCN-NEXT:    s_load_dword s3, s[0:1], 0xc
1144; GCN-NEXT:    s_load_dword s6, s[0:1], 0xd
1145; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
1146; GCN-NEXT:    s_mov_b32 s7, 0xf000
1147; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1148; GCN-NEXT:    v_mov_b32_e32 v2, s2
1149; GCN-NEXT:    s_sext_i32_i16 s1, s3
1150; GCN-NEXT:    v_mov_b32_e32 v0, s6
1151; GCN-NEXT:    s_sext_i32_i16 s0, s0
1152; GCN-NEXT:    v_alignbit_b32 v0, s0, v0, 24
1153; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
1154; GCN-NEXT:    v_alignbit_b32 v2, s1, v2, 24
1155; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
1156; GCN-NEXT:    v_xor_b32_e32 v5, v2, v0
1157; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v1
1158; GCN-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
1159; GCN-NEXT:    v_or_b32_e32 v5, 1, v5
1160; GCN-NEXT:    s_mov_b32 s6, -1
1161; GCN-NEXT:    v_mul_f32_e32 v4, v3, v4
1162; GCN-NEXT:    v_trunc_f32_e32 v4, v4
1163; GCN-NEXT:    v_mad_f32 v3, -v4, v1, v3
1164; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
1165; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1166; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
1167; GCN-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
1168; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
1169; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v2, v0
1170; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1171; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1172; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
1173; GCN-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
1174; GCN-NEXT:    s_endpgm
1175;
1176; GCN-IR-LABEL: s_test_srem24_48:
1177; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1178; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
1179; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xb
1180; GCN-IR-NEXT:    s_load_dword s3, s[0:1], 0xc
1181; GCN-IR-NEXT:    s_load_dword s6, s[0:1], 0xd
1182; GCN-IR-NEXT:    s_load_dword s0, s[0:1], 0xe
1183; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1184; GCN-IR-NEXT:    s_sext_i32_i16 s3, s3
1185; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[2:3], 24
1186; GCN-IR-NEXT:    s_sext_i32_i16 s7, s0
1187; GCN-IR-NEXT:    s_ashr_i32 s0, s3, 31
1188; GCN-IR-NEXT:    s_ashr_i32 s12, s7, 31
1189; GCN-IR-NEXT:    s_mov_b32 s1, s0
1190; GCN-IR-NEXT:    s_ashr_i64 s[10:11], s[6:7], 24
1191; GCN-IR-NEXT:    s_mov_b32 s13, s12
1192; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[8:9], s[0:1]
1193; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[10:11], s[12:13]
1194; GCN-IR-NEXT:    s_sub_u32 s2, s2, s0
1195; GCN-IR-NEXT:    s_subb_u32 s3, s3, s0
1196; GCN-IR-NEXT:    s_sub_u32 s6, s6, s12
1197; GCN-IR-NEXT:    s_subb_u32 s7, s7, s12
1198; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
1199; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[2:3], 0
1200; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1201; GCN-IR-NEXT:    s_or_b64 s[14:15], s[10:11], s[12:13]
1202; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s6
1203; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
1204; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s7
1205; GCN-IR-NEXT:    s_cmp_eq_u32 s7, 0
1206; GCN-IR-NEXT:    s_cselect_b32 s12, s10, s11
1207; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s2
1208; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
1209; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s3
1210; GCN-IR-NEXT:    s_cmp_eq_u32 s3, 0
1211; GCN-IR-NEXT:    s_cselect_b32 s16, s10, s11
1212; GCN-IR-NEXT:    s_sub_u32 s10, s12, s16
1213; GCN-IR-NEXT:    s_subb_u32 s11, 0, 0
1214; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[18:19], s[10:11], 63
1215; GCN-IR-NEXT:    s_mov_b32 s13, 0
1216; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[18:19]
1217; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[18:19], s[10:11], 63
1218; GCN-IR-NEXT:    s_xor_b64 s[20:21], s[14:15], -1
1219; GCN-IR-NEXT:    s_and_b64 s[18:19], s[20:21], s[18:19]
1220; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[18:19]
1221; GCN-IR-NEXT:    s_cbranch_vccz BB9_5
1222; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1223; GCN-IR-NEXT:    s_add_u32 s18, s10, 1
1224; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
1225; GCN-IR-NEXT:    s_addc_u32 s19, s11, 0
1226; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
1227; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[18:19], v[0:1]
1228; GCN-IR-NEXT:    s_sub_i32 s10, 63, s10
1229; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1230; GCN-IR-NEXT:    s_lshl_b64 s[14:15], s[2:3], s10
1231; GCN-IR-NEXT:    s_cbranch_vccz BB9_4
1232; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1233; GCN-IR-NEXT:    s_lshr_b64 s[18:19], s[2:3], s18
1234; GCN-IR-NEXT:    s_add_u32 s10, s6, -1
1235; GCN-IR-NEXT:    s_addc_u32 s11, s7, -1
1236; GCN-IR-NEXT:    s_not_b64 s[8:9], s[12:13]
1237; GCN-IR-NEXT:    s_mov_b32 s17, s13
1238; GCN-IR-NEXT:    s_add_u32 s12, s8, s16
1239; GCN-IR-NEXT:    s_addc_u32 s13, s9, s13
1240; GCN-IR-NEXT:    s_mov_b64 s[16:17], 0
1241; GCN-IR-NEXT:    s_mov_b32 s9, 0
1242; GCN-IR-NEXT:  BB9_3: ; %udiv-do-while
1243; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1244; GCN-IR-NEXT:    s_lshr_b32 s8, s15, 31
1245; GCN-IR-NEXT:    s_lshl_b64 s[18:19], s[18:19], 1
1246; GCN-IR-NEXT:    s_lshl_b64 s[14:15], s[14:15], 1
1247; GCN-IR-NEXT:    s_or_b64 s[18:19], s[18:19], s[8:9]
1248; GCN-IR-NEXT:    s_or_b64 s[14:15], s[16:17], s[14:15]
1249; GCN-IR-NEXT:    s_sub_u32 s8, s10, s18
1250; GCN-IR-NEXT:    s_subb_u32 s8, s11, s19
1251; GCN-IR-NEXT:    s_ashr_i32 s16, s8, 31
1252; GCN-IR-NEXT:    s_mov_b32 s17, s16
1253; GCN-IR-NEXT:    s_and_b32 s8, s16, 1
1254; GCN-IR-NEXT:    s_and_b64 s[20:21], s[16:17], s[6:7]
1255; GCN-IR-NEXT:    s_sub_u32 s18, s18, s20
1256; GCN-IR-NEXT:    v_mov_b32_e32 v0, s12
1257; GCN-IR-NEXT:    s_subb_u32 s19, s19, s21
1258; GCN-IR-NEXT:    v_mov_b32_e32 v1, s13
1259; GCN-IR-NEXT:    s_add_u32 s12, s12, 1
1260; GCN-IR-NEXT:    s_addc_u32 s13, s13, 0
1261; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[12:13], v[0:1]
1262; GCN-IR-NEXT:    s_mov_b64 s[16:17], s[8:9]
1263; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1264; GCN-IR-NEXT:    s_cbranch_vccz BB9_3
1265; GCN-IR-NEXT:  BB9_4: ; %Flow3
1266; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[14:15], 1
1267; GCN-IR-NEXT:    s_or_b64 s[8:9], s[8:9], s[10:11]
1268; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
1269; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
1270; GCN-IR-NEXT:    s_branch BB9_6
1271; GCN-IR-NEXT:  BB9_5:
1272; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
1273; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[14:15]
1274; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1275; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[14:15]
1276; GCN-IR-NEXT:  BB9_6: ; %udiv-end
1277; GCN-IR-NEXT:    v_mul_lo_u32 v1, s6, v1
1278; GCN-IR-NEXT:    v_mul_hi_u32 v2, s6, v0
1279; GCN-IR-NEXT:    v_mul_lo_u32 v3, s7, v0
1280; GCN-IR-NEXT:    v_mul_lo_u32 v0, s6, v0
1281; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1282; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1283; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1284; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1285; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
1286; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
1287; GCN-IR-NEXT:    v_xor_b32_e32 v0, s0, v0
1288; GCN-IR-NEXT:    v_xor_b32_e32 v1, s1, v1
1289; GCN-IR-NEXT:    v_mov_b32_e32 v2, s1
1290; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
1291; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1292; GCN-IR-NEXT:    s_mov_b32 s6, -1
1293; GCN-IR-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
1294; GCN-IR-NEXT:    buffer_store_dword v0, off, s[4:7], 0
1295; GCN-IR-NEXT:    s_endpgm
1296  %1 = ashr i48 %x, 24
1297  %2 = ashr i48 %y, 24
1298  %result = srem i48 %1, %2
1299  store i48 %result, i48 addrspace(1)* %out
1300  ret void
1301}
1302
1303define amdgpu_kernel void @s_test_srem_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1304; GCN-LABEL: s_test_srem_k_num_i64:
1305; GCN:       ; %bb.0:
1306; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1307; GCN-NEXT:    v_mov_b32_e32 v2, 0
1308; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1309; GCN-NEXT:    s_ashr_i32 s0, s7, 31
1310; GCN-NEXT:    s_add_u32 s2, s6, s0
1311; GCN-NEXT:    s_addc_u32 s3, s7, s0
1312; GCN-NEXT:    s_mov_b32 s1, s0
1313; GCN-NEXT:    s_xor_b64 s[8:9], s[2:3], s[0:1]
1314; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
1315; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s9
1316; GCN-NEXT:    s_sub_u32 s2, 0, s8
1317; GCN-NEXT:    s_subb_u32 s3, 0, s9
1318; GCN-NEXT:    s_mov_b32 s7, 0xf000
1319; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
1320; GCN-NEXT:    v_rcp_f32_e32 v0, v0
1321; GCN-NEXT:    v_mov_b32_e32 v1, 0
1322; GCN-NEXT:    s_mov_b32 s6, -1
1323; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
1324; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
1325; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1326; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
1327; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
1328; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1329; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
1330; GCN-NEXT:    v_mul_lo_u32 v4, s2, v3
1331; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
1332; GCN-NEXT:    v_mul_lo_u32 v6, s2, v0
1333; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1334; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
1335; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
1336; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
1337; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
1338; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
1339; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
1340; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
1341; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
1342; GCN-NEXT:    v_mul_hi_u32 v9, v3, v4
1343; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1344; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
1345; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
1346; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v1, vcc
1347; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1348; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
1349; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
1350; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
1351; GCN-NEXT:    v_mul_lo_u32 v6, s2, v4
1352; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
1353; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
1354; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1355; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
1356; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
1357; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
1358; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
1359; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
1360; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
1361; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
1362; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
1363; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
1364; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
1365; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
1366; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
1367; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
1368; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v1, vcc
1369; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
1370; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
1371; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1372; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
1373; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
1374; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1375; GCN-NEXT:    v_mul_hi_u32 v5, 24, v0
1376; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
1377; GCN-NEXT:    v_mul_hi_u32 v6, 24, v3
1378; GCN-NEXT:    v_mul_hi_u32 v0, 0, v0
1379; GCN-NEXT:    v_mul_hi_u32 v3, 0, v3
1380; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1381; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v6, vcc
1382; GCN-NEXT:    v_add_i32_e32 v4, vcc, 0, v4
1383; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v2, v0, vcc
1384; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
1385; GCN-NEXT:    v_mul_lo_u32 v1, s8, v1
1386; GCN-NEXT:    v_mul_hi_u32 v2, s8, v0
1387; GCN-NEXT:    v_mul_lo_u32 v3, s9, v0
1388; GCN-NEXT:    v_mul_lo_u32 v0, s8, v0
1389; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1390; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1391; GCN-NEXT:    v_sub_i32_e64 v0, s[0:1], 24, v0
1392; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
1393; GCN-NEXT:    v_mov_b32_e32 v3, s9
1394; GCN-NEXT:    v_subb_u32_e64 v2, vcc, v2, v3, s[0:1]
1395; GCN-NEXT:    v_subrev_i32_e64 v4, s[2:3], s8, v0
1396; GCN-NEXT:    v_subbrev_u32_e64 v5, vcc, 0, v2, s[2:3]
1397; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s9, v5
1398; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1399; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s8, v4
1400; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
1401; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v5
1402; GCN-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc
1403; GCN-NEXT:    v_subb_u32_e64 v2, vcc, v2, v3, s[2:3]
1404; GCN-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v4
1405; GCN-NEXT:    v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
1406; GCN-NEXT:    v_subb_u32_e64 v1, vcc, 0, v1, s[0:1]
1407; GCN-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v6
1408; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
1409; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[2:3]
1410; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
1411; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
1412; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1413; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v1
1414; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
1415; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
1416; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1417; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[2:3]
1418; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1419; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1420; GCN-NEXT:    s_endpgm
1421;
1422; GCN-IR-LABEL: s_test_srem_k_num_i64:
1423; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1424; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1425; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1426; GCN-IR-NEXT:    s_ashr_i32 s4, s3, 31
1427; GCN-IR-NEXT:    s_mov_b32 s5, s4
1428; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[2:3], s[4:5]
1429; GCN-IR-NEXT:    s_sub_u32 s2, s2, s4
1430; GCN-IR-NEXT:    s_subb_u32 s3, s3, s4
1431; GCN-IR-NEXT:    s_flbit_i32_b32 s4, s2
1432; GCN-IR-NEXT:    s_add_i32 s4, s4, 32
1433; GCN-IR-NEXT:    s_flbit_i32_b32 s5, s3
1434; GCN-IR-NEXT:    s_cmp_eq_u32 s3, 0
1435; GCN-IR-NEXT:    s_cselect_b32 s8, s4, s5
1436; GCN-IR-NEXT:    s_add_u32 s6, s8, 0xffffffc5
1437; GCN-IR-NEXT:    s_addc_u32 s7, 0, -1
1438; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
1439; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[12:13], s[6:7], 63
1440; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0
1441; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
1442; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[12:13], s[6:7], 63
1443; GCN-IR-NEXT:    s_xor_b64 s[14:15], s[10:11], -1
1444; GCN-IR-NEXT:    s_and_b64 s[12:13], s[14:15], s[12:13]
1445; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
1446; GCN-IR-NEXT:    s_cbranch_vccz BB10_5
1447; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1448; GCN-IR-NEXT:    s_add_u32 s12, s6, 1
1449; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1450; GCN-IR-NEXT:    s_addc_u32 s13, s7, 0
1451; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
1452; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[12:13], v[0:1]
1453; GCN-IR-NEXT:    s_sub_i32 s6, 63, s6
1454; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1455; GCN-IR-NEXT:    s_lshl_b64 s[10:11], 24, s6
1456; GCN-IR-NEXT:    s_cbranch_vccz BB10_4
1457; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1458; GCN-IR-NEXT:    s_lshr_b64 s[14:15], 24, s12
1459; GCN-IR-NEXT:    s_add_u32 s6, s2, -1
1460; GCN-IR-NEXT:    s_addc_u32 s7, s3, -1
1461; GCN-IR-NEXT:    s_sub_u32 s8, 58, s8
1462; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
1463; GCN-IR-NEXT:    s_mov_b64 s[12:13], 0
1464; GCN-IR-NEXT:    s_mov_b32 s5, 0
1465; GCN-IR-NEXT:  BB10_3: ; %udiv-do-while
1466; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1467; GCN-IR-NEXT:    s_lshr_b32 s4, s11, 31
1468; GCN-IR-NEXT:    s_lshl_b64 s[14:15], s[14:15], 1
1469; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
1470; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[4:5]
1471; GCN-IR-NEXT:    s_or_b64 s[10:11], s[12:13], s[10:11]
1472; GCN-IR-NEXT:    s_sub_u32 s4, s6, s14
1473; GCN-IR-NEXT:    s_subb_u32 s4, s7, s15
1474; GCN-IR-NEXT:    s_ashr_i32 s12, s4, 31
1475; GCN-IR-NEXT:    s_mov_b32 s13, s12
1476; GCN-IR-NEXT:    s_and_b32 s4, s12, 1
1477; GCN-IR-NEXT:    s_and_b64 s[16:17], s[12:13], s[2:3]
1478; GCN-IR-NEXT:    s_sub_u32 s14, s14, s16
1479; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
1480; GCN-IR-NEXT:    s_subb_u32 s15, s15, s17
1481; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
1482; GCN-IR-NEXT:    s_add_u32 s8, s8, 1
1483; GCN-IR-NEXT:    s_addc_u32 s9, s9, 0
1484; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
1485; GCN-IR-NEXT:    s_mov_b64 s[12:13], s[4:5]
1486; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1487; GCN-IR-NEXT:    s_cbranch_vccz BB10_3
1488; GCN-IR-NEXT:  BB10_4: ; %Flow5
1489; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[10:11], 1
1490; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], s[6:7]
1491; GCN-IR-NEXT:    v_mov_b32_e32 v0, s4
1492; GCN-IR-NEXT:    v_mov_b32_e32 v1, s5
1493; GCN-IR-NEXT:    s_branch BB10_6
1494; GCN-IR-NEXT:  BB10_5:
1495; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1496; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, 24, 0, s[10:11]
1497; GCN-IR-NEXT:  BB10_6: ; %udiv-end
1498; GCN-IR-NEXT:    v_mul_lo_u32 v1, s2, v1
1499; GCN-IR-NEXT:    v_mul_hi_u32 v2, s2, v0
1500; GCN-IR-NEXT:    v_mul_lo_u32 v3, s3, v0
1501; GCN-IR-NEXT:    v_mul_lo_u32 v0, s2, v0
1502; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1503; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1504; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1505; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1506; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1507; GCN-IR-NEXT:    s_mov_b32 s2, -1
1508; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1509; GCN-IR-NEXT:    s_endpgm
1510  %result = srem i64 24, %x
1511  store i64 %result, i64 addrspace(1)* %out
1512  ret void
1513}
1514
1515define i64 @v_test_srem_k_num_i64(i64 %x) {
1516; GCN-LABEL: v_test_srem_k_num_i64:
1517; GCN:       ; %bb.0:
1518; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1519; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1520; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1521; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1522; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1523; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1524; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1525; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1526; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1527; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1528; GCN-NEXT:    v_mov_b32_e32 v12, 0
1529; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
1530; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1531; GCN-NEXT:    v_mov_b32_e32 v11, 0
1532; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1533; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1534; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1535; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1536; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1537; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1538; GCN-NEXT:    v_mul_hi_u32 v6, v4, v2
1539; GCN-NEXT:    v_mul_lo_u32 v7, v4, v3
1540; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1541; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
1542; GCN-NEXT:    v_mul_lo_u32 v7, v4, v2
1543; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1544; GCN-NEXT:    v_mul_lo_u32 v9, v2, v6
1545; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
1546; GCN-NEXT:    v_mul_hi_u32 v10, v2, v7
1547; GCN-NEXT:    v_mul_hi_u32 v13, v3, v6
1548; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1549; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1550; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
1551; GCN-NEXT:    v_mul_hi_u32 v7, v3, v7
1552; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v8, vcc
1553; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
1554; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v7, vcc
1555; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v11, vcc
1556; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1557; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v6
1558; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v8, vcc
1559; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v3, v7, s[4:5]
1560; GCN-NEXT:    v_mul_lo_u32 v8, v4, v6
1561; GCN-NEXT:    v_mul_hi_u32 v9, v4, v2
1562; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1563; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1564; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1565; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
1566; GCN-NEXT:    v_mul_lo_u32 v10, v2, v5
1567; GCN-NEXT:    v_mul_hi_u32 v13, v2, v4
1568; GCN-NEXT:    v_mul_hi_u32 v14, v2, v5
1569; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
1570; GCN-NEXT:    v_mul_lo_u32 v4, v6, v4
1571; GCN-NEXT:    v_add_i32_e32 v10, vcc, v13, v10
1572; GCN-NEXT:    v_mul_hi_u32 v8, v6, v5
1573; GCN-NEXT:    v_addc_u32_e32 v13, vcc, v12, v14, vcc
1574; GCN-NEXT:    v_mul_lo_u32 v5, v6, v5
1575; GCN-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
1576; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v13, v9, vcc
1577; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v11, vcc
1578; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1579; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
1580; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
1581; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
1582; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1583; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1584; GCN-NEXT:    v_mul_hi_u32 v5, 24, v2
1585; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
1586; GCN-NEXT:    v_mul_hi_u32 v6, 24, v3
1587; GCN-NEXT:    v_mul_hi_u32 v2, 0, v2
1588; GCN-NEXT:    v_mul_hi_u32 v3, 0, v3
1589; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1590; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
1591; GCN-NEXT:    v_add_i32_e32 v4, vcc, 0, v4
1592; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v2, vcc
1593; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v11, vcc
1594; GCN-NEXT:    v_mul_lo_u32 v3, v0, v3
1595; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1596; GCN-NEXT:    v_mul_lo_u32 v5, v1, v2
1597; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
1598; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1599; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1600; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
1601; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 24, v2
1602; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
1603; GCN-NEXT:    v_sub_i32_e64 v5, s[4:5], v2, v0
1604; GCN-NEXT:    v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
1605; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v1
1606; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[6:7]
1607; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v5, v0
1608; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
1609; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v6, v1
1610; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
1611; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1612; GCN-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[6:7]
1613; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v5, v0
1614; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
1615; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1616; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1617; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
1618; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v0
1619; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1620; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1621; GCN-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
1622; GCN-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[4:5]
1623; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1624; GCN-NEXT:    v_cndmask_b32_e64 v1, v6, v4, s[4:5]
1625; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1626; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1627; GCN-NEXT:    s_setpc_b64 s[30:31]
1628;
1629; GCN-IR-LABEL: v_test_srem_k_num_i64:
1630; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1631; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1632; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1633; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1634; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
1635; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1636; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1637; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1638; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1639; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1640; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
1641; GCN-IR-NEXT:    v_cndmask_b32_e32 v8, v3, v2, vcc
1642; GCN-IR-NEXT:    s_movk_i32 s6, 0xffc5
1643; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, s6, v8
1644; GCN-IR-NEXT:    v_addc_u32_e64 v4, s[6:7], 0, -1, vcc
1645; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1646; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[3:4]
1647; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1648; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1649; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[3:4]
1650; GCN-IR-NEXT:    v_cndmask_b32_e64 v2, 24, 0, s[4:5]
1651; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1652; GCN-IR-NEXT:    v_mov_b32_e32 v5, v9
1653; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1654; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1655; GCN-IR-NEXT:    s_cbranch_execz BB11_6
1656; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1657; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 1, v3
1658; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, 0, v4, vcc
1659; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v3
1660; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[6:7], v[3:4]
1661; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1662; GCN-IR-NEXT:    v_lshl_b64 v[2:3], 24, v2
1663; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1664; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1665; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1666; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
1667; GCN-IR-NEXT:    s_cbranch_execz BB11_5
1668; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1669; GCN-IR-NEXT:    v_lshr_b64 v[10:11], 24, v6
1670; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, -1, v0
1671; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, -1, v1, vcc
1672; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, 58, v8
1673; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1674; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, 0, v9, vcc
1675; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1676; GCN-IR-NEXT:  BB11_3: ; %udiv-do-while
1677; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1678; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
1679; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1680; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v4
1681; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1682; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, v6, v10
1683; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, v7, v11, vcc
1684; GCN-IR-NEXT:    v_or_b32_e32 v2, v12, v2
1685; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v4
1686; GCN-IR-NEXT:    v_and_b32_e32 v15, v12, v0
1687; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v12
1688; GCN-IR-NEXT:    v_and_b32_e32 v14, v12, v1
1689; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
1690; GCN-IR-NEXT:    v_or_b32_e32 v3, v13, v3
1691; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
1692; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
1693; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
1694; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1695; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v15
1696; GCN-IR-NEXT:    v_mov_b32_e32 v9, v13
1697; GCN-IR-NEXT:    v_mov_b32_e32 v13, v5
1698; GCN-IR-NEXT:    v_subb_u32_e64 v11, s[4:5], v11, v14, s[4:5]
1699; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
1700; GCN-IR-NEXT:    v_mov_b32_e32 v12, v4
1701; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
1702; GCN-IR-NEXT:    s_cbranch_execnz BB11_3
1703; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1704; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1705; GCN-IR-NEXT:  BB11_5: ; %Flow3
1706; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1707; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1708; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1709; GCN-IR-NEXT:    v_or_b32_e32 v2, v4, v2
1710; GCN-IR-NEXT:  BB11_6: ; %Flow4
1711; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1712; GCN-IR-NEXT:    v_mul_lo_u32 v3, v0, v5
1713; GCN-IR-NEXT:    v_mul_hi_u32 v4, v0, v2
1714; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v2
1715; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, v2
1716; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1717; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
1718; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1719; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1720; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1721  %result = srem i64 24, %x
1722  ret i64 %result
1723}
1724
1725define i64 @v_test_srem_pow2_k_num_i64(i64 %x) {
1726; GCN-LABEL: v_test_srem_pow2_k_num_i64:
1727; GCN:       ; %bb.0:
1728; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1729; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1730; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1731; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1732; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1733; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1734; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1735; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1736; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1737; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1738; GCN-NEXT:    v_mov_b32_e32 v12, 0
1739; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
1740; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1741; GCN-NEXT:    v_mov_b32_e32 v11, 0
1742; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1743; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1744; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1745; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1746; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1747; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1748; GCN-NEXT:    v_mul_hi_u32 v6, v4, v2
1749; GCN-NEXT:    v_mul_lo_u32 v7, v4, v3
1750; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1751; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
1752; GCN-NEXT:    v_mul_lo_u32 v7, v4, v2
1753; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1754; GCN-NEXT:    v_mul_lo_u32 v9, v2, v6
1755; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
1756; GCN-NEXT:    v_mul_hi_u32 v10, v2, v7
1757; GCN-NEXT:    v_mul_hi_u32 v13, v3, v6
1758; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1759; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1760; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
1761; GCN-NEXT:    v_mul_hi_u32 v7, v3, v7
1762; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v8, vcc
1763; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
1764; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v7, vcc
1765; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v11, vcc
1766; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1767; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v6
1768; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v8, vcc
1769; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v3, v7, s[4:5]
1770; GCN-NEXT:    v_mul_lo_u32 v8, v4, v6
1771; GCN-NEXT:    v_mul_hi_u32 v9, v4, v2
1772; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1773; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1774; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1775; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
1776; GCN-NEXT:    v_mul_lo_u32 v10, v2, v5
1777; GCN-NEXT:    v_mul_hi_u32 v13, v2, v4
1778; GCN-NEXT:    v_mul_hi_u32 v14, v2, v5
1779; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
1780; GCN-NEXT:    v_mul_lo_u32 v4, v6, v4
1781; GCN-NEXT:    v_add_i32_e32 v10, vcc, v13, v10
1782; GCN-NEXT:    v_mul_hi_u32 v8, v6, v5
1783; GCN-NEXT:    v_addc_u32_e32 v13, vcc, v12, v14, vcc
1784; GCN-NEXT:    v_mul_lo_u32 v5, v6, v5
1785; GCN-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
1786; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v13, v9, vcc
1787; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v11, vcc
1788; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1789; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
1790; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
1791; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
1792; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1793; GCN-NEXT:    s_mov_b32 s4, 0x8000
1794; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1795; GCN-NEXT:    v_mul_hi_u32 v4, s4, v2
1796; GCN-NEXT:    v_mul_hi_u32 v5, s4, v3
1797; GCN-NEXT:    v_lshlrev_b32_e32 v6, 15, v3
1798; GCN-NEXT:    v_mul_hi_u32 v2, 0, v2
1799; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
1800; GCN-NEXT:    v_mul_hi_u32 v3, 0, v3
1801; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v5, vcc
1802; GCN-NEXT:    v_add_i32_e32 v4, vcc, 0, v4
1803; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v2, vcc
1804; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v11, vcc
1805; GCN-NEXT:    v_mul_lo_u32 v3, v0, v3
1806; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1807; GCN-NEXT:    v_mul_lo_u32 v5, v1, v2
1808; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
1809; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1810; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1811; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
1812; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s4, v2
1813; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
1814; GCN-NEXT:    v_sub_i32_e64 v5, s[4:5], v2, v0
1815; GCN-NEXT:    v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
1816; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v1
1817; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[6:7]
1818; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v5, v0
1819; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
1820; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v6, v1
1821; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
1822; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1823; GCN-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[6:7]
1824; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v5, v0
1825; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
1826; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1827; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1828; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
1829; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v0
1830; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1831; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1832; GCN-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
1833; GCN-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[4:5]
1834; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1835; GCN-NEXT:    v_cndmask_b32_e64 v1, v6, v4, s[4:5]
1836; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1837; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1838; GCN-NEXT:    s_setpc_b64 s[30:31]
1839;
1840; GCN-IR-LABEL: v_test_srem_pow2_k_num_i64:
1841; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1842; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1843; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1844; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1845; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
1846; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1847; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1848; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1849; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1850; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1851; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
1852; GCN-IR-NEXT:    v_cndmask_b32_e32 v8, v3, v2, vcc
1853; GCN-IR-NEXT:    s_movk_i32 s6, 0xffd0
1854; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, s6, v8
1855; GCN-IR-NEXT:    v_addc_u32_e64 v3, s[6:7], 0, -1, vcc
1856; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1857; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[2:3]
1858; GCN-IR-NEXT:    s_mov_b32 s8, 0x8000
1859; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1860; GCN-IR-NEXT:    v_mov_b32_e32 v4, s8
1861; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[2:3]
1862; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1863; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v4, 0, s[4:5]
1864; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1865; GCN-IR-NEXT:    s_mov_b32 s9, 0
1866; GCN-IR-NEXT:    v_mov_b32_e32 v5, v9
1867; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1868; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1869; GCN-IR-NEXT:    s_cbranch_execz BB12_6
1870; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1871; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 1, v2
1872; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, 0, v3, vcc
1873; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[6:7], v[2:3]
1874; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v2
1875; GCN-IR-NEXT:    v_lshl_b64 v[2:3], s[8:9], v2
1876; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1877; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1878; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1879; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1880; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
1881; GCN-IR-NEXT:    s_cbranch_execz BB12_5
1882; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1883; GCN-IR-NEXT:    s_mov_b32 s5, 0
1884; GCN-IR-NEXT:    s_mov_b32 s4, 0x8000
1885; GCN-IR-NEXT:    v_lshr_b64 v[10:11], s[4:5], v6
1886; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, -1, v0
1887; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, -1, v1, vcc
1888; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, 47, v8
1889; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1890; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, 0, v9, vcc
1891; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1892; GCN-IR-NEXT:  BB12_3: ; %udiv-do-while
1893; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1894; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
1895; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1896; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v4
1897; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1898; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, v6, v10
1899; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, v7, v11, vcc
1900; GCN-IR-NEXT:    v_or_b32_e32 v2, v12, v2
1901; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v4
1902; GCN-IR-NEXT:    v_and_b32_e32 v15, v12, v0
1903; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v12
1904; GCN-IR-NEXT:    v_and_b32_e32 v14, v12, v1
1905; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
1906; GCN-IR-NEXT:    v_or_b32_e32 v3, v13, v3
1907; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
1908; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
1909; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
1910; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1911; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v15
1912; GCN-IR-NEXT:    v_mov_b32_e32 v9, v13
1913; GCN-IR-NEXT:    v_mov_b32_e32 v13, v5
1914; GCN-IR-NEXT:    v_subb_u32_e64 v11, s[4:5], v11, v14, s[4:5]
1915; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
1916; GCN-IR-NEXT:    v_mov_b32_e32 v12, v4
1917; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
1918; GCN-IR-NEXT:    s_cbranch_execnz BB12_3
1919; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1920; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1921; GCN-IR-NEXT:  BB12_5: ; %Flow3
1922; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1923; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1924; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1925; GCN-IR-NEXT:    v_or_b32_e32 v4, v4, v2
1926; GCN-IR-NEXT:  BB12_6: ; %Flow4
1927; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1928; GCN-IR-NEXT:    v_mul_lo_u32 v2, v0, v5
1929; GCN-IR-NEXT:    v_mul_hi_u32 v3, v0, v4
1930; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v4
1931; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, v4
1932; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1933; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1934; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1935; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1936; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1937  %result = srem i64 32768, %x
1938  ret i64 %result
1939}
1940
1941define i64 @v_test_srem_pow2_k_den_i64(i64 %x) {
1942; GCN-LABEL: v_test_srem_pow2_k_den_i64:
1943; GCN:       ; %bb.0:
1944; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1945; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1946; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1947; GCN-NEXT:    v_add_i32_e32 v2, vcc, v0, v2
1948; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
1949; GCN-NEXT:    v_and_b32_e32 v2, 0xffff8000, v2
1950; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1951; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1952; GCN-NEXT:    s_setpc_b64 s[30:31]
1953;
1954; GCN-IR-LABEL: v_test_srem_pow2_k_den_i64:
1955; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1956; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1957; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1958; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1959; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1960; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
1961; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v0
1962; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1963; GCN-IR-NEXT:    v_add_i32_e64 v3, s[4:5], 32, v3
1964; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v1
1965; GCN-IR-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v1
1966; GCN-IR-NEXT:    v_cndmask_b32_e64 v8, v4, v3, s[4:5]
1967; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 48, v8
1968; GCN-IR-NEXT:    v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5]
1969; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1970; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
1971; GCN-IR-NEXT:    v_mov_b32_e32 v3, v2
1972; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1973; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1974; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1975; GCN-IR-NEXT:    v_cndmask_b32_e64 v7, v1, 0, s[4:5]
1976; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v0, 0, s[4:5]
1977; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1978; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1979; GCN-IR-NEXT:    s_cbranch_execz BB13_6
1980; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1981; GCN-IR-NEXT:    v_add_i32_e32 v9, vcc, 1, v4
1982; GCN-IR-NEXT:    v_addc_u32_e32 v10, vcc, 0, v5, vcc
1983; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[9:10], v[4:5]
1984; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v4
1985; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1986; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[0:1], v4
1987; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1988; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1989; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1990; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
1991; GCN-IR-NEXT:    s_cbranch_execz BB13_5
1992; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1993; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1994; GCN-IR-NEXT:    v_lshr_b64 v[10:11], v[0:1], v9
1995; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 0xffffffcf, v8
1996; GCN-IR-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, -1, vcc
1997; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1998; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
1999; GCN-IR-NEXT:  BB13_3: ; %udiv-do-while
2000; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
2001; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
2002; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
2003; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v6
2004; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
2005; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, s12, v10
2006; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, 0, v11, vcc
2007; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
2008; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v6
2009; GCN-IR-NEXT:    v_and_b32_e32 v14, 0x8000, v12
2010; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v12
2011; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
2012; GCN-IR-NEXT:    v_or_b32_e32 v5, v13, v5
2013; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
2014; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
2015; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
2016; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
2017; GCN-IR-NEXT:    v_mov_b32_e32 v9, v13
2018; GCN-IR-NEXT:    v_mov_b32_e32 v13, v7
2019; GCN-IR-NEXT:    v_mov_b32_e32 v15, 0
2020; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v14
2021; GCN-IR-NEXT:    v_subb_u32_e64 v11, s[4:5], v11, v15, s[4:5]
2022; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
2023; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
2024; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
2025; GCN-IR-NEXT:    s_cbranch_execnz BB13_3
2026; GCN-IR-NEXT:  ; %bb.4: ; %Flow
2027; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
2028; GCN-IR-NEXT:  BB13_5: ; %Flow3
2029; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
2030; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
2031; GCN-IR-NEXT:    v_or_b32_e32 v7, v7, v5
2032; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v4
2033; GCN-IR-NEXT:  BB13_6: ; %Flow4
2034; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
2035; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[6:7], 15
2036; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
2037; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
2038; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
2039; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v3
2040; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
2041; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
2042; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2043  %result = srem i64 %x, 32768
2044  ret i64 %result
2045}
2046
2047define amdgpu_kernel void @s_test_srem24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
2048; GCN-LABEL: s_test_srem24_k_num_i64:
2049; GCN:       ; %bb.0:
2050; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
2051; GCN-NEXT:    s_mov_b32 s6, 0x41c00000
2052; GCN-NEXT:    s_waitcnt lgkmcnt(0)
2053; GCN-NEXT:    s_ashr_i64 s[4:5], s[2:3], 40
2054; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
2055; GCN-NEXT:    s_ashr_i32 s5, s4, 30
2056; GCN-NEXT:    s_or_b32 s5, s5, 1
2057; GCN-NEXT:    s_mov_b32 s3, 0xf000
2058; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
2059; GCN-NEXT:    s_mov_b32 s2, -1
2060; GCN-NEXT:    v_mul_f32_e32 v1, s6, v1
2061; GCN-NEXT:    v_trunc_f32_e32 v1, v1
2062; GCN-NEXT:    v_mad_f32 v2, -v1, v0, s6
2063; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
2064; GCN-NEXT:    v_cmp_ge_f32_e64 s[6:7], |v2|, |v0|
2065; GCN-NEXT:    s_cmp_lg_u32 s6, 0
2066; GCN-NEXT:    s_cselect_b32 s5, s5, 0
2067; GCN-NEXT:    v_add_i32_e32 v0, vcc, s5, v1
2068; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
2069; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2070; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2071; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2072; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2073; GCN-NEXT:    s_endpgm
2074;
2075; GCN-IR-LABEL: s_test_srem24_k_num_i64:
2076; GCN-IR:       ; %bb.0:
2077; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
2078; GCN-IR-NEXT:    s_mov_b32 s6, 0x41c00000
2079; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
2080; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[2:3], 40
2081; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
2082; GCN-IR-NEXT:    s_ashr_i32 s5, s4, 30
2083; GCN-IR-NEXT:    s_or_b32 s5, s5, 1
2084; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
2085; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
2086; GCN-IR-NEXT:    s_mov_b32 s2, -1
2087; GCN-IR-NEXT:    v_mul_f32_e32 v1, s6, v1
2088; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
2089; GCN-IR-NEXT:    v_mad_f32 v2, -v1, v0, s6
2090; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
2091; GCN-IR-NEXT:    v_cmp_ge_f32_e64 s[6:7], |v2|, |v0|
2092; GCN-IR-NEXT:    s_cmp_lg_u32 s6, 0
2093; GCN-IR-NEXT:    s_cselect_b32 s5, s5, 0
2094; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, s5, v1
2095; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
2096; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2097; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2098; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2099; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2100; GCN-IR-NEXT:    s_endpgm
2101  %x.shr = ashr i64 %x, 40
2102  %result = srem i64 24, %x.shr
2103  store i64 %result, i64 addrspace(1)* %out
2104  ret void
2105}
2106
2107define amdgpu_kernel void @s_test_srem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
2108; GCN-LABEL: s_test_srem24_k_den_i64:
2109; GCN:       ; %bb.0:
2110; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
2111; GCN-NEXT:    s_mov_b32 s1, 0x46b6fe00
2112; GCN-NEXT:    s_mov_b32 s3, 0xf000
2113; GCN-NEXT:    s_mov_b32 s2, -1
2114; GCN-NEXT:    s_waitcnt lgkmcnt(0)
2115; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
2116; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s6
2117; GCN-NEXT:    s_ashr_i32 s0, s6, 30
2118; GCN-NEXT:    s_or_b32 s7, s0, 1
2119; GCN-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
2120; GCN-NEXT:    v_trunc_f32_e32 v1, v1
2121; GCN-NEXT:    v_mad_f32 v0, -v1, s1, v0
2122; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
2123; GCN-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v0|, s1
2124; GCN-NEXT:    s_cmp_lg_u32 s0, 0
2125; GCN-NEXT:    s_cselect_b32 s0, s7, 0
2126; GCN-NEXT:    v_add_i32_e32 v0, vcc, s0, v1
2127; GCN-NEXT:    s_movk_i32 s0, 0x5b7f
2128; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
2129; GCN-NEXT:    s_mov_b32 s0, s4
2130; GCN-NEXT:    s_mov_b32 s1, s5
2131; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
2132; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2133; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2134; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2135; GCN-NEXT:    s_endpgm
2136;
2137; GCN-IR-LABEL: s_test_srem24_k_den_i64:
2138; GCN-IR:       ; %bb.0:
2139; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
2140; GCN-IR-NEXT:    s_mov_b32 s1, 0x46b6fe00
2141; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
2142; GCN-IR-NEXT:    s_mov_b32 s2, -1
2143; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
2144; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
2145; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s6
2146; GCN-IR-NEXT:    s_ashr_i32 s0, s6, 30
2147; GCN-IR-NEXT:    s_or_b32 s7, s0, 1
2148; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
2149; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
2150; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s1, v0
2151; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
2152; GCN-IR-NEXT:    v_cmp_ge_f32_e64 s[0:1], |v0|, s1
2153; GCN-IR-NEXT:    s_cmp_lg_u32 s0, 0
2154; GCN-IR-NEXT:    s_cselect_b32 s0, s7, 0
2155; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, s0, v1
2156; GCN-IR-NEXT:    s_movk_i32 s0, 0x5b7f
2157; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
2158; GCN-IR-NEXT:    s_mov_b32 s0, s4
2159; GCN-IR-NEXT:    s_mov_b32 s1, s5
2160; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
2161; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2162; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2163; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2164; GCN-IR-NEXT:    s_endpgm
2165  %x.shr = ashr i64 %x, 40
2166  %result = srem i64 %x.shr, 23423
2167  store i64 %result, i64 addrspace(1)* %out
2168  ret void
2169}
2170
2171define i64 @v_test_srem24_k_num_i64(i64 %x) {
2172; GCN-LABEL: v_test_srem24_k_num_i64:
2173; GCN:       ; %bb.0:
2174; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2175; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2176; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
2177; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
2178; GCN-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2179; GCN-NEXT:    v_or_b32_e32 v3, 1, v3
2180; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2181; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
2182; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2183; GCN-NEXT:    v_mad_f32 v4, -v2, v1, s4
2184; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2185; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2186; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2187; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2188; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
2189; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2190; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2191; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2192; GCN-NEXT:    s_setpc_b64 s[30:31]
2193;
2194; GCN-IR-LABEL: v_test_srem24_k_num_i64:
2195; GCN-IR:       ; %bb.0:
2196; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2197; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2198; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
2199; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2200; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2201; GCN-IR-NEXT:    v_or_b32_e32 v3, 1, v3
2202; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2203; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
2204; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2205; GCN-IR-NEXT:    v_mad_f32 v4, -v2, v1, s4
2206; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2207; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2208; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2209; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2210; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
2211; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2212; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2213; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2214; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2215  %x.shr = ashr i64 %x, 40
2216  %result = srem i64 24, %x.shr
2217  ret i64 %result
2218}
2219
2220define i64 @v_test_srem24_pow2_k_num_i64(i64 %x) {
2221; GCN-LABEL: v_test_srem24_pow2_k_num_i64:
2222; GCN:       ; %bb.0:
2223; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2224; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2225; GCN-NEXT:    s_mov_b32 s4, 0x47000000
2226; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
2227; GCN-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2228; GCN-NEXT:    v_or_b32_e32 v3, 1, v3
2229; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2230; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
2231; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2232; GCN-NEXT:    v_mad_f32 v4, -v2, v1, s4
2233; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2234; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2235; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2236; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2237; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
2238; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
2239; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2240; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2241; GCN-NEXT:    s_setpc_b64 s[30:31]
2242;
2243; GCN-IR-LABEL: v_test_srem24_pow2_k_num_i64:
2244; GCN-IR:       ; %bb.0:
2245; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2246; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2247; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2248; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2249; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2250; GCN-IR-NEXT:    v_or_b32_e32 v3, 1, v3
2251; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2252; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
2253; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2254; GCN-IR-NEXT:    v_mad_f32 v4, -v2, v1, s4
2255; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2256; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2257; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2258; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2259; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
2260; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
2261; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2262; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2263; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2264  %x.shr = ashr i64 %x, 40
2265  %result = srem i64 32768, %x.shr
2266  ret i64 %result
2267}
2268
2269define i64 @v_test_srem24_pow2_k_den_i64(i64 %x) {
2270; GCN-LABEL: v_test_srem24_pow2_k_den_i64:
2271; GCN:       ; %bb.0:
2272; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2273; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2274; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v1
2275; GCN-NEXT:    v_add_i32_e32 v2, vcc, v0, v2
2276; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
2277; GCN-NEXT:    v_and_b32_e32 v2, 0xffff8000, v2
2278; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
2279; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
2280; GCN-NEXT:    s_setpc_b64 s[30:31]
2281;
2282; GCN-IR-LABEL: v_test_srem24_pow2_k_den_i64:
2283; GCN-IR:       ; %bb.0:
2284; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2285; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2286; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2287; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2288; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 30, v0
2289; GCN-IR-NEXT:    v_or_b32_e32 v2, 1, v2
2290; GCN-IR-NEXT:    v_mul_f32_e32 v3, 0x38000000, v1
2291; GCN-IR-NEXT:    v_trunc_f32_e32 v3, v3
2292; GCN-IR-NEXT:    v_mad_f32 v1, -v3, s4, v1
2293; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v3
2294; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
2295; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
2296; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
2297; GCN-IR-NEXT:    v_lshlrev_b32_e32 v1, 15, v1
2298; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
2299; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2300; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2301; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2302  %x.shr = ashr i64 %x, 40
2303  %result = srem i64 %x.shr, 32768
2304  ret i64 %result
2305}
2306