1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_srem(i64 addrspace(1)* %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_srem:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
9; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
10; GCN-NEXT:    s_mov_b32 s7, 0xf000
11; GCN-NEXT:    s_mov_b32 s6, -1
12; GCN-NEXT:    s_waitcnt lgkmcnt(0)
13; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
14; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
15; GCN-NEXT:    s_sub_u32 s0, 0, s12
16; GCN-NEXT:    s_subb_u32 s1, 0, s13
17; GCN-NEXT:    s_mov_b32 s4, s8
18; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
19; GCN-NEXT:    v_rcp_f32_e32 v0, v0
20; GCN-NEXT:    v_mov_b32_e32 v1, 0
21; GCN-NEXT:    s_mov_b32 s5, s9
22; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
23; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
24; GCN-NEXT:    v_trunc_f32_e32 v2, v2
25; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
26; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
27; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
28; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
29; GCN-NEXT:    v_mul_hi_u32 v4, s0, v0
30; GCN-NEXT:    v_mul_lo_u32 v6, s1, v0
31; GCN-NEXT:    v_mul_lo_u32 v5, s0, v0
32; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
33; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
34; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
35; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
36; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
37; GCN-NEXT:    v_mul_lo_u32 v7, v2, v5
38; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
39; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
40; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
41; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
42; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
43; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
44; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
45; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
46; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
47; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
48; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
49; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
50; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
51; GCN-NEXT:    v_mul_hi_u32 v4, s0, v0
52; GCN-NEXT:    v_mul_lo_u32 v5, s1, v0
53; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
54; GCN-NEXT:    v_mul_lo_u32 v4, s0, v0
55; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
56; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
57; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
58; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
59; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
60; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
61; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
62; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
63; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
64; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
65; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
66; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
67; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v1, vcc
68; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
69; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
70; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
71; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
72; GCN-NEXT:    v_mul_lo_u32 v3, s10, v2
73; GCN-NEXT:    v_mul_hi_u32 v4, s10, v0
74; GCN-NEXT:    v_mul_hi_u32 v5, s10, v2
75; GCN-NEXT:    v_mul_hi_u32 v6, s11, v2
76; GCN-NEXT:    v_mul_lo_u32 v2, s11, v2
77; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
78; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
79; GCN-NEXT:    v_mul_lo_u32 v5, s11, v0
80; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
81; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
82; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
83; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
84; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
85; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
86; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
87; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
88; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
89; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
90; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
91; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
92; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s11, v1
93; GCN-NEXT:    v_mov_b32_e32 v3, s13
94; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s10, v0
95; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
96; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
97; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
98; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
99; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
100; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
101; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
102; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
103; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
104; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
105; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
106; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
107; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
108; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
109; GCN-NEXT:    v_mov_b32_e32 v5, s11
110; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
111; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
112; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
113; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
114; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
115; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
116; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
117; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
118; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
119; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
120; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
121; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
122; GCN-NEXT:    s_endpgm
123;
124; GCN-IR-LABEL: s_test_srem:
125; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
126; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
127; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
128; GCN-IR-NEXT:    s_mov_b64 s[6:7], 0
129; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
130; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[4:5], 0
131; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
132; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s4
133; GCN-IR-NEXT:    s_add_i32 s14, s12, 32
134; GCN-IR-NEXT:    s_or_b64 s[12:13], s[8:9], s[10:11]
135; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s5
136; GCN-IR-NEXT:    s_min_u32 s10, s14, s8
137; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s2
138; GCN-IR-NEXT:    s_add_i32 s8, s8, 32
139; GCN-IR-NEXT:    s_flbit_i32_b32 s9, s3
140; GCN-IR-NEXT:    s_min_u32 s14, s8, s9
141; GCN-IR-NEXT:    s_sub_u32 s8, s10, s14
142; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
143; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[16:17], s[8:9], 63
144; GCN-IR-NEXT:    s_mov_b32 s11, 0
145; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[16:17]
146; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[16:17], s[8:9], 63
147; GCN-IR-NEXT:    s_xor_b64 s[18:19], s[12:13], -1
148; GCN-IR-NEXT:    s_and_b64 s[16:17], s[18:19], s[16:17]
149; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[16:17]
150; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_5
151; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
152; GCN-IR-NEXT:    s_add_u32 s12, s8, 1
153; GCN-IR-NEXT:    s_addc_u32 s13, s9, 0
154; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[16:17], s[12:13], 0
155; GCN-IR-NEXT:    s_sub_i32 s8, 63, s8
156; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[16:17]
157; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[2:3], s8
158; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_4
159; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
160; GCN-IR-NEXT:    s_lshr_b64 s[12:13], s[2:3], s12
161; GCN-IR-NEXT:    s_add_u32 s16, s4, -1
162; GCN-IR-NEXT:    s_addc_u32 s17, s5, -1
163; GCN-IR-NEXT:    s_not_b64 s[6:7], s[10:11]
164; GCN-IR-NEXT:    s_mov_b32 s15, s11
165; GCN-IR-NEXT:    s_add_u32 s10, s6, s14
166; GCN-IR-NEXT:    s_addc_u32 s11, s7, s11
167; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
168; GCN-IR-NEXT:    s_mov_b32 s7, 0
169; GCN-IR-NEXT:  .LBB0_3: ; %udiv-do-while
170; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
171; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
172; GCN-IR-NEXT:    s_lshr_b32 s6, s9, 31
173; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
174; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[6:7]
175; GCN-IR-NEXT:    s_or_b64 s[8:9], s[14:15], s[8:9]
176; GCN-IR-NEXT:    s_sub_u32 s6, s16, s12
177; GCN-IR-NEXT:    s_subb_u32 s6, s17, s13
178; GCN-IR-NEXT:    s_ashr_i32 s14, s6, 31
179; GCN-IR-NEXT:    s_mov_b32 s15, s14
180; GCN-IR-NEXT:    s_and_b32 s6, s14, 1
181; GCN-IR-NEXT:    s_and_b64 s[14:15], s[14:15], s[4:5]
182; GCN-IR-NEXT:    s_sub_u32 s12, s12, s14
183; GCN-IR-NEXT:    s_subb_u32 s13, s13, s15
184; GCN-IR-NEXT:    s_add_u32 s10, s10, 1
185; GCN-IR-NEXT:    s_addc_u32 s11, s11, 0
186; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[18:19], s[10:11], 0
187; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[6:7]
188; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[18:19]
189; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_3
190; GCN-IR-NEXT:  .LBB0_4: ; %Flow6
191; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
192; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], s[8:9]
193; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
194; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
195; GCN-IR-NEXT:    s_branch .LBB0_6
196; GCN-IR-NEXT:  .LBB0_5:
197; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
198; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[12:13]
199; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
200; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[12:13]
201; GCN-IR-NEXT:  .LBB0_6: ; %udiv-end
202; GCN-IR-NEXT:    v_mul_lo_u32 v1, s4, v1
203; GCN-IR-NEXT:    v_mul_hi_u32 v2, s4, v0
204; GCN-IR-NEXT:    v_mul_lo_u32 v3, s5, v0
205; GCN-IR-NEXT:    v_mul_lo_u32 v0, s4, v0
206; GCN-IR-NEXT:    s_mov_b32 s11, 0xf000
207; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
208; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
209; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
210; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
211; GCN-IR-NEXT:    s_mov_b32 s10, -1
212; GCN-IR-NEXT:    s_mov_b32 s8, s0
213; GCN-IR-NEXT:    s_mov_b32 s9, s1
214; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
215; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
216; GCN-IR-NEXT:    s_endpgm
217  %result = urem i64 %x, %y
218  store i64 %result, i64 addrspace(1)* %out
219  ret void
220}
221
222define i64 @v_test_srem(i64 %x, i64 %y) {
223; GCN-LABEL: v_test_srem:
224; GCN:       ; %bb.0:
225; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
226; GCN-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
227; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
228; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
229; GCN-NEXT:    v_xor_b32_e32 v3, v3, v4
230; GCN-NEXT:    v_xor_b32_e32 v2, v2, v4
231; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v2
232; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v3
233; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v2
234; GCN-NEXT:    v_subb_u32_e32 v7, vcc, 0, v3, vcc
235; GCN-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
236; GCN-NEXT:    v_rcp_f32_e32 v4, v4
237; GCN-NEXT:    v_mov_b32_e32 v13, 0
238; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
239; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
240; GCN-NEXT:    v_trunc_f32_e32 v5, v5
241; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
242; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
243; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
244; GCN-NEXT:    v_mul_hi_u32 v8, v6, v4
245; GCN-NEXT:    v_mul_lo_u32 v9, v6, v5
246; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
247; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
248; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
249; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
250; GCN-NEXT:    v_mul_lo_u32 v10, v4, v8
251; GCN-NEXT:    v_mul_hi_u32 v11, v4, v9
252; GCN-NEXT:    v_mul_hi_u32 v12, v4, v8
253; GCN-NEXT:    v_mul_hi_u32 v14, v5, v8
254; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
255; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
256; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
257; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
258; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
259; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
260; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v11, v9, vcc
261; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v13, vcc
262; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
263; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
264; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
265; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v9, vcc
266; GCN-NEXT:    v_mul_lo_u32 v8, v6, v5
267; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
268; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
269; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
270; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
271; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
272; GCN-NEXT:    v_mul_lo_u32 v10, v4, v7
273; GCN-NEXT:    v_mul_hi_u32 v11, v4, v6
274; GCN-NEXT:    v_mul_hi_u32 v12, v4, v7
275; GCN-NEXT:    v_mul_hi_u32 v9, v5, v6
276; GCN-NEXT:    v_mul_lo_u32 v6, v5, v6
277; GCN-NEXT:    v_mul_hi_u32 v8, v5, v7
278; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
279; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
280; GCN-NEXT:    v_mul_lo_u32 v7, v5, v7
281; GCN-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
282; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
283; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v8, v13, vcc
284; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
285; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
286; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
287; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
288; GCN-NEXT:    v_ashrrev_i32_e32 v6, 31, v1
289; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
290; GCN-NEXT:    v_xor_b32_e32 v0, v0, v6
291; GCN-NEXT:    v_mul_lo_u32 v7, v0, v5
292; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
293; GCN-NEXT:    v_mul_hi_u32 v9, v0, v5
294; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v6, vcc
295; GCN-NEXT:    v_xor_b32_e32 v1, v1, v6
296; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
297; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
298; GCN-NEXT:    v_mul_lo_u32 v9, v1, v4
299; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
300; GCN-NEXT:    v_mul_hi_u32 v10, v1, v5
301; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
302; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
303; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
304; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v10, v13, vcc
305; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
306; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
307; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
308; GCN-NEXT:    v_mul_hi_u32 v7, v2, v4
309; GCN-NEXT:    v_mul_lo_u32 v8, v3, v4
310; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
311; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
312; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
313; GCN-NEXT:    v_sub_i32_e32 v7, vcc, v1, v5
314; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
315; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v7, v3, vcc
316; GCN-NEXT:    v_sub_i32_e64 v7, s[4:5], v0, v2
317; GCN-NEXT:    v_subbrev_u32_e64 v8, s[6:7], 0, v4, s[4:5]
318; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v8, v3
319; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[6:7]
320; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v7, v2
321; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
322; GCN-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[6:7]
323; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v8, v3
324; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v3, s[4:5]
325; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
326; GCN-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[6:7]
327; GCN-NEXT:    v_sub_i32_e64 v10, s[4:5], v7, v2
328; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
329; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
330; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
331; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
332; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
333; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v9
334; GCN-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
335; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
336; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v10, s[4:5]
337; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v4, s[4:5]
338; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
339; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
340; GCN-NEXT:    v_xor_b32_e32 v0, v0, v6
341; GCN-NEXT:    v_xor_b32_e32 v1, v1, v6
342; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
343; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
344; GCN-NEXT:    s_setpc_b64 s[30:31]
345;
346; GCN-IR-LABEL: v_test_srem:
347; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
348; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
349; GCN-IR-NEXT:    v_ashrrev_i32_e32 v4, 31, v1
350; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v4
351; GCN-IR-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
352; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v4
353; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
354; GCN-IR-NEXT:    v_xor_b32_e32 v2, v2, v6
355; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc
356; GCN-IR-NEXT:    v_xor_b32_e32 v3, v3, v6
357; GCN-IR-NEXT:    v_sub_i32_e32 v5, vcc, v2, v6
358; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v3, v6, vcc
359; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[5:6]
360; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
361; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v5
362; GCN-IR-NEXT:    s_or_b64 s[6:7], vcc, s[4:5]
363; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, 32, v3
364; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v6
365; GCN-IR-NEXT:    v_min_u32_e32 v3, v3, v7
366; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v0
367; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 32, v7
368; GCN-IR-NEXT:    v_ffbh_u32_e32 v8, v1
369; GCN-IR-NEXT:    v_min_u32_e32 v12, v7, v8
370; GCN-IR-NEXT:    v_sub_i32_e32 v7, vcc, v3, v12
371; GCN-IR-NEXT:    v_subb_u32_e64 v8, s[4:5], 0, 0, vcc
372; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[7:8]
373; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[4:5], 63, v[7:8]
374; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], vcc
375; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
376; GCN-IR-NEXT:    s_xor_b64 s[8:9], s[6:7], -1
377; GCN-IR-NEXT:    v_mov_b32_e32 v2, v4
378; GCN-IR-NEXT:    v_mov_b32_e32 v13, v11
379; GCN-IR-NEXT:    v_cndmask_b32_e64 v10, v1, 0, s[6:7]
380; GCN-IR-NEXT:    s_and_b64 s[4:5], s[8:9], s[4:5]
381; GCN-IR-NEXT:    v_cndmask_b32_e64 v9, v0, 0, s[6:7]
382; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
383; GCN-IR-NEXT:    s_cbranch_execz .LBB1_6
384; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
385; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, 1, v7
386; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, 0, v8, vcc
387; GCN-IR-NEXT:    v_sub_i32_e64 v7, s[4:5], 63, v7
388; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[14:15]
389; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[0:1], v7
390; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
391; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
392; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
393; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
394; GCN-IR-NEXT:    s_cbranch_execz .LBB1_5
395; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
396; GCN-IR-NEXT:    v_add_i32_e32 v18, vcc, -1, v5
397; GCN-IR-NEXT:    v_addc_u32_e32 v19, vcc, -1, v6, vcc
398; GCN-IR-NEXT:    v_not_b32_e32 v3, v3
399; GCN-IR-NEXT:    v_lshr_b64 v[14:15], v[0:1], v14
400; GCN-IR-NEXT:    v_not_b32_e32 v9, v11
401; GCN-IR-NEXT:    v_add_i32_e32 v11, vcc, v3, v12
402; GCN-IR-NEXT:    v_mov_b32_e32 v16, 0
403; GCN-IR-NEXT:    v_addc_u32_e32 v12, vcc, v9, v13, vcc
404; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
405; GCN-IR-NEXT:    v_mov_b32_e32 v17, 0
406; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
407; GCN-IR-NEXT:  .LBB1_3: ; %udiv-do-while
408; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
409; GCN-IR-NEXT:    v_lshl_b64 v[14:15], v[14:15], 1
410; GCN-IR-NEXT:    v_lshrrev_b32_e32 v3, 31, v8
411; GCN-IR-NEXT:    v_or_b32_e32 v3, v14, v3
412; GCN-IR-NEXT:    v_sub_i32_e32 v9, vcc, v18, v3
413; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
414; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, v19, v15, vcc
415; GCN-IR-NEXT:    v_ashrrev_i32_e32 v13, 31, v9
416; GCN-IR-NEXT:    v_add_i32_e32 v11, vcc, 1, v11
417; GCN-IR-NEXT:    v_or_b32_e32 v7, v16, v7
418; GCN-IR-NEXT:    v_and_b32_e32 v9, 1, v13
419; GCN-IR-NEXT:    v_and_b32_e32 v16, v13, v6
420; GCN-IR-NEXT:    v_and_b32_e32 v13, v13, v5
421; GCN-IR-NEXT:    v_addc_u32_e32 v12, vcc, 0, v12, vcc
422; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[11:12]
423; GCN-IR-NEXT:    v_sub_i32_e64 v14, s[4:5], v3, v13
424; GCN-IR-NEXT:    v_or_b32_e32 v8, v17, v8
425; GCN-IR-NEXT:    v_subb_u32_e64 v15, s[4:5], v15, v16, s[4:5]
426; GCN-IR-NEXT:    v_mov_b32_e32 v17, v10
427; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
428; GCN-IR-NEXT:    v_mov_b32_e32 v16, v9
429; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
430; GCN-IR-NEXT:    s_cbranch_execnz .LBB1_3
431; GCN-IR-NEXT:  ; %bb.4: ; %Flow
432; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
433; GCN-IR-NEXT:  .LBB1_5: ; %Flow3
434; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
435; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
436; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v8
437; GCN-IR-NEXT:    v_or_b32_e32 v9, v9, v7
438; GCN-IR-NEXT:  .LBB1_6: ; %Flow4
439; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
440; GCN-IR-NEXT:    v_mul_lo_u32 v3, v5, v10
441; GCN-IR-NEXT:    v_mul_hi_u32 v7, v5, v9
442; GCN-IR-NEXT:    v_mul_lo_u32 v6, v6, v9
443; GCN-IR-NEXT:    v_mul_lo_u32 v5, v5, v9
444; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
445; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
446; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v5
447; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
448; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v4
449; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
450; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
451; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
452; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
453  %result = srem i64 %x, %y
454  ret i64 %result
455}
456
457define amdgpu_kernel void @s_test_srem23_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
458; GCN-LABEL: s_test_srem23_64:
459; GCN:       ; %bb.0:
460; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
461; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
462; GCN-NEXT:    s_mov_b32 s7, 0xf000
463; GCN-NEXT:    s_mov_b32 s6, -1
464; GCN-NEXT:    s_waitcnt lgkmcnt(0)
465; GCN-NEXT:    s_ashr_i64 s[4:5], s[4:5], 41
466; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
467; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 41
468; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s2
469; GCN-NEXT:    s_xor_b32 s3, s2, s4
470; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
471; GCN-NEXT:    s_ashr_i32 s3, s3, 30
472; GCN-NEXT:    s_or_b32 s3, s3, 1
473; GCN-NEXT:    v_mov_b32_e32 v3, s3
474; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
475; GCN-NEXT:    v_trunc_f32_e32 v2, v2
476; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
477; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
478; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
479; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
480; GCN-NEXT:    s_mov_b32 s5, s1
481; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
482; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
483; GCN-NEXT:    s_mov_b32 s4, s0
484; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
485; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 23
486; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
487; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
488; GCN-NEXT:    s_endpgm
489;
490; GCN-IR-LABEL: s_test_srem23_64:
491; GCN-IR:       ; %bb.0:
492; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
493; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
494; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
495; GCN-IR-NEXT:    s_mov_b32 s6, -1
496; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
497; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[4:5], 41
498; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
499; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 41
500; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s2
501; GCN-IR-NEXT:    s_xor_b32 s3, s2, s4
502; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
503; GCN-IR-NEXT:    s_ashr_i32 s3, s3, 30
504; GCN-IR-NEXT:    s_or_b32 s3, s3, 1
505; GCN-IR-NEXT:    v_mov_b32_e32 v3, s3
506; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
507; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
508; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
509; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
510; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
511; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
512; GCN-IR-NEXT:    s_mov_b32 s5, s1
513; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
514; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
515; GCN-IR-NEXT:    s_mov_b32 s4, s0
516; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
517; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 23
518; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
519; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
520; GCN-IR-NEXT:    s_endpgm
521  %1 = ashr i64 %x, 41
522  %2 = ashr i64 %y, 41
523  %result = srem i64 %1, %2
524  store i64 %result, i64 addrspace(1)* %out
525  ret void
526}
527
528define amdgpu_kernel void @s_test_srem24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
529; GCN-LABEL: s_test_srem24_64:
530; GCN:       ; %bb.0:
531; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
532; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
533; GCN-NEXT:    s_mov_b32 s7, 0xf000
534; GCN-NEXT:    s_mov_b32 s6, -1
535; GCN-NEXT:    s_waitcnt lgkmcnt(0)
536; GCN-NEXT:    s_ashr_i64 s[4:5], s[4:5], 40
537; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
538; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
539; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s2
540; GCN-NEXT:    s_xor_b32 s3, s2, s4
541; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
542; GCN-NEXT:    s_ashr_i32 s3, s3, 30
543; GCN-NEXT:    s_or_b32 s3, s3, 1
544; GCN-NEXT:    v_mov_b32_e32 v3, s3
545; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
546; GCN-NEXT:    v_trunc_f32_e32 v2, v2
547; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
548; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
549; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
550; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
551; GCN-NEXT:    s_mov_b32 s5, s1
552; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
553; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
554; GCN-NEXT:    s_mov_b32 s4, s0
555; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
556; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
557; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
558; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
559; GCN-NEXT:    s_endpgm
560;
561; GCN-IR-LABEL: s_test_srem24_64:
562; GCN-IR:       ; %bb.0:
563; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
564; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
565; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
566; GCN-IR-NEXT:    s_mov_b32 s6, -1
567; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
568; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[4:5], 40
569; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
570; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
571; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s2
572; GCN-IR-NEXT:    s_xor_b32 s3, s2, s4
573; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
574; GCN-IR-NEXT:    s_ashr_i32 s3, s3, 30
575; GCN-IR-NEXT:    s_or_b32 s3, s3, 1
576; GCN-IR-NEXT:    v_mov_b32_e32 v3, s3
577; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
578; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
579; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
580; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
581; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
582; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
583; GCN-IR-NEXT:    s_mov_b32 s5, s1
584; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
585; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
586; GCN-IR-NEXT:    s_mov_b32 s4, s0
587; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
588; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
589; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
590; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
591; GCN-IR-NEXT:    s_endpgm
592  %1 = ashr i64 %x, 40
593  %2 = ashr i64 %y, 40
594  %result = srem i64 %1, %2
595  store i64 %result, i64 addrspace(1)* %out
596  ret void
597}
598
599define i64 @v_test_srem24_64(i64 %x, i64 %y) {
600; GCN-LABEL: v_test_srem24_64:
601; GCN:       ; %bb.0:
602; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
603; GCN-NEXT:    v_ashr_i64 v[2:3], v[2:3], 40
604; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
605; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
606; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
607; GCN-NEXT:    v_xor_b32_e32 v5, v0, v2
608; GCN-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
609; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v3
610; GCN-NEXT:    v_or_b32_e32 v5, 1, v5
611; GCN-NEXT:    v_mul_f32_e32 v4, v1, v4
612; GCN-NEXT:    v_trunc_f32_e32 v4, v4
613; GCN-NEXT:    v_mad_f32 v1, -v4, v3, v1
614; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
615; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
616; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
617; GCN-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
618; GCN-NEXT:    v_mul_lo_u32 v1, v1, v2
619; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
620; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
621; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
622; GCN-NEXT:    s_setpc_b64 s[30:31]
623;
624; GCN-IR-LABEL: v_test_srem24_64:
625; GCN-IR:       ; %bb.0:
626; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
627; GCN-IR-NEXT:    v_ashr_i64 v[2:3], v[2:3], 40
628; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
629; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v3, v2
630; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
631; GCN-IR-NEXT:    v_xor_b32_e32 v5, v0, v2
632; GCN-IR-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
633; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v4, v3
634; GCN-IR-NEXT:    v_or_b32_e32 v5, 1, v5
635; GCN-IR-NEXT:    v_mul_f32_e32 v4, v1, v4
636; GCN-IR-NEXT:    v_trunc_f32_e32 v4, v4
637; GCN-IR-NEXT:    v_mad_f32 v1, -v4, v3, v1
638; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v4, v4
639; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
640; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
641; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
642; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v2
643; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
644; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
645; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
646; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
647  %1 = ashr i64 %x, 40
648  %2 = ashr i64 %y, 40
649  %result = srem i64 %1, %2
650  ret i64 %result
651}
652
653define amdgpu_kernel void @s_test_srem25_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
654; GCN-LABEL: s_test_srem25_64:
655; GCN:       ; %bb.0:
656; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
657; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
658; GCN-NEXT:    s_mov_b32 s7, 0xf000
659; GCN-NEXT:    s_mov_b32 s6, -1
660; GCN-NEXT:    s_waitcnt lgkmcnt(0)
661; GCN-NEXT:    s_ashr_i64 s[4:5], s[4:5], 39
662; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
663; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 39
664; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s2
665; GCN-NEXT:    s_xor_b32 s3, s2, s4
666; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
667; GCN-NEXT:    s_ashr_i32 s3, s3, 30
668; GCN-NEXT:    s_or_b32 s3, s3, 1
669; GCN-NEXT:    v_mov_b32_e32 v3, s3
670; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
671; GCN-NEXT:    v_trunc_f32_e32 v2, v2
672; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
673; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
674; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
675; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
676; GCN-NEXT:    s_mov_b32 s5, s1
677; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
678; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
679; GCN-NEXT:    s_mov_b32 s4, s0
680; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
681; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 25
682; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
683; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
684; GCN-NEXT:    s_endpgm
685;
686; GCN-IR-LABEL: s_test_srem25_64:
687; GCN-IR:       ; %bb.0:
688; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
689; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
690; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
691; GCN-IR-NEXT:    s_mov_b32 s6, -1
692; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
693; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[4:5], 39
694; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
695; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 39
696; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s2
697; GCN-IR-NEXT:    s_xor_b32 s3, s2, s4
698; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
699; GCN-IR-NEXT:    s_ashr_i32 s3, s3, 30
700; GCN-IR-NEXT:    s_or_b32 s3, s3, 1
701; GCN-IR-NEXT:    v_mov_b32_e32 v3, s3
702; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
703; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
704; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
705; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
706; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
707; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
708; GCN-IR-NEXT:    s_mov_b32 s5, s1
709; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
710; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
711; GCN-IR-NEXT:    s_mov_b32 s4, s0
712; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
713; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 25
714; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
715; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
716; GCN-IR-NEXT:    s_endpgm
717  %1 = ashr i64 %x, 39
718  %2 = ashr i64 %y, 39
719  %result = srem i64 %1, %2
720  store i64 %result, i64 addrspace(1)* %out
721  ret void
722}
723
724define amdgpu_kernel void @s_test_srem31_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
725; GCN-LABEL: s_test_srem31_64:
726; GCN:       ; %bb.0:
727; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
728; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
729; GCN-NEXT:    s_mov_b32 s7, 0xf000
730; GCN-NEXT:    s_mov_b32 s6, -1
731; GCN-NEXT:    s_waitcnt lgkmcnt(0)
732; GCN-NEXT:    s_ashr_i64 s[4:5], s[4:5], 33
733; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
734; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 33
735; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s2
736; GCN-NEXT:    s_xor_b32 s3, s2, s4
737; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
738; GCN-NEXT:    s_ashr_i32 s3, s3, 30
739; GCN-NEXT:    s_or_b32 s3, s3, 1
740; GCN-NEXT:    v_mov_b32_e32 v3, s3
741; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
742; GCN-NEXT:    v_trunc_f32_e32 v2, v2
743; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
744; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
745; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
746; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
747; GCN-NEXT:    s_mov_b32 s5, s1
748; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
749; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
750; GCN-NEXT:    s_mov_b32 s4, s0
751; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
752; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 31
753; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
754; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
755; GCN-NEXT:    s_endpgm
756;
757; GCN-IR-LABEL: s_test_srem31_64:
758; GCN-IR:       ; %bb.0:
759; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
760; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
761; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
762; GCN-IR-NEXT:    s_mov_b32 s6, -1
763; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
764; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[4:5], 33
765; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
766; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 33
767; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s2
768; GCN-IR-NEXT:    s_xor_b32 s3, s2, s4
769; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
770; GCN-IR-NEXT:    s_ashr_i32 s3, s3, 30
771; GCN-IR-NEXT:    s_or_b32 s3, s3, 1
772; GCN-IR-NEXT:    v_mov_b32_e32 v3, s3
773; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
774; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
775; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
776; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
777; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
778; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
779; GCN-IR-NEXT:    s_mov_b32 s5, s1
780; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
781; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
782; GCN-IR-NEXT:    s_mov_b32 s4, s0
783; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
784; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 31
785; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
786; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
787; GCN-IR-NEXT:    s_endpgm
788  %1 = ashr i64 %x, 33
789  %2 = ashr i64 %y, 33
790  %result = srem i64 %1, %2
791  store i64 %result, i64 addrspace(1)* %out
792  ret void
793}
794
795; 32 known sign bits
796define amdgpu_kernel void @s_test_srem32_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
797; GCN-LABEL: s_test_srem32_64:
798; GCN:       ; %bb.0:
799; GCN-NEXT:    s_load_dword s4, s[0:1], 0xe
800; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
801; GCN-NEXT:    s_mov_b32 s7, 0xf000
802; GCN-NEXT:    s_mov_b32 s6, -1
803; GCN-NEXT:    s_waitcnt lgkmcnt(0)
804; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
805; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s3
806; GCN-NEXT:    s_xor_b32 s2, s3, s4
807; GCN-NEXT:    s_ashr_i32 s2, s2, 30
808; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
809; GCN-NEXT:    s_or_b32 s2, s2, 1
810; GCN-NEXT:    v_mov_b32_e32 v3, s2
811; GCN-NEXT:    s_mov_b32 s5, s1
812; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
813; GCN-NEXT:    v_trunc_f32_e32 v2, v2
814; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
815; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
816; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
817; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
818; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
819; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
820; GCN-NEXT:    s_mov_b32 s4, s0
821; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s3, v0
822; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
823; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
824; GCN-NEXT:    s_endpgm
825;
826; GCN-IR-LABEL: s_test_srem32_64:
827; GCN-IR:       ; %bb.0:
828; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xe
829; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
830; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
831; GCN-IR-NEXT:    s_mov_b32 s6, -1
832; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
833; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
834; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s3
835; GCN-IR-NEXT:    s_xor_b32 s2, s3, s4
836; GCN-IR-NEXT:    s_ashr_i32 s2, s2, 30
837; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
838; GCN-IR-NEXT:    s_or_b32 s2, s2, 1
839; GCN-IR-NEXT:    v_mov_b32_e32 v3, s2
840; GCN-IR-NEXT:    s_mov_b32 s5, s1
841; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
842; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
843; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
844; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
845; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
846; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
847; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
848; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
849; GCN-IR-NEXT:    s_mov_b32 s4, s0
850; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s3, v0
851; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
852; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
853; GCN-IR-NEXT:    s_endpgm
854  %1 = ashr i64 %x, 32
855  %2 = ashr i64 %y, 32
856  %result = srem i64 %1, %2
857  store i64 %result, i64 addrspace(1)* %out
858  ret void
859}
860
861; 33 known sign bits
862define amdgpu_kernel void @s_test_srem33_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
863; GCN-LABEL: s_test_srem33_64:
864; GCN:       ; %bb.0:
865; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
866; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
867; GCN-NEXT:    v_mov_b32_e32 v6, 0
868; GCN-NEXT:    s_mov_b32 s7, 0xf000
869; GCN-NEXT:    s_mov_b32 s6, -1
870; GCN-NEXT:    s_waitcnt lgkmcnt(0)
871; GCN-NEXT:    s_ashr_i64 s[2:3], s[10:11], 31
872; GCN-NEXT:    s_ashr_i64 s[4:5], s[0:1], 31
873; GCN-NEXT:    s_ashr_i32 s0, s1, 31
874; GCN-NEXT:    s_add_u32 s4, s4, s0
875; GCN-NEXT:    s_mov_b32 s1, s0
876; GCN-NEXT:    s_addc_u32 s5, s5, s0
877; GCN-NEXT:    s_xor_b64 s[12:13], s[4:5], s[0:1]
878; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
879; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
880; GCN-NEXT:    s_sub_u32 s0, 0, s12
881; GCN-NEXT:    s_subb_u32 s1, 0, s13
882; GCN-NEXT:    s_ashr_i32 s10, s11, 31
883; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
884; GCN-NEXT:    v_rcp_f32_e32 v0, v0
885; GCN-NEXT:    s_mov_b32 s11, s10
886; GCN-NEXT:    s_mov_b32 s4, s8
887; GCN-NEXT:    s_mov_b32 s5, s9
888; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
889; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
890; GCN-NEXT:    v_trunc_f32_e32 v1, v1
891; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
892; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
893; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
894; GCN-NEXT:    v_mul_lo_u32 v2, s0, v1
895; GCN-NEXT:    v_mul_hi_u32 v3, s0, v0
896; GCN-NEXT:    v_mul_lo_u32 v5, s1, v0
897; GCN-NEXT:    v_mul_lo_u32 v4, s0, v0
898; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
899; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
900; GCN-NEXT:    v_mul_hi_u32 v3, v0, v4
901; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
902; GCN-NEXT:    v_mul_hi_u32 v7, v0, v2
903; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
904; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
905; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
906; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
907; GCN-NEXT:    v_mul_lo_u32 v7, v1, v4
908; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
909; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
910; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
911; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
912; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
913; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
914; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
915; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
916; GCN-NEXT:    v_mul_lo_u32 v2, s0, v1
917; GCN-NEXT:    v_mul_hi_u32 v3, s0, v0
918; GCN-NEXT:    v_mul_lo_u32 v4, s1, v0
919; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
920; GCN-NEXT:    v_mul_lo_u32 v3, s0, v0
921; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
922; GCN-NEXT:    v_mul_lo_u32 v7, v0, v2
923; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
924; GCN-NEXT:    v_mul_hi_u32 v9, v0, v2
925; GCN-NEXT:    v_mul_hi_u32 v5, v1, v3
926; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
927; GCN-NEXT:    v_mul_hi_u32 v4, v1, v2
928; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
929; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
930; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
931; GCN-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
932; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v5, vcc
933; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
934; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
935; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
936; GCN-NEXT:    s_add_u32 s0, s2, s10
937; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
938; GCN-NEXT:    s_addc_u32 s1, s3, s10
939; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
940; GCN-NEXT:    s_xor_b64 s[14:15], s[0:1], s[10:11]
941; GCN-NEXT:    v_mul_lo_u32 v2, s14, v1
942; GCN-NEXT:    v_mul_hi_u32 v3, s14, v0
943; GCN-NEXT:    v_mul_hi_u32 v4, s14, v1
944; GCN-NEXT:    v_mul_hi_u32 v5, s15, v1
945; GCN-NEXT:    v_mul_lo_u32 v1, s15, v1
946; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
947; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
948; GCN-NEXT:    v_mul_lo_u32 v4, s15, v0
949; GCN-NEXT:    v_mul_hi_u32 v0, s15, v0
950; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
951; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
952; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v6, vcc
953; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
954; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
955; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
956; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
957; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
958; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
959; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
960; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
961; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s15, v1
962; GCN-NEXT:    v_mov_b32_e32 v3, s13
963; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s14, v0
964; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
965; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
966; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
967; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
968; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
969; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
970; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
971; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
972; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
973; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
974; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
975; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
976; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
977; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
978; GCN-NEXT:    v_mov_b32_e32 v5, s15
979; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
980; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
981; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
982; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
983; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
984; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
985; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
986; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
987; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
988; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
989; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
990; GCN-NEXT:    v_xor_b32_e32 v0, s10, v0
991; GCN-NEXT:    v_xor_b32_e32 v1, s10, v1
992; GCN-NEXT:    v_mov_b32_e32 v2, s10
993; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s10, v0
994; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
995; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
996; GCN-NEXT:    s_endpgm
997;
998; GCN-IR-LABEL: s_test_srem33_64:
999; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1000; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1001; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
1002; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1003; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[6:7], 31
1004; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[0:1], 31
1005; GCN-IR-NEXT:    s_ashr_i32 s0, s7, 31
1006; GCN-IR-NEXT:    s_ashr_i32 s6, s1, 31
1007; GCN-IR-NEXT:    s_mov_b32 s1, s0
1008; GCN-IR-NEXT:    s_mov_b32 s7, s6
1009; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[2:3], s[0:1]
1010; GCN-IR-NEXT:    s_xor_b64 s[8:9], s[8:9], s[6:7]
1011; GCN-IR-NEXT:    s_sub_u32 s2, s2, s0
1012; GCN-IR-NEXT:    s_subb_u32 s3, s3, s0
1013; GCN-IR-NEXT:    s_sub_u32 s8, s8, s6
1014; GCN-IR-NEXT:    s_subb_u32 s9, s9, s6
1015; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[8:9], 0
1016; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[2:3], 0
1017; GCN-IR-NEXT:    s_mov_b64 s[6:7], 0
1018; GCN-IR-NEXT:    s_or_b64 s[14:15], s[10:11], s[12:13]
1019; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s8
1020; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
1021; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s9
1022; GCN-IR-NEXT:    s_min_u32 s12, s10, s11
1023; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s2
1024; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
1025; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s3
1026; GCN-IR-NEXT:    s_min_u32 s16, s10, s11
1027; GCN-IR-NEXT:    s_sub_u32 s10, s12, s16
1028; GCN-IR-NEXT:    s_subb_u32 s11, 0, 0
1029; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[18:19], s[10:11], 63
1030; GCN-IR-NEXT:    s_mov_b32 s13, 0
1031; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[18:19]
1032; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[18:19], s[10:11], 63
1033; GCN-IR-NEXT:    s_xor_b64 s[20:21], s[14:15], -1
1034; GCN-IR-NEXT:    s_and_b64 s[18:19], s[20:21], s[18:19]
1035; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[18:19]
1036; GCN-IR-NEXT:    s_cbranch_vccz .LBB8_5
1037; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1038; GCN-IR-NEXT:    s_add_u32 s14, s10, 1
1039; GCN-IR-NEXT:    s_addc_u32 s15, s11, 0
1040; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[18:19], s[14:15], 0
1041; GCN-IR-NEXT:    s_sub_i32 s10, 63, s10
1042; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[18:19]
1043; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[2:3], s10
1044; GCN-IR-NEXT:    s_cbranch_vccz .LBB8_4
1045; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1046; GCN-IR-NEXT:    s_lshr_b64 s[14:15], s[2:3], s14
1047; GCN-IR-NEXT:    s_add_u32 s18, s8, -1
1048; GCN-IR-NEXT:    s_addc_u32 s19, s9, -1
1049; GCN-IR-NEXT:    s_not_b64 s[6:7], s[12:13]
1050; GCN-IR-NEXT:    s_mov_b32 s17, s13
1051; GCN-IR-NEXT:    s_add_u32 s12, s6, s16
1052; GCN-IR-NEXT:    s_addc_u32 s13, s7, s13
1053; GCN-IR-NEXT:    s_mov_b64 s[16:17], 0
1054; GCN-IR-NEXT:    s_mov_b32 s7, 0
1055; GCN-IR-NEXT:  .LBB8_3: ; %udiv-do-while
1056; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1057; GCN-IR-NEXT:    s_lshl_b64 s[14:15], s[14:15], 1
1058; GCN-IR-NEXT:    s_lshr_b32 s6, s11, 31
1059; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
1060; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[6:7]
1061; GCN-IR-NEXT:    s_or_b64 s[10:11], s[16:17], s[10:11]
1062; GCN-IR-NEXT:    s_sub_u32 s6, s18, s14
1063; GCN-IR-NEXT:    s_subb_u32 s6, s19, s15
1064; GCN-IR-NEXT:    s_ashr_i32 s16, s6, 31
1065; GCN-IR-NEXT:    s_mov_b32 s17, s16
1066; GCN-IR-NEXT:    s_and_b32 s6, s16, 1
1067; GCN-IR-NEXT:    s_and_b64 s[16:17], s[16:17], s[8:9]
1068; GCN-IR-NEXT:    s_sub_u32 s14, s14, s16
1069; GCN-IR-NEXT:    s_subb_u32 s15, s15, s17
1070; GCN-IR-NEXT:    s_add_u32 s12, s12, 1
1071; GCN-IR-NEXT:    s_addc_u32 s13, s13, 0
1072; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[20:21], s[12:13], 0
1073; GCN-IR-NEXT:    s_mov_b64 s[16:17], s[6:7]
1074; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[20:21]
1075; GCN-IR-NEXT:    s_cbranch_vccz .LBB8_3
1076; GCN-IR-NEXT:  .LBB8_4: ; %Flow6
1077; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
1078; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], s[10:11]
1079; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1080; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
1081; GCN-IR-NEXT:    s_branch .LBB8_6
1082; GCN-IR-NEXT:  .LBB8_5:
1083; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
1084; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[14:15]
1085; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1086; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[14:15]
1087; GCN-IR-NEXT:  .LBB8_6: ; %udiv-end
1088; GCN-IR-NEXT:    v_mul_lo_u32 v1, s8, v1
1089; GCN-IR-NEXT:    v_mul_hi_u32 v2, s8, v0
1090; GCN-IR-NEXT:    v_mul_lo_u32 v3, s9, v0
1091; GCN-IR-NEXT:    v_mul_lo_u32 v0, s8, v0
1092; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1093; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1094; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1095; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
1096; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1097; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
1098; GCN-IR-NEXT:    v_xor_b32_e32 v0, s0, v0
1099; GCN-IR-NEXT:    v_xor_b32_e32 v1, s1, v1
1100; GCN-IR-NEXT:    v_mov_b32_e32 v2, s1
1101; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
1102; GCN-IR-NEXT:    s_mov_b32 s6, -1
1103; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1104; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1105; GCN-IR-NEXT:    s_endpgm
1106  %1 = ashr i64 %x, 31
1107  %2 = ashr i64 %y, 31
1108  %result = srem i64 %1, %2
1109  store i64 %result, i64 addrspace(1)* %out
1110  ret void
1111}
1112
1113define amdgpu_kernel void @s_test_srem24_48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
1114; GCN-LABEL: s_test_srem24_48:
1115; GCN:       ; %bb.0:
1116; GCN-NEXT:    s_load_dword s2, s[0:1], 0xc
1117; GCN-NEXT:    s_load_dword s3, s[0:1], 0xe
1118; GCN-NEXT:    s_load_dword s6, s[0:1], 0xd
1119; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
1120; GCN-NEXT:    s_load_dword s0, s[0:1], 0xb
1121; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1122; GCN-NEXT:    s_sext_i32_i16 s1, s2
1123; GCN-NEXT:    s_sext_i32_i16 s2, s3
1124; GCN-NEXT:    v_mov_b32_e32 v0, s6
1125; GCN-NEXT:    v_alignbit_b32 v0, s2, v0, 24
1126; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
1127; GCN-NEXT:    v_mov_b32_e32 v2, s0
1128; GCN-NEXT:    v_alignbit_b32 v2, s1, v2, 24
1129; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
1130; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v1
1131; GCN-NEXT:    v_xor_b32_e32 v5, v2, v0
1132; GCN-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
1133; GCN-NEXT:    v_or_b32_e32 v5, 1, v5
1134; GCN-NEXT:    v_mul_f32_e32 v4, v3, v4
1135; GCN-NEXT:    v_trunc_f32_e32 v4, v4
1136; GCN-NEXT:    v_mad_f32 v3, -v4, v1, v3
1137; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
1138; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1139; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
1140; GCN-NEXT:    s_mov_b32 s7, 0xf000
1141; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
1142; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
1143; GCN-NEXT:    s_mov_b32 s6, -1
1144; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v2, v0
1145; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1146; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1147; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
1148; GCN-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
1149; GCN-NEXT:    s_endpgm
1150;
1151; GCN-IR-LABEL: s_test_srem24_48:
1152; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1153; GCN-IR-NEXT:    s_load_dword s3, s[0:1], 0xc
1154; GCN-IR-NEXT:    s_load_dword s5, s[0:1], 0xe
1155; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xb
1156; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xd
1157; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
1158; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1159; GCN-IR-NEXT:    s_sext_i32_i16 s3, s3
1160; GCN-IR-NEXT:    s_sext_i32_i16 s5, s5
1161; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[2:3], 24
1162; GCN-IR-NEXT:    s_ashr_i32 s2, s3, 31
1163; GCN-IR-NEXT:    s_ashr_i32 s10, s5, 31
1164; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[4:5], 24
1165; GCN-IR-NEXT:    s_mov_b32 s3, s2
1166; GCN-IR-NEXT:    s_mov_b32 s11, s10
1167; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[6:7], s[2:3]
1168; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[8:9], s[10:11]
1169; GCN-IR-NEXT:    s_sub_u32 s4, s4, s2
1170; GCN-IR-NEXT:    s_subb_u32 s5, s5, s2
1171; GCN-IR-NEXT:    s_sub_u32 s6, s6, s10
1172; GCN-IR-NEXT:    s_subb_u32 s7, s7, s10
1173; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
1174; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[4:5], 0
1175; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1176; GCN-IR-NEXT:    s_or_b64 s[14:15], s[10:11], s[12:13]
1177; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s6
1178; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
1179; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s7
1180; GCN-IR-NEXT:    s_min_u32 s12, s10, s11
1181; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s4
1182; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
1183; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s5
1184; GCN-IR-NEXT:    s_min_u32 s16, s10, s11
1185; GCN-IR-NEXT:    s_sub_u32 s10, s12, s16
1186; GCN-IR-NEXT:    s_subb_u32 s11, 0, 0
1187; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[18:19], s[10:11], 63
1188; GCN-IR-NEXT:    s_mov_b32 s13, 0
1189; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[18:19]
1190; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[18:19], s[10:11], 63
1191; GCN-IR-NEXT:    s_xor_b64 s[20:21], s[14:15], -1
1192; GCN-IR-NEXT:    s_and_b64 s[18:19], s[20:21], s[18:19]
1193; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[18:19]
1194; GCN-IR-NEXT:    s_cbranch_vccz .LBB9_5
1195; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1196; GCN-IR-NEXT:    s_add_u32 s14, s10, 1
1197; GCN-IR-NEXT:    s_addc_u32 s15, s11, 0
1198; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[18:19], s[14:15], 0
1199; GCN-IR-NEXT:    s_sub_i32 s10, 63, s10
1200; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[18:19]
1201; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[4:5], s10
1202; GCN-IR-NEXT:    s_cbranch_vccz .LBB9_4
1203; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1204; GCN-IR-NEXT:    s_lshr_b64 s[14:15], s[4:5], s14
1205; GCN-IR-NEXT:    s_add_u32 s18, s6, -1
1206; GCN-IR-NEXT:    s_addc_u32 s19, s7, -1
1207; GCN-IR-NEXT:    s_not_b64 s[8:9], s[12:13]
1208; GCN-IR-NEXT:    s_mov_b32 s17, s13
1209; GCN-IR-NEXT:    s_add_u32 s12, s8, s16
1210; GCN-IR-NEXT:    s_addc_u32 s13, s9, s13
1211; GCN-IR-NEXT:    s_mov_b64 s[16:17], 0
1212; GCN-IR-NEXT:    s_mov_b32 s9, 0
1213; GCN-IR-NEXT:  .LBB9_3: ; %udiv-do-while
1214; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1215; GCN-IR-NEXT:    s_lshl_b64 s[14:15], s[14:15], 1
1216; GCN-IR-NEXT:    s_lshr_b32 s8, s11, 31
1217; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
1218; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[8:9]
1219; GCN-IR-NEXT:    s_or_b64 s[10:11], s[16:17], s[10:11]
1220; GCN-IR-NEXT:    s_sub_u32 s8, s18, s14
1221; GCN-IR-NEXT:    s_subb_u32 s8, s19, s15
1222; GCN-IR-NEXT:    s_ashr_i32 s16, s8, 31
1223; GCN-IR-NEXT:    s_mov_b32 s17, s16
1224; GCN-IR-NEXT:    s_and_b32 s8, s16, 1
1225; GCN-IR-NEXT:    s_and_b64 s[16:17], s[16:17], s[6:7]
1226; GCN-IR-NEXT:    s_sub_u32 s14, s14, s16
1227; GCN-IR-NEXT:    s_subb_u32 s15, s15, s17
1228; GCN-IR-NEXT:    s_add_u32 s12, s12, 1
1229; GCN-IR-NEXT:    s_addc_u32 s13, s13, 0
1230; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[20:21], s[12:13], 0
1231; GCN-IR-NEXT:    s_mov_b64 s[16:17], s[8:9]
1232; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[20:21]
1233; GCN-IR-NEXT:    s_cbranch_vccz .LBB9_3
1234; GCN-IR-NEXT:  .LBB9_4: ; %Flow3
1235; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
1236; GCN-IR-NEXT:    s_or_b64 s[8:9], s[8:9], s[10:11]
1237; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
1238; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
1239; GCN-IR-NEXT:    s_branch .LBB9_6
1240; GCN-IR-NEXT:  .LBB9_5:
1241; GCN-IR-NEXT:    v_mov_b32_e32 v0, s5
1242; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[14:15]
1243; GCN-IR-NEXT:    v_mov_b32_e32 v0, s4
1244; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[14:15]
1245; GCN-IR-NEXT:  .LBB9_6: ; %udiv-end
1246; GCN-IR-NEXT:    v_mul_lo_u32 v1, s6, v1
1247; GCN-IR-NEXT:    v_mul_hi_u32 v2, s6, v0
1248; GCN-IR-NEXT:    v_mul_lo_u32 v3, s7, v0
1249; GCN-IR-NEXT:    v_mul_lo_u32 v0, s6, v0
1250; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1251; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1252; GCN-IR-NEXT:    v_mov_b32_e32 v2, s5
1253; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
1254; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
1255; GCN-IR-NEXT:    v_xor_b32_e32 v0, s2, v0
1256; GCN-IR-NEXT:    v_xor_b32_e32 v1, s3, v1
1257; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
1258; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
1259; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1260; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1261; GCN-IR-NEXT:    s_mov_b32 s2, -1
1262; GCN-IR-NEXT:    buffer_store_short v1, off, s[0:3], 0 offset:4
1263; GCN-IR-NEXT:    buffer_store_dword v0, off, s[0:3], 0
1264; GCN-IR-NEXT:    s_endpgm
1265  %1 = ashr i48 %x, 24
1266  %2 = ashr i48 %y, 24
1267  %result = srem i48 %1, %2
1268  store i48 %result, i48 addrspace(1)* %out
1269  ret void
1270}
1271
1272define amdgpu_kernel void @s_test_srem_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1273; GCN-LABEL: s_test_srem_k_num_i64:
1274; GCN:       ; %bb.0:
1275; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1276; GCN-NEXT:    s_mov_b32 s7, 0xf000
1277; GCN-NEXT:    s_mov_b32 s6, -1
1278; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1279; GCN-NEXT:    s_ashr_i32 s4, s3, 31
1280; GCN-NEXT:    s_add_u32 s2, s2, s4
1281; GCN-NEXT:    s_mov_b32 s5, s4
1282; GCN-NEXT:    s_addc_u32 s3, s3, s4
1283; GCN-NEXT:    s_xor_b64 s[8:9], s[2:3], s[4:5]
1284; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
1285; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s9
1286; GCN-NEXT:    s_sub_u32 s2, 0, s8
1287; GCN-NEXT:    s_subb_u32 s3, 0, s9
1288; GCN-NEXT:    s_mov_b32 s4, s0
1289; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
1290; GCN-NEXT:    v_rcp_f32_e32 v0, v0
1291; GCN-NEXT:    v_mov_b32_e32 v1, 0
1292; GCN-NEXT:    s_mov_b32 s5, s1
1293; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
1294; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
1295; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1296; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
1297; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1298; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
1299; GCN-NEXT:    v_mul_lo_u32 v3, s2, v2
1300; GCN-NEXT:    v_mul_hi_u32 v4, s2, v0
1301; GCN-NEXT:    v_mul_lo_u32 v6, s3, v0
1302; GCN-NEXT:    v_mul_lo_u32 v5, s2, v0
1303; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1304; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
1305; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
1306; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
1307; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
1308; GCN-NEXT:    v_mul_hi_u32 v7, v2, v5
1309; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
1310; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
1311; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
1312; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
1313; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
1314; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1315; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v7, vcc
1316; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
1317; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1318; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
1319; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
1320; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
1321; GCN-NEXT:    v_mul_lo_u32 v3, s2, v2
1322; GCN-NEXT:    v_mul_hi_u32 v4, s2, v0
1323; GCN-NEXT:    v_mul_lo_u32 v5, s3, v0
1324; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1325; GCN-NEXT:    v_mul_lo_u32 v4, s2, v0
1326; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
1327; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
1328; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
1329; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
1330; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
1331; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
1332; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
1333; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1334; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
1335; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
1336; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
1337; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
1338; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v5, v1, vcc
1339; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1340; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1341; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
1342; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
1343; GCN-NEXT:    v_mul_lo_u32 v2, v1, 24
1344; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
1345; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
1346; GCN-NEXT:    v_mov_b32_e32 v3, s9
1347; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1348; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v1, vcc
1349; GCN-NEXT:    v_mul_lo_u32 v1, s9, v0
1350; GCN-NEXT:    v_mul_hi_u32 v2, s8, v0
1351; GCN-NEXT:    v_mul_lo_u32 v0, s8, v0
1352; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1353; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
1354; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1355; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
1356; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s8, v0
1357; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
1358; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s9, v5
1359; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
1360; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s8, v4
1361; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
1362; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
1363; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s9, v5
1364; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s8, v4
1365; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
1366; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
1367; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1368; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
1369; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
1370; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
1371; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
1372; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
1373; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1374; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v1
1375; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
1376; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
1377; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1378; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
1379; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1380; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1381; GCN-NEXT:    s_endpgm
1382;
1383; GCN-IR-LABEL: s_test_srem_k_num_i64:
1384; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1385; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1386; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1387; GCN-IR-NEXT:    s_ashr_i32 s6, s3, 31
1388; GCN-IR-NEXT:    s_mov_b32 s7, s6
1389; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[2:3], s[6:7]
1390; GCN-IR-NEXT:    s_sub_u32 s4, s2, s6
1391; GCN-IR-NEXT:    s_subb_u32 s5, s3, s6
1392; GCN-IR-NEXT:    s_flbit_i32_b32 s2, s4
1393; GCN-IR-NEXT:    s_add_i32 s2, s2, 32
1394; GCN-IR-NEXT:    s_flbit_i32_b32 s3, s5
1395; GCN-IR-NEXT:    s_min_u32 s8, s2, s3
1396; GCN-IR-NEXT:    s_add_u32 s6, s8, 0xffffffc5
1397; GCN-IR-NEXT:    s_addc_u32 s7, 0, -1
1398; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[4:5], 0
1399; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[12:13], s[6:7], 63
1400; GCN-IR-NEXT:    s_mov_b64 s[2:3], 0
1401; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
1402; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[12:13], s[6:7], 63
1403; GCN-IR-NEXT:    s_xor_b64 s[14:15], s[10:11], -1
1404; GCN-IR-NEXT:    s_and_b64 s[12:13], s[14:15], s[12:13]
1405; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
1406; GCN-IR-NEXT:    s_cbranch_vccz .LBB10_5
1407; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1408; GCN-IR-NEXT:    s_add_u32 s10, s6, 1
1409; GCN-IR-NEXT:    s_addc_u32 s11, s7, 0
1410; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[10:11], 0
1411; GCN-IR-NEXT:    s_sub_i32 s6, 63, s6
1412; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[12:13]
1413; GCN-IR-NEXT:    s_lshl_b64 s[6:7], 24, s6
1414; GCN-IR-NEXT:    s_cbranch_vccz .LBB10_4
1415; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1416; GCN-IR-NEXT:    s_lshr_b64 s[10:11], 24, s10
1417; GCN-IR-NEXT:    s_add_u32 s14, s4, -1
1418; GCN-IR-NEXT:    s_addc_u32 s15, s5, -1
1419; GCN-IR-NEXT:    s_sub_u32 s8, 58, s8
1420; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
1421; GCN-IR-NEXT:    s_mov_b64 s[12:13], 0
1422; GCN-IR-NEXT:    s_mov_b32 s3, 0
1423; GCN-IR-NEXT:  .LBB10_3: ; %udiv-do-while
1424; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1425; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
1426; GCN-IR-NEXT:    s_lshr_b32 s2, s7, 31
1427; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[6:7], 1
1428; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[2:3]
1429; GCN-IR-NEXT:    s_or_b64 s[6:7], s[12:13], s[6:7]
1430; GCN-IR-NEXT:    s_sub_u32 s2, s14, s10
1431; GCN-IR-NEXT:    s_subb_u32 s2, s15, s11
1432; GCN-IR-NEXT:    s_ashr_i32 s12, s2, 31
1433; GCN-IR-NEXT:    s_mov_b32 s13, s12
1434; GCN-IR-NEXT:    s_and_b32 s2, s12, 1
1435; GCN-IR-NEXT:    s_and_b64 s[12:13], s[12:13], s[4:5]
1436; GCN-IR-NEXT:    s_sub_u32 s10, s10, s12
1437; GCN-IR-NEXT:    s_subb_u32 s11, s11, s13
1438; GCN-IR-NEXT:    s_add_u32 s8, s8, 1
1439; GCN-IR-NEXT:    s_addc_u32 s9, s9, 0
1440; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[16:17], s[8:9], 0
1441; GCN-IR-NEXT:    s_mov_b64 s[12:13], s[2:3]
1442; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[16:17]
1443; GCN-IR-NEXT:    s_cbranch_vccz .LBB10_3
1444; GCN-IR-NEXT:  .LBB10_4: ; %Flow5
1445; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[6:7], 1
1446; GCN-IR-NEXT:    s_or_b64 s[2:3], s[2:3], s[6:7]
1447; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1448; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
1449; GCN-IR-NEXT:    s_branch .LBB10_6
1450; GCN-IR-NEXT:  .LBB10_5:
1451; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1452; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, 24, 0, s[10:11]
1453; GCN-IR-NEXT:  .LBB10_6: ; %udiv-end
1454; GCN-IR-NEXT:    v_mul_lo_u32 v1, s4, v1
1455; GCN-IR-NEXT:    v_mul_hi_u32 v2, s4, v0
1456; GCN-IR-NEXT:    v_mul_lo_u32 v3, s5, v0
1457; GCN-IR-NEXT:    v_mul_lo_u32 v0, s4, v0
1458; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1459; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1460; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1461; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1462; GCN-IR-NEXT:    s_mov_b32 s2, -1
1463; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1464; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1465; GCN-IR-NEXT:    s_endpgm
1466  %result = srem i64 24, %x
1467  store i64 %result, i64 addrspace(1)* %out
1468  ret void
1469}
1470
1471define i64 @v_test_srem_k_num_i64(i64 %x) {
1472; GCN-LABEL: v_test_srem_k_num_i64:
1473; GCN:       ; %bb.0:
1474; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1475; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1476; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1477; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1478; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1479; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1480; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1481; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1482; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1483; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1484; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
1485; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1486; GCN-NEXT:    v_mov_b32_e32 v11, 0
1487; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1488; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1489; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1490; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1491; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1492; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1493; GCN-NEXT:    v_mul_hi_u32 v6, v4, v2
1494; GCN-NEXT:    v_mul_lo_u32 v7, v4, v3
1495; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1496; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
1497; GCN-NEXT:    v_mul_lo_u32 v7, v4, v2
1498; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1499; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
1500; GCN-NEXT:    v_mul_hi_u32 v9, v2, v7
1501; GCN-NEXT:    v_mul_hi_u32 v10, v2, v6
1502; GCN-NEXT:    v_mul_hi_u32 v12, v3, v6
1503; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1504; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1505; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
1506; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
1507; GCN-NEXT:    v_mul_hi_u32 v7, v3, v7
1508; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
1509; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v7, vcc
1510; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v11, vcc
1511; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1512; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
1513; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
1514; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v7, vcc
1515; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1516; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1517; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1518; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1519; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1520; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
1521; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
1522; GCN-NEXT:    v_mul_hi_u32 v9, v2, v4
1523; GCN-NEXT:    v_mul_hi_u32 v10, v2, v5
1524; GCN-NEXT:    v_mul_hi_u32 v7, v3, v4
1525; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1526; GCN-NEXT:    v_mul_hi_u32 v6, v3, v5
1527; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1528; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
1529; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
1530; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
1531; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
1532; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v11, vcc
1533; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1534; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
1535; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1536; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
1537; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
1538; GCN-NEXT:    v_mul_hi_u32 v2, v2, 24
1539; GCN-NEXT:    v_mul_hi_u32 v3, v3, 24
1540; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1541; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
1542; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
1543; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1544; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
1545; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1546; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
1547; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 24, v2
1548; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
1549; GCN-NEXT:    v_sub_i32_e64 v5, s[4:5], v2, v0
1550; GCN-NEXT:    v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
1551; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v1
1552; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[6:7]
1553; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v5, v0
1554; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
1555; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v6, v1
1556; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
1557; GCN-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[6:7]
1558; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v5, v0
1559; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1560; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
1561; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1562; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1563; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
1564; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v0
1565; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1566; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1567; GCN-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
1568; GCN-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[4:5]
1569; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1570; GCN-NEXT:    v_cndmask_b32_e64 v1, v6, v4, s[4:5]
1571; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1572; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1573; GCN-NEXT:    s_setpc_b64 s[30:31]
1574;
1575; GCN-IR-LABEL: v_test_srem_k_num_i64:
1576; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1577; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1578; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1579; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1580; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
1581; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1582; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1583; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1584; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1585; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1586; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1587; GCN-IR-NEXT:    s_movk_i32 s6, 0xffc5
1588; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, s6, v6
1589; GCN-IR-NEXT:    v_addc_u32_e64 v4, s[6:7], 0, -1, vcc
1590; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1591; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[3:4]
1592; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1593; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1594; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[3:4]
1595; GCN-IR-NEXT:    v_cndmask_b32_e64 v2, 24, 0, s[4:5]
1596; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1597; GCN-IR-NEXT:    v_mov_b32_e32 v5, v7
1598; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1599; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1600; GCN-IR-NEXT:    s_cbranch_execz .LBB11_6
1601; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1602; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v3
1603; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v4, vcc
1604; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v3
1605; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[8:9]
1606; GCN-IR-NEXT:    v_lshl_b64 v[2:3], 24, v2
1607; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1608; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1609; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1610; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1611; GCN-IR-NEXT:    s_cbranch_execz .LBB11_5
1612; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1613; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, -1, v0
1614; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, -1, v1, vcc
1615; GCN-IR-NEXT:    v_lshr_b64 v[8:9], 24, v8
1616; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, 58, v6
1617; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1618; GCN-IR-NEXT:    v_subb_u32_e32 v7, vcc, 0, v7, vcc
1619; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1620; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1621; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1622; GCN-IR-NEXT:  .LBB11_3: ; %udiv-do-while
1623; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1624; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1625; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1626; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1627; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1628; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, v12, v8
1629; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, v13, v9, vcc
1630; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1631; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1632; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 1, v6
1633; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1634; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1635; GCN-IR-NEXT:    v_and_b32_e32 v11, v10, v1
1636; GCN-IR-NEXT:    v_and_b32_e32 v10, v10, v0
1637; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
1638; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[6:7]
1639; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v10
1640; GCN-IR-NEXT:    v_subb_u32_e64 v9, s[4:5], v9, v11, s[4:5]
1641; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1642; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1643; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1644; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1645; GCN-IR-NEXT:    s_cbranch_execnz .LBB11_3
1646; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1647; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1648; GCN-IR-NEXT:  .LBB11_5: ; %Flow3
1649; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1650; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1651; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1652; GCN-IR-NEXT:    v_or_b32_e32 v2, v4, v2
1653; GCN-IR-NEXT:  .LBB11_6: ; %Flow4
1654; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1655; GCN-IR-NEXT:    v_mul_lo_u32 v3, v0, v5
1656; GCN-IR-NEXT:    v_mul_hi_u32 v4, v0, v2
1657; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v2
1658; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, v2
1659; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1660; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
1661; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1662; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1663; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1664  %result = srem i64 24, %x
1665  ret i64 %result
1666}
1667
1668define i64 @v_test_srem_pow2_k_num_i64(i64 %x) {
1669; GCN-LABEL: v_test_srem_pow2_k_num_i64:
1670; GCN:       ; %bb.0:
1671; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1672; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1673; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1674; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1675; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1676; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1677; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1678; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1679; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1680; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1681; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
1682; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1683; GCN-NEXT:    v_mov_b32_e32 v11, 0
1684; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1685; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1686; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1687; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1688; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1689; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1690; GCN-NEXT:    v_mul_hi_u32 v6, v4, v2
1691; GCN-NEXT:    v_mul_lo_u32 v7, v4, v3
1692; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1693; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
1694; GCN-NEXT:    v_mul_lo_u32 v7, v4, v2
1695; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1696; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
1697; GCN-NEXT:    v_mul_hi_u32 v9, v2, v7
1698; GCN-NEXT:    v_mul_hi_u32 v10, v2, v6
1699; GCN-NEXT:    v_mul_hi_u32 v12, v3, v6
1700; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1701; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1702; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
1703; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
1704; GCN-NEXT:    v_mul_hi_u32 v7, v3, v7
1705; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
1706; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v7, vcc
1707; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v11, vcc
1708; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1709; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
1710; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
1711; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v7, vcc
1712; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1713; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1714; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1715; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1716; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1717; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
1718; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
1719; GCN-NEXT:    v_mul_hi_u32 v9, v2, v4
1720; GCN-NEXT:    v_mul_hi_u32 v10, v2, v5
1721; GCN-NEXT:    v_mul_hi_u32 v7, v3, v4
1722; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1723; GCN-NEXT:    v_mul_hi_u32 v6, v3, v5
1724; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1725; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
1726; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
1727; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
1728; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
1729; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v11, vcc
1730; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1731; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
1732; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1733; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v3, v5, vcc
1734; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1735; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
1736; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1737; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
1738; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1739; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
1740; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0x8000, v2
1741; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
1742; GCN-NEXT:    v_sub_i32_e64 v5, s[4:5], v2, v0
1743; GCN-NEXT:    v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
1744; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v1
1745; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[6:7]
1746; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v5, v0
1747; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
1748; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v6, v1
1749; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
1750; GCN-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[6:7]
1751; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v5, v0
1752; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1753; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
1754; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1755; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1756; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
1757; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v0
1758; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1759; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1760; GCN-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
1761; GCN-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[4:5]
1762; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1763; GCN-NEXT:    v_cndmask_b32_e64 v1, v6, v4, s[4:5]
1764; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1765; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1766; GCN-NEXT:    s_setpc_b64 s[30:31]
1767;
1768; GCN-IR-LABEL: v_test_srem_pow2_k_num_i64:
1769; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1770; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1771; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1772; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1773; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
1774; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1775; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1776; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1777; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1778; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1779; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1780; GCN-IR-NEXT:    s_movk_i32 s6, 0xffd0
1781; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, s6, v6
1782; GCN-IR-NEXT:    v_addc_u32_e64 v3, s[6:7], 0, -1, vcc
1783; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1784; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[2:3]
1785; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0x8000
1786; GCN-IR-NEXT:    v_mov_b32_e32 v4, s8
1787; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1788; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[2:3]
1789; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1790; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v4, 0, s[4:5]
1791; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1792; GCN-IR-NEXT:    v_mov_b32_e32 v5, v7
1793; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1794; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1795; GCN-IR-NEXT:    s_cbranch_execz .LBB12_6
1796; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1797; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v2
1798; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v3, vcc
1799; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v2
1800; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[8:9]
1801; GCN-IR-NEXT:    v_lshl_b64 v[2:3], s[8:9], v2
1802; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1803; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1804; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1805; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1806; GCN-IR-NEXT:    s_cbranch_execz .LBB12_5
1807; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1808; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, -1, v0
1809; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0x8000
1810; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, -1, v1, vcc
1811; GCN-IR-NEXT:    v_lshr_b64 v[8:9], s[4:5], v8
1812; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, 47, v6
1813; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1814; GCN-IR-NEXT:    v_subb_u32_e32 v7, vcc, 0, v7, vcc
1815; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1816; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1817; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1818; GCN-IR-NEXT:  .LBB12_3: ; %udiv-do-while
1819; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1820; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1821; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1822; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1823; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1824; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, v12, v8
1825; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, v13, v9, vcc
1826; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1827; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1828; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 1, v6
1829; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1830; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1831; GCN-IR-NEXT:    v_and_b32_e32 v11, v10, v1
1832; GCN-IR-NEXT:    v_and_b32_e32 v10, v10, v0
1833; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
1834; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[6:7]
1835; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v10
1836; GCN-IR-NEXT:    v_subb_u32_e64 v9, s[4:5], v9, v11, s[4:5]
1837; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1838; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1839; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1840; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1841; GCN-IR-NEXT:    s_cbranch_execnz .LBB12_3
1842; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1843; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1844; GCN-IR-NEXT:  .LBB12_5: ; %Flow3
1845; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1846; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1847; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1848; GCN-IR-NEXT:    v_or_b32_e32 v4, v4, v2
1849; GCN-IR-NEXT:  .LBB12_6: ; %Flow4
1850; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1851; GCN-IR-NEXT:    v_mul_lo_u32 v2, v0, v5
1852; GCN-IR-NEXT:    v_mul_hi_u32 v3, v0, v4
1853; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v4
1854; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, v4
1855; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1856; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1857; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1858; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1859; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1860  %result = srem i64 32768, %x
1861  ret i64 %result
1862}
1863
1864define i64 @v_test_srem_pow2_k_den_i64(i64 %x) {
1865; GCN-LABEL: v_test_srem_pow2_k_den_i64:
1866; GCN:       ; %bb.0:
1867; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1868; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1869; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1870; GCN-NEXT:    v_add_i32_e32 v2, vcc, v0, v2
1871; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
1872; GCN-NEXT:    v_and_b32_e32 v2, 0xffff8000, v2
1873; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1874; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1875; GCN-NEXT:    s_setpc_b64 s[30:31]
1876;
1877; GCN-IR-LABEL: v_test_srem_pow2_k_den_i64:
1878; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1879; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1880; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1881; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1882; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
1883; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1884; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1885; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v0
1886; GCN-IR-NEXT:    v_add_i32_e64 v3, s[4:5], 32, v3
1887; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v1
1888; GCN-IR-NEXT:    v_min_u32_e32 v8, v3, v4
1889; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 48, v8
1890; GCN-IR-NEXT:    v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5]
1891; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1892; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
1893; GCN-IR-NEXT:    v_mov_b32_e32 v3, v2
1894; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1895; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1896; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1897; GCN-IR-NEXT:    v_cndmask_b32_e64 v7, v1, 0, s[4:5]
1898; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v0, 0, s[4:5]
1899; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1900; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1901; GCN-IR-NEXT:    s_cbranch_execz .LBB13_6
1902; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1903; GCN-IR-NEXT:    v_add_i32_e32 v9, vcc, 1, v4
1904; GCN-IR-NEXT:    v_addc_u32_e32 v10, vcc, 0, v5, vcc
1905; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v4
1906; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[9:10]
1907; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[0:1], v4
1908; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1909; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1910; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1911; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1912; GCN-IR-NEXT:    s_cbranch_execz .LBB13_5
1913; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1914; GCN-IR-NEXT:    v_lshr_b64 v[10:11], v[0:1], v9
1915; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 0xffffffcf, v8
1916; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1917; GCN-IR-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, -1, vcc
1918; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1919; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1920; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1921; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
1922; GCN-IR-NEXT:  .LBB13_3: ; %udiv-do-while
1923; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1924; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
1925; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
1926; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v6
1927; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, s12, v10
1928; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
1929; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, 0, v11, vcc
1930; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v8
1931; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
1932; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v6
1933; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
1934; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v12
1935; GCN-IR-NEXT:    v_and_b32_e32 v12, 0x8000, v12
1936; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[8:9]
1937; GCN-IR-NEXT:    v_or_b32_e32 v5, v13, v5
1938; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v12
1939; GCN-IR-NEXT:    v_mov_b32_e32 v13, v7
1940; GCN-IR-NEXT:    v_subbrev_u32_e64 v11, s[4:5], 0, v11, s[4:5]
1941; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1942; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
1943; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1944; GCN-IR-NEXT:    s_cbranch_execnz .LBB13_3
1945; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1946; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1947; GCN-IR-NEXT:  .LBB13_5: ; %Flow3
1948; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1949; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
1950; GCN-IR-NEXT:    v_or_b32_e32 v7, v7, v5
1951; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v4
1952; GCN-IR-NEXT:  .LBB13_6: ; %Flow4
1953; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1954; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[6:7], 15
1955; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
1956; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
1957; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1958; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v3
1959; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1960; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1961; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1962  %result = srem i64 %x, 32768
1963  ret i64 %result
1964}
1965
1966define amdgpu_kernel void @s_test_srem24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1967; GCN-LABEL: s_test_srem24_k_num_i64:
1968; GCN:       ; %bb.0:
1969; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1970; GCN-NEXT:    s_mov_b32 s6, 0x41c00000
1971; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1972; GCN-NEXT:    s_ashr_i64 s[4:5], s[2:3], 40
1973; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
1974; GCN-NEXT:    s_ashr_i32 s5, s4, 30
1975; GCN-NEXT:    s_or_b32 s5, s5, 1
1976; GCN-NEXT:    v_mov_b32_e32 v3, s5
1977; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1978; GCN-NEXT:    s_mov_b32 s3, 0xf000
1979; GCN-NEXT:    s_mov_b32 s2, -1
1980; GCN-NEXT:    v_mul_f32_e32 v1, s6, v1
1981; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1982; GCN-NEXT:    v_mad_f32 v2, -v1, v0, s6
1983; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
1984; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
1985; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
1986; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1987; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
1988; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1989; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1990; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1991; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1992; GCN-NEXT:    s_endpgm
1993;
1994; GCN-IR-LABEL: s_test_srem24_k_num_i64:
1995; GCN-IR:       ; %bb.0:
1996; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1997; GCN-IR-NEXT:    s_mov_b32 s6, 0x41c00000
1998; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1999; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[2:3], 40
2000; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
2001; GCN-IR-NEXT:    s_ashr_i32 s5, s4, 30
2002; GCN-IR-NEXT:    s_or_b32 s5, s5, 1
2003; GCN-IR-NEXT:    v_mov_b32_e32 v3, s5
2004; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
2005; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
2006; GCN-IR-NEXT:    s_mov_b32 s2, -1
2007; GCN-IR-NEXT:    v_mul_f32_e32 v1, s6, v1
2008; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
2009; GCN-IR-NEXT:    v_mad_f32 v2, -v1, v0, s6
2010; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
2011; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
2012; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
2013; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
2014; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
2015; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2016; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2017; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2018; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2019; GCN-IR-NEXT:    s_endpgm
2020  %x.shr = ashr i64 %x, 40
2021  %result = srem i64 24, %x.shr
2022  store i64 %result, i64 addrspace(1)* %out
2023  ret void
2024}
2025
2026define amdgpu_kernel void @s_test_srem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
2027; GCN-LABEL: s_test_srem24_k_den_i64:
2028; GCN:       ; %bb.0:
2029; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
2030; GCN-NEXT:    s_mov_b32 s4, 0x46b6fe00
2031; GCN-NEXT:    s_mov_b32 s7, 0xf000
2032; GCN-NEXT:    s_mov_b32 s6, -1
2033; GCN-NEXT:    s_waitcnt lgkmcnt(0)
2034; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
2035; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s2
2036; GCN-NEXT:    s_ashr_i32 s3, s2, 30
2037; GCN-NEXT:    s_or_b32 s3, s3, 1
2038; GCN-NEXT:    v_mov_b32_e32 v1, s3
2039; GCN-NEXT:    v_mul_f32_e32 v2, 0x38331158, v0
2040; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2041; GCN-NEXT:    v_mad_f32 v0, -v2, s4, v0
2042; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2043; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
2044; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
2045; GCN-NEXT:    s_movk_i32 s3, 0x5b7f
2046; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
2047; GCN-NEXT:    v_mul_lo_u32 v0, v0, s3
2048; GCN-NEXT:    s_mov_b32 s4, s0
2049; GCN-NEXT:    s_mov_b32 s5, s1
2050; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
2051; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2052; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2053; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
2054; GCN-NEXT:    s_endpgm
2055;
2056; GCN-IR-LABEL: s_test_srem24_k_den_i64:
2057; GCN-IR:       ; %bb.0:
2058; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
2059; GCN-IR-NEXT:    s_mov_b32 s4, 0x46b6fe00
2060; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
2061; GCN-IR-NEXT:    s_mov_b32 s6, -1
2062; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
2063; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
2064; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s2
2065; GCN-IR-NEXT:    s_ashr_i32 s3, s2, 30
2066; GCN-IR-NEXT:    s_or_b32 s3, s3, 1
2067; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
2068; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x38331158, v0
2069; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2070; GCN-IR-NEXT:    v_mad_f32 v0, -v2, s4, v0
2071; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2072; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
2073; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
2074; GCN-IR-NEXT:    s_movk_i32 s3, 0x5b7f
2075; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
2076; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s3
2077; GCN-IR-NEXT:    s_mov_b32 s4, s0
2078; GCN-IR-NEXT:    s_mov_b32 s5, s1
2079; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
2080; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2081; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2082; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
2083; GCN-IR-NEXT:    s_endpgm
2084  %x.shr = ashr i64 %x, 40
2085  %result = srem i64 %x.shr, 23423
2086  store i64 %result, i64 addrspace(1)* %out
2087  ret void
2088}
2089
2090define i64 @v_test_srem24_k_num_i64(i64 %x) {
2091; GCN-LABEL: v_test_srem24_k_num_i64:
2092; GCN:       ; %bb.0:
2093; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2094; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2095; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
2096; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
2097; GCN-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2098; GCN-NEXT:    v_or_b32_e32 v3, 1, v3
2099; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2100; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
2101; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2102; GCN-NEXT:    v_mad_f32 v4, -v2, v1, s4
2103; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2104; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2105; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2106; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2107; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
2108; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2109; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2110; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2111; GCN-NEXT:    s_setpc_b64 s[30:31]
2112;
2113; GCN-IR-LABEL: v_test_srem24_k_num_i64:
2114; GCN-IR:       ; %bb.0:
2115; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2116; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2117; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
2118; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2119; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2120; GCN-IR-NEXT:    v_or_b32_e32 v3, 1, v3
2121; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2122; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
2123; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2124; GCN-IR-NEXT:    v_mad_f32 v4, -v2, v1, s4
2125; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2126; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2127; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2128; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2129; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
2130; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2131; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2132; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2133; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2134  %x.shr = ashr i64 %x, 40
2135  %result = srem i64 24, %x.shr
2136  ret i64 %result
2137}
2138
2139define i64 @v_test_srem24_pow2_k_num_i64(i64 %x) {
2140; GCN-LABEL: v_test_srem24_pow2_k_num_i64:
2141; GCN:       ; %bb.0:
2142; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2143; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2144; GCN-NEXT:    s_mov_b32 s4, 0x47000000
2145; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
2146; GCN-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2147; GCN-NEXT:    v_or_b32_e32 v3, 1, v3
2148; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2149; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
2150; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2151; GCN-NEXT:    v_mad_f32 v4, -v2, v1, s4
2152; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2153; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2154; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2155; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2156; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
2157; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
2158; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2159; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2160; GCN-NEXT:    s_setpc_b64 s[30:31]
2161;
2162; GCN-IR-LABEL: v_test_srem24_pow2_k_num_i64:
2163; GCN-IR:       ; %bb.0:
2164; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2165; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2166; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2167; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2168; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2169; GCN-IR-NEXT:    v_or_b32_e32 v3, 1, v3
2170; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2171; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
2172; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2173; GCN-IR-NEXT:    v_mad_f32 v4, -v2, v1, s4
2174; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2175; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2176; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2177; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2178; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
2179; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
2180; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2181; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2182; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2183  %x.shr = ashr i64 %x, 40
2184  %result = srem i64 32768, %x.shr
2185  ret i64 %result
2186}
2187
2188define i64 @v_test_srem24_pow2_k_den_i64(i64 %x) {
2189; GCN-LABEL: v_test_srem24_pow2_k_den_i64:
2190; GCN:       ; %bb.0:
2191; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2192; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2193; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v1
2194; GCN-NEXT:    v_add_i32_e32 v2, vcc, v0, v2
2195; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
2196; GCN-NEXT:    v_and_b32_e32 v2, 0xffff8000, v2
2197; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
2198; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
2199; GCN-NEXT:    s_setpc_b64 s[30:31]
2200;
2201; GCN-IR-LABEL: v_test_srem24_pow2_k_den_i64:
2202; GCN-IR:       ; %bb.0:
2203; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2204; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2205; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2206; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2207; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 30, v0
2208; GCN-IR-NEXT:    v_or_b32_e32 v2, 1, v2
2209; GCN-IR-NEXT:    v_mul_f32_e32 v3, 0x38000000, v1
2210; GCN-IR-NEXT:    v_trunc_f32_e32 v3, v3
2211; GCN-IR-NEXT:    v_mad_f32 v1, -v3, s4, v1
2212; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v3
2213; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
2214; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
2215; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
2216; GCN-IR-NEXT:    v_lshlrev_b32_e32 v1, 15, v1
2217; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
2218; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2219; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2220; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2221  %x.shr = ashr i64 %x, 40
2222  %result = srem i64 %x.shr, 32768
2223  ret i64 %result
2224}
2225