1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_srem(i64 addrspace(1)* %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_srem:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
9; GCN-NEXT:    v_mov_b32_e32 v2, 0
10; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
11; GCN-NEXT:    s_mov_b32 s7, 0xf000
12; GCN-NEXT:    s_mov_b32 s6, -1
13; GCN-NEXT:    s_waitcnt lgkmcnt(0)
14; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
15; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
16; GCN-NEXT:    s_sub_u32 s2, 0, s12
17; GCN-NEXT:    s_subb_u32 s3, 0, s13
18; GCN-NEXT:    s_mov_b32 s4, s8
19; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
20; GCN-NEXT:    v_rcp_f32_e32 v0, v0
21; GCN-NEXT:    v_mov_b32_e32 v1, 0
22; GCN-NEXT:    s_mov_b32 s5, s9
23; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
24; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
25; GCN-NEXT:    v_trunc_f32_e32 v3, v3
26; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
27; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
28; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
29; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
30; GCN-NEXT:    v_mul_lo_u32 v4, s2, v3
31; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
32; GCN-NEXT:    v_mul_lo_u32 v6, s2, v0
33; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
34; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
35; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
36; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
37; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
38; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
39; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
40; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
41; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
42; GCN-NEXT:    v_mul_hi_u32 v9, v3, v4
43; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
44; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
45; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
46; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v1, vcc
47; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
48; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
49; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
50; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
51; GCN-NEXT:    v_mul_lo_u32 v6, s2, v4
52; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
53; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
54; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
55; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
56; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
57; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
58; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
59; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
60; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
61; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
62; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
63; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
64; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
65; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
66; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
67; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
68; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v1, vcc
69; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
70; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
71; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
72; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
73; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
74; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
75; GCN-NEXT:    v_mul_lo_u32 v4, s10, v3
76; GCN-NEXT:    v_mul_hi_u32 v5, s10, v0
77; GCN-NEXT:    v_mul_hi_u32 v6, s10, v3
78; GCN-NEXT:    v_mul_hi_u32 v7, s11, v3
79; GCN-NEXT:    v_mul_lo_u32 v3, s11, v3
80; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
81; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
82; GCN-NEXT:    v_mul_lo_u32 v6, s11, v0
83; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
84; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
85; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
86; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
87; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
88; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
89; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
90; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
91; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
92; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
93; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
94; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
95; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s11, v1
96; GCN-NEXT:    v_mov_b32_e32 v3, s13
97; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s10, v0
98; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
99; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
100; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
101; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
102; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
103; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
104; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
105; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
106; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
107; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
108; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
109; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
110; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
111; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
112; GCN-NEXT:    v_mov_b32_e32 v5, s11
113; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
114; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
115; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
116; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
117; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
118; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
119; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
120; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
121; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
122; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
123; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
124; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
125; GCN-NEXT:    s_endpgm
126;
127; GCN-IR-LABEL: s_test_srem:
128; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
129; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
130; GCN-IR-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
131; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
132; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[6:7], 0
133; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[0:1], s[2:3], 0
134; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s2
135; GCN-IR-NEXT:    s_or_b64 s[8:9], s[0:1], s[8:9]
136; GCN-IR-NEXT:    s_flbit_i32_b32 s0, s6
137; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s3
138; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
139; GCN-IR-NEXT:    v_mov_b32_e32 v0, s11
140; GCN-IR-NEXT:    v_mov_b32_e32 v1, s10
141; GCN-IR-NEXT:    v_cmp_eq_u32_e64 vcc, s3, 0
142; GCN-IR-NEXT:    s_add_i32 s0, s0, 32
143; GCN-IR-NEXT:    s_flbit_i32_b32 s1, s7
144; GCN-IR-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
145; GCN-IR-NEXT:    v_mov_b32_e32 v0, s1
146; GCN-IR-NEXT:    v_mov_b32_e32 v1, s0
147; GCN-IR-NEXT:    v_cmp_eq_u32_e64 vcc, s7, 0
148; GCN-IR-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
149; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v2, v3
150; GCN-IR-NEXT:    v_subb_u32_e64 v1, s[0:1], 0, 0, vcc
151; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[0:1]
152; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[0:1], 63, v[0:1]
153; GCN-IR-NEXT:    s_or_b64 s[8:9], s[8:9], vcc
154; GCN-IR-NEXT:    s_or_b64 s[0:1], s[8:9], s[0:1]
155; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[0:1]
156; GCN-IR-NEXT:    s_cbranch_vccz BB0_2
157; GCN-IR-NEXT:  ; %bb.1:
158; GCN-IR-NEXT:    v_mov_b32_e32 v0, s7
159; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[8:9]
160; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
161; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[8:9]
162; GCN-IR-NEXT:    s_branch BB0_7
163; GCN-IR-NEXT:  BB0_2: ; %udiv-bb1
164; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
165; GCN-IR-NEXT:    v_addc_u32_e32 v5, vcc, 0, v1, vcc
166; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1]
167; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 63, v0
168; GCN-IR-NEXT:    v_lshl_b64 v[0:1], s[6:7], v0
169; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[0:1]
170; GCN-IR-NEXT:    s_cbranch_vccz BB0_4
171; GCN-IR-NEXT:  ; %bb.3:
172; GCN-IR-NEXT:    v_mov_b32_e32 v2, 0
173; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
174; GCN-IR-NEXT:    s_branch BB0_6
175; GCN-IR-NEXT:  BB0_4: ; %udiv-preheader
176; GCN-IR-NEXT:    v_not_b32_e32 v2, v2
177; GCN-IR-NEXT:    s_add_u32 s8, s2, -1
178; GCN-IR-NEXT:    v_lshr_b64 v[6:7], s[6:7], v4
179; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, v2, v3
180; GCN-IR-NEXT:    v_mov_b32_e32 v8, 0
181; GCN-IR-NEXT:    s_addc_u32 s9, s3, -1
182; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[0:1], -1, 0, vcc
183; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
184; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
185; GCN-IR-NEXT:  BB0_5: ; %udiv-do-while
186; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
187; GCN-IR-NEXT:    v_lshl_b64 v[6:7], v[6:7], 1
188; GCN-IR-NEXT:    v_lshrrev_b32_e32 v2, 31, v1
189; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
190; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v2
191; GCN-IR-NEXT:    v_or_b32_e32 v0, v8, v0
192; GCN-IR-NEXT:    v_mov_b32_e32 v2, s9
193; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, s8, v6
194; GCN-IR-NEXT:    v_subb_u32_e32 v2, vcc, v2, v7, vcc
195; GCN-IR-NEXT:    v_ashrrev_i32_e32 v8, 31, v2
196; GCN-IR-NEXT:    v_and_b32_e32 v10, s2, v8
197; GCN-IR-NEXT:    v_and_b32_e32 v2, 1, v8
198; GCN-IR-NEXT:    v_and_b32_e32 v11, s3, v8
199; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
200; GCN-IR-NEXT:    v_or_b32_e32 v1, v9, v1
201; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
202; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
203; GCN-IR-NEXT:    v_mov_b32_e32 v4, v8
204; GCN-IR-NEXT:    v_sub_i32_e64 v6, s[0:1], v6, v10
205; GCN-IR-NEXT:    v_mov_b32_e32 v5, v9
206; GCN-IR-NEXT:    v_mov_b32_e32 v9, v3
207; GCN-IR-NEXT:    v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1]
208; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
209; GCN-IR-NEXT:    v_mov_b32_e32 v8, v2
210; GCN-IR-NEXT:    s_cbranch_vccz BB0_5
211; GCN-IR-NEXT:  BB0_6: ; %udiv-loop-exit
212; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
213; GCN-IR-NEXT:    v_or_b32_e32 v0, v2, v0
214; GCN-IR-NEXT:    v_or_b32_e32 v1, v3, v1
215; GCN-IR-NEXT:  BB0_7: ; %udiv-end
216; GCN-IR-NEXT:    v_mul_lo_u32 v1, s2, v1
217; GCN-IR-NEXT:    v_mul_hi_u32 v2, s2, v0
218; GCN-IR-NEXT:    v_mul_lo_u32 v3, s3, v0
219; GCN-IR-NEXT:    v_mul_lo_u32 v0, s2, v0
220; GCN-IR-NEXT:    s_mov_b32 s11, 0xf000
221; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
222; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
223; GCN-IR-NEXT:    v_mov_b32_e32 v2, s7
224; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
225; GCN-IR-NEXT:    s_mov_b32 s10, -1
226; GCN-IR-NEXT:    s_mov_b32 s8, s4
227; GCN-IR-NEXT:    s_mov_b32 s9, s5
228; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
229; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
230; GCN-IR-NEXT:    s_endpgm
231  %result = urem i64 %x, %y
232  store i64 %result, i64 addrspace(1)* %out
233  ret void
234}
235
236define i64 @v_test_srem(i64 %x, i64 %y) {
237; GCN-LABEL: v_test_srem:
238; GCN:       ; %bb.0:
239; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
240; GCN-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
241; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
242; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
243; GCN-NEXT:    v_xor_b32_e32 v3, v3, v4
244; GCN-NEXT:    v_xor_b32_e32 v2, v2, v4
245; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v2
246; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v3
247; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v2
248; GCN-NEXT:    v_subb_u32_e32 v7, vcc, 0, v3, vcc
249; GCN-NEXT:    v_mov_b32_e32 v14, 0
250; GCN-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
251; GCN-NEXT:    v_rcp_f32_e32 v4, v4
252; GCN-NEXT:    v_mov_b32_e32 v13, 0
253; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
254; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
255; GCN-NEXT:    v_trunc_f32_e32 v5, v5
256; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
257; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
258; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
259; GCN-NEXT:    v_mul_hi_u32 v8, v6, v4
260; GCN-NEXT:    v_mul_lo_u32 v9, v6, v5
261; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
262; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
263; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
264; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
265; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
266; GCN-NEXT:    v_mul_hi_u32 v10, v4, v8
267; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
268; GCN-NEXT:    v_mul_hi_u32 v15, v5, v8
269; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
270; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
271; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
272; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
273; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v10, vcc
274; GCN-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
275; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v10, v9, vcc
276; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v15, v13, vcc
277; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
278; GCN-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v8
279; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v10, vcc
280; GCN-NEXT:    v_addc_u32_e64 v8, vcc, v5, v9, s[4:5]
281; GCN-NEXT:    v_mul_lo_u32 v10, v6, v8
282; GCN-NEXT:    v_mul_hi_u32 v11, v6, v4
283; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
284; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
285; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
286; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
287; GCN-NEXT:    v_mul_lo_u32 v12, v4, v7
288; GCN-NEXT:    v_mul_hi_u32 v15, v4, v6
289; GCN-NEXT:    v_mul_hi_u32 v16, v4, v7
290; GCN-NEXT:    v_mul_hi_u32 v11, v8, v6
291; GCN-NEXT:    v_mul_lo_u32 v6, v8, v6
292; GCN-NEXT:    v_add_i32_e32 v12, vcc, v15, v12
293; GCN-NEXT:    v_mul_hi_u32 v10, v8, v7
294; GCN-NEXT:    v_addc_u32_e32 v15, vcc, v14, v16, vcc
295; GCN-NEXT:    v_mul_lo_u32 v7, v8, v7
296; GCN-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
297; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v15, v11, vcc
298; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v13, vcc
299; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
300; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v14, v8, vcc
301; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
302; GCN-NEXT:    v_addc_u32_e64 v5, vcc, v5, v7, s[4:5]
303; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
304; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
305; GCN-NEXT:    v_ashrrev_i32_e32 v6, 31, v1
306; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
307; GCN-NEXT:    v_xor_b32_e32 v0, v0, v6
308; GCN-NEXT:    v_mul_lo_u32 v7, v0, v5
309; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
310; GCN-NEXT:    v_mul_hi_u32 v9, v0, v5
311; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v6, vcc
312; GCN-NEXT:    v_xor_b32_e32 v1, v1, v6
313; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
314; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v14, v9, vcc
315; GCN-NEXT:    v_mul_lo_u32 v9, v1, v4
316; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
317; GCN-NEXT:    v_mul_hi_u32 v10, v1, v5
318; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
319; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
320; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
321; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v10, v13, vcc
322; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
323; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v14, v7, vcc
324; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
325; GCN-NEXT:    v_mul_hi_u32 v7, v2, v4
326; GCN-NEXT:    v_mul_lo_u32 v8, v3, v4
327; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
328; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
329; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
330; GCN-NEXT:    v_sub_i32_e32 v7, vcc, v1, v5
331; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
332; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v7, v3, vcc
333; GCN-NEXT:    v_sub_i32_e64 v7, s[4:5], v0, v2
334; GCN-NEXT:    v_subbrev_u32_e64 v8, s[6:7], 0, v4, s[4:5]
335; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v8, v3
336; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
337; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[6:7]
338; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v7, v2
339; GCN-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[6:7]
340; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v8, v3
341; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
342; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v3, s[4:5]
343; GCN-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[6:7]
344; GCN-NEXT:    v_sub_i32_e64 v10, s[4:5], v7, v2
345; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
346; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
347; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
348; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
349; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
350; GCN-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
351; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v9
352; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
353; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v10, s[4:5]
354; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
355; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v4, s[4:5]
356; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
357; GCN-NEXT:    v_xor_b32_e32 v0, v0, v6
358; GCN-NEXT:    v_xor_b32_e32 v1, v1, v6
359; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
360; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
361; GCN-NEXT:    s_setpc_b64 s[30:31]
362;
363; GCN-IR-LABEL: v_test_srem:
364; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
365; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
366; GCN-IR-NEXT:    v_ashrrev_i32_e32 v4, 31, v1
367; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v4
368; GCN-IR-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
369; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v4
370; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
371; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc
372; GCN-IR-NEXT:    v_xor_b32_e32 v2, v2, v6
373; GCN-IR-NEXT:    v_sub_i32_e32 v5, vcc, v2, v6
374; GCN-IR-NEXT:    v_xor_b32_e32 v3, v3, v6
375; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v3, v6, vcc
376; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[5:6]
377; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
378; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v5
379; GCN-IR-NEXT:    s_or_b64 s[6:7], vcc, s[4:5]
380; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, 32, v3
381; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v6
382; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v6
383; GCN-IR-NEXT:    v_cndmask_b32_e32 v12, v7, v3, vcc
384; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v0
385; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, 32, v3
386; GCN-IR-NEXT:    v_ffbh_u32_e32 v7, v1
387; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
388; GCN-IR-NEXT:    v_cndmask_b32_e32 v14, v7, v3, vcc
389; GCN-IR-NEXT:    v_sub_i32_e32 v7, vcc, v12, v14
390; GCN-IR-NEXT:    v_subb_u32_e64 v8, s[4:5], 0, 0, vcc
391; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[7:8]
392; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[4:5], 63, v[7:8]
393; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], vcc
394; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
395; GCN-IR-NEXT:    s_xor_b64 s[8:9], s[6:7], -1
396; GCN-IR-NEXT:    v_mov_b32_e32 v2, v4
397; GCN-IR-NEXT:    v_mov_b32_e32 v15, v13
398; GCN-IR-NEXT:    v_cndmask_b32_e64 v3, v1, 0, s[6:7]
399; GCN-IR-NEXT:    s_and_b64 s[4:5], s[8:9], s[4:5]
400; GCN-IR-NEXT:    v_cndmask_b32_e64 v9, v0, 0, s[6:7]
401; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
402; GCN-IR-NEXT:    s_cbranch_execz BB1_6
403; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
404; GCN-IR-NEXT:    v_add_i32_e32 v9, vcc, 1, v7
405; GCN-IR-NEXT:    v_addc_u32_e32 v10, vcc, 0, v8, vcc
406; GCN-IR-NEXT:    v_sub_i32_e64 v3, s[4:5], 63, v7
407; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[9:10], v[7:8]
408; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
409; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[0:1], v3
410; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
411; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
412; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
413; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
414; GCN-IR-NEXT:    s_cbranch_execz BB1_5
415; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
416; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, -1, v5
417; GCN-IR-NEXT:    v_lshr_b64 v[16:17], v[0:1], v9
418; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, -1, v6, vcc
419; GCN-IR-NEXT:    v_not_b32_e32 v10, v12
420; GCN-IR-NEXT:    v_not_b32_e32 v11, v13
421; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, v10, v14
422; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, v11, v15, vcc
423; GCN-IR-NEXT:    v_mov_b32_e32 v14, 0
424; GCN-IR-NEXT:    v_mov_b32_e32 v15, 0
425; GCN-IR-NEXT:  BB1_3: ; %udiv-do-while
426; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
427; GCN-IR-NEXT:    v_lshl_b64 v[16:17], v[16:17], 1
428; GCN-IR-NEXT:    v_lshrrev_b32_e32 v10, 31, v8
429; GCN-IR-NEXT:    v_or_b32_e32 v16, v16, v10
430; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
431; GCN-IR-NEXT:    v_sub_i32_e32 v10, vcc, v3, v16
432; GCN-IR-NEXT:    v_subb_u32_e32 v10, vcc, v9, v17, vcc
433; GCN-IR-NEXT:    v_or_b32_e32 v7, v14, v7
434; GCN-IR-NEXT:    v_ashrrev_i32_e32 v14, 31, v10
435; GCN-IR-NEXT:    v_and_b32_e32 v19, v14, v5
436; GCN-IR-NEXT:    v_and_b32_e32 v10, 1, v14
437; GCN-IR-NEXT:    v_and_b32_e32 v18, v14, v6
438; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, 1, v12
439; GCN-IR-NEXT:    v_or_b32_e32 v8, v15, v8
440; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, 0, v13, vcc
441; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[14:15], v[12:13]
442; GCN-IR-NEXT:    v_mov_b32_e32 v12, v14
443; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
444; GCN-IR-NEXT:    v_sub_i32_e64 v16, s[4:5], v16, v19
445; GCN-IR-NEXT:    v_mov_b32_e32 v13, v15
446; GCN-IR-NEXT:    v_mov_b32_e32 v15, v11
447; GCN-IR-NEXT:    v_subb_u32_e64 v17, s[4:5], v17, v18, s[4:5]
448; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
449; GCN-IR-NEXT:    v_mov_b32_e32 v14, v10
450; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
451; GCN-IR-NEXT:    s_cbranch_execnz BB1_3
452; GCN-IR-NEXT:  ; %bb.4: ; %Flow
453; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
454; GCN-IR-NEXT:  BB1_5: ; %Flow3
455; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
456; GCN-IR-NEXT:    v_lshl_b64 v[7:8], v[7:8], 1
457; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v8
458; GCN-IR-NEXT:    v_or_b32_e32 v9, v10, v7
459; GCN-IR-NEXT:  BB1_6: ; %Flow4
460; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
461; GCN-IR-NEXT:    v_mul_lo_u32 v3, v5, v3
462; GCN-IR-NEXT:    v_mul_hi_u32 v7, v5, v9
463; GCN-IR-NEXT:    v_mul_lo_u32 v6, v6, v9
464; GCN-IR-NEXT:    v_mul_lo_u32 v5, v5, v9
465; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
466; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
467; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v5
468; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
469; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v4
470; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
471; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
472; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
473; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
474  %result = srem i64 %x, %y
475  ret i64 %result
476}
477
478define amdgpu_kernel void @s_test_srem23_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
479; GCN-LABEL: s_test_srem23_64:
480; GCN:       ; %bb.0:
481; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
482; GCN-NEXT:    s_load_dword s1, s[0:1], 0xe
483; GCN-NEXT:    s_mov_b32 s3, 0xf000
484; GCN-NEXT:    s_mov_b32 s2, -1
485; GCN-NEXT:    s_waitcnt lgkmcnt(0)
486; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 41
487; GCN-NEXT:    s_ashr_i64 s[0:1], s[0:1], 41
488; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
489; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s6
490; GCN-NEXT:    s_xor_b32 s1, s6, s0
491; GCN-NEXT:    s_ashr_i32 s1, s1, 30
492; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
493; GCN-NEXT:    s_or_b32 s1, s1, 1
494; GCN-NEXT:    v_mov_b32_e32 v3, s1
495; GCN-NEXT:    s_mov_b32 s1, s5
496; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
497; GCN-NEXT:    v_trunc_f32_e32 v2, v2
498; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
499; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
500; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
501; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
502; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
503; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
504; GCN-NEXT:    s_mov_b32 s0, s4
505; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
506; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 23
507; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
508; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
509; GCN-NEXT:    s_endpgm
510;
511; GCN-IR-LABEL: s_test_srem23_64:
512; GCN-IR:       ; %bb.0:
513; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
514; GCN-IR-NEXT:    s_load_dword s1, s[0:1], 0xe
515; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
516; GCN-IR-NEXT:    s_mov_b32 s2, -1
517; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
518; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 41
519; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[0:1], 41
520; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
521; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s6
522; GCN-IR-NEXT:    s_xor_b32 s1, s6, s0
523; GCN-IR-NEXT:    s_ashr_i32 s1, s1, 30
524; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
525; GCN-IR-NEXT:    s_or_b32 s1, s1, 1
526; GCN-IR-NEXT:    v_mov_b32_e32 v3, s1
527; GCN-IR-NEXT:    s_mov_b32 s1, s5
528; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
529; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
530; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
531; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
532; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
533; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
534; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
535; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
536; GCN-IR-NEXT:    s_mov_b32 s0, s4
537; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
538; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 23
539; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
540; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
541; GCN-IR-NEXT:    s_endpgm
542  %1 = ashr i64 %x, 41
543  %2 = ashr i64 %y, 41
544  %result = srem i64 %1, %2
545  store i64 %result, i64 addrspace(1)* %out
546  ret void
547}
548
549define amdgpu_kernel void @s_test_srem24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
550; GCN-LABEL: s_test_srem24_64:
551; GCN:       ; %bb.0:
552; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
553; GCN-NEXT:    s_load_dword s1, s[0:1], 0xe
554; GCN-NEXT:    s_mov_b32 s3, 0xf000
555; GCN-NEXT:    s_mov_b32 s2, -1
556; GCN-NEXT:    s_waitcnt lgkmcnt(0)
557; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
558; GCN-NEXT:    s_ashr_i64 s[0:1], s[0:1], 40
559; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
560; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s6
561; GCN-NEXT:    s_xor_b32 s1, s6, s0
562; GCN-NEXT:    s_ashr_i32 s1, s1, 30
563; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
564; GCN-NEXT:    s_or_b32 s1, s1, 1
565; GCN-NEXT:    v_mov_b32_e32 v3, s1
566; GCN-NEXT:    s_mov_b32 s1, s5
567; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
568; GCN-NEXT:    v_trunc_f32_e32 v2, v2
569; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
570; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
571; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
572; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
573; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
574; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
575; GCN-NEXT:    s_mov_b32 s0, s4
576; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
577; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
578; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
579; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
580; GCN-NEXT:    s_endpgm
581;
582; GCN-IR-LABEL: s_test_srem24_64:
583; GCN-IR:       ; %bb.0:
584; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
585; GCN-IR-NEXT:    s_load_dword s1, s[0:1], 0xe
586; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
587; GCN-IR-NEXT:    s_mov_b32 s2, -1
588; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
589; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
590; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[0:1], 40
591; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
592; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s6
593; GCN-IR-NEXT:    s_xor_b32 s1, s6, s0
594; GCN-IR-NEXT:    s_ashr_i32 s1, s1, 30
595; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
596; GCN-IR-NEXT:    s_or_b32 s1, s1, 1
597; GCN-IR-NEXT:    v_mov_b32_e32 v3, s1
598; GCN-IR-NEXT:    s_mov_b32 s1, s5
599; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
600; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
601; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
602; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
603; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
604; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
605; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
606; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
607; GCN-IR-NEXT:    s_mov_b32 s0, s4
608; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
609; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
610; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
611; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
612; GCN-IR-NEXT:    s_endpgm
613  %1 = ashr i64 %x, 40
614  %2 = ashr i64 %y, 40
615  %result = srem i64 %1, %2
616  store i64 %result, i64 addrspace(1)* %out
617  ret void
618}
619
620define i64 @v_test_srem24_64(i64 %x, i64 %y) {
621; GCN-LABEL: v_test_srem24_64:
622; GCN:       ; %bb.0:
623; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
624; GCN-NEXT:    v_ashr_i64 v[2:3], v[2:3], 40
625; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
626; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
627; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
628; GCN-NEXT:    v_xor_b32_e32 v5, v0, v2
629; GCN-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
630; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v3
631; GCN-NEXT:    v_or_b32_e32 v5, 1, v5
632; GCN-NEXT:    v_mul_f32_e32 v4, v1, v4
633; GCN-NEXT:    v_trunc_f32_e32 v4, v4
634; GCN-NEXT:    v_mad_f32 v1, -v4, v3, v1
635; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
636; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
637; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
638; GCN-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
639; GCN-NEXT:    v_mul_lo_u32 v1, v1, v2
640; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
641; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
642; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
643; GCN-NEXT:    s_setpc_b64 s[30:31]
644;
645; GCN-IR-LABEL: v_test_srem24_64:
646; GCN-IR:       ; %bb.0:
647; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
648; GCN-IR-NEXT:    v_ashr_i64 v[2:3], v[2:3], 40
649; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
650; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v3, v2
651; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
652; GCN-IR-NEXT:    v_xor_b32_e32 v5, v0, v2
653; GCN-IR-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
654; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v4, v3
655; GCN-IR-NEXT:    v_or_b32_e32 v5, 1, v5
656; GCN-IR-NEXT:    v_mul_f32_e32 v4, v1, v4
657; GCN-IR-NEXT:    v_trunc_f32_e32 v4, v4
658; GCN-IR-NEXT:    v_mad_f32 v1, -v4, v3, v1
659; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v4, v4
660; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
661; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
662; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
663; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v2
664; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
665; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
666; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
667; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
668  %1 = ashr i64 %x, 40
669  %2 = ashr i64 %y, 40
670  %result = srem i64 %1, %2
671  ret i64 %result
672}
673
674define amdgpu_kernel void @s_test_srem25_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
675; GCN-LABEL: s_test_srem25_64:
676; GCN:       ; %bb.0:
677; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
678; GCN-NEXT:    s_load_dword s1, s[0:1], 0xe
679; GCN-NEXT:    s_mov_b32 s3, 0xf000
680; GCN-NEXT:    s_mov_b32 s2, -1
681; GCN-NEXT:    s_waitcnt lgkmcnt(0)
682; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 39
683; GCN-NEXT:    s_ashr_i64 s[0:1], s[0:1], 39
684; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
685; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s6
686; GCN-NEXT:    s_xor_b32 s1, s6, s0
687; GCN-NEXT:    s_ashr_i32 s1, s1, 30
688; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
689; GCN-NEXT:    s_or_b32 s1, s1, 1
690; GCN-NEXT:    v_mov_b32_e32 v3, s1
691; GCN-NEXT:    s_mov_b32 s1, s5
692; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
693; GCN-NEXT:    v_trunc_f32_e32 v2, v2
694; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
695; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
696; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
697; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
698; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
699; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
700; GCN-NEXT:    s_mov_b32 s0, s4
701; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
702; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 25
703; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
704; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
705; GCN-NEXT:    s_endpgm
706;
707; GCN-IR-LABEL: s_test_srem25_64:
708; GCN-IR:       ; %bb.0:
709; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
710; GCN-IR-NEXT:    s_load_dword s1, s[0:1], 0xe
711; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
712; GCN-IR-NEXT:    s_mov_b32 s2, -1
713; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
714; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 39
715; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[0:1], 39
716; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
717; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s6
718; GCN-IR-NEXT:    s_xor_b32 s1, s6, s0
719; GCN-IR-NEXT:    s_ashr_i32 s1, s1, 30
720; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
721; GCN-IR-NEXT:    s_or_b32 s1, s1, 1
722; GCN-IR-NEXT:    v_mov_b32_e32 v3, s1
723; GCN-IR-NEXT:    s_mov_b32 s1, s5
724; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
725; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
726; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
727; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
728; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
729; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
730; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
731; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
732; GCN-IR-NEXT:    s_mov_b32 s0, s4
733; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
734; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 25
735; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
736; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
737; GCN-IR-NEXT:    s_endpgm
738  %1 = ashr i64 %x, 39
739  %2 = ashr i64 %y, 39
740  %result = srem i64 %1, %2
741  store i64 %result, i64 addrspace(1)* %out
742  ret void
743}
744
745define amdgpu_kernel void @s_test_srem31_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
746; GCN-LABEL: s_test_srem31_64:
747; GCN:       ; %bb.0:
748; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
749; GCN-NEXT:    s_load_dword s1, s[0:1], 0xe
750; GCN-NEXT:    s_mov_b32 s3, 0xf000
751; GCN-NEXT:    s_mov_b32 s2, -1
752; GCN-NEXT:    s_waitcnt lgkmcnt(0)
753; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 33
754; GCN-NEXT:    s_ashr_i64 s[0:1], s[0:1], 33
755; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
756; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s6
757; GCN-NEXT:    s_xor_b32 s1, s6, s0
758; GCN-NEXT:    s_ashr_i32 s1, s1, 30
759; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
760; GCN-NEXT:    s_or_b32 s1, s1, 1
761; GCN-NEXT:    v_mov_b32_e32 v3, s1
762; GCN-NEXT:    s_mov_b32 s1, s5
763; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
764; GCN-NEXT:    v_trunc_f32_e32 v2, v2
765; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
766; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
767; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
768; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
769; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
770; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
771; GCN-NEXT:    s_mov_b32 s0, s4
772; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
773; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 31
774; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
775; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
776; GCN-NEXT:    s_endpgm
777;
778; GCN-IR-LABEL: s_test_srem31_64:
779; GCN-IR:       ; %bb.0:
780; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
781; GCN-IR-NEXT:    s_load_dword s1, s[0:1], 0xe
782; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
783; GCN-IR-NEXT:    s_mov_b32 s2, -1
784; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
785; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 33
786; GCN-IR-NEXT:    s_ashr_i64 s[0:1], s[0:1], 33
787; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
788; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s6
789; GCN-IR-NEXT:    s_xor_b32 s1, s6, s0
790; GCN-IR-NEXT:    s_ashr_i32 s1, s1, 30
791; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
792; GCN-IR-NEXT:    s_or_b32 s1, s1, 1
793; GCN-IR-NEXT:    v_mov_b32_e32 v3, s1
794; GCN-IR-NEXT:    s_mov_b32 s1, s5
795; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
796; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
797; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
798; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
799; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
800; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
801; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
802; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
803; GCN-IR-NEXT:    s_mov_b32 s0, s4
804; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
805; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 31
806; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
807; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
808; GCN-IR-NEXT:    s_endpgm
809  %1 = ashr i64 %x, 33
810  %2 = ashr i64 %y, 33
811  %result = srem i64 %1, %2
812  store i64 %result, i64 addrspace(1)* %out
813  ret void
814}
815
816; 32 known sign bits
817define amdgpu_kernel void @s_test_srem32_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
818; GCN-LABEL: s_test_srem32_64:
819; GCN:       ; %bb.0:
820; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
821; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
822; GCN-NEXT:    s_mov_b32 s3, 0xf000
823; GCN-NEXT:    s_mov_b32 s2, -1
824; GCN-NEXT:    s_waitcnt lgkmcnt(0)
825; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s7
826; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
827; GCN-NEXT:    s_xor_b32 s1, s7, s0
828; GCN-NEXT:    s_ashr_i32 s1, s1, 30
829; GCN-NEXT:    s_or_b32 s1, s1, 1
830; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
831; GCN-NEXT:    v_mov_b32_e32 v3, s1
832; GCN-NEXT:    s_mov_b32 s1, s5
833; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
834; GCN-NEXT:    v_trunc_f32_e32 v2, v2
835; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
836; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
837; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
838; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
839; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
840; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
841; GCN-NEXT:    s_mov_b32 s0, s4
842; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s7, v0
843; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
844; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
845; GCN-NEXT:    s_endpgm
846;
847; GCN-IR-LABEL: s_test_srem32_64:
848; GCN-IR:       ; %bb.0:
849; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
850; GCN-IR-NEXT:    s_load_dword s0, s[0:1], 0xe
851; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
852; GCN-IR-NEXT:    s_mov_b32 s2, -1
853; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
854; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s7
855; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
856; GCN-IR-NEXT:    s_xor_b32 s1, s7, s0
857; GCN-IR-NEXT:    s_ashr_i32 s1, s1, 30
858; GCN-IR-NEXT:    s_or_b32 s1, s1, 1
859; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
860; GCN-IR-NEXT:    v_mov_b32_e32 v3, s1
861; GCN-IR-NEXT:    s_mov_b32 s1, s5
862; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
863; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
864; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
865; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
866; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
867; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
868; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
869; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
870; GCN-IR-NEXT:    s_mov_b32 s0, s4
871; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s7, v0
872; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
873; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
874; GCN-IR-NEXT:    s_endpgm
875  %1 = ashr i64 %x, 32
876  %2 = ashr i64 %y, 32
877  %result = srem i64 %1, %2
878  store i64 %result, i64 addrspace(1)* %out
879  ret void
880}
881
882; 33 known sign bits
883define amdgpu_kernel void @s_test_srem33_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
884; GCN-LABEL: s_test_srem33_64:
885; GCN:       ; %bb.0:
886; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
887; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
888; GCN-NEXT:    v_mov_b32_e32 v7, 0
889; GCN-NEXT:    s_mov_b32 s7, 0xf000
890; GCN-NEXT:    s_mov_b32 s6, -1
891; GCN-NEXT:    s_waitcnt lgkmcnt(0)
892; GCN-NEXT:    s_ashr_i64 s[2:3], s[10:11], 31
893; GCN-NEXT:    s_ashr_i64 s[4:5], s[0:1], 31
894; GCN-NEXT:    s_ashr_i32 s0, s1, 31
895; GCN-NEXT:    s_add_u32 s4, s4, s0
896; GCN-NEXT:    s_mov_b32 s1, s0
897; GCN-NEXT:    s_addc_u32 s5, s5, s0
898; GCN-NEXT:    s_xor_b64 s[12:13], s[4:5], s[0:1]
899; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
900; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
901; GCN-NEXT:    s_sub_u32 s4, 0, s12
902; GCN-NEXT:    s_subb_u32 s5, 0, s13
903; GCN-NEXT:    s_ashr_i32 s10, s11, 31
904; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
905; GCN-NEXT:    v_rcp_f32_e32 v0, v0
906; GCN-NEXT:    v_mov_b32_e32 v1, 0
907; GCN-NEXT:    s_mov_b32 s11, s10
908; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
909; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
910; GCN-NEXT:    v_trunc_f32_e32 v2, v2
911; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
912; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
913; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
914; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
915; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
916; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
917; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
918; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
919; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
920; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
921; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
922; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
923; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
924; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
925; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
926; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v7, v8, vcc
927; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
928; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
929; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
930; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
931; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
932; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
933; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v3
934; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
935; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v2, v4, s[0:1]
936; GCN-NEXT:    v_mul_lo_u32 v5, s4, v3
937; GCN-NEXT:    v_mul_hi_u32 v6, s4, v0
938; GCN-NEXT:    v_mul_lo_u32 v8, s5, v0
939; GCN-NEXT:    s_mov_b32 s5, s9
940; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
941; GCN-NEXT:    v_mul_lo_u32 v6, s4, v0
942; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
943; GCN-NEXT:    v_mul_lo_u32 v10, v0, v5
944; GCN-NEXT:    v_mul_hi_u32 v12, v0, v5
945; GCN-NEXT:    v_mul_hi_u32 v11, v0, v6
946; GCN-NEXT:    v_mul_hi_u32 v9, v3, v6
947; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
948; GCN-NEXT:    v_mul_hi_u32 v8, v3, v5
949; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
950; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v7, v12, vcc
951; GCN-NEXT:    v_mul_lo_u32 v3, v3, v5
952; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
953; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
954; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v1, vcc
955; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
956; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v5, vcc
957; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
958; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v5, s[0:1]
959; GCN-NEXT:    s_add_u32 s0, s2, s10
960; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
961; GCN-NEXT:    s_addc_u32 s1, s3, s10
962; GCN-NEXT:    s_xor_b64 s[14:15], s[0:1], s[10:11]
963; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
964; GCN-NEXT:    v_mul_lo_u32 v3, s14, v2
965; GCN-NEXT:    v_mul_hi_u32 v4, s14, v0
966; GCN-NEXT:    v_mul_hi_u32 v5, s14, v2
967; GCN-NEXT:    v_mul_hi_u32 v6, s15, v2
968; GCN-NEXT:    v_mul_lo_u32 v2, s15, v2
969; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
970; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
971; GCN-NEXT:    v_mul_lo_u32 v5, s15, v0
972; GCN-NEXT:    v_mul_hi_u32 v0, s15, v0
973; GCN-NEXT:    s_mov_b32 s4, s8
974; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
975; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
976; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
977; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
978; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
979; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
980; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
981; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
982; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
983; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
984; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
985; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s15, v1
986; GCN-NEXT:    v_mov_b32_e32 v3, s13
987; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s14, v0
988; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
989; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
990; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
991; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
992; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
993; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
994; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
995; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
996; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
997; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
998; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
999; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
1000; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
1001; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
1002; GCN-NEXT:    v_mov_b32_e32 v5, s15
1003; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
1004; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
1005; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
1006; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
1007; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1008; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
1009; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
1010; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
1011; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1012; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
1013; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1014; GCN-NEXT:    v_xor_b32_e32 v0, s10, v0
1015; GCN-NEXT:    v_xor_b32_e32 v1, s10, v1
1016; GCN-NEXT:    v_mov_b32_e32 v2, s10
1017; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s10, v0
1018; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1019; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1020; GCN-NEXT:    s_endpgm
1021;
1022; GCN-IR-LABEL: s_test_srem33_64:
1023; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1024; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1025; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
1026; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1027; GCN-IR-NEXT:    s_ashr_i32 s2, s7, 31
1028; GCN-IR-NEXT:    s_ashr_i64 s[10:11], s[0:1], 31
1029; GCN-IR-NEXT:    s_ashr_i32 s0, s1, 31
1030; GCN-IR-NEXT:    s_mov_b32 s1, s0
1031; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[6:7], 31
1032; GCN-IR-NEXT:    s_mov_b32 s3, s2
1033; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[8:9], s[2:3]
1034; GCN-IR-NEXT:    s_xor_b64 s[10:11], s[10:11], s[0:1]
1035; GCN-IR-NEXT:    s_sub_u32 s8, s6, s2
1036; GCN-IR-NEXT:    s_subb_u32 s9, s7, s2
1037; GCN-IR-NEXT:    s_sub_u32 s10, s10, s0
1038; GCN-IR-NEXT:    s_subb_u32 s11, s11, s0
1039; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[0:1], s[10:11], 0
1040; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[6:7], s[8:9], 0
1041; GCN-IR-NEXT:    v_cmp_eq_u32_e64 vcc, s11, 0
1042; GCN-IR-NEXT:    s_or_b64 s[6:7], s[0:1], s[6:7]
1043; GCN-IR-NEXT:    s_flbit_i32_b32 s0, s10
1044; GCN-IR-NEXT:    s_add_i32 s0, s0, 32
1045; GCN-IR-NEXT:    s_flbit_i32_b32 s1, s11
1046; GCN-IR-NEXT:    v_mov_b32_e32 v1, s0
1047; GCN-IR-NEXT:    s_flbit_i32_b32 s0, s8
1048; GCN-IR-NEXT:    v_mov_b32_e32 v0, s1
1049; GCN-IR-NEXT:    s_add_i32 s0, s0, 32
1050; GCN-IR-NEXT:    s_flbit_i32_b32 s1, s9
1051; GCN-IR-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
1052; GCN-IR-NEXT:    v_mov_b32_e32 v0, s1
1053; GCN-IR-NEXT:    v_mov_b32_e32 v1, s0
1054; GCN-IR-NEXT:    v_cmp_eq_u32_e64 vcc, s9, 0
1055; GCN-IR-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
1056; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v2, v3
1057; GCN-IR-NEXT:    v_subb_u32_e64 v1, s[0:1], 0, 0, vcc
1058; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[0:1]
1059; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[0:1], 63, v[0:1]
1060; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], vcc
1061; GCN-IR-NEXT:    s_or_b64 s[0:1], s[6:7], s[0:1]
1062; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[0:1]
1063; GCN-IR-NEXT:    s_cbranch_vccz BB8_2
1064; GCN-IR-NEXT:  ; %bb.1:
1065; GCN-IR-NEXT:    v_mov_b32_e32 v0, s9
1066; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[6:7]
1067; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
1068; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[6:7]
1069; GCN-IR-NEXT:    s_branch BB8_7
1070; GCN-IR-NEXT:  BB8_2: ; %udiv-bb1
1071; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
1072; GCN-IR-NEXT:    v_addc_u32_e32 v5, vcc, 0, v1, vcc
1073; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1]
1074; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 63, v0
1075; GCN-IR-NEXT:    v_lshl_b64 v[0:1], s[8:9], v0
1076; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[0:1]
1077; GCN-IR-NEXT:    s_cbranch_vccz BB8_4
1078; GCN-IR-NEXT:  ; %bb.3:
1079; GCN-IR-NEXT:    v_mov_b32_e32 v2, 0
1080; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
1081; GCN-IR-NEXT:    s_branch BB8_6
1082; GCN-IR-NEXT:  BB8_4: ; %udiv-preheader
1083; GCN-IR-NEXT:    v_not_b32_e32 v2, v2
1084; GCN-IR-NEXT:    s_add_u32 s6, s10, -1
1085; GCN-IR-NEXT:    v_lshr_b64 v[6:7], s[8:9], v4
1086; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, v2, v3
1087; GCN-IR-NEXT:    v_mov_b32_e32 v8, 0
1088; GCN-IR-NEXT:    s_addc_u32 s7, s11, -1
1089; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[0:1], -1, 0, vcc
1090; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1091; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
1092; GCN-IR-NEXT:  BB8_5: ; %udiv-do-while
1093; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1094; GCN-IR-NEXT:    v_lshl_b64 v[6:7], v[6:7], 1
1095; GCN-IR-NEXT:    v_lshrrev_b32_e32 v2, 31, v1
1096; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
1097; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v2
1098; GCN-IR-NEXT:    v_or_b32_e32 v0, v8, v0
1099; GCN-IR-NEXT:    v_mov_b32_e32 v2, s7
1100; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, s6, v6
1101; GCN-IR-NEXT:    v_subb_u32_e32 v2, vcc, v2, v7, vcc
1102; GCN-IR-NEXT:    v_ashrrev_i32_e32 v8, 31, v2
1103; GCN-IR-NEXT:    v_and_b32_e32 v10, s10, v8
1104; GCN-IR-NEXT:    v_and_b32_e32 v2, 1, v8
1105; GCN-IR-NEXT:    v_and_b32_e32 v11, s11, v8
1106; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
1107; GCN-IR-NEXT:    v_or_b32_e32 v1, v9, v1
1108; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
1109; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
1110; GCN-IR-NEXT:    v_mov_b32_e32 v4, v8
1111; GCN-IR-NEXT:    v_sub_i32_e64 v6, s[0:1], v6, v10
1112; GCN-IR-NEXT:    v_mov_b32_e32 v5, v9
1113; GCN-IR-NEXT:    v_mov_b32_e32 v9, v3
1114; GCN-IR-NEXT:    v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1]
1115; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1116; GCN-IR-NEXT:    v_mov_b32_e32 v8, v2
1117; GCN-IR-NEXT:    s_cbranch_vccz BB8_5
1118; GCN-IR-NEXT:  BB8_6: ; %udiv-loop-exit
1119; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
1120; GCN-IR-NEXT:    v_or_b32_e32 v0, v2, v0
1121; GCN-IR-NEXT:    v_or_b32_e32 v1, v3, v1
1122; GCN-IR-NEXT:  BB8_7: ; %udiv-end
1123; GCN-IR-NEXT:    v_mul_lo_u32 v1, s10, v1
1124; GCN-IR-NEXT:    v_mul_hi_u32 v2, s10, v0
1125; GCN-IR-NEXT:    v_mul_lo_u32 v3, s11, v0
1126; GCN-IR-NEXT:    v_mul_lo_u32 v0, s10, v0
1127; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1128; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1129; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1130; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s8, v0
1131; GCN-IR-NEXT:    v_mov_b32_e32 v2, s9
1132; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
1133; GCN-IR-NEXT:    v_xor_b32_e32 v0, s2, v0
1134; GCN-IR-NEXT:    v_xor_b32_e32 v1, s3, v1
1135; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
1136; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
1137; GCN-IR-NEXT:    s_mov_b32 s6, -1
1138; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1139; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1140; GCN-IR-NEXT:    s_endpgm
1141  %1 = ashr i64 %x, 31
1142  %2 = ashr i64 %y, 31
1143  %result = srem i64 %1, %2
1144  store i64 %result, i64 addrspace(1)* %out
1145  ret void
1146}
1147
1148define amdgpu_kernel void @s_test_srem24_48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
1149; GCN-LABEL: s_test_srem24_48:
1150; GCN:       ; %bb.0:
1151; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
1152; GCN-NEXT:    s_load_dword s2, s[0:1], 0xb
1153; GCN-NEXT:    s_load_dword s3, s[0:1], 0xc
1154; GCN-NEXT:    s_load_dword s6, s[0:1], 0xd
1155; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
1156; GCN-NEXT:    s_mov_b32 s7, 0xf000
1157; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1158; GCN-NEXT:    v_mov_b32_e32 v2, s2
1159; GCN-NEXT:    s_sext_i32_i16 s1, s3
1160; GCN-NEXT:    v_mov_b32_e32 v0, s6
1161; GCN-NEXT:    s_sext_i32_i16 s0, s0
1162; GCN-NEXT:    v_alignbit_b32 v0, s0, v0, 24
1163; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
1164; GCN-NEXT:    v_alignbit_b32 v2, s1, v2, 24
1165; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
1166; GCN-NEXT:    v_xor_b32_e32 v5, v2, v0
1167; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v1
1168; GCN-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
1169; GCN-NEXT:    v_or_b32_e32 v5, 1, v5
1170; GCN-NEXT:    s_mov_b32 s6, -1
1171; GCN-NEXT:    v_mul_f32_e32 v4, v3, v4
1172; GCN-NEXT:    v_trunc_f32_e32 v4, v4
1173; GCN-NEXT:    v_mad_f32 v3, -v4, v1, v3
1174; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
1175; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1176; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
1177; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
1178; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
1179; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v2, v0
1180; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
1181; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
1182; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
1183; GCN-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
1184; GCN-NEXT:    s_endpgm
1185;
1186; GCN-IR-LABEL: s_test_srem24_48:
1187; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1188; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xb
1189; GCN-IR-NEXT:    s_load_dword s3, s[0:1], 0xc
1190; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xd
1191; GCN-IR-NEXT:    s_load_dword s5, s[0:1], 0xe
1192; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1193; GCN-IR-NEXT:    s_sext_i32_i16 s3, s3
1194; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[2:3], 24
1195; GCN-IR-NEXT:    s_sext_i32_i16 s5, s5
1196; GCN-IR-NEXT:    s_ashr_i32 s2, s3, 31
1197; GCN-IR-NEXT:    s_ashr_i64 s[8:9], s[4:5], 24
1198; GCN-IR-NEXT:    s_ashr_i32 s4, s5, 31
1199; GCN-IR-NEXT:    s_mov_b32 s3, s2
1200; GCN-IR-NEXT:    s_mov_b32 s5, s4
1201; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[6:7], s[2:3]
1202; GCN-IR-NEXT:    s_xor_b64 s[8:9], s[8:9], s[4:5]
1203; GCN-IR-NEXT:    s_sub_u32 s6, s6, s2
1204; GCN-IR-NEXT:    s_subb_u32 s7, s7, s2
1205; GCN-IR-NEXT:    s_sub_u32 s8, s8, s4
1206; GCN-IR-NEXT:    s_subb_u32 s9, s9, s4
1207; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
1208; GCN-IR-NEXT:    s_flbit_i32_b32 s0, s8
1209; GCN-IR-NEXT:    s_add_i32 s0, s0, 32
1210; GCN-IR-NEXT:    s_flbit_i32_b32 s1, s9
1211; GCN-IR-NEXT:    v_mov_b32_e32 v1, s0
1212; GCN-IR-NEXT:    s_flbit_i32_b32 s0, s6
1213; GCN-IR-NEXT:    v_mov_b32_e32 v0, s1
1214; GCN-IR-NEXT:    v_cmp_eq_u32_e64 vcc, s9, 0
1215; GCN-IR-NEXT:    s_add_i32 s0, s0, 32
1216; GCN-IR-NEXT:    s_flbit_i32_b32 s1, s7
1217; GCN-IR-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
1218; GCN-IR-NEXT:    v_mov_b32_e32 v0, s1
1219; GCN-IR-NEXT:    v_mov_b32_e32 v1, s0
1220; GCN-IR-NEXT:    v_cmp_eq_u32_e64 vcc, s7, 0
1221; GCN-IR-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
1222; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v2, v3
1223; GCN-IR-NEXT:    v_subb_u32_e64 v1, s[0:1], 0, 0, vcc
1224; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[8:9], 0
1225; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[6:7], 0
1226; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[0:1]
1227; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
1228; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[0:1], 63, v[0:1]
1229; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], vcc
1230; GCN-IR-NEXT:    s_or_b64 s[0:1], s[10:11], s[0:1]
1231; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[0:1]
1232; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1233; GCN-IR-NEXT:    s_mov_b64 vcc, vcc
1234; GCN-IR-NEXT:    s_cbranch_vccz BB9_2
1235; GCN-IR-NEXT:  ; %bb.1:
1236; GCN-IR-NEXT:    v_mov_b32_e32 v0, s7
1237; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[10:11]
1238; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1239; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[10:11]
1240; GCN-IR-NEXT:    s_branch BB9_7
1241; GCN-IR-NEXT:  BB9_2: ; %udiv-bb1
1242; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
1243; GCN-IR-NEXT:    v_addc_u32_e32 v5, vcc, 0, v1, vcc
1244; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1]
1245; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 63, v0
1246; GCN-IR-NEXT:    v_lshl_b64 v[0:1], s[6:7], v0
1247; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[0:1]
1248; GCN-IR-NEXT:    s_cbranch_vccz BB9_4
1249; GCN-IR-NEXT:  ; %bb.3:
1250; GCN-IR-NEXT:    v_mov_b32_e32 v2, 0
1251; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
1252; GCN-IR-NEXT:    s_branch BB9_6
1253; GCN-IR-NEXT:  BB9_4: ; %udiv-preheader
1254; GCN-IR-NEXT:    v_not_b32_e32 v2, v2
1255; GCN-IR-NEXT:    s_add_u32 s10, s8, -1
1256; GCN-IR-NEXT:    v_lshr_b64 v[6:7], s[6:7], v4
1257; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, v2, v3
1258; GCN-IR-NEXT:    v_mov_b32_e32 v8, 0
1259; GCN-IR-NEXT:    s_addc_u32 s11, s9, -1
1260; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[0:1], -1, 0, vcc
1261; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1262; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
1263; GCN-IR-NEXT:  BB9_5: ; %udiv-do-while
1264; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1265; GCN-IR-NEXT:    v_lshl_b64 v[6:7], v[6:7], 1
1266; GCN-IR-NEXT:    v_lshrrev_b32_e32 v2, 31, v1
1267; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
1268; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v2
1269; GCN-IR-NEXT:    v_or_b32_e32 v0, v8, v0
1270; GCN-IR-NEXT:    v_mov_b32_e32 v2, s11
1271; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, s10, v6
1272; GCN-IR-NEXT:    v_subb_u32_e32 v2, vcc, v2, v7, vcc
1273; GCN-IR-NEXT:    v_ashrrev_i32_e32 v8, 31, v2
1274; GCN-IR-NEXT:    v_and_b32_e32 v10, s8, v8
1275; GCN-IR-NEXT:    v_and_b32_e32 v2, 1, v8
1276; GCN-IR-NEXT:    v_and_b32_e32 v11, s9, v8
1277; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
1278; GCN-IR-NEXT:    v_or_b32_e32 v1, v9, v1
1279; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
1280; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
1281; GCN-IR-NEXT:    v_mov_b32_e32 v4, v8
1282; GCN-IR-NEXT:    v_sub_i32_e64 v6, s[0:1], v6, v10
1283; GCN-IR-NEXT:    v_mov_b32_e32 v5, v9
1284; GCN-IR-NEXT:    v_mov_b32_e32 v9, v3
1285; GCN-IR-NEXT:    v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1]
1286; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1287; GCN-IR-NEXT:    v_mov_b32_e32 v8, v2
1288; GCN-IR-NEXT:    s_cbranch_vccz BB9_5
1289; GCN-IR-NEXT:  BB9_6: ; %udiv-loop-exit
1290; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
1291; GCN-IR-NEXT:    v_or_b32_e32 v0, v2, v0
1292; GCN-IR-NEXT:    v_or_b32_e32 v1, v3, v1
1293; GCN-IR-NEXT:  BB9_7: ; %udiv-end
1294; GCN-IR-NEXT:    v_mul_lo_u32 v1, s8, v1
1295; GCN-IR-NEXT:    v_mul_hi_u32 v2, s8, v0
1296; GCN-IR-NEXT:    v_mul_lo_u32 v3, s9, v0
1297; GCN-IR-NEXT:    v_mul_lo_u32 v0, s8, v0
1298; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1299; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1300; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
1301; GCN-IR-NEXT:    v_mov_b32_e32 v2, s7
1302; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
1303; GCN-IR-NEXT:    v_xor_b32_e32 v0, s2, v0
1304; GCN-IR-NEXT:    v_xor_b32_e32 v1, s3, v1
1305; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
1306; GCN-IR-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
1307; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1308; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1309; GCN-IR-NEXT:    s_mov_b32 s6, -1
1310; GCN-IR-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
1311; GCN-IR-NEXT:    buffer_store_dword v0, off, s[4:7], 0
1312; GCN-IR-NEXT:    s_endpgm
1313  %1 = ashr i48 %x, 24
1314  %2 = ashr i48 %y, 24
1315  %result = srem i48 %1, %2
1316  store i48 %result, i48 addrspace(1)* %out
1317  ret void
1318}
1319
1320define amdgpu_kernel void @s_test_srem_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1321; GCN-LABEL: s_test_srem_k_num_i64:
1322; GCN:       ; %bb.0:
1323; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1324; GCN-NEXT:    v_mov_b32_e32 v2, 0
1325; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1326; GCN-NEXT:    s_ashr_i32 s0, s7, 31
1327; GCN-NEXT:    s_add_u32 s2, s6, s0
1328; GCN-NEXT:    s_addc_u32 s3, s7, s0
1329; GCN-NEXT:    s_mov_b32 s1, s0
1330; GCN-NEXT:    s_xor_b64 s[8:9], s[2:3], s[0:1]
1331; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
1332; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s9
1333; GCN-NEXT:    s_sub_u32 s2, 0, s8
1334; GCN-NEXT:    s_subb_u32 s3, 0, s9
1335; GCN-NEXT:    s_mov_b32 s7, 0xf000
1336; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
1337; GCN-NEXT:    v_rcp_f32_e32 v0, v0
1338; GCN-NEXT:    v_mov_b32_e32 v1, 0
1339; GCN-NEXT:    s_mov_b32 s6, -1
1340; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
1341; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
1342; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1343; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
1344; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
1345; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1346; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
1347; GCN-NEXT:    v_mul_lo_u32 v4, s2, v3
1348; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
1349; GCN-NEXT:    v_mul_lo_u32 v6, s2, v0
1350; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1351; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
1352; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
1353; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
1354; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
1355; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
1356; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
1357; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
1358; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
1359; GCN-NEXT:    v_mul_hi_u32 v9, v3, v4
1360; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1361; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
1362; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
1363; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v1, vcc
1364; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1365; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
1366; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
1367; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
1368; GCN-NEXT:    v_mul_lo_u32 v6, s2, v4
1369; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
1370; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
1371; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1372; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
1373; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
1374; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
1375; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
1376; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
1377; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
1378; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
1379; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
1380; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
1381; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
1382; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
1383; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
1384; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
1385; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v1, vcc
1386; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
1387; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
1388; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1389; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
1390; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
1391; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1392; GCN-NEXT:    v_mul_hi_u32 v5, 24, v0
1393; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
1394; GCN-NEXT:    v_mul_hi_u32 v6, 24, v3
1395; GCN-NEXT:    v_mul_hi_u32 v0, 0, v0
1396; GCN-NEXT:    v_mul_hi_u32 v3, 0, v3
1397; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1398; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v6, vcc
1399; GCN-NEXT:    v_add_i32_e32 v4, vcc, 0, v4
1400; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v2, v0, vcc
1401; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
1402; GCN-NEXT:    v_mul_lo_u32 v1, s8, v1
1403; GCN-NEXT:    v_mul_hi_u32 v2, s8, v0
1404; GCN-NEXT:    v_mul_lo_u32 v3, s9, v0
1405; GCN-NEXT:    v_mul_lo_u32 v0, s8, v0
1406; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1407; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1408; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
1409; GCN-NEXT:    v_mov_b32_e32 v3, s9
1410; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1411; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
1412; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s8, v0
1413; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
1414; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s9, v5
1415; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
1416; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
1417; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s8, v4
1418; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s8, v4
1419; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
1420; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s9, v5
1421; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1422; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
1423; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
1424; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
1425; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
1426; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
1427; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
1428; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
1429; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1430; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v1
1431; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
1432; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
1433; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
1434; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
1435; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1436; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1437; GCN-NEXT:    s_endpgm
1438;
1439; GCN-IR-LABEL: s_test_srem_k_num_i64:
1440; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1441; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1442; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1443; GCN-IR-NEXT:    s_ashr_i32 s0, s7, 31
1444; GCN-IR-NEXT:    s_mov_b32 s1, s0
1445; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[6:7], s[0:1]
1446; GCN-IR-NEXT:    s_sub_u32 s2, s2, s0
1447; GCN-IR-NEXT:    s_subb_u32 s3, s3, s0
1448; GCN-IR-NEXT:    s_flbit_i32_b32 s0, s2
1449; GCN-IR-NEXT:    s_add_i32 s0, s0, 32
1450; GCN-IR-NEXT:    s_flbit_i32_b32 s1, s3
1451; GCN-IR-NEXT:    v_mov_b32_e32 v0, s1
1452; GCN-IR-NEXT:    v_mov_b32_e32 v1, s0
1453; GCN-IR-NEXT:    v_cmp_eq_u32_e64 vcc, s3, 0
1454; GCN-IR-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
1455; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, 0xffffffc5, v2
1456; GCN-IR-NEXT:    v_addc_u32_e64 v1, s[0:1], 0, -1, vcc
1457; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[2:3], 0
1458; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[0:1]
1459; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[0:1], 63, v[0:1]
1460; GCN-IR-NEXT:    s_or_b64 s[8:9], s[8:9], vcc
1461; GCN-IR-NEXT:    s_or_b64 s[0:1], s[8:9], s[0:1]
1462; GCN-IR-NEXT:    s_mov_b32 s6, -1
1463; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[0:1]
1464; GCN-IR-NEXT:    s_cbranch_vccz BB10_2
1465; GCN-IR-NEXT:  ; %bb.1:
1466; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1467; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, 24, 0, s[8:9]
1468; GCN-IR-NEXT:    s_branch BB10_7
1469; GCN-IR-NEXT:  BB10_2: ; %udiv-bb1
1470; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
1471; GCN-IR-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
1472; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[0:1], v[3:4], v[0:1]
1473; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 63, v0
1474; GCN-IR-NEXT:    v_lshl_b64 v[0:1], 24, v0
1475; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[0:1]
1476; GCN-IR-NEXT:    s_cbranch_vccz BB10_4
1477; GCN-IR-NEXT:  ; %bb.3:
1478; GCN-IR-NEXT:    v_mov_b32_e32 v2, 0
1479; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
1480; GCN-IR-NEXT:    s_branch BB10_6
1481; GCN-IR-NEXT:  BB10_4: ; %udiv-preheader
1482; GCN-IR-NEXT:    s_add_u32 s7, s2, -1
1483; GCN-IR-NEXT:    v_lshr_b64 v[6:7], 24, v3
1484; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, 58, v2
1485; GCN-IR-NEXT:    v_mov_b32_e32 v8, 0
1486; GCN-IR-NEXT:    s_addc_u32 s8, s3, -1
1487; GCN-IR-NEXT:    v_subb_u32_e64 v5, s[0:1], 0, 0, vcc
1488; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1489; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
1490; GCN-IR-NEXT:  BB10_5: ; %udiv-do-while
1491; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1492; GCN-IR-NEXT:    v_lshl_b64 v[6:7], v[6:7], 1
1493; GCN-IR-NEXT:    v_lshrrev_b32_e32 v2, 31, v1
1494; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
1495; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v2
1496; GCN-IR-NEXT:    v_or_b32_e32 v0, v8, v0
1497; GCN-IR-NEXT:    v_mov_b32_e32 v2, s8
1498; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, s7, v6
1499; GCN-IR-NEXT:    v_subb_u32_e32 v2, vcc, v2, v7, vcc
1500; GCN-IR-NEXT:    v_ashrrev_i32_e32 v8, 31, v2
1501; GCN-IR-NEXT:    v_and_b32_e32 v10, s2, v8
1502; GCN-IR-NEXT:    v_and_b32_e32 v2, 1, v8
1503; GCN-IR-NEXT:    v_and_b32_e32 v11, s3, v8
1504; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
1505; GCN-IR-NEXT:    v_or_b32_e32 v1, v9, v1
1506; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
1507; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
1508; GCN-IR-NEXT:    v_mov_b32_e32 v4, v8
1509; GCN-IR-NEXT:    v_sub_i32_e64 v6, s[0:1], v6, v10
1510; GCN-IR-NEXT:    v_mov_b32_e32 v5, v9
1511; GCN-IR-NEXT:    v_mov_b32_e32 v9, v3
1512; GCN-IR-NEXT:    v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1]
1513; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1514; GCN-IR-NEXT:    v_mov_b32_e32 v8, v2
1515; GCN-IR-NEXT:    s_cbranch_vccz BB10_5
1516; GCN-IR-NEXT:  BB10_6: ; %udiv-loop-exit
1517; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
1518; GCN-IR-NEXT:    v_or_b32_e32 v0, v2, v0
1519; GCN-IR-NEXT:    v_or_b32_e32 v1, v3, v1
1520; GCN-IR-NEXT:  BB10_7: ; %udiv-end
1521; GCN-IR-NEXT:    v_mul_lo_u32 v1, s2, v1
1522; GCN-IR-NEXT:    v_mul_hi_u32 v2, s2, v0
1523; GCN-IR-NEXT:    v_mul_lo_u32 v3, s3, v0
1524; GCN-IR-NEXT:    v_mul_lo_u32 v0, s2, v0
1525; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1526; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1527; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1528; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1529; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1530; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1531; GCN-IR-NEXT:    s_endpgm
1532  %result = srem i64 24, %x
1533  store i64 %result, i64 addrspace(1)* %out
1534  ret void
1535}
1536
1537define i64 @v_test_srem_k_num_i64(i64 %x) {
1538; GCN-LABEL: v_test_srem_k_num_i64:
1539; GCN:       ; %bb.0:
1540; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1541; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1542; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1543; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1544; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1545; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1546; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1547; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1548; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1549; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1550; GCN-NEXT:    v_mov_b32_e32 v12, 0
1551; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
1552; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1553; GCN-NEXT:    v_mov_b32_e32 v11, 0
1554; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1555; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1556; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1557; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1558; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1559; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1560; GCN-NEXT:    v_mul_hi_u32 v6, v4, v2
1561; GCN-NEXT:    v_mul_lo_u32 v7, v4, v3
1562; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1563; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
1564; GCN-NEXT:    v_mul_lo_u32 v7, v4, v2
1565; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1566; GCN-NEXT:    v_mul_lo_u32 v9, v2, v6
1567; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
1568; GCN-NEXT:    v_mul_hi_u32 v10, v2, v7
1569; GCN-NEXT:    v_mul_hi_u32 v13, v3, v6
1570; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1571; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1572; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
1573; GCN-NEXT:    v_mul_hi_u32 v7, v3, v7
1574; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v8, vcc
1575; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
1576; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v7, vcc
1577; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v11, vcc
1578; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1579; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v6
1580; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v8, vcc
1581; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v3, v7, s[4:5]
1582; GCN-NEXT:    v_mul_lo_u32 v8, v4, v6
1583; GCN-NEXT:    v_mul_hi_u32 v9, v4, v2
1584; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1585; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1586; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1587; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
1588; GCN-NEXT:    v_mul_lo_u32 v10, v2, v5
1589; GCN-NEXT:    v_mul_hi_u32 v13, v2, v4
1590; GCN-NEXT:    v_mul_hi_u32 v14, v2, v5
1591; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
1592; GCN-NEXT:    v_mul_lo_u32 v4, v6, v4
1593; GCN-NEXT:    v_add_i32_e32 v10, vcc, v13, v10
1594; GCN-NEXT:    v_mul_hi_u32 v8, v6, v5
1595; GCN-NEXT:    v_addc_u32_e32 v13, vcc, v12, v14, vcc
1596; GCN-NEXT:    v_mul_lo_u32 v5, v6, v5
1597; GCN-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
1598; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v13, v9, vcc
1599; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v11, vcc
1600; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1601; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
1602; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
1603; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
1604; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1605; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1606; GCN-NEXT:    v_mul_hi_u32 v5, 24, v2
1607; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
1608; GCN-NEXT:    v_mul_hi_u32 v6, 24, v3
1609; GCN-NEXT:    v_mul_hi_u32 v2, 0, v2
1610; GCN-NEXT:    v_mul_hi_u32 v3, 0, v3
1611; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
1612; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
1613; GCN-NEXT:    v_add_i32_e32 v4, vcc, 0, v4
1614; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v2, vcc
1615; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v11, vcc
1616; GCN-NEXT:    v_mul_lo_u32 v3, v0, v3
1617; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1618; GCN-NEXT:    v_mul_lo_u32 v5, v1, v2
1619; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
1620; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1621; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1622; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
1623; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 24, v2
1624; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
1625; GCN-NEXT:    v_sub_i32_e64 v5, s[4:5], v2, v0
1626; GCN-NEXT:    v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
1627; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v1
1628; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[6:7]
1629; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v5, v0
1630; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
1631; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v6, v1
1632; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
1633; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1634; GCN-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[6:7]
1635; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v5, v0
1636; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
1637; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1638; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1639; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
1640; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v0
1641; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1642; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1643; GCN-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
1644; GCN-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[4:5]
1645; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1646; GCN-NEXT:    v_cndmask_b32_e64 v1, v6, v4, s[4:5]
1647; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1648; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1649; GCN-NEXT:    s_setpc_b64 s[30:31]
1650;
1651; GCN-IR-LABEL: v_test_srem_k_num_i64:
1652; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1653; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1654; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1655; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1656; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
1657; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1658; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1659; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1660; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1661; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1662; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
1663; GCN-IR-NEXT:    v_cndmask_b32_e32 v8, v3, v2, vcc
1664; GCN-IR-NEXT:    s_movk_i32 s6, 0xffc5
1665; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, s6, v8
1666; GCN-IR-NEXT:    v_addc_u32_e64 v4, s[6:7], 0, -1, vcc
1667; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1668; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[3:4]
1669; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1670; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1671; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[3:4]
1672; GCN-IR-NEXT:    v_cndmask_b32_e64 v2, 24, 0, s[4:5]
1673; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1674; GCN-IR-NEXT:    v_mov_b32_e32 v5, v9
1675; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1676; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1677; GCN-IR-NEXT:    s_cbranch_execz BB11_6
1678; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1679; GCN-IR-NEXT:    v_add_i32_e32 v5, vcc, 1, v3
1680; GCN-IR-NEXT:    v_addc_u32_e32 v6, vcc, 0, v4, vcc
1681; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v3
1682; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[5:6], v[3:4]
1683; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1684; GCN-IR-NEXT:    v_lshl_b64 v[2:3], 24, v2
1685; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1686; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1687; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1688; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
1689; GCN-IR-NEXT:    s_cbranch_execz BB11_5
1690; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1691; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, -1, v0
1692; GCN-IR-NEXT:    v_lshr_b64 v[10:11], 24, v5
1693; GCN-IR-NEXT:    v_addc_u32_e32 v5, vcc, -1, v1, vcc
1694; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, 58, v8
1695; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1696; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, 0, v9, vcc
1697; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1698; GCN-IR-NEXT:  BB11_3: ; %udiv-do-while
1699; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1700; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
1701; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v3
1702; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v6
1703; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1704; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v4, v10
1705; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v5, v11, vcc
1706; GCN-IR-NEXT:    v_or_b32_e32 v2, v12, v2
1707; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v6
1708; GCN-IR-NEXT:    v_and_b32_e32 v15, v12, v0
1709; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v12
1710; GCN-IR-NEXT:    v_and_b32_e32 v14, v12, v1
1711; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
1712; GCN-IR-NEXT:    v_or_b32_e32 v3, v13, v3
1713; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
1714; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
1715; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
1716; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1717; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v15
1718; GCN-IR-NEXT:    v_mov_b32_e32 v9, v13
1719; GCN-IR-NEXT:    v_mov_b32_e32 v13, v7
1720; GCN-IR-NEXT:    v_subb_u32_e64 v11, s[4:5], v11, v14, s[4:5]
1721; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
1722; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
1723; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
1724; GCN-IR-NEXT:    s_cbranch_execnz BB11_3
1725; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1726; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1727; GCN-IR-NEXT:  BB11_5: ; %Flow3
1728; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1729; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1730; GCN-IR-NEXT:    v_or_b32_e32 v5, v7, v3
1731; GCN-IR-NEXT:    v_or_b32_e32 v2, v6, v2
1732; GCN-IR-NEXT:  BB11_6: ; %Flow4
1733; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1734; GCN-IR-NEXT:    v_mul_lo_u32 v3, v0, v5
1735; GCN-IR-NEXT:    v_mul_hi_u32 v4, v0, v2
1736; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v2
1737; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, v2
1738; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1739; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
1740; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1741; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1742; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1743  %result = srem i64 24, %x
1744  ret i64 %result
1745}
1746
1747define i64 @v_test_srem_pow2_k_num_i64(i64 %x) {
1748; GCN-LABEL: v_test_srem_pow2_k_num_i64:
1749; GCN:       ; %bb.0:
1750; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1751; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1752; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1753; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
1754; GCN-NEXT:    v_xor_b32_e32 v1, v1, v2
1755; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
1756; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1757; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1758; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1759; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1760; GCN-NEXT:    v_mov_b32_e32 v12, 0
1761; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
1762; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1763; GCN-NEXT:    v_mov_b32_e32 v11, 0
1764; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1765; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1766; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1767; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1768; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1769; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1770; GCN-NEXT:    v_mul_hi_u32 v6, v4, v2
1771; GCN-NEXT:    v_mul_lo_u32 v7, v4, v3
1772; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1773; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
1774; GCN-NEXT:    v_mul_lo_u32 v7, v4, v2
1775; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1776; GCN-NEXT:    v_mul_lo_u32 v9, v2, v6
1777; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
1778; GCN-NEXT:    v_mul_hi_u32 v10, v2, v7
1779; GCN-NEXT:    v_mul_hi_u32 v13, v3, v6
1780; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1781; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
1782; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
1783; GCN-NEXT:    v_mul_hi_u32 v7, v3, v7
1784; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v8, vcc
1785; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
1786; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v7, vcc
1787; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v11, vcc
1788; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1789; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v6
1790; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v8, vcc
1791; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v3, v7, s[4:5]
1792; GCN-NEXT:    v_mul_lo_u32 v8, v4, v6
1793; GCN-NEXT:    v_mul_hi_u32 v9, v4, v2
1794; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1795; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1796; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1797; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
1798; GCN-NEXT:    v_mul_lo_u32 v10, v2, v5
1799; GCN-NEXT:    v_mul_hi_u32 v13, v2, v4
1800; GCN-NEXT:    v_mul_hi_u32 v14, v2, v5
1801; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
1802; GCN-NEXT:    v_mul_lo_u32 v4, v6, v4
1803; GCN-NEXT:    v_add_i32_e32 v10, vcc, v13, v10
1804; GCN-NEXT:    v_mul_hi_u32 v8, v6, v5
1805; GCN-NEXT:    v_addc_u32_e32 v13, vcc, v12, v14, vcc
1806; GCN-NEXT:    v_mul_lo_u32 v5, v6, v5
1807; GCN-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
1808; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v13, v9, vcc
1809; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v11, vcc
1810; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1811; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
1812; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
1813; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
1814; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1815; GCN-NEXT:    s_mov_b32 s4, 0x8000
1816; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
1817; GCN-NEXT:    v_mul_hi_u32 v4, s4, v2
1818; GCN-NEXT:    v_mul_hi_u32 v5, s4, v3
1819; GCN-NEXT:    v_lshlrev_b32_e32 v6, 15, v3
1820; GCN-NEXT:    v_mul_hi_u32 v2, 0, v2
1821; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
1822; GCN-NEXT:    v_mul_hi_u32 v3, 0, v3
1823; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v5, vcc
1824; GCN-NEXT:    v_add_i32_e32 v4, vcc, 0, v4
1825; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v2, vcc
1826; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v11, vcc
1827; GCN-NEXT:    v_mul_lo_u32 v3, v0, v3
1828; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1829; GCN-NEXT:    v_mul_lo_u32 v5, v1, v2
1830; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
1831; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1832; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
1833; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
1834; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s4, v2
1835; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
1836; GCN-NEXT:    v_sub_i32_e64 v5, s[4:5], v2, v0
1837; GCN-NEXT:    v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
1838; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v1
1839; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[6:7]
1840; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v5, v0
1841; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
1842; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v6, v1
1843; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
1844; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1845; GCN-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[6:7]
1846; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v5, v0
1847; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
1848; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1849; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1850; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
1851; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v0
1852; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1853; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1854; GCN-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
1855; GCN-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[4:5]
1856; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1857; GCN-NEXT:    v_cndmask_b32_e64 v1, v6, v4, s[4:5]
1858; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1859; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1860; GCN-NEXT:    s_setpc_b64 s[30:31]
1861;
1862; GCN-IR-LABEL: v_test_srem_pow2_k_num_i64:
1863; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1864; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1865; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1866; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1867; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
1868; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1869; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1870; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1871; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1872; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1873; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
1874; GCN-IR-NEXT:    v_cndmask_b32_e32 v8, v3, v2, vcc
1875; GCN-IR-NEXT:    s_movk_i32 s6, 0xffd0
1876; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, s6, v8
1877; GCN-IR-NEXT:    v_addc_u32_e64 v3, s[6:7], 0, -1, vcc
1878; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1879; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[2:3]
1880; GCN-IR-NEXT:    s_mov_b32 s8, 0x8000
1881; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1882; GCN-IR-NEXT:    v_mov_b32_e32 v4, s8
1883; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[2:3]
1884; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1885; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v4, 0, s[4:5]
1886; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1887; GCN-IR-NEXT:    s_mov_b32 s9, 0
1888; GCN-IR-NEXT:    v_mov_b32_e32 v5, v9
1889; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1890; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1891; GCN-IR-NEXT:    s_cbranch_execz BB12_6
1892; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1893; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 1, v2
1894; GCN-IR-NEXT:    v_addc_u32_e32 v5, vcc, 0, v3, vcc
1895; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[4:5], v[2:3]
1896; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v2
1897; GCN-IR-NEXT:    v_lshl_b64 v[2:3], s[8:9], v2
1898; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1899; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1900; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1901; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1902; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
1903; GCN-IR-NEXT:    s_cbranch_execz BB12_5
1904; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1905; GCN-IR-NEXT:    s_mov_b32 s5, 0
1906; GCN-IR-NEXT:    s_mov_b32 s4, 0x8000
1907; GCN-IR-NEXT:    v_lshr_b64 v[10:11], s[4:5], v4
1908; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, -1, v0
1909; GCN-IR-NEXT:    v_addc_u32_e32 v5, vcc, -1, v1, vcc
1910; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, 47, v8
1911; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1912; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, 0, v9, vcc
1913; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1914; GCN-IR-NEXT:  BB12_3: ; %udiv-do-while
1915; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1916; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
1917; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v3
1918; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v6
1919; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1920; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v4, v10
1921; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v5, v11, vcc
1922; GCN-IR-NEXT:    v_or_b32_e32 v2, v12, v2
1923; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v6
1924; GCN-IR-NEXT:    v_and_b32_e32 v15, v12, v0
1925; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v12
1926; GCN-IR-NEXT:    v_and_b32_e32 v14, v12, v1
1927; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
1928; GCN-IR-NEXT:    v_or_b32_e32 v3, v13, v3
1929; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
1930; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
1931; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
1932; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1933; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v15
1934; GCN-IR-NEXT:    v_mov_b32_e32 v9, v13
1935; GCN-IR-NEXT:    v_mov_b32_e32 v13, v7
1936; GCN-IR-NEXT:    v_subb_u32_e64 v11, s[4:5], v11, v14, s[4:5]
1937; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
1938; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
1939; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
1940; GCN-IR-NEXT:    s_cbranch_execnz BB12_3
1941; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1942; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1943; GCN-IR-NEXT:  BB12_5: ; %Flow3
1944; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1945; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1946; GCN-IR-NEXT:    v_or_b32_e32 v5, v7, v3
1947; GCN-IR-NEXT:    v_or_b32_e32 v4, v6, v2
1948; GCN-IR-NEXT:  BB12_6: ; %Flow4
1949; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1950; GCN-IR-NEXT:    v_mul_lo_u32 v2, v0, v5
1951; GCN-IR-NEXT:    v_mul_hi_u32 v3, v0, v4
1952; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v4
1953; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, v4
1954; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1955; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1956; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1957; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1958; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1959  %result = srem i64 32768, %x
1960  ret i64 %result
1961}
1962
1963define i64 @v_test_srem_pow2_k_den_i64(i64 %x) {
1964; GCN-LABEL: v_test_srem_pow2_k_den_i64:
1965; GCN:       ; %bb.0:
1966; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1967; GCN-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1968; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1969; GCN-NEXT:    v_add_i32_e32 v2, vcc, v0, v2
1970; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
1971; GCN-NEXT:    v_and_b32_e32 v2, 0xffff8000, v2
1972; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1973; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1974; GCN-NEXT:    s_setpc_b64 s[30:31]
1975;
1976; GCN-IR-LABEL: v_test_srem_pow2_k_den_i64:
1977; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1978; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1979; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
1980; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
1981; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1982; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v2
1983; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v0
1984; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
1985; GCN-IR-NEXT:    v_add_i32_e64 v3, s[4:5], 32, v3
1986; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v1
1987; GCN-IR-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v1
1988; GCN-IR-NEXT:    v_cndmask_b32_e64 v8, v4, v3, s[4:5]
1989; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 48, v8
1990; GCN-IR-NEXT:    v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5]
1991; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1992; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
1993; GCN-IR-NEXT:    v_mov_b32_e32 v3, v2
1994; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1995; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1996; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1997; GCN-IR-NEXT:    v_cndmask_b32_e64 v7, v1, 0, s[4:5]
1998; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v0, 0, s[4:5]
1999; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
2000; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
2001; GCN-IR-NEXT:    s_cbranch_execz BB13_6
2002; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
2003; GCN-IR-NEXT:    v_add_i32_e32 v9, vcc, 1, v4
2004; GCN-IR-NEXT:    v_addc_u32_e32 v10, vcc, 0, v5, vcc
2005; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[9:10], v[4:5]
2006; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v4
2007; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
2008; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[0:1], v4
2009; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
2010; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
2011; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
2012; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
2013; GCN-IR-NEXT:    s_cbranch_execz BB13_5
2014; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
2015; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
2016; GCN-IR-NEXT:    v_lshr_b64 v[10:11], v[0:1], v9
2017; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 0xffffffcf, v8
2018; GCN-IR-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, -1, vcc
2019; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
2020; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
2021; GCN-IR-NEXT:  BB13_3: ; %udiv-do-while
2022; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
2023; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
2024; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
2025; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v6
2026; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
2027; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, s12, v10
2028; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, 0, v11, vcc
2029; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
2030; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v6
2031; GCN-IR-NEXT:    v_and_b32_e32 v14, 0x8000, v12
2032; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v12
2033; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
2034; GCN-IR-NEXT:    v_or_b32_e32 v5, v13, v5
2035; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
2036; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
2037; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
2038; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
2039; GCN-IR-NEXT:    v_mov_b32_e32 v9, v13
2040; GCN-IR-NEXT:    v_mov_b32_e32 v13, v7
2041; GCN-IR-NEXT:    v_mov_b32_e32 v15, 0
2042; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v14
2043; GCN-IR-NEXT:    v_subb_u32_e64 v11, s[4:5], v11, v15, s[4:5]
2044; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
2045; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
2046; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
2047; GCN-IR-NEXT:    s_cbranch_execnz BB13_3
2048; GCN-IR-NEXT:  ; %bb.4: ; %Flow
2049; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
2050; GCN-IR-NEXT:  BB13_5: ; %Flow3
2051; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
2052; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
2053; GCN-IR-NEXT:    v_or_b32_e32 v7, v7, v5
2054; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v4
2055; GCN-IR-NEXT:  BB13_6: ; %Flow4
2056; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
2057; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[6:7], 15
2058; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
2059; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
2060; GCN-IR-NEXT:    v_xor_b32_e32 v0, v0, v2
2061; GCN-IR-NEXT:    v_xor_b32_e32 v1, v1, v3
2062; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
2063; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
2064; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2065  %result = srem i64 %x, 32768
2066  ret i64 %result
2067}
2068
2069define amdgpu_kernel void @s_test_srem24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
2070; GCN-LABEL: s_test_srem24_k_num_i64:
2071; GCN:       ; %bb.0:
2072; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
2073; GCN-NEXT:    s_mov_b32 s6, 0x41c00000
2074; GCN-NEXT:    s_waitcnt lgkmcnt(0)
2075; GCN-NEXT:    s_ashr_i64 s[4:5], s[2:3], 40
2076; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
2077; GCN-NEXT:    s_ashr_i32 s5, s4, 30
2078; GCN-NEXT:    s_or_b32 s5, s5, 1
2079; GCN-NEXT:    v_mov_b32_e32 v3, s5
2080; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
2081; GCN-NEXT:    s_mov_b32 s3, 0xf000
2082; GCN-NEXT:    s_mov_b32 s2, -1
2083; GCN-NEXT:    v_mul_f32_e32 v1, s6, v1
2084; GCN-NEXT:    v_trunc_f32_e32 v1, v1
2085; GCN-NEXT:    v_mad_f32 v2, -v1, v0, s6
2086; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
2087; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
2088; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
2089; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
2090; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
2091; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2092; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2093; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2094; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2095; GCN-NEXT:    s_endpgm
2096;
2097; GCN-IR-LABEL: s_test_srem24_k_num_i64:
2098; GCN-IR:       ; %bb.0:
2099; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
2100; GCN-IR-NEXT:    s_mov_b32 s6, 0x41c00000
2101; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
2102; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[2:3], 40
2103; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
2104; GCN-IR-NEXT:    s_ashr_i32 s5, s4, 30
2105; GCN-IR-NEXT:    s_or_b32 s5, s5, 1
2106; GCN-IR-NEXT:    v_mov_b32_e32 v3, s5
2107; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
2108; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
2109; GCN-IR-NEXT:    s_mov_b32 s2, -1
2110; GCN-IR-NEXT:    v_mul_f32_e32 v1, s6, v1
2111; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
2112; GCN-IR-NEXT:    v_mad_f32 v2, -v1, v0, s6
2113; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
2114; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
2115; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
2116; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
2117; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
2118; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2119; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2120; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2121; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2122; GCN-IR-NEXT:    s_endpgm
2123  %x.shr = ashr i64 %x, 40
2124  %result = srem i64 24, %x.shr
2125  store i64 %result, i64 addrspace(1)* %out
2126  ret void
2127}
2128
2129define amdgpu_kernel void @s_test_srem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
2130; GCN-LABEL: s_test_srem24_k_den_i64:
2131; GCN:       ; %bb.0:
2132; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
2133; GCN-NEXT:    s_mov_b32 s8, 0x46b6fe00
2134; GCN-NEXT:    s_mov_b32 s3, 0xf000
2135; GCN-NEXT:    s_mov_b32 s2, -1
2136; GCN-NEXT:    s_waitcnt lgkmcnt(0)
2137; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
2138; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s6
2139; GCN-NEXT:    s_ashr_i32 s0, s6, 30
2140; GCN-NEXT:    s_or_b32 s0, s0, 1
2141; GCN-NEXT:    v_mov_b32_e32 v1, s0
2142; GCN-NEXT:    v_mul_f32_e32 v2, 0x38331158, v0
2143; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2144; GCN-NEXT:    v_mad_f32 v0, -v2, s8, v0
2145; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2146; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s8
2147; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
2148; GCN-NEXT:    s_movk_i32 s0, 0x5b7f
2149; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
2150; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
2151; GCN-NEXT:    s_mov_b32 s0, s4
2152; GCN-NEXT:    s_mov_b32 s1, s5
2153; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
2154; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2155; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2156; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2157; GCN-NEXT:    s_endpgm
2158;
2159; GCN-IR-LABEL: s_test_srem24_k_den_i64:
2160; GCN-IR:       ; %bb.0:
2161; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
2162; GCN-IR-NEXT:    s_mov_b32 s8, 0x46b6fe00
2163; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
2164; GCN-IR-NEXT:    s_mov_b32 s2, -1
2165; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
2166; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
2167; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s6
2168; GCN-IR-NEXT:    s_ashr_i32 s0, s6, 30
2169; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
2170; GCN-IR-NEXT:    v_mov_b32_e32 v1, s0
2171; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x38331158, v0
2172; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2173; GCN-IR-NEXT:    v_mad_f32 v0, -v2, s8, v0
2174; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2175; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s8
2176; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
2177; GCN-IR-NEXT:    s_movk_i32 s0, 0x5b7f
2178; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
2179; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
2180; GCN-IR-NEXT:    s_mov_b32 s0, s4
2181; GCN-IR-NEXT:    s_mov_b32 s1, s5
2182; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
2183; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2184; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2185; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
2186; GCN-IR-NEXT:    s_endpgm
2187  %x.shr = ashr i64 %x, 40
2188  %result = srem i64 %x.shr, 23423
2189  store i64 %result, i64 addrspace(1)* %out
2190  ret void
2191}
2192
2193define i64 @v_test_srem24_k_num_i64(i64 %x) {
2194; GCN-LABEL: v_test_srem24_k_num_i64:
2195; GCN:       ; %bb.0:
2196; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2197; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2198; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
2199; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
2200; GCN-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2201; GCN-NEXT:    v_or_b32_e32 v3, 1, v3
2202; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2203; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
2204; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2205; GCN-NEXT:    v_mad_f32 v4, -v2, v1, s4
2206; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2207; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2208; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2209; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2210; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
2211; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2212; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2213; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2214; GCN-NEXT:    s_setpc_b64 s[30:31]
2215;
2216; GCN-IR-LABEL: v_test_srem24_k_num_i64:
2217; GCN-IR:       ; %bb.0:
2218; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2219; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2220; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
2221; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2222; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2223; GCN-IR-NEXT:    v_or_b32_e32 v3, 1, v3
2224; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2225; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
2226; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2227; GCN-IR-NEXT:    v_mad_f32 v4, -v2, v1, s4
2228; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2229; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2230; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2231; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2232; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
2233; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
2234; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2235; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2236; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2237  %x.shr = ashr i64 %x, 40
2238  %result = srem i64 24, %x.shr
2239  ret i64 %result
2240}
2241
2242define i64 @v_test_srem24_pow2_k_num_i64(i64 %x) {
2243; GCN-LABEL: v_test_srem24_pow2_k_num_i64:
2244; GCN:       ; %bb.0:
2245; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2246; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2247; GCN-NEXT:    s_mov_b32 s4, 0x47000000
2248; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
2249; GCN-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2250; GCN-NEXT:    v_or_b32_e32 v3, 1, v3
2251; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2252; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
2253; GCN-NEXT:    v_trunc_f32_e32 v2, v2
2254; GCN-NEXT:    v_mad_f32 v4, -v2, v1, s4
2255; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
2256; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2257; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2258; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2259; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
2260; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
2261; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
2262; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2263; GCN-NEXT:    s_setpc_b64 s[30:31]
2264;
2265; GCN-IR-LABEL: v_test_srem24_pow2_k_num_i64:
2266; GCN-IR:       ; %bb.0:
2267; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2268; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2269; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2270; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2271; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
2272; GCN-IR-NEXT:    v_or_b32_e32 v3, 1, v3
2273; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
2274; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
2275; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
2276; GCN-IR-NEXT:    v_mad_f32 v4, -v2, v1, s4
2277; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
2278; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
2279; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
2280; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
2281; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
2282; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
2283; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2284; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2285; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2286  %x.shr = ashr i64 %x, 40
2287  %result = srem i64 32768, %x.shr
2288  ret i64 %result
2289}
2290
2291define i64 @v_test_srem24_pow2_k_den_i64(i64 %x) {
2292; GCN-LABEL: v_test_srem24_pow2_k_den_i64:
2293; GCN:       ; %bb.0:
2294; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2295; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2296; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v1
2297; GCN-NEXT:    v_add_i32_e32 v2, vcc, v0, v2
2298; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
2299; GCN-NEXT:    v_and_b32_e32 v2, 0xffff8000, v2
2300; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
2301; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
2302; GCN-NEXT:    s_setpc_b64 s[30:31]
2303;
2304; GCN-IR-LABEL: v_test_srem24_pow2_k_den_i64:
2305; GCN-IR:       ; %bb.0:
2306; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2307; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
2308; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
2309; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
2310; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 30, v0
2311; GCN-IR-NEXT:    v_or_b32_e32 v2, 1, v2
2312; GCN-IR-NEXT:    v_mul_f32_e32 v3, 0x38000000, v1
2313; GCN-IR-NEXT:    v_trunc_f32_e32 v3, v3
2314; GCN-IR-NEXT:    v_mad_f32 v1, -v3, s4, v1
2315; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v3
2316; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
2317; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
2318; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
2319; GCN-IR-NEXT:    v_lshlrev_b32_e32 v1, 15, v1
2320; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
2321; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
2322; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
2323; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
2324  %x.shr = ashr i64 %x, 40
2325  %result = srem i64 %x.shr, 32768
2326  ret i64 %result
2327}
2328