1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mtriple=amdgcn-- -mcpu=verde -verify-machineinstrs < %s | FileCheck %s -check-prefixes=SI
3; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefixes=VI
4; RUN:  llc -amdgpu-scalarize-global-loads=false  -march=r600 -mtriple=r600-- -mcpu=redwood -verify-machineinstrs < %s | FileCheck %s -check-prefixes=EG
5
6declare i32 @llvm.amdgcn.workitem.id.x() #0
7
8define amdgpu_kernel void @ashr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
9; SI-LABEL: ashr_v2i32:
10; SI:       ; %bb.0:
11; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
12; SI-NEXT:    s_mov_b32 s3, 0xf000
13; SI-NEXT:    s_mov_b32 s2, -1
14; SI-NEXT:    s_mov_b32 s10, s2
15; SI-NEXT:    s_mov_b32 s11, s3
16; SI-NEXT:    s_waitcnt lgkmcnt(0)
17; SI-NEXT:    s_mov_b32 s8, s6
18; SI-NEXT:    s_mov_b32 s9, s7
19; SI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
20; SI-NEXT:    s_mov_b32 s0, s4
21; SI-NEXT:    s_mov_b32 s1, s5
22; SI-NEXT:    s_waitcnt vmcnt(0)
23; SI-NEXT:    v_ashr_i32_e32 v1, v1, v3
24; SI-NEXT:    v_ashr_i32_e32 v0, v0, v2
25; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
26; SI-NEXT:    s_endpgm
27;
28; VI-LABEL: ashr_v2i32:
29; VI:       ; %bb.0:
30; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
31; VI-NEXT:    s_mov_b32 s3, 0xf000
32; VI-NEXT:    s_mov_b32 s2, -1
33; VI-NEXT:    s_mov_b32 s10, s2
34; VI-NEXT:    s_mov_b32 s11, s3
35; VI-NEXT:    s_waitcnt lgkmcnt(0)
36; VI-NEXT:    s_mov_b32 s8, s6
37; VI-NEXT:    s_mov_b32 s9, s7
38; VI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
39; VI-NEXT:    s_mov_b32 s0, s4
40; VI-NEXT:    s_mov_b32 s1, s5
41; VI-NEXT:    s_waitcnt vmcnt(0)
42; VI-NEXT:    v_ashrrev_i32_e32 v1, v3, v1
43; VI-NEXT:    v_ashrrev_i32_e32 v0, v2, v0
44; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
45; VI-NEXT:    s_endpgm
46;
47; EG-LABEL: ashr_v2i32:
48; EG:       ; %bb.0:
49; EG-NEXT:    ALU 0, @10, KC0[CB0:0-32], KC1[]
50; EG-NEXT:    TEX 1 @6
51; EG-NEXT:    ALU 3, @11, KC0[CB0:0-32], KC1[]
52; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
53; EG-NEXT:    CF_END
54; EG-NEXT:    PAD
55; EG-NEXT:    Fetch clause starting at 6:
56; EG-NEXT:     VTX_READ_64 T1.XY, T0.X, 8, #1
57; EG-NEXT:     VTX_READ_64 T0.XY, T0.X, 0, #1
58; EG-NEXT:    ALU clause starting at 10:
59; EG-NEXT:     MOV * T0.X, KC0[2].Z,
60; EG-NEXT:    ALU clause starting at 11:
61; EG-NEXT:     ASHR * T0.Y, T0.Y, T1.Y,
62; EG-NEXT:     ASHR T0.X, T0.X, T1.X,
63; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
64; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
65  %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
66  %a = load <2 x i32>, <2 x i32> addrspace(1)* %in
67  %b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr
68  %result = ashr <2 x i32> %a, %b
69  store <2 x i32> %result, <2 x i32> addrspace(1)* %out
70  ret void
71}
72
73define amdgpu_kernel void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
74; SI-LABEL: ashr_v4i32:
75; SI:       ; %bb.0:
76; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
77; SI-NEXT:    s_mov_b32 s3, 0xf000
78; SI-NEXT:    s_mov_b32 s2, -1
79; SI-NEXT:    s_mov_b32 s10, s2
80; SI-NEXT:    s_mov_b32 s11, s3
81; SI-NEXT:    s_waitcnt lgkmcnt(0)
82; SI-NEXT:    s_mov_b32 s8, s6
83; SI-NEXT:    s_mov_b32 s9, s7
84; SI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
85; SI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
86; SI-NEXT:    s_mov_b32 s0, s4
87; SI-NEXT:    s_mov_b32 s1, s5
88; SI-NEXT:    s_waitcnt vmcnt(0)
89; SI-NEXT:    v_ashr_i32_e32 v3, v3, v7
90; SI-NEXT:    v_ashr_i32_e32 v2, v2, v6
91; SI-NEXT:    v_ashr_i32_e32 v1, v1, v5
92; SI-NEXT:    v_ashr_i32_e32 v0, v0, v4
93; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
94; SI-NEXT:    s_endpgm
95;
96; VI-LABEL: ashr_v4i32:
97; VI:       ; %bb.0:
98; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
99; VI-NEXT:    s_mov_b32 s3, 0xf000
100; VI-NEXT:    s_mov_b32 s2, -1
101; VI-NEXT:    s_mov_b32 s10, s2
102; VI-NEXT:    s_mov_b32 s11, s3
103; VI-NEXT:    s_waitcnt lgkmcnt(0)
104; VI-NEXT:    s_mov_b32 s8, s6
105; VI-NEXT:    s_mov_b32 s9, s7
106; VI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
107; VI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
108; VI-NEXT:    s_mov_b32 s0, s4
109; VI-NEXT:    s_mov_b32 s1, s5
110; VI-NEXT:    s_waitcnt vmcnt(0)
111; VI-NEXT:    v_ashrrev_i32_e32 v3, v7, v3
112; VI-NEXT:    v_ashrrev_i32_e32 v2, v6, v2
113; VI-NEXT:    v_ashrrev_i32_e32 v1, v5, v1
114; VI-NEXT:    v_ashrrev_i32_e32 v0, v4, v0
115; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
116; VI-NEXT:    s_endpgm
117;
118; EG-LABEL: ashr_v4i32:
119; EG:       ; %bb.0:
120; EG-NEXT:    ALU 0, @10, KC0[CB0:0-32], KC1[]
121; EG-NEXT:    TEX 1 @6
122; EG-NEXT:    ALU 5, @11, KC0[CB0:0-32], KC1[]
123; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
124; EG-NEXT:    CF_END
125; EG-NEXT:    PAD
126; EG-NEXT:    Fetch clause starting at 6:
127; EG-NEXT:     VTX_READ_128 T1.XYZW, T0.X, 16, #1
128; EG-NEXT:     VTX_READ_128 T0.XYZW, T0.X, 0, #1
129; EG-NEXT:    ALU clause starting at 10:
130; EG-NEXT:     MOV * T0.X, KC0[2].Z,
131; EG-NEXT:    ALU clause starting at 11:
132; EG-NEXT:     ASHR * T0.W, T0.W, T1.W,
133; EG-NEXT:     ASHR * T0.Z, T0.Z, T1.Z,
134; EG-NEXT:     ASHR * T0.Y, T0.Y, T1.Y,
135; EG-NEXT:     ASHR T0.X, T0.X, T1.X,
136; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
137; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
138  %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
139  %a = load <4 x i32>, <4 x i32> addrspace(1)* %in
140  %b = load <4 x i32>, <4 x i32> addrspace(1)* %b_ptr
141  %result = ashr <4 x i32> %a, %b
142  store <4 x i32> %result, <4 x i32> addrspace(1)* %out
143  ret void
144}
145
146; FIXME: The ashr operation is uniform, but because its operands come from a
147; global load we end up with the vector instructions rather than scalar.
148define amdgpu_kernel void @ashr_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) {
149; SI-LABEL: ashr_v2i16:
150; SI:       ; %bb.0:
151; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
152; SI-NEXT:    s_mov_b32 s3, 0xf000
153; SI-NEXT:    s_mov_b32 s2, -1
154; SI-NEXT:    s_mov_b32 s10, s2
155; SI-NEXT:    s_mov_b32 s11, s3
156; SI-NEXT:    s_waitcnt lgkmcnt(0)
157; SI-NEXT:    s_mov_b32 s8, s6
158; SI-NEXT:    s_mov_b32 s9, s7
159; SI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[8:11], 0
160; SI-NEXT:    s_mov_b32 s6, 0xffff
161; SI-NEXT:    s_mov_b32 s0, s4
162; SI-NEXT:    s_mov_b32 s1, s5
163; SI-NEXT:    s_waitcnt vmcnt(0)
164; SI-NEXT:    v_bfe_i32 v2, v0, 0, 16
165; SI-NEXT:    v_and_b32_e32 v3, s6, v1
166; SI-NEXT:    v_ashrrev_i32_e32 v0, 16, v0
167; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
168; SI-NEXT:    v_ashrrev_i32_e32 v0, v1, v0
169; SI-NEXT:    v_ashrrev_i32_e32 v1, v3, v2
170; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
171; SI-NEXT:    v_and_b32_e32 v1, s6, v1
172; SI-NEXT:    v_or_b32_e32 v0, v1, v0
173; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
174; SI-NEXT:    s_endpgm
175;
176; VI-LABEL: ashr_v2i16:
177; VI:       ; %bb.0:
178; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
179; VI-NEXT:    s_mov_b32 s3, 0xf000
180; VI-NEXT:    s_mov_b32 s2, -1
181; VI-NEXT:    s_mov_b32 s10, s2
182; VI-NEXT:    s_mov_b32 s11, s3
183; VI-NEXT:    s_waitcnt lgkmcnt(0)
184; VI-NEXT:    s_mov_b32 s8, s6
185; VI-NEXT:    s_mov_b32 s9, s7
186; VI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[8:11], 0
187; VI-NEXT:    s_mov_b32 s0, s4
188; VI-NEXT:    s_mov_b32 s1, s5
189; VI-NEXT:    s_waitcnt vmcnt(0)
190; VI-NEXT:    v_ashrrev_i32_sdwa v2, sext(v1), sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
191; VI-NEXT:    v_ashrrev_i32_sdwa v0, sext(v1), sext(v0) dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
192; VI-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
193; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
194; VI-NEXT:    s_endpgm
195;
196; EG-LABEL: ashr_v2i16:
197; EG:       ; %bb.0:
198; EG-NEXT:    ALU 1, @10, KC0[CB0:0-32], KC1[]
199; EG-NEXT:    TEX 1 @6
200; EG-NEXT:    ALU 14, @12, KC0[CB0:0-32], KC1[]
201; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T6.X, T7.X, 1
202; EG-NEXT:    CF_END
203; EG-NEXT:    PAD
204; EG-NEXT:    Fetch clause starting at 6:
205; EG-NEXT:     VTX_READ_32 T7.X, T7.X, 0, #1
206; EG-NEXT:     VTX_READ_32 T6.X, T6.X, 4, #1
207; EG-NEXT:    ALU clause starting at 10:
208; EG-NEXT:     MOV * T6.X, KC0[2].Z,
209; EG-NEXT:     MOV * T7.X, PV.X,
210; EG-NEXT:    ALU clause starting at 12:
211; EG-NEXT:     LSHR * T0.W, T7.X, literal.x,
212; EG-NEXT:    16(2.242078e-44), 0(0.000000e+00)
213; EG-NEXT:     BFE_INT T0.Y, PV.W, 0.0, literal.x,
214; EG-NEXT:     LSHR T0.Z, T6.X, literal.x,
215; EG-NEXT:     BFE_INT T0.W, T7.X, 0.0, literal.x, BS:VEC_120/SCL_212
216; EG-NEXT:     AND_INT * T1.W, T6.X, literal.y,
217; EG-NEXT:    16(2.242078e-44), 65535(9.183409e-41)
218; EG-NEXT:     ASHR T0.W, PV.W, PS,
219; EG-NEXT:     ASHR * T1.W, PV.Y, PV.Z,
220; EG-NEXT:     LSHL T1.W, PS, literal.x,
221; EG-NEXT:     AND_INT * T0.W, PV.W, literal.y,
222; EG-NEXT:    16(2.242078e-44), 65535(9.183409e-41)
223; EG-NEXT:     OR_INT T6.X, PS, PV.W,
224; EG-NEXT:     LSHR * T7.X, KC0[2].Y, literal.x,
225; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
226  %b_ptr = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %in, i16 1
227  %a = load <2 x i16>, <2 x i16> addrspace(1)* %in
228  %b = load <2 x i16>, <2 x i16> addrspace(1)* %b_ptr
229  %result = ashr <2 x i16> %a, %b
230  store <2 x i16> %result, <2 x i16> addrspace(1)* %out
231  ret void
232}
233
234; FIXME: The ashr operation is uniform, but because its operands come from a
235; global load we end up with the vector instructions rather than scalar.
236define amdgpu_kernel void @ashr_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) {
237; SI-LABEL: ashr_v4i16:
238; SI:       ; %bb.0:
239; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
240; SI-NEXT:    s_mov_b32 s3, 0xf000
241; SI-NEXT:    s_mov_b32 s2, -1
242; SI-NEXT:    s_mov_b32 s10, s2
243; SI-NEXT:    s_mov_b32 s11, s3
244; SI-NEXT:    s_waitcnt lgkmcnt(0)
245; SI-NEXT:    s_mov_b32 s8, s6
246; SI-NEXT:    s_mov_b32 s9, s7
247; SI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
248; SI-NEXT:    s_mov_b32 s6, 0xffff
249; SI-NEXT:    s_mov_b32 s0, s4
250; SI-NEXT:    s_mov_b32 s1, s5
251; SI-NEXT:    s_waitcnt vmcnt(0)
252; SI-NEXT:    v_bfe_i32 v4, v0, 0, 16
253; SI-NEXT:    v_bfe_i32 v5, v1, 0, 16
254; SI-NEXT:    v_and_b32_e32 v6, s6, v2
255; SI-NEXT:    v_and_b32_e32 v7, s6, v3
256; SI-NEXT:    v_ashrrev_i32_e32 v0, 16, v0
257; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
258; SI-NEXT:    v_ashrrev_i32_e32 v1, 16, v1
259; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
260; SI-NEXT:    v_ashrrev_i32_e32 v1, v3, v1
261; SI-NEXT:    v_ashrrev_i32_e32 v0, v2, v0
262; SI-NEXT:    v_ashrrev_i32_e32 v3, v7, v5
263; SI-NEXT:    v_ashrrev_i32_e32 v2, v6, v4
264; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
265; SI-NEXT:    v_and_b32_e32 v3, s6, v3
266; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
267; SI-NEXT:    v_and_b32_e32 v2, s6, v2
268; SI-NEXT:    v_or_b32_e32 v1, v3, v1
269; SI-NEXT:    v_or_b32_e32 v0, v2, v0
270; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
271; SI-NEXT:    s_endpgm
272;
273; VI-LABEL: ashr_v4i16:
274; VI:       ; %bb.0:
275; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
276; VI-NEXT:    s_mov_b32 s3, 0xf000
277; VI-NEXT:    s_mov_b32 s2, -1
278; VI-NEXT:    s_mov_b32 s10, s2
279; VI-NEXT:    s_mov_b32 s11, s3
280; VI-NEXT:    s_waitcnt lgkmcnt(0)
281; VI-NEXT:    s_mov_b32 s8, s6
282; VI-NEXT:    s_mov_b32 s9, s7
283; VI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
284; VI-NEXT:    s_mov_b32 s0, s4
285; VI-NEXT:    s_mov_b32 s1, s5
286; VI-NEXT:    s_waitcnt vmcnt(0)
287; VI-NEXT:    v_ashrrev_i32_sdwa v4, sext(v2), sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
288; VI-NEXT:    v_ashrrev_i32_sdwa v0, sext(v2), sext(v0) dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
289; VI-NEXT:    v_ashrrev_i32_sdwa v2, sext(v3), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
290; VI-NEXT:    v_ashrrev_i32_sdwa v1, sext(v3), sext(v1) dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
291; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
292; VI-NEXT:    v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
293; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
294; VI-NEXT:    s_endpgm
295;
296; EG-LABEL: ashr_v4i16:
297; EG:       ; %bb.0:
298; EG-NEXT:    ALU 0, @12, KC0[CB0:0-32], KC1[]
299; EG-NEXT:    TEX 0 @8
300; EG-NEXT:    ALU 3, @13, KC0[], KC1[]
301; EG-NEXT:    TEX 0 @10
302; EG-NEXT:    ALU 54, @17, KC0[CB0:0-32], KC1[]
303; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T10.XY, T9.X, 1
304; EG-NEXT:    CF_END
305; EG-NEXT:    PAD
306; EG-NEXT:    Fetch clause starting at 8:
307; EG-NEXT:     VTX_READ_64 T10.XY, T9.X, 0, #1
308; EG-NEXT:    Fetch clause starting at 10:
309; EG-NEXT:     VTX_READ_64 T9.XY, T9.X, 8, #1
310; EG-NEXT:    ALU clause starting at 12:
311; EG-NEXT:     MOV * T9.X, KC0[2].Z,
312; EG-NEXT:    ALU clause starting at 13:
313; EG-NEXT:     MOV T4.X, T10.X,
314; EG-NEXT:     MOV * T5.X, T10.Y,
315; EG-NEXT:     MOV T0.Y, PV.X,
316; EG-NEXT:     MOV * T0.Z, PS,
317; EG-NEXT:    ALU clause starting at 17:
318; EG-NEXT:     MOV T2.X, T9.X,
319; EG-NEXT:     MOV * T3.X, T9.Y,
320; EG-NEXT:     MOV * T0.W, T6.X,
321; EG-NEXT:     MOV T1.Y, T2.X,
322; EG-NEXT:     BFE_INT * T1.W, T0.Y, 0.0, literal.x,
323; EG-NEXT:    16(2.242078e-44), 0(0.000000e+00)
324; EG-NEXT:     AND_INT * T2.W, PV.Y, literal.x,
325; EG-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
326; EG-NEXT:     ASHR * T1.W, T1.W, PV.W,
327; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
328; EG-NEXT:     AND_INT * T0.W, T0.W, literal.y,
329; EG-NEXT:    65535(9.183409e-41), -65536(nan)
330; EG-NEXT:     OR_INT * T0.W, PS, PV.W,
331; EG-NEXT:     MOV * T1.Z, T3.X,
332; EG-NEXT:     MOV * T6.X, T0.W,
333; EG-NEXT:     MOV T0.W, PV.X,
334; EG-NEXT:     LSHR * T1.W, T0.Y, literal.x,
335; EG-NEXT:    16(2.242078e-44), 0(0.000000e+00)
336; EG-NEXT:     BFE_INT T1.W, PS, 0.0, literal.x,
337; EG-NEXT:     LSHR * T2.W, T1.Y, literal.x,
338; EG-NEXT:    16(2.242078e-44), 0(0.000000e+00)
339; EG-NEXT:     ASHR T1.W, PV.W, PS,
340; EG-NEXT:     AND_INT * T0.W, T0.W, literal.x,
341; EG-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
342; EG-NEXT:     LSHL * T1.W, PV.W, literal.x,
343; EG-NEXT:    16(2.242078e-44), 0(0.000000e+00)
344; EG-NEXT:     OR_INT * T0.W, T0.W, PV.W,
345; EG-NEXT:     MOV T6.X, PV.W,
346; EG-NEXT:     MOV T0.Y, T7.X,
347; EG-NEXT:     BFE_INT T0.W, T0.Z, 0.0, literal.x,
348; EG-NEXT:     AND_INT * T1.W, T1.Z, literal.y,
349; EG-NEXT:    16(2.242078e-44), 65535(9.183409e-41)
350; EG-NEXT:     ASHR T0.W, PV.W, PS,
351; EG-NEXT:     AND_INT * T1.W, PV.Y, literal.x,
352; EG-NEXT:    -65536(nan), 0(0.000000e+00)
353; EG-NEXT:     AND_INT * T0.W, PV.W, literal.x,
354; EG-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
355; EG-NEXT:     OR_INT * T0.W, T1.W, PV.W,
356; EG-NEXT:     MOV * T7.X, PV.W,
357; EG-NEXT:     MOV T0.Y, PV.X,
358; EG-NEXT:     LSHR * T0.W, T0.Z, literal.x,
359; EG-NEXT:    16(2.242078e-44), 0(0.000000e+00)
360; EG-NEXT:     BFE_INT T0.W, PV.W, 0.0, literal.x,
361; EG-NEXT:     LSHR * T1.W, T1.Z, literal.x,
362; EG-NEXT:    16(2.242078e-44), 0(0.000000e+00)
363; EG-NEXT:     ASHR T0.W, PV.W, PS,
364; EG-NEXT:     AND_INT * T1.W, T0.Y, literal.x,
365; EG-NEXT:    65535(9.183409e-41), 0(0.000000e+00)
366; EG-NEXT:     LSHL * T0.W, PV.W, literal.x,
367; EG-NEXT:    16(2.242078e-44), 0(0.000000e+00)
368; EG-NEXT:     LSHR T9.X, KC0[2].Y, literal.x,
369; EG-NEXT:     OR_INT * T10.Y, T1.W, PV.W,
370; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
371; EG-NEXT:     MOV T7.X, PV.Y,
372; EG-NEXT:     MOV * T10.X, T6.X,
373  %b_ptr = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %in, i16 1
374  %a = load <4 x i16>, <4 x i16> addrspace(1)* %in
375  %b = load <4 x i16>, <4 x i16> addrspace(1)* %b_ptr
376  %result = ashr <4 x i16> %a, %b
377  store <4 x i16> %result, <4 x i16> addrspace(1)* %out
378  ret void
379}
380
381define amdgpu_kernel void @s_ashr_i64(i64 addrspace(1)* %out, i32 %in) {
382; SI-LABEL: s_ashr_i64:
383; SI:       ; %bb.0: ; %entry
384; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
385; SI-NEXT:    s_load_dword s0, s[0:1], 0xb
386; SI-NEXT:    s_mov_b32 s7, 0xf000
387; SI-NEXT:    s_mov_b32 s6, -1
388; SI-NEXT:    s_waitcnt lgkmcnt(0)
389; SI-NEXT:    s_ashr_i32 s1, s0, 31
390; SI-NEXT:    s_ashr_i64 s[0:1], s[0:1], 8
391; SI-NEXT:    v_mov_b32_e32 v0, s0
392; SI-NEXT:    v_mov_b32_e32 v1, s1
393; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
394; SI-NEXT:    s_endpgm
395;
396; VI-LABEL: s_ashr_i64:
397; VI:       ; %bb.0: ; %entry
398; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
399; VI-NEXT:    s_load_dword s0, s[0:1], 0x2c
400; VI-NEXT:    s_mov_b32 s7, 0xf000
401; VI-NEXT:    s_mov_b32 s6, -1
402; VI-NEXT:    s_waitcnt lgkmcnt(0)
403; VI-NEXT:    s_ashr_i32 s1, s0, 31
404; VI-NEXT:    s_ashr_i64 s[0:1], s[0:1], 8
405; VI-NEXT:    v_mov_b32_e32 v0, s0
406; VI-NEXT:    v_mov_b32_e32 v1, s1
407; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
408; VI-NEXT:    s_endpgm
409;
410; EG-LABEL: s_ashr_i64:
411; EG:       ; %bb.0: ; %entry
412; EG-NEXT:    ALU 4, @4, KC0[CB0:0-32], KC1[]
413; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
414; EG-NEXT:    CF_END
415; EG-NEXT:    PAD
416; EG-NEXT:    ALU clause starting at 4:
417; EG-NEXT:     ASHR * T0.Y, KC0[2].Z, literal.x,
418; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
419; EG-NEXT:     BIT_ALIGN_INT T0.X, PV.Y, KC0[2].Z, literal.x,
420; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.y,
421; EG-NEXT:    8(1.121039e-44), 2(2.802597e-45)
422entry:
423  %in.ext = sext i32 %in to i64
424  %ashr = ashr i64 %in.ext, 8
425  store i64 %ashr, i64 addrspace(1)* %out
426  ret void
427}
428
429define amdgpu_kernel void @ashr_i64_2(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
430; SI-LABEL: ashr_i64_2:
431; SI:       ; %bb.0: ; %entry
432; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
433; SI-NEXT:    s_mov_b32 s3, 0xf000
434; SI-NEXT:    s_mov_b32 s2, -1
435; SI-NEXT:    s_mov_b32 s10, s2
436; SI-NEXT:    s_mov_b32 s11, s3
437; SI-NEXT:    s_waitcnt lgkmcnt(0)
438; SI-NEXT:    s_mov_b32 s8, s6
439; SI-NEXT:    s_mov_b32 s9, s7
440; SI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
441; SI-NEXT:    s_mov_b32 s0, s4
442; SI-NEXT:    s_mov_b32 s1, s5
443; SI-NEXT:    s_waitcnt vmcnt(0)
444; SI-NEXT:    v_ashr_i64 v[0:1], v[0:1], v2
445; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
446; SI-NEXT:    s_endpgm
447;
448; VI-LABEL: ashr_i64_2:
449; VI:       ; %bb.0: ; %entry
450; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
451; VI-NEXT:    s_mov_b32 s3, 0xf000
452; VI-NEXT:    s_mov_b32 s2, -1
453; VI-NEXT:    s_mov_b32 s10, s2
454; VI-NEXT:    s_mov_b32 s11, s3
455; VI-NEXT:    s_waitcnt lgkmcnt(0)
456; VI-NEXT:    s_mov_b32 s8, s6
457; VI-NEXT:    s_mov_b32 s9, s7
458; VI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
459; VI-NEXT:    s_mov_b32 s0, s4
460; VI-NEXT:    s_mov_b32 s1, s5
461; VI-NEXT:    s_waitcnt vmcnt(0)
462; VI-NEXT:    v_ashrrev_i64 v[0:1], v2, v[0:1]
463; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
464; VI-NEXT:    s_endpgm
465;
466; EG-LABEL: ashr_i64_2:
467; EG:       ; %bb.0: ; %entry
468; EG-NEXT:    ALU 0, @8, KC0[CB0:0-32], KC1[]
469; EG-NEXT:    TEX 0 @6
470; EG-NEXT:    ALU 10, @9, KC0[CB0:0-32], KC1[]
471; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
472; EG-NEXT:    CF_END
473; EG-NEXT:    PAD
474; EG-NEXT:    Fetch clause starting at 6:
475; EG-NEXT:     VTX_READ_128 T0.XYZW, T0.X, 0, #1
476; EG-NEXT:    ALU clause starting at 8:
477; EG-NEXT:     MOV * T0.X, KC0[2].Z,
478; EG-NEXT:    ALU clause starting at 9:
479; EG-NEXT:     AND_INT * T0.W, T0.Z, literal.x,
480; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
481; EG-NEXT:     ASHR T1.Z, T0.Y, PV.W,
482; EG-NEXT:     BIT_ALIGN_INT T0.W, T0.Y, T0.X, T0.Z,
483; EG-NEXT:     AND_INT * T1.W, T0.Z, literal.x,
484; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
485; EG-NEXT:     CNDE_INT T0.X, PS, PV.W, PV.Z,
486; EG-NEXT:     ASHR T0.W, T0.Y, literal.x,
487; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.y,
488; EG-NEXT:    31(4.344025e-44), 2(2.802597e-45)
489; EG-NEXT:     CNDE_INT * T0.Y, T1.W, T1.Z, PV.W,
490entry:
491  %b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1
492  %a = load i64, i64 addrspace(1)* %in
493  %b = load i64, i64 addrspace(1)* %b_ptr
494  %result = ashr i64 %a, %b
495  store i64 %result, i64 addrspace(1)* %out
496  ret void
497}
498
499define amdgpu_kernel void @ashr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {
500; SI-LABEL: ashr_v2i64:
501; SI:       ; %bb.0:
502; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
503; SI-NEXT:    s_mov_b32 s3, 0xf000
504; SI-NEXT:    s_mov_b32 s2, -1
505; SI-NEXT:    s_mov_b32 s10, s2
506; SI-NEXT:    s_mov_b32 s11, s3
507; SI-NEXT:    s_waitcnt lgkmcnt(0)
508; SI-NEXT:    s_mov_b32 s8, s6
509; SI-NEXT:    s_mov_b32 s9, s7
510; SI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
511; SI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
512; SI-NEXT:    s_mov_b32 s0, s4
513; SI-NEXT:    s_mov_b32 s1, s5
514; SI-NEXT:    s_waitcnt vmcnt(0)
515; SI-NEXT:    v_ashr_i64 v[2:3], v[2:3], v6
516; SI-NEXT:    v_ashr_i64 v[0:1], v[0:1], v4
517; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
518; SI-NEXT:    s_endpgm
519;
520; VI-LABEL: ashr_v2i64:
521; VI:       ; %bb.0:
522; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
523; VI-NEXT:    s_mov_b32 s3, 0xf000
524; VI-NEXT:    s_mov_b32 s2, -1
525; VI-NEXT:    s_mov_b32 s10, s2
526; VI-NEXT:    s_mov_b32 s11, s3
527; VI-NEXT:    s_waitcnt lgkmcnt(0)
528; VI-NEXT:    s_mov_b32 s8, s6
529; VI-NEXT:    s_mov_b32 s9, s7
530; VI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
531; VI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
532; VI-NEXT:    s_mov_b32 s0, s4
533; VI-NEXT:    s_mov_b32 s1, s5
534; VI-NEXT:    s_waitcnt vmcnt(0)
535; VI-NEXT:    v_ashrrev_i64 v[2:3], v6, v[2:3]
536; VI-NEXT:    v_ashrrev_i64 v[0:1], v4, v[0:1]
537; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
538; VI-NEXT:    s_endpgm
539;
540; EG-LABEL: ashr_v2i64:
541; EG:       ; %bb.0:
542; EG-NEXT:    ALU 0, @10, KC0[CB0:0-32], KC1[]
543; EG-NEXT:    TEX 1 @6
544; EG-NEXT:    ALU 19, @11, KC0[CB0:0-32], KC1[]
545; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
546; EG-NEXT:    CF_END
547; EG-NEXT:    PAD
548; EG-NEXT:    Fetch clause starting at 6:
549; EG-NEXT:     VTX_READ_128 T1.XYZW, T0.X, 16, #1
550; EG-NEXT:     VTX_READ_128 T0.XYZW, T0.X, 0, #1
551; EG-NEXT:    ALU clause starting at 10:
552; EG-NEXT:     MOV * T0.X, KC0[2].Z,
553; EG-NEXT:    ALU clause starting at 11:
554; EG-NEXT:     AND_INT * T1.W, T1.Z, literal.x,
555; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
556; EG-NEXT:     ASHR T1.Y, T0.W, PV.W,
557; EG-NEXT:     AND_INT T2.Z, T1.Z, literal.x,
558; EG-NEXT:     BIT_ALIGN_INT T1.W, T0.W, T0.Z, T1.Z,
559; EG-NEXT:     AND_INT * T2.W, T1.X, literal.y,
560; EG-NEXT:    32(4.484155e-44), 31(4.344025e-44)
561; EG-NEXT:     ASHR T2.Y, T0.Y, PS,
562; EG-NEXT:     CNDE_INT T0.Z, PV.Z, PV.W, PV.Y,
563; EG-NEXT:     BIT_ALIGN_INT T1.W, T0.Y, T0.X, T1.X,
564; EG-NEXT:     AND_INT * T2.W, T1.X, literal.x,
565; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
566; EG-NEXT:     CNDE_INT T0.X, PS, PV.W, PV.Y,
567; EG-NEXT:     ASHR T0.W, T0.W, literal.x,
568; EG-NEXT:     ASHR * T1.W, T0.Y, literal.x,
569; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
570; EG-NEXT:     CNDE_INT * T0.W, T2.Z, T1.Y, PV.W,
571; EG-NEXT:     LSHR T1.X, KC0[2].Y, literal.x,
572; EG-NEXT:     CNDE_INT * T0.Y, T2.W, T2.Y, T1.W,
573; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
574  %b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %in, i64 1
575  %a = load <2 x i64>, <2 x i64> addrspace(1)* %in
576  %b = load <2 x i64>, <2 x i64> addrspace(1)* %b_ptr
577  %result = ashr <2 x i64> %a, %b
578  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
579  ret void
580}
581
582; FIXME: Broken on r600
583define amdgpu_kernel void @ashr_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
584; SI-LABEL: ashr_v4i64:
585; SI:       ; %bb.0:
586; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
587; SI-NEXT:    s_mov_b32 s3, 0xf000
588; SI-NEXT:    s_mov_b32 s2, -1
589; SI-NEXT:    s_mov_b32 s10, s2
590; SI-NEXT:    s_mov_b32 s11, s3
591; SI-NEXT:    s_waitcnt lgkmcnt(0)
592; SI-NEXT:    s_mov_b32 s8, s6
593; SI-NEXT:    s_mov_b32 s9, s7
594; SI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
595; SI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
596; SI-NEXT:    buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:32
597; SI-NEXT:    buffer_load_dwordx4 v[11:14], off, s[8:11], 0 offset:48
598; SI-NEXT:    s_mov_b32 s0, s4
599; SI-NEXT:    s_mov_b32 s1, s5
600; SI-NEXT:    s_waitcnt vmcnt(1)
601; SI-NEXT:    v_ashr_i64 v[2:3], v[2:3], v10
602; SI-NEXT:    s_waitcnt vmcnt(0)
603; SI-NEXT:    v_ashr_i64 v[6:7], v[6:7], v13
604; SI-NEXT:    v_ashr_i64 v[4:5], v[4:5], v11
605; SI-NEXT:    v_ashr_i64 v[0:1], v[0:1], v8
606; SI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
607; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
608; SI-NEXT:    s_endpgm
609;
610; VI-LABEL: ashr_v4i64:
611; VI:       ; %bb.0:
612; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
613; VI-NEXT:    s_mov_b32 s3, 0xf000
614; VI-NEXT:    s_mov_b32 s2, -1
615; VI-NEXT:    s_mov_b32 s10, s2
616; VI-NEXT:    s_mov_b32 s11, s3
617; VI-NEXT:    s_waitcnt lgkmcnt(0)
618; VI-NEXT:    s_mov_b32 s8, s6
619; VI-NEXT:    s_mov_b32 s9, s7
620; VI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
621; VI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
622; VI-NEXT:    buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:32
623; VI-NEXT:    buffer_load_dwordx4 v[11:14], off, s[8:11], 0 offset:48
624; VI-NEXT:    s_mov_b32 s0, s4
625; VI-NEXT:    s_mov_b32 s1, s5
626; VI-NEXT:    s_waitcnt vmcnt(1)
627; VI-NEXT:    v_ashrrev_i64 v[2:3], v10, v[2:3]
628; VI-NEXT:    s_waitcnt vmcnt(0)
629; VI-NEXT:    v_ashrrev_i64 v[6:7], v13, v[6:7]
630; VI-NEXT:    v_ashrrev_i64 v[4:5], v11, v[4:5]
631; VI-NEXT:    v_ashrrev_i64 v[0:1], v8, v[0:1]
632; VI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
633; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
634; VI-NEXT:    s_endpgm
635;
636; EG-LABEL: ashr_v4i64:
637; EG:       ; %bb.0:
638; EG-NEXT:    ALU 0, @14, KC0[CB0:0-32], KC1[]
639; EG-NEXT:    TEX 3 @6
640; EG-NEXT:    ALU 39, @15, KC0[CB0:0-32], KC1[]
641; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T3.X, 0
642; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
643; EG-NEXT:    CF_END
644; EG-NEXT:    Fetch clause starting at 6:
645; EG-NEXT:     VTX_READ_128 T1.XYZW, T0.X, 32, #1
646; EG-NEXT:     VTX_READ_128 T2.XYZW, T0.X, 48, #1
647; EG-NEXT:     VTX_READ_128 T3.XYZW, T0.X, 0, #1
648; EG-NEXT:     VTX_READ_128 T0.XYZW, T0.X, 16, #1
649; EG-NEXT:    ALU clause starting at 14:
650; EG-NEXT:     MOV * T0.X, KC0[2].Z,
651; EG-NEXT:    ALU clause starting at 15:
652; EG-NEXT:     AND_INT * T1.W, T1.Z, literal.x,
653; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
654; EG-NEXT:     ASHR T1.Y, T0.W, literal.x,
655; EG-NEXT:     ASHR T4.Z, T3.W, PV.W, BS:VEC_120/SCL_212
656; EG-NEXT:     AND_INT T1.W, T1.Z, literal.y,
657; EG-NEXT:     AND_INT * T2.W, T2.Z, literal.x,
658; EG-NEXT:    31(4.344025e-44), 32(4.484155e-44)
659; EG-NEXT:     BIT_ALIGN_INT T4.X, T3.W, T3.Z, T1.Z,
660; EG-NEXT:     ASHR T2.Y, T0.W, PS, BS:VEC_120/SCL_212
661; EG-NEXT:     AND_INT * T1.Z, T2.Z, literal.x,
662; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
663; EG-NEXT:     BIT_ALIGN_INT T0.W, T0.W, T0.Z, T2.Z,
664; EG-NEXT:     AND_INT * T2.W, T2.X, literal.x,
665; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
666; EG-NEXT:     AND_INT T5.X, T1.X, literal.x,
667; EG-NEXT:     ASHR T4.Y, T0.Y, PS,
668; EG-NEXT:     CNDE_INT T0.Z, T1.Z, PV.W, T2.Y,
669; EG-NEXT:     BIT_ALIGN_INT T0.W, T0.Y, T0.X, T2.X,
670; EG-NEXT:     AND_INT * T2.W, T2.X, literal.y,
671; EG-NEXT:    31(4.344025e-44), 32(4.484155e-44)
672; EG-NEXT:     CNDE_INT T0.X, PS, PV.W, PV.Y,
673; EG-NEXT:     ASHR T5.Y, T3.Y, PV.X,
674; EG-NEXT:     CNDE_INT T2.Z, T1.W, T4.X, T4.Z,
675; EG-NEXT:     BIT_ALIGN_INT T0.W, T3.Y, T3.X, T1.X, BS:VEC_102/SCL_221
676; EG-NEXT:     AND_INT * T4.W, T1.X, literal.x,
677; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
678; EG-NEXT:     CNDE_INT T2.X, PS, PV.W, PV.Y,
679; EG-NEXT:     ASHR T6.Y, T3.W, literal.x,
680; EG-NEXT:     ASHR T3.Z, T0.Y, literal.x, BS:VEC_201
681; EG-NEXT:     ADD_INT T3.W, KC0[2].Y, literal.y,
682; EG-NEXT:     CNDE_INT * T0.W, T1.Z, T2.Y, T1.Y,
683; EG-NEXT:    31(4.344025e-44), 16(2.242078e-44)
684; EG-NEXT:     LSHR T1.X, PV.W, literal.x,
685; EG-NEXT:     CNDE_INT T0.Y, T2.W, T4.Y, PV.Z,
686; EG-NEXT:     ASHR T3.W, T3.Y, literal.y,
687; EG-NEXT:     CNDE_INT * T2.W, T1.W, T4.Z, PV.Y,
688; EG-NEXT:    2(2.802597e-45), 31(4.344025e-44)
689; EG-NEXT:     LSHR T3.X, KC0[2].Y, literal.x,
690; EG-NEXT:     CNDE_INT * T2.Y, T4.W, T5.Y, PV.W,
691; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
692  %b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i64 1
693  %a = load <4 x i64>, <4 x i64> addrspace(1)* %in
694  %b = load <4 x i64>, <4 x i64> addrspace(1)* %b_ptr
695  %result = ashr <4 x i64> %a, %b
696  store <4 x i64> %result, <4 x i64> addrspace(1)* %out
697  ret void
698}
699
700define amdgpu_kernel void @s_ashr_32_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a, [8 x i32], i64 %b) {
701; SI-LABEL: s_ashr_32_i64:
702; SI:       ; %bb.0:
703; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
704; SI-NEXT:    s_load_dword s2, s[0:1], 0x14
705; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x1d
706; SI-NEXT:    s_mov_b32 s7, 0xf000
707; SI-NEXT:    s_mov_b32 s6, -1
708; SI-NEXT:    s_waitcnt lgkmcnt(0)
709; SI-NEXT:    s_ashr_i32 s3, s2, 31
710; SI-NEXT:    s_add_u32 s0, s2, s0
711; SI-NEXT:    s_addc_u32 s1, s3, s1
712; SI-NEXT:    v_mov_b32_e32 v0, s0
713; SI-NEXT:    v_mov_b32_e32 v1, s1
714; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
715; SI-NEXT:    s_endpgm
716;
717; VI-LABEL: s_ashr_32_i64:
718; VI:       ; %bb.0:
719; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
720; VI-NEXT:    s_load_dword s2, s[0:1], 0x50
721; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x74
722; VI-NEXT:    s_mov_b32 s7, 0xf000
723; VI-NEXT:    s_mov_b32 s6, -1
724; VI-NEXT:    s_waitcnt lgkmcnt(0)
725; VI-NEXT:    s_ashr_i32 s3, s2, 31
726; VI-NEXT:    s_add_u32 s0, s2, s0
727; VI-NEXT:    s_addc_u32 s1, s3, s1
728; VI-NEXT:    v_mov_b32_e32 v0, s0
729; VI-NEXT:    v_mov_b32_e32 v1, s1
730; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
731; VI-NEXT:    s_endpgm
732;
733; EG-LABEL: s_ashr_32_i64:
734; EG:       ; %bb.0:
735; EG-NEXT:    ALU 7, @4, KC0[CB0:0-32], KC1[]
736; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
737; EG-NEXT:    CF_END
738; EG-NEXT:    PAD
739; EG-NEXT:    ALU clause starting at 4:
740; EG-NEXT:     ASHR * T0.W, KC0[5].X, literal.x,
741; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
742; EG-NEXT:     ADD_INT * T0.W, PV.W, KC0[7].Z,
743; EG-NEXT:     ADDC_UINT * T1.W, KC0[5].X, KC0[7].Y,
744; EG-NEXT:     ADD_INT * T0.Y, T0.W, PV.W,
745; EG-NEXT:     ADD_INT * T0.X, KC0[5].X, KC0[7].Y,
746; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
747; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
748  %result = ashr i64 %a, 32
749  %add = add i64 %result, %b
750  store i64 %add, i64 addrspace(1)* %out
751  ret void
752}
753
754define amdgpu_kernel void @v_ashr_32_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
755; SI-LABEL: v_ashr_32_i64:
756; SI:       ; %bb.0:
757; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
758; SI-NEXT:    s_mov_b32 s7, 0xf000
759; SI-NEXT:    s_mov_b32 s6, 0
760; SI-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
761; SI-NEXT:    v_mov_b32_e32 v1, 0
762; SI-NEXT:    s_waitcnt lgkmcnt(0)
763; SI-NEXT:    s_mov_b64 s[4:5], s[0:1]
764; SI-NEXT:    s_mov_b64 s[0:1], s[2:3]
765; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]
766; SI-NEXT:    buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 offset:4
767; SI-NEXT:    s_waitcnt vmcnt(0)
768; SI-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
769; SI-NEXT:    buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
770; SI-NEXT:    s_endpgm
771;
772; VI-LABEL: v_ashr_32_i64:
773; VI:       ; %bb.0:
774; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
775; VI-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
776; VI-NEXT:    s_waitcnt lgkmcnt(0)
777; VI-NEXT:    v_mov_b32_e32 v1, s3
778; VI-NEXT:    v_add_u32_e32 v2, vcc, s2, v0
779; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
780; VI-NEXT:    v_mov_b32_e32 v1, s1
781; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
782; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
783; VI-NEXT:    v_add_u32_e32 v2, vcc, 4, v2
784; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
785; VI-NEXT:    flat_load_dword v2, v[2:3]
786; VI-NEXT:    s_waitcnt vmcnt(0)
787; VI-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
788; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
789; VI-NEXT:    s_endpgm
790;
791; EG-LABEL: v_ashr_32_i64:
792; EG:       ; %bb.0:
793; EG-NEXT:    ALU 2, @8, KC0[CB0:0-32], KC1[]
794; EG-NEXT:    TEX 0 @6
795; EG-NEXT:    ALU 3, @11, KC0[CB0:0-32], KC1[]
796; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
797; EG-NEXT:    CF_END
798; EG-NEXT:    PAD
799; EG-NEXT:    Fetch clause starting at 6:
800; EG-NEXT:     VTX_READ_32 T0.X, T0.X, 4, #1
801; EG-NEXT:    ALU clause starting at 8:
802; EG-NEXT:     LSHL * T0.W, T0.X, literal.x,
803; EG-NEXT:    3(4.203895e-45), 0(0.000000e+00)
804; EG-NEXT:     ADD_INT * T0.X, KC0[2].Z, PV.W,
805; EG-NEXT:    ALU clause starting at 11:
806; EG-NEXT:     ADD_INT * T0.W, KC0[2].Y, T0.W,
807; EG-NEXT:     LSHR T1.X, PV.W, literal.x,
808; EG-NEXT:     ASHR * T0.Y, T0.X, literal.y,
809; EG-NEXT:    2(2.802597e-45), 31(4.344025e-44)
810  %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
811  %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
812  %gep.out = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
813  %a = load i64, i64 addrspace(1)* %gep.in
814  %result = ashr i64 %a, 32
815  store i64 %result, i64 addrspace(1)* %gep.out
816  ret void
817}
818
819define amdgpu_kernel void @s_ashr_63_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a, [8 x i32], i64 %b) {
820; SI-LABEL: s_ashr_63_i64:
821; SI:       ; %bb.0:
822; SI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
823; SI-NEXT:    s_load_dword s2, s[0:1], 0x14
824; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x1d
825; SI-NEXT:    s_mov_b32 s7, 0xf000
826; SI-NEXT:    s_mov_b32 s6, -1
827; SI-NEXT:    s_waitcnt lgkmcnt(0)
828; SI-NEXT:    s_ashr_i32 s2, s2, 31
829; SI-NEXT:    s_add_u32 s0, s2, s0
830; SI-NEXT:    s_addc_u32 s1, s2, s1
831; SI-NEXT:    v_mov_b32_e32 v0, s0
832; SI-NEXT:    v_mov_b32_e32 v1, s1
833; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
834; SI-NEXT:    s_endpgm
835;
836; VI-LABEL: s_ashr_63_i64:
837; VI:       ; %bb.0:
838; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
839; VI-NEXT:    s_load_dword s2, s[0:1], 0x50
840; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x74
841; VI-NEXT:    s_mov_b32 s7, 0xf000
842; VI-NEXT:    s_mov_b32 s6, -1
843; VI-NEXT:    s_waitcnt lgkmcnt(0)
844; VI-NEXT:    s_ashr_i32 s2, s2, 31
845; VI-NEXT:    s_add_u32 s0, s2, s0
846; VI-NEXT:    s_addc_u32 s1, s2, s1
847; VI-NEXT:    v_mov_b32_e32 v0, s0
848; VI-NEXT:    v_mov_b32_e32 v1, s1
849; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
850; VI-NEXT:    s_endpgm
851;
852; EG-LABEL: s_ashr_63_i64:
853; EG:       ; %bb.0:
854; EG-NEXT:    ALU 7, @4, KC0[CB0:0-32], KC1[]
855; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
856; EG-NEXT:    CF_END
857; EG-NEXT:    PAD
858; EG-NEXT:    ALU clause starting at 4:
859; EG-NEXT:     ASHR * T0.W, KC0[5].X, literal.x,
860; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
861; EG-NEXT:     ADD_INT T1.W, PV.W, KC0[7].Z,
862; EG-NEXT:     ADDC_UINT * T2.W, PV.W, KC0[7].Y,
863; EG-NEXT:     ADD_INT * T0.Y, PV.W, PS,
864; EG-NEXT:     ADD_INT T0.X, T0.W, KC0[7].Y,
865; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
866; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
867  %result = ashr i64 %a, 63
868  %add = add i64 %result, %b
869  store i64 %add, i64 addrspace(1)* %out
870  ret void
871}
872
873define amdgpu_kernel void @v_ashr_63_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
874; SI-LABEL: v_ashr_63_i64:
875; SI:       ; %bb.0:
876; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
877; SI-NEXT:    s_mov_b32 s7, 0xf000
878; SI-NEXT:    s_mov_b32 s6, 0
879; SI-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
880; SI-NEXT:    v_mov_b32_e32 v1, 0
881; SI-NEXT:    s_waitcnt lgkmcnt(0)
882; SI-NEXT:    s_mov_b64 s[4:5], s[0:1]
883; SI-NEXT:    s_mov_b64 s[0:1], s[2:3]
884; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]
885; SI-NEXT:    buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 offset:4
886; SI-NEXT:    s_waitcnt vmcnt(0)
887; SI-NEXT:    v_ashrrev_i32_e32 v2, 31, v2
888; SI-NEXT:    v_mov_b32_e32 v3, v2
889; SI-NEXT:    buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
890; SI-NEXT:    s_endpgm
891;
892; VI-LABEL: v_ashr_63_i64:
893; VI:       ; %bb.0:
894; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
895; VI-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
896; VI-NEXT:    s_waitcnt lgkmcnt(0)
897; VI-NEXT:    v_mov_b32_e32 v1, s3
898; VI-NEXT:    v_add_u32_e32 v2, vcc, s2, v0
899; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v1, vcc
900; VI-NEXT:    v_mov_b32_e32 v1, s1
901; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
902; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
903; VI-NEXT:    v_add_u32_e32 v2, vcc, 4, v2
904; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
905; VI-NEXT:    flat_load_dword v2, v[2:3]
906; VI-NEXT:    s_waitcnt vmcnt(0)
907; VI-NEXT:    v_ashrrev_i32_e32 v2, 31, v2
908; VI-NEXT:    v_mov_b32_e32 v3, v2
909; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
910; VI-NEXT:    s_endpgm
911;
912; EG-LABEL: v_ashr_63_i64:
913; EG:       ; %bb.0:
914; EG-NEXT:    ALU 2, @8, KC0[CB0:0-32], KC1[]
915; EG-NEXT:    TEX 0 @6
916; EG-NEXT:    ALU 5, @11, KC0[CB0:0-32], KC1[]
917; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
918; EG-NEXT:    CF_END
919; EG-NEXT:    PAD
920; EG-NEXT:    Fetch clause starting at 6:
921; EG-NEXT:     VTX_READ_32 T0.X, T0.X, 4, #1
922; EG-NEXT:    ALU clause starting at 8:
923; EG-NEXT:     LSHL * T0.W, T0.X, literal.x,
924; EG-NEXT:    3(4.203895e-45), 0(0.000000e+00)
925; EG-NEXT:     ADD_INT * T0.X, KC0[2].Z, PV.W,
926; EG-NEXT:    ALU clause starting at 11:
927; EG-NEXT:     ASHR T0.X, T0.X, literal.x,
928; EG-NEXT:     ADD_INT * T0.W, KC0[2].Y, T0.W,
929; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
930; EG-NEXT:     LSHR T1.X, PV.W, literal.x,
931; EG-NEXT:     MOV * T0.Y, PV.X,
932; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
933  %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
934  %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
935  %gep.out = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
936  %a = load i64, i64 addrspace(1)* %gep.in
937  %result = ashr i64 %a, 63
938  store i64 %result, i64 addrspace(1)* %gep.out
939  ret void
940}
941
942attributes #0 = { nounwind readnone }
943