1; RUN: llc -O0 -march=amdgcn -mcpu=fiji -amdgpu-spill-sgpr-to-smem=0 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=VGPR %s
2; RUN: llc -O0 -march=amdgcn -mcpu=fiji -amdgpu-spill-sgpr-to-smem=1 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=SMEM %s
3; RUN: llc -O0 -march=amdgcn -mcpu=fiji -amdgpu-spill-sgpr-to-smem=0 -amdgpu-spill-sgpr-to-vgpr=0 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=VMEM %s
4
5; ALL-LABEL: {{^}}spill_sgpr_x2:
6; SMEM: s_add_u32 m0, s3, 0x100{{$}}
7; SMEM: s_buffer_store_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[8:11], m0 ; 8-byte Folded Spill
8; SMEM: s_cbranch_scc1
9
10; SMEM: s_add_u32 m0, s3, 0x100{{$}}
11; SMEM: s_buffer_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[8:11], m0 ; 8-byte Folded Reload
12
13; SMEM: s_dcache_wb
14; SMEM: s_endpgm
15
16; FIXME: Should only need 4 bytes
17; SMEM: ScratchSize: 12
18
19
20; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
21; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
22; VGPR: s_cbranch_scc1
23
24; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
25; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
26
27; VMEM: buffer_store_dword
28; VMEM: buffer_store_dword
29; VMEM: s_cbranch_scc1
30
31; VMEM: buffer_load_dword
32; VMEM: buffer_load_dword
33define amdgpu_kernel void @spill_sgpr_x2(i32 addrspace(1)* %out, i32 %in) #0 {
34  %wide.sgpr = call <2 x i32>  asm sideeffect "; def $0", "=s" () #0
35  %cmp = icmp eq i32 %in, 0
36  br i1 %cmp, label %bb0, label %ret
37
38bb0:
39  call void asm sideeffect "; use $0", "s"(<2 x i32> %wide.sgpr) #0
40  br label %ret
41
42ret:
43  ret void
44}
45
46; ALL-LABEL: {{^}}spill_sgpr_x3:
47; SMEM: s_add_u32 m0, s3, 0x100{{$}}
48; SMEM: s_buffer_store_dword s
49; SMEM: s_buffer_store_dword s
50; SMEM: s_buffer_store_dword s
51; SMEM: s_cbranch_scc1
52
53; SMEM: s_add_u32 m0, s3, 0x100{{$}}
54; SMEM: s_buffer_load_dword s
55; SMEM: s_buffer_load_dword s
56; SMEM: s_buffer_load_dword s
57; SMEM: s_dcache_wb
58; SMEM: s_endpgm
59
60; FIXME: Should only need 4 bytes
61; SMEM: ScratchSize: 16
62
63; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
64; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
65; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2
66; VGPR: s_cbranch_scc1
67
68; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
69; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
70; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
71
72
73; VMEM: buffer_store_dword
74; VMEM: buffer_store_dword
75; VMEM: buffer_store_dword
76; VMEM: s_cbranch_scc1
77
78; VMEM: buffer_load_dword
79; VMEM: buffer_load_dword
80; VMEM: buffer_load_dword
81define amdgpu_kernel void @spill_sgpr_x3(i32 addrspace(1)* %out, i32 %in) #0 {
82  %wide.sgpr = call <3 x i32>  asm sideeffect "; def $0", "=s" () #0
83  %cmp = icmp eq i32 %in, 0
84  br i1 %cmp, label %bb0, label %ret
85
86bb0:
87  call void asm sideeffect "; use $0", "s"(<3 x i32> %wide.sgpr) #0
88  br label %ret
89
90ret:
91  ret void
92}
93
94; ALL-LABEL: {{^}}spill_sgpr_x4:
95; SMEM: s_add_u32 m0, s3, 0x100{{$}}
96; SMEM: s_buffer_store_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[VALS:[0-9]+:[0-9]+]]{{\]}}, m0 ; 16-byte Folded Spill
97; SMEM: s_cbranch_scc1
98
99; SMEM: s_add_u32 m0, s3, 0x100{{$}}
100; SMEM: s_buffer_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[VALS]]{{\]}}, m0 ; 16-byte Folded Reload
101; SMEM: s_dcache_wb
102; SMEM: s_endpgm
103
104; FIXME: Should only need 4 bytes
105; SMEM: ScratchSize: 20
106
107; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
108; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
109; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2
110; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3
111; VGPR: s_cbranch_scc1
112
113; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
114; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
115; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
116; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
117
118
119; VMEM: buffer_store_dword
120; VMEM: buffer_store_dword
121; VMEM: buffer_store_dword
122; VMEM: buffer_store_dword
123; VMEM: s_cbranch_scc1
124
125; VMEM: buffer_load_dword
126; VMEM: buffer_load_dword
127; VMEM: buffer_load_dword
128; VMEM: buffer_load_dword
129define amdgpu_kernel void @spill_sgpr_x4(i32 addrspace(1)* %out, i32 %in) #0 {
130  %wide.sgpr = call <4 x i32>  asm sideeffect "; def $0", "=s" () #0
131  %cmp = icmp eq i32 %in, 0
132  br i1 %cmp, label %bb0, label %ret
133
134bb0:
135  call void asm sideeffect "; use $0", "s"(<4 x i32> %wide.sgpr) #0
136  br label %ret
137
138ret:
139  ret void
140}
141
142; ALL-LABEL: {{^}}spill_sgpr_x5:
143; SMEM: s_add_u32 m0, s3, 0x100{{$}}
144; SMEM: s_buffer_store_dword s
145; SMEM: s_buffer_store_dword s
146; SMEM: s_buffer_store_dword s
147; SMEM: s_buffer_store_dword s
148; SMEM: s_buffer_store_dword s
149; SMEM: s_cbranch_scc1
150
151; SMEM: s_add_u32 m0, s3, 0x100{{$}}
152; SMEM: s_buffer_load_dword s
153; SMEM: s_buffer_load_dword s
154; SMEM: s_buffer_load_dword s
155; SMEM: s_buffer_load_dword s
156; SMEM: s_buffer_load_dword s
157; SMEM: s_dcache_wb
158; SMEM: s_endpgm
159
160; FIXME: Should only need 4 bytes
161; SMEM: ScratchSize: 24
162
163; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
164; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
165; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2
166; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3
167; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 4
168; VGPR: s_cbranch_scc1
169
170; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
171; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
172; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
173; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
174; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 4
175
176
177; VMEM: buffer_store_dword
178; VMEM: buffer_store_dword
179; VMEM: buffer_store_dword
180; VMEM: buffer_store_dword
181; VMEM: buffer_store_dword
182; VMEM: s_cbranch_scc1
183
184; VMEM: buffer_load_dword
185; VMEM: buffer_load_dword
186; VMEM: buffer_load_dword
187; VMEM: buffer_load_dword
188; VMEM: buffer_load_dword
189define amdgpu_kernel void @spill_sgpr_x5(i32 addrspace(1)* %out, i32 %in) #0 {
190  %wide.sgpr = call <5 x i32>  asm sideeffect "; def $0", "=s" () #0
191  %cmp = icmp eq i32 %in, 0
192  br i1 %cmp, label %bb0, label %ret
193
194bb0:
195  call void asm sideeffect "; use $0", "s"(<5 x i32> %wide.sgpr) #0
196  br label %ret
197
198ret:
199  ret void
200}
201
202; ALL-LABEL: {{^}}spill_sgpr_x8:
203
204; SMEM: s_add_u32 m0, s3, 0x100{{$}}
205; SMEM: s_buffer_store_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[VALS:[0-9]+:[0-9]+]]{{\]}}, m0 ; 16-byte Folded Spill
206; SMEM: s_add_u32 m0, s3, 0x110{{$}}
207; SMEM: s_buffer_store_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[VALS]]{{\]}}, m0 ; 16-byte Folded Spill
208; SMEM: s_cbranch_scc1
209
210; SMEM: s_add_u32 m0, s3, 0x100{{$}}
211; SMEM: s_buffer_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[VALS]]{{\]}}, m0 ; 16-byte Folded Reload
212; SMEM: s_add_u32 m0, s3, 0x110{{$}}
213; SMEM: s_buffer_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[VALS]]{{\]}}, m0 ; 16-byte Folded Reload
214
215; SMEM: s_dcache_wb
216; SMEM: s_endpgm
217
218; SMEM: ScratchSize: 36
219
220; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
221; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
222; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2
223; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3
224; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 4
225; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 5
226; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 6
227; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 7
228; VGPR: s_cbranch_scc1
229
230; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
231; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
232; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
233; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
234; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 4
235; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 5
236; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 6
237; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 7
238
239; VMEM: buffer_store_dword
240; VMEM: buffer_store_dword
241; VMEM: buffer_store_dword
242; VMEM: buffer_store_dword
243; VMEM: buffer_store_dword
244; VMEM: buffer_store_dword
245; VMEM: buffer_store_dword
246; VMEM: buffer_store_dword
247; VMEM: s_cbranch_scc1
248
249; VMEM: buffer_load_dword
250; VMEM: buffer_load_dword
251; VMEM: buffer_load_dword
252; VMEM: buffer_load_dword
253; VMEM: buffer_load_dword
254; VMEM: buffer_load_dword
255; VMEM: buffer_load_dword
256; VMEM: buffer_load_dword
257define amdgpu_kernel void @spill_sgpr_x8(i32 addrspace(1)* %out, i32 %in) #0 {
258  %wide.sgpr = call <8 x i32>  asm sideeffect "; def $0", "=s" () #0
259  %cmp = icmp eq i32 %in, 0
260  br i1 %cmp, label %bb0, label %ret
261
262bb0:
263  call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr) #0
264  br label %ret
265
266ret:
267  ret void
268}
269
270; FIXME: x16 inlineasm seems broken
271; define amdgpu_kernel void @spill_sgpr_x16(i32 addrspace(1)* %out, i32 %in) #0 {
272;   %wide.sgpr = call <16 x i32>  asm sideeffect "; def $0", "=s" () #0
273;   %cmp = icmp eq i32 %in, 0
274;   br i1 %cmp, label %bb0, label %ret
275
276; bb0:
277;   call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr) #0
278;   br label %ret
279
280; ret:
281;   ret void
282; }
283
284attributes #0 = { nounwind }
285