1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
3
4; Spill an SGPR to scratch without having spare SGPRs available to save exec
5
6define amdgpu_kernel void @test() #1 {
7; GFX10-LABEL: test:
8; GFX10:       ; %bb.0:
9; GFX10-NEXT:    s_mov_b32 s8, SCRATCH_RSRC_DWORD0
10; GFX10-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
11; GFX10-NEXT:    s_mov_b32 s10, -1
12; GFX10-NEXT:    s_mov_b32 s11, 0x31e16000
13; GFX10-NEXT:    s_add_u32 s8, s8, s1
14; GFX10-NEXT:    s_addc_u32 s9, s9, 0
15; GFX10-NEXT:    ;;#ASMSTART
16; GFX10-NEXT:    ; def s[0:7]
17; GFX10-NEXT:    ;;#ASMEND
18; GFX10-NEXT:    ;;#ASMSTART
19; GFX10-NEXT:    ; def s[8:12]
20; GFX10-NEXT:    ;;#ASMEND
21; GFX10-NEXT:    s_not_b64 exec, exec
22; GFX10-NEXT:    buffer_store_dword v0, off, s[8:11], 0
23; GFX10-NEXT:    v_writelane_b32 v0, s8, 0
24; GFX10-NEXT:    v_writelane_b32 v0, s9, 1
25; GFX10-NEXT:    v_writelane_b32 v0, s10, 2
26; GFX10-NEXT:    v_writelane_b32 v0, s11, 3
27; GFX10-NEXT:    v_writelane_b32 v0, s12, 4
28; GFX10-NEXT:    buffer_store_dword v0, off, s[8:11], 0 offset:4 ; 4-byte Folded Spill
29; GFX10-NEXT:    s_waitcnt_depctr 0xffe3
30; GFX10-NEXT:    s_not_b64 exec, exec
31; GFX10-NEXT:    buffer_store_dword v0, off, s[8:11], 0 offset:4 ; 4-byte Folded Spill
32; GFX10-NEXT:    s_waitcnt_depctr 0xffe3
33; GFX10-NEXT:    s_not_b64 exec, exec
34; GFX10-NEXT:    buffer_load_dword v0, off, s[8:11], 0
35; GFX10-NEXT:    s_waitcnt vmcnt(0)
36; GFX10-NEXT:    s_waitcnt_depctr 0xffe3
37; GFX10-NEXT:    s_not_b64 exec, exec
38; GFX10-NEXT:    ;;#ASMSTART
39; GFX10-NEXT:    ;;#ASMEND
40; GFX10-NEXT:    ;;#ASMSTART
41; GFX10-NEXT:    ; use s[0:7]
42; GFX10-NEXT:    ;;#ASMEND
43; GFX10-NEXT:    s_mov_b64 s[6:7], exec
44; GFX10-NEXT:    s_mov_b64 exec, 31
45; GFX10-NEXT:    buffer_store_dword v0, off, s[8:11], 0
46; GFX10-NEXT:    buffer_load_dword v0, off, s[8:11], 0 offset:4 ; 4-byte Folded Reload
47; GFX10-NEXT:    s_waitcnt vmcnt(0)
48; GFX10-NEXT:    v_readlane_b32 s0, v0, 0
49; GFX10-NEXT:    v_readlane_b32 s1, v0, 1
50; GFX10-NEXT:    v_readlane_b32 s2, v0, 2
51; GFX10-NEXT:    v_readlane_b32 s3, v0, 3
52; GFX10-NEXT:    v_readlane_b32 s4, v0, 4
53; GFX10-NEXT:    buffer_load_dword v0, off, s[8:11], 0
54; GFX10-NEXT:    s_waitcnt vmcnt(0)
55; GFX10-NEXT:    s_waitcnt_depctr 0xffe3
56; GFX10-NEXT:    s_mov_b64 exec, s[6:7]
57; GFX10-NEXT:    ;;#ASMSTART
58; GFX10-NEXT:    ; use s[0:4]
59; GFX10-NEXT:    ;;#ASMEND
60; GFX10-NEXT:    s_endpgm
61  %wide.sgpr0 = call <8 x i32> asm sideeffect "; def $0", "={s[0:7]}" () #0
62  %wide.sgpr2 = call <5 x i32> asm sideeffect "; def $0", "={s[8:12]}" () #0
63  call void asm sideeffect "", "~{v[0:7]}" () #0
64  call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr0) #0
65  call void asm sideeffect "; use $0", "s"(<5 x i32> %wide.sgpr2) #0
66  ret void
67}
68
69attributes #0 = { nounwind }
70attributes #1 = { nounwind "amdgpu-num-sgpr"="16" "amdgpu-num-vgpr"="8" }
71