1# REQUIRES: asserts
2# RUN: llc -mtriple=amdgcn--- -verify-machineinstrs -debug-only=regalloc -run-pass=greedy -o /dev/null %s 2>&1 | FileCheck %s
3
4---
5# Check that physreg candidate is not used since cannot be spilled in a block,
6# e.g. before exec mask preamble
7# CHECK: , cannot spill all interferences.
8
9name:            foo
10tracksRegLiveness: true
11registers:
12  - { id: 0, class: sreg_64 }
13  - { id: 1100, class: sreg_128 }
14  - { id: 1101, class: sreg_128 }
15  - { id: 1102, class: sreg_128 }
16  - { id: 1103, class: sreg_128 }
17  - { id: 1104, class: sreg_128 }
18  - { id: 1105, class: sreg_128 }
19  - { id: 1106, class: sreg_128 }
20  - { id: 1107, class: sreg_128 }
21  - { id: 1108, class: sreg_128 }
22  - { id: 1109, class: sreg_128 }
23  - { id: 1110, class: sreg_128 }
24  - { id: 1111, class: sreg_128 }
25  - { id: 1112, class: sreg_128 }
26  - { id: 1113, class: sreg_128 }
27  - { id: 1114, class: sreg_128 }
28  - { id: 1115, class: sreg_128 }
29  - { id: 1116, class: sreg_128 }
30  - { id: 1117, class: sreg_128 }
31  - { id: 1118, class: sreg_128 }
32  - { id: 1119, class: sreg_128 }
33  - { id: 1120, class: sreg_128 }
34  - { id: 1121, class: sreg_128 }
35body:             |
36  bb.0:
37    successors: %bb.1
38    liveins: $sgpr96_sgpr97, $sgpr98_sgpr99, $sgpr100_sgpr101, $sgpr102_sgpr103
39    %0:sreg_64 = COPY $sgpr102_sgpr103
40    %1100 = COPY $sgpr100_sgpr101_sgpr102_sgpr103
41    %1101 = COPY %1100
42    %1102 = COPY %1100
43    %1103 = COPY %1100
44    %1104 = COPY %1100
45    %1105 = COPY %1100
46    %1106 = COPY %1100
47    %1107 = COPY %1100
48    %1108 = COPY %1100
49    %1109 = COPY %1100
50    %1110 = COPY %1100
51    %1111 = COPY %1100
52    %1112 = COPY %1100
53    %1113 = COPY %1100
54    %1114 = COPY %1100
55    %1115 = COPY %1100
56    %1116 = COPY %1100
57    %1117 = COPY %1100
58    %1118 = COPY %1100
59    %1119 = COPY %1100
60    %1120 = COPY %1100
61    %1121 = COPY %1100
62    S_BRANCH %bb.1
63
64  bb.1:
65    liveins: $sgpr96_sgpr97, $sgpr98_sgpr99, $sgpr102_sgpr103
66    %0 = S_OR_SAVEEXEC_B64 $sgpr96_sgpr97, implicit-def $exec, implicit-def $scc, implicit $exec
67    $exec = S_XOR_B64_term $exec, %0, implicit-def $scc
68    SI_MASK_BRANCH %bb.100, implicit $exec
69    S_BRANCH %bb.2
70
71  bb.2:
72    liveins: $sgpr98_sgpr99, $sgpr102_sgpr103
73    %0:sreg_64 = S_OR_SAVEEXEC_B64 $sgpr98_sgpr99, implicit-def $exec, implicit-def $scc, implicit $exec
74    $exec = S_XOR_B64_term $exec, %0, implicit-def $scc
75    SI_MASK_BRANCH %bb.100, implicit $exec
76    S_BRANCH %bb.200
77
78  bb.100:
79    liveins: $sgpr102_sgpr103
80    %0:sreg_64 = S_OR_SAVEEXEC_B64 $sgpr102_sgpr103, implicit-def $exec, implicit-def $scc, implicit $exec
81    $exec = S_XOR_B64_term $exec, %0, implicit-def $scc
82    S_BRANCH %bb.200
83
84  bb.200:
85    S_CMP_EQ_U64 %1100.sub0_sub1, %1101.sub2_sub3, implicit-def $scc
86    S_CMP_EQ_U64 %1102.sub0_sub1, %1103.sub2_sub3, implicit-def $scc
87    S_CMP_EQ_U64 %1104.sub0_sub1, %1105.sub2_sub3, implicit-def $scc
88    S_CMP_EQ_U64 %1106.sub0_sub1, %1107.sub2_sub3, implicit-def $scc
89    S_CMP_EQ_U64 %1108.sub0_sub1, %1109.sub2_sub3, implicit-def $scc
90    S_CMP_EQ_U64 %1110.sub0_sub1, %1111.sub2_sub3, implicit-def $scc
91    S_CMP_EQ_U64 %1112.sub0_sub1, %1113.sub2_sub3, implicit-def $scc
92    S_CMP_EQ_U64 %1114.sub0_sub1, %1115.sub2_sub3, implicit-def $scc
93    S_CMP_EQ_U64 %1116.sub0_sub1, %1117.sub2_sub3, implicit-def $scc
94    S_CMP_EQ_U64 %1118.sub0_sub1, %1119.sub2_sub3, implicit-def $scc
95    S_CMP_EQ_U64 %1120.sub0_sub1, %1121.sub2_sub3, implicit-def $scc
96
97    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
98    S_SETPC_B64_return %0, implicit $vgpr0
99
100...
101