1; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=SICIVI -check-prefix=SICI -check-prefix=SIVIGFX9 %s 2; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=SICIVI -check-prefix=SICI %s 3; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=SICIVI -check-prefix=VIGFX9 -check-prefix=SIVIGFX9 %s 4; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN -check-prefix=VIGFX9 -check-prefix=SIVIGFX9 %s 5 6; SMRD load with an immediate offset. 7; GCN-LABEL: {{^}}smrd0: 8; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x01 9; VIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 10define amdgpu_kernel void @smrd0(i32 addrspace(1)* %out, i32 addrspace(4)* %ptr) #0 { 11entry: 12 %tmp = getelementptr i32, i32 addrspace(4)* %ptr, i64 1 13 %tmp1 = load i32, i32 addrspace(4)* %tmp 14 store i32 %tmp1, i32 addrspace(1)* %out 15 ret void 16} 17 18; SMRD load with the largest possible immediate offset. 19; GCN-LABEL: {{^}}smrd1: 20; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff,0x{{[0-9]+[137]}} 21; VIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc 22define amdgpu_kernel void @smrd1(i32 addrspace(1)* %out, i32 addrspace(4)* %ptr) #0 { 23entry: 24 %tmp = getelementptr i32, i32 addrspace(4)* %ptr, i64 255 25 %tmp1 = load i32, i32 addrspace(4)* %tmp 26 store i32 %tmp1, i32 addrspace(1)* %out 27 ret void 28} 29 30; SMRD load with an offset greater than the largest possible immediate. 31; GCN-LABEL: {{^}}smrd2: 32; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400 33; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]] 34; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100 35; VIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400 36; GCN: s_endpgm 37define amdgpu_kernel void @smrd2(i32 addrspace(1)* %out, i32 addrspace(4)* %ptr) #0 { 38entry: 39 %tmp = getelementptr i32, i32 addrspace(4)* %ptr, i64 256 40 %tmp1 = load i32, i32 addrspace(4)* %tmp 41 store i32 %tmp1, i32 addrspace(1)* %out 42 ret void 43} 44 45; SMRD load with a 64-bit offset 46; GCN-LABEL: {{^}}smrd3: 47; FIXME: There are too many copies here because we don't fold immediates 48; through REG_SEQUENCE 49; SI: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0x13 ; encoding: [0x13 50; TODO: Add VI checks 51; GCN: s_endpgm 52define amdgpu_kernel void @smrd3(i32 addrspace(1)* %out, [8 x i32], i32 addrspace(4)* %ptr) #0 { 53entry: 54 %tmp = getelementptr i32, i32 addrspace(4)* %ptr, i64 4294967296 55 %tmp1 = load i32, i32 addrspace(4)* %tmp 56 store i32 %tmp1, i32 addrspace(1)* %out 57 ret void 58} 59 60; SMRD load with the largest possible immediate offset on VI 61; GCN-LABEL: {{^}}smrd4: 62; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc 63; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]] 64; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff 65; VIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc 66define amdgpu_kernel void @smrd4(i32 addrspace(1)* %out, i32 addrspace(4)* %ptr) #0 { 67entry: 68 %tmp = getelementptr i32, i32 addrspace(4)* %ptr, i64 262143 69 %tmp1 = load i32, i32 addrspace(4)* %tmp 70 store i32 %tmp1, i32 addrspace(1)* %out 71 ret void 72} 73 74; SMRD load with an offset greater than the largest possible immediate on VI 75; GCN-LABEL: {{^}}smrd5: 76; SIVIGFX9: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000 77; SIVIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]] 78; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000 79; GCN: s_endpgm 80define amdgpu_kernel void @smrd5(i32 addrspace(1)* %out, i32 addrspace(4)* %ptr) #0 { 81entry: 82 %tmp = getelementptr i32, i32 addrspace(4)* %ptr, i64 262144 83 %tmp1 = load i32, i32 addrspace(4)* %tmp 84 store i32 %tmp1, i32 addrspace(1)* %out 85 ret void 86} 87 88; GCN-LABEL: {{^}}smrd_hazard: 89; GCN-DAG: s_mov_b32 s3, 3 90; GCN-DAG: s_mov_b32 s2, 2 91; GCN-DAG: s_mov_b32 s1, 1 92; GCN-DAG: s_mov_b32 s0, 0 93; SI-NEXT: nop 3 94; GCN-NEXT: s_buffer_load_dword s0, s[0:3], 0x0 95define amdgpu_ps float @smrd_hazard(<4 x i32> inreg %desc) #0 { 96main_body: 97 %d0 = insertelement <4 x i32> undef, i32 0, i32 0 98 %d1 = insertelement <4 x i32> %d0, i32 1, i32 1 99 %d2 = insertelement <4 x i32> %d1, i32 2, i32 2 100 %d3 = insertelement <4 x i32> %d2, i32 3, i32 3 101 %r = call float @llvm.SI.load.const.v4i32(<4 x i32> %d3, i32 0) 102 ret float %r 103} 104 105; SMRD load using the load.const.v4i32 intrinsic with an immediate offset 106; GCN-LABEL: {{^}}smrd_load_const0: 107; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 ; encoding: [0x04 108; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x10 109define amdgpu_ps void @smrd_load_const0(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in) #0 { 110main_body: 111 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0 112 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp 113 %tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 16) 114 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %tmp21, i1 true, i1 true) #0 115 ret void 116} 117 118; SMRD load using the load.const.v4i32 intrinsic with the largest possible immediate 119; offset. 120; GCN-LABEL: {{^}}smrd_load_const1: 121; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff 122; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff glc ; encoding: [0xff 123; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc 124; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc glc 125define amdgpu_ps void @smrd_load_const1(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in) #0 { 126main_body: 127 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0 128 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp 129 %tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 1020) 130 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %in 131 %s.buffer = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %tmp22, i32 1020, i32 1) 132 %s.buffer.float = bitcast i32 %s.buffer to float 133 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %s.buffer.float, i1 true, i1 true) #0 134 ret void 135} 136 137; SMRD load using the load.const.v4i32 intrinsic with an offset greater than the 138; largets possible immediate. 139; immediate offset. 140; GCN-LABEL: {{^}}smrd_load_const2: 141; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400 142; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]] 143; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]] 144; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100 145; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100 146; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400 147; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400 148define amdgpu_ps void @smrd_load_const2(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in) #0 { 149main_body: 150 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0 151 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp 152 %tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 1024) 153 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %in 154 %s.buffer = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %tmp22, i32 1024, i32 0) 155 %s.buffer.float = bitcast i32 %s.buffer to float 156 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %s.buffer.float, i1 true, i1 true) #0 157 ret void 158} 159 160; SMRD load with the largest possible immediate offset on VI 161; GCN-LABEL: {{^}}smrd_load_const3: 162; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc 163; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]] 164; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]] 165; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff 166; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff 167; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc 168; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc 169define amdgpu_ps void @smrd_load_const3(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in) #0 { 170main_body: 171 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0 172 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp 173 %tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 1048572) 174 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %in 175 %s.buffer = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %tmp22, i32 1048572, i32 0) 176 %s.buffer.float = bitcast i32 %s.buffer to float 177 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %s.buffer.float, i1 true, i1 true) #0 178 ret void 179} 180 181; SMRD load with an offset greater than the largest possible immediate on VI 182; GCN-LABEL: {{^}}smrd_load_const4: 183; SIVIGFX9: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000 184; SIVIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]] 185; SIVIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]] 186; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000 187; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000 188; GCN: s_endpgm 189define amdgpu_ps void @smrd_load_const4(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in) #0 { 190main_body: 191 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0 192 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp 193 %tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 1048576) 194 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %in 195 %s.buffer = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %tmp22, i32 1048576, i32 0) 196 %s.buffer.float = bitcast i32 %s.buffer to float 197 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %s.buffer.float, i1 true, i1 true) #0 198 ret void 199} 200 201; dwordx2 s.buffer.load 202; GCN-LABEL: {{^}}s_buffer_load_dwordx2: 203; VIGFX9: s_buffer_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x80 204; SICI: s_buffer_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x20 205define amdgpu_ps void @s_buffer_load_dwordx2(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in) #0 { 206main_body: 207 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %in 208 %s.buffer = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %tmp22, i32 128, i32 0) 209 %s.buffer.0 = extractelement <2 x i32> %s.buffer, i32 0 210 %s.buffer.0.float = bitcast i32 %s.buffer.0 to float 211 %s.buffer.1 = extractelement <2 x i32> %s.buffer, i32 1 212 %s.buffer.1.float = bitcast i32 %s.buffer.1 to float 213 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %s.buffer.0.float, float %s.buffer.1.float, float %s.buffer.0.float, float %s.buffer.1.float, i1 true, i1 true) #0 214 ret void 215} 216 217; dwordx4 s.buffer.load 218; GCN-LABEL: {{^}}s_buffer_load_dwordx4: 219; VIGFX9: s_buffer_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x80 220; SICI: s_buffer_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x20 221define amdgpu_ps void @s_buffer_load_dwordx4(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in) #0 { 222main_body: 223 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %in 224 %s.buffer = call <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32> %tmp22, i32 128, i32 0) 225 %s.buffer.0 = extractelement <4 x i32> %s.buffer, i32 0 226 %s.buffer.0.float = bitcast i32 %s.buffer.0 to float 227 %s.buffer.1 = extractelement <4 x i32> %s.buffer, i32 1 228 %s.buffer.1.float = bitcast i32 %s.buffer.1 to float 229 %s.buffer.2 = extractelement <4 x i32> %s.buffer, i32 2 230 %s.buffer.2.float = bitcast i32 %s.buffer.2 to float 231 %s.buffer.3 = extractelement <4 x i32> %s.buffer, i32 3 232 %s.buffer.3.float = bitcast i32 %s.buffer.3 to float 233 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %s.buffer.0.float, float %s.buffer.1.float, float %s.buffer.2.float, float %s.buffer.3.float, i1 true, i1 true) #0 234 ret void 235} 236 237; dwordx8 s.buffer.load 238; GCN-LABEL: {{^}}s_buffer_load_dwordx8: 239; VIGFX9: s_buffer_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x80 240; SICI: s_buffer_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x20 241define amdgpu_ps void @s_buffer_load_dwordx8(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in) #0 { 242main_body: 243 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %in 244 %s.buffer = call <8 x i32> @llvm.amdgcn.s.buffer.load.v8i32(<4 x i32> %tmp22, i32 128, i32 0) 245 %s.buffer.0 = extractelement <8 x i32> %s.buffer, i32 0 246 %s.buffer.0.float = bitcast i32 %s.buffer.0 to float 247 %s.buffer.1 = extractelement <8 x i32> %s.buffer, i32 2 248 %s.buffer.1.float = bitcast i32 %s.buffer.1 to float 249 %s.buffer.2 = extractelement <8 x i32> %s.buffer, i32 5 250 %s.buffer.2.float = bitcast i32 %s.buffer.2 to float 251 %s.buffer.3 = extractelement <8 x i32> %s.buffer, i32 7 252 %s.buffer.3.float = bitcast i32 %s.buffer.3 to float 253 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %s.buffer.0.float, float %s.buffer.1.float, float %s.buffer.2.float, float %s.buffer.3.float, i1 true, i1 true) #0 254 ret void 255} 256 257; dwordx16 s.buffer.load 258; GCN-LABEL: {{^}}s_buffer_load_dwordx16: 259; VIGFX9: s_buffer_load_dwordx16 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x80 260; SICI: s_buffer_load_dwordx16 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]:[0-9]}}], 0x20 261define amdgpu_ps void @s_buffer_load_dwordx16(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in) #0 { 262main_body: 263 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %in 264 %s.buffer = call <16 x i32> @llvm.amdgcn.s.buffer.load.v16i32(<4 x i32> %tmp22, i32 128, i32 0) 265 %s.buffer.0 = extractelement <16 x i32> %s.buffer, i32 0 266 %s.buffer.0.float = bitcast i32 %s.buffer.0 to float 267 %s.buffer.1 = extractelement <16 x i32> %s.buffer, i32 3 268 %s.buffer.1.float = bitcast i32 %s.buffer.1 to float 269 %s.buffer.2 = extractelement <16 x i32> %s.buffer, i32 12 270 %s.buffer.2.float = bitcast i32 %s.buffer.2 to float 271 %s.buffer.3 = extractelement <16 x i32> %s.buffer, i32 15 272 %s.buffer.3.float = bitcast i32 %s.buffer.3 to float 273 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %s.buffer.0.float, float %s.buffer.1.float, float %s.buffer.2.float, float %s.buffer.3.float, i1 true, i1 true) #0 274 ret void 275} 276 277; GCN-LABEL: {{^}}smrd_sgpr_offset: 278; GCN: s_buffer_load_dword s{{[0-9]}}, s[0:3], s4 279define amdgpu_ps float @smrd_sgpr_offset(<4 x i32> inreg %desc, i32 inreg %offset) #0 { 280main_body: 281 %r = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %offset) 282 ret float %r 283} 284 285; GCN-LABEL: {{^}}smrd_vgpr_offset: 286; GCN: buffer_load_dword v{{[0-9]}}, v0, s[0:3], 0 offen ; 287define amdgpu_ps float @smrd_vgpr_offset(<4 x i32> inreg %desc, i32 %offset) #0 { 288main_body: 289 %r = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %offset) 290 ret float %r 291} 292 293; GCN-LABEL: {{^}}smrd_vgpr_offset_imm: 294; GCN-NEXT: %bb. 295; GCN-NEXT: buffer_load_dword v{{[0-9]}}, v0, s[0:3], 0 offen offset:4092 ; 296define amdgpu_ps float @smrd_vgpr_offset_imm(<4 x i32> inreg %desc, i32 %offset) #0 { 297main_body: 298 %off = add i32 %offset, 4092 299 %r = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %off) 300 ret float %r 301} 302 303; GCN-LABEL: {{^}}smrd_vgpr_offset_imm_too_large: 304; GCN-NEXT: %bb. 305; SICI-NEXT: v_add_{{i|u}}32_e32 v0, {{(vcc, )?}}0x1000, v0 306; SICI-NEXT: buffer_load_dword v{{[0-9]}}, v0, s[0:3], 0 offen ; 307; VIGFX9-NEXT: buffer_load_dword v{{[0-9]}}, v0, s[0:3], 4 offen offset:4092 ; 308define amdgpu_ps float @smrd_vgpr_offset_imm_too_large(<4 x i32> inreg %desc, i32 %offset) #0 { 309main_body: 310 %off = add i32 %offset, 4096 311 %r = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %off) 312 ret float %r 313} 314 315; GCN-LABEL: {{^}}smrd_imm_merged: 316; GCN-NEXT: %bb. 317; SICI-NEXT: s_buffer_load_dwordx4 s[{{[0-9]}}:{{[0-9]}}], s[0:3], 0x1 318; SICI-NEXT: s_buffer_load_dwordx2 s[{{[0-9]}}:{{[0-9]}}], s[0:3], 0x7 319; VIGFX9-NEXT: s_buffer_load_dwordx4 s[{{[0-9]}}:{{[0-9]}}], s[0:3], 0x4 320; VIGFX9-NEXT: s_buffer_load_dwordx2 s[{{[0-9]}}:{{[0-9]}}], s[0:3], 0x1c 321define amdgpu_ps void @smrd_imm_merged(<4 x i32> inreg %desc) #0 { 322main_body: 323 %r1 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 4) 324 %r2 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 8) 325 %r3 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 12) 326 %r4 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 16) 327 %r5 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 28) 328 %r6 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 32) 329 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) #0 330 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) #0 331 ret void 332} 333 334; GCN-LABEL: {{^}}smrd_imm_merge_m0: 335; 336; SICIVI: s_buffer_load_dwordx2 337; SICIVI: s_mov_b32 m0 338; SICIVI_DAG: v_interp_p1_f32 339; SICIVI_DAG: v_interp_p1_f32 340; SICIVI_DAG: v_interp_p1_f32 341; SICIVI_DAG: v_interp_p2_f32 342; SICIVI_DAG: v_interp_p2_f32 343; SICIVI_DAG: v_interp_p2_f32 344; SICIVI: s_mov_b32 m0 345; SICIVI: v_movrels_b32_e32 346; 347; Merging is still thwarted on GFX9 due to s_set_gpr_idx 348; 349; GFX9: s_buffer_load_dword 350; GFX9: s_buffer_load_dword 351define amdgpu_ps float @smrd_imm_merge_m0(<4 x i32> inreg %desc, i32 inreg %prim, float %u, float %v) #0 { 352main_body: 353 %idx1.f = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 0) 354 %idx1 = bitcast float %idx1.f to i32 355 356 %v0.x1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 0, i32 0, i32 %prim) 357 %v0.x = call nsz float @llvm.amdgcn.interp.p2(float %v0.x1, float %v, i32 0, i32 0, i32 %prim) 358 %v0.y1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 0, i32 1, i32 %prim) 359 %v0.y = call nsz float @llvm.amdgcn.interp.p2(float %v0.y1, float %v, i32 0, i32 1, i32 %prim) 360 %v0.z1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 0, i32 2, i32 %prim) 361 %v0.z = call nsz float @llvm.amdgcn.interp.p2(float %v0.z1, float %v, i32 0, i32 2, i32 %prim) 362 %v0.tmp0 = insertelement <3 x float> undef, float %v0.x, i32 0 363 %v0.tmp1 = insertelement <3 x float> %v0.tmp0, float %v0.y, i32 1 364 %v0 = insertelement <3 x float> %v0.tmp1, float %v0.z, i32 2 365 %a = extractelement <3 x float> %v0, i32 %idx1 366 367 %v1.x1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 1, i32 0, i32 %prim) 368 %v1.x = call nsz float @llvm.amdgcn.interp.p2(float %v1.x1, float %v, i32 1, i32 0, i32 %prim) 369 %v1.y1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 1, i32 1, i32 %prim) 370 %v1.y = call nsz float @llvm.amdgcn.interp.p2(float %v1.y1, float %v, i32 1, i32 1, i32 %prim) 371 %v1.z1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 1, i32 2, i32 %prim) 372 %v1.z = call nsz float @llvm.amdgcn.interp.p2(float %v1.z1, float %v, i32 1, i32 2, i32 %prim) 373 %v1.tmp0 = insertelement <3 x float> undef, float %v0.x, i32 0 374 %v1.tmp1 = insertelement <3 x float> %v0.tmp0, float %v0.y, i32 1 375 %v1 = insertelement <3 x float> %v0.tmp1, float %v0.z, i32 2 376 377 %b = extractelement <3 x float> %v1, i32 %idx1 378 %c = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 4) 379 380 %res.tmp = fadd float %a, %b 381 %res = fadd float %res.tmp, %c 382 ret float %res 383} 384 385; GCN-LABEL: {{^}}smrd_vgpr_merged: 386; GCN-NEXT: %bb. 387; GCN-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4 388; GCN-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28 389define amdgpu_ps void @smrd_vgpr_merged(<4 x i32> inreg %desc, i32 %a) #0 { 390main_body: 391 %a1 = add i32 %a, 4 392 %a2 = add i32 %a, 8 393 %a3 = add i32 %a, 12 394 %a4 = add i32 %a, 16 395 %a5 = add i32 %a, 28 396 %a6 = add i32 %a, 32 397 %r1 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %a1) 398 %r2 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %a2) 399 %r3 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %a3) 400 %r4 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %a4) 401 %r5 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %a5) 402 %r6 = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %a6) 403 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true) #0 404 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) #0 405 ret void 406} 407 408; GCN-LABEL: {{^}}smrd_sgpr_descriptor_promoted 409; GCN: v_readfirstlane 410define amdgpu_cs void @smrd_sgpr_descriptor_promoted([0 x i8] addrspace(4)* inreg noalias dereferenceable(18446744073709551615), i32) #0 { 411main_body: 412 %descptr = bitcast [0 x i8] addrspace(4)* %0 to <4 x i32> addrspace(4)*, !amdgpu.uniform !0 413 br label %.outer_loop_header 414 415ret_block: ; preds = %.outer, %.label22, %main_body 416 ret void 417 418.outer_loop_header: 419 br label %.inner_loop_header 420 421.inner_loop_header: ; preds = %.inner_loop_body, %.outer_loop_header 422 %loopctr.1 = phi i32 [ 0, %.outer_loop_header ], [ %loopctr.2, %.inner_loop_body ] 423 %loopctr.2 = add i32 %loopctr.1, 1 424 %inner_br1 = icmp slt i32 %loopctr.2, 10 425 br i1 %inner_br1, label %.inner_loop_body, label %ret_block 426 427.inner_loop_body: 428 %descriptor = load <4 x i32>, <4 x i32> addrspace(4)* %descptr, align 16, !invariant.load !0 429 %load1result = call float @llvm.SI.load.const.v4i32(<4 x i32> %descriptor, i32 0) 430 store float %load1result, float addrspace(1)* undef 431 %inner_br2 = icmp uge i32 %1, 10 432 br i1 %inner_br2, label %.inner_loop_header, label %.outer_loop_body 433 434.outer_loop_body: 435 %offset = shl i32 %loopctr.2, 6 436 %load2result = call float @llvm.SI.load.const.v4i32(<4 x i32> %descriptor, i32 %offset) 437 %outer_br = fcmp ueq float %load2result, 0x0 438 br i1 %outer_br, label %.outer_loop_header, label %ret_block 439} 440 441; SMRD load with a non-const offset 442; GCN-LABEL: {{^}}smrd_load_nonconst0: 443; SIVIGFX9: s_buffer_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} 444; SIVIGFX9: s_buffer_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} 445; CI: s_buffer_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} 446; CI: s_buffer_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} 447; GCN: s_endpgm 448define amdgpu_ps void @smrd_load_nonconst0(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in, i32 inreg %ncoff) #0 { 449main_body: 450 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0 451 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp 452 %tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 %ncoff) 453 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %in 454 %s.buffer = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %tmp22, i32 %ncoff, i32 0) 455 %s.buffer.float = bitcast i32 %s.buffer to float 456 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %s.buffer.float, i1 true, i1 true) #0 457 ret void 458} 459 460; SMRD load with a non-const non-uniform offset 461; GCN-LABEL: {{^}}smrd_load_nonconst1: 462; SIVIGFX9: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen 463; SIVIGFX9: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen 464; CI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen 465; CI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen 466; GCN: s_endpgm 467define amdgpu_ps void @smrd_load_nonconst1(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in, i32 %ncoff) #0 { 468main_body: 469 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0 470 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp 471 %tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 %ncoff) 472 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %in 473 %s.buffer = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %tmp22, i32 %ncoff, i32 0) 474 %s.buffer.float = bitcast i32 %s.buffer to float 475 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %s.buffer.float, i1 true, i1 true) #0 476 ret void 477} 478 479; SMRD load with a non-const non-uniform offset of > 4 dwords (requires splitting) 480; GCN-LABEL: {{^}}smrd_load_nonconst2: 481; SIVIGFX9: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen 482; SIVIGFX9: buffer_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen 483; CI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen 484; CI: buffer_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen 485; GCN: s_endpgm 486define amdgpu_ps void @smrd_load_nonconst2(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in, i32 %ncoff) #0 { 487main_body: 488 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0 489 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp 490 %tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 %ncoff) 491 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %in 492 %s.buffer = call <8 x i32> @llvm.amdgcn.s.buffer.load.v8i32(<4 x i32> %tmp22, i32 %ncoff, i32 0) 493 %s.buffer.elt = extractelement <8 x i32> %s.buffer, i32 1 494 %s.buffer.float = bitcast i32 %s.buffer.elt to float 495 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %s.buffer.float, i1 true, i1 true) #0 496 ret void 497} 498 499; SMRD load with a non-const non-uniform offset of > 4 dwords (requires splitting) 500; GCN-LABEL: {{^}}smrd_load_nonconst3: 501; GCN-DAG: buffer_load_dwordx4 v[0:3], v{{[0-9]+}}, s[0:3], 0 offen ; 502; GCN-DAG: buffer_load_dwordx4 v[4:7], v{{[0-9]+}}, s[0:3], 0 offen offset:16 ; 503; GCN-DAG: buffer_load_dwordx4 v[8:11], v{{[0-9]+}}, s[0:3], 0 offen offset:32 ; 504; GCN-DAG: buffer_load_dwordx4 v[12:15], v{{[0-9]+}}, s[0:3], 0 offen offset:48 ; 505; GCN: ; return to shader part epilog 506define amdgpu_ps <16 x float> @smrd_load_nonconst3(<4 x i32> inreg %rsrc, i32 %off) #0 { 507main_body: 508 %ld = call <16 x i32> @llvm.amdgcn.s.buffer.load.v16i32(<4 x i32> %rsrc, i32 %off, i32 0) 509 %bc = bitcast <16 x i32> %ld to <16 x float> 510 ret <16 x float> %bc 511} 512 513; GCN-LABEL: {{^}}smrd_load_nonconst4: 514; SICI: v_add_i32_e32 v{{[0-9]+}}, vcc, 0xff8, v0 ; 515; SICI-DAG: buffer_load_dwordx4 v[0:3], v{{[0-9]+}}, s[0:3], 0 offen ; 516; SICI-DAG: buffer_load_dwordx4 v[4:7], v{{[0-9]+}}, s[0:3], 0 offen offset:16 ; 517; SICI-DAG: buffer_load_dwordx4 v[8:11], v{{[0-9]+}}, s[0:3], 0 offen offset:32 ; 518; SICI-DAG: buffer_load_dwordx4 v[12:15], v{{[0-9]+}}, s[0:3], 0 offen offset:48 ; 519; VIGFX9-DAG: buffer_load_dwordx4 v[0:3], v{{[0-9]+}}, s[0:3], 56 offen offset:4032 ; 520; VIGFX9-DAG: buffer_load_dwordx4 v[4:7], v{{[0-9]+}}, s[0:3], 56 offen offset:4048 ; 521; VIGFX9-DAG: buffer_load_dwordx4 v[8:11], v{{[0-9]+}}, s[0:3], 56 offen offset:4064 ; 522; VIGFX9-DAG: buffer_load_dwordx4 v[12:15], v{{[0-9]+}}, s[0:3], 56 offen offset:4080 ; 523; GCN: ; return to shader part epilog 524define amdgpu_ps <16 x float> @smrd_load_nonconst4(<4 x i32> inreg %rsrc, i32 %off) #0 { 525main_body: 526 %off.2 = add i32 %off, 4088 527 %ld = call <16 x i32> @llvm.amdgcn.s.buffer.load.v16i32(<4 x i32> %rsrc, i32 %off.2, i32 0) 528 %bc = bitcast <16 x i32> %ld to <16 x float> 529 ret <16 x float> %bc 530} 531 532; GCN-LABEL: {{^}}smrd_load_nonconst5: 533; SICI: v_add_i32_e32 v{{[0-9]+}}, vcc, 0x1004, v0 534; SICI-DAG: buffer_load_dwordx4 v[0:3], v{{[0-9]+}}, s[0:3], 0 offen ; 535; SICI-DAG: buffer_load_dwordx4 v[4:7], v{{[0-9]+}}, s[0:3], 0 offen offset:16 ; 536; SICI-DAG: buffer_load_dwordx4 v[8:11], v{{[0-9]+}}, s[0:3], 0 offen offset:32 ; 537; SICI-DAG: buffer_load_dwordx4 v[12:15], v{{[0-9]+}}, s[0:3], 0 offen offset:48 ; 538; VIGFX9: s_movk_i32 s4, 0xfc0 539; VIGFX9-DAG: buffer_load_dwordx4 v[0:3], v{{[0-9]+}}, s[0:3], s4 offen offset:68 ; 540; VIGFX9-DAG: buffer_load_dwordx4 v[4:7], v{{[0-9]+}}, s[0:3], s4 offen offset:84 ; 541; VIGFX9-DAG: buffer_load_dwordx4 v[8:11], v{{[0-9]+}}, s[0:3], s4 offen offset:100 ; 542; VIGFX9-DAG: buffer_load_dwordx4 v[12:15], v{{[0-9]+}}, s[0:3], s4 offen offset:116 ; 543; GCN: ; return to shader part epilog 544define amdgpu_ps <16 x float> @smrd_load_nonconst5(<4 x i32> inreg %rsrc, i32 %off) #0 { 545main_body: 546 %off.2 = add i32 %off, 4100 547 %ld = call <16 x i32> @llvm.amdgcn.s.buffer.load.v16i32(<4 x i32> %rsrc, i32 %off.2, i32 0) 548 %bc = bitcast <16 x i32> %ld to <16 x float> 549 ret <16 x float> %bc 550} 551 552; SMRD load dwordx2 553; GCN-LABEL: {{^}}smrd_load_dwordx2: 554; SIVIGFX9: s_buffer_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} 555; CI: s_buffer_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} 556; GCN: s_endpgm 557define amdgpu_ps void @smrd_load_dwordx2(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, <4 x i32> addrspace(4)* inreg %in, i32 inreg %ncoff) #0 { 558main_body: 559 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %in 560 %s.buffer = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %tmp22, i32 %ncoff, i32 0) 561 %s.buffer.float = bitcast <2 x i32> %s.buffer to <2 x float> 562 %r.1 = extractelement <2 x float> %s.buffer.float, i32 0 563 %r.2 = extractelement <2 x float> %s.buffer.float, i32 1 564 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r.1, float %r.1, float %r.1, float %r.2, i1 true, i1 true) #0 565 ret void 566} 567 568; GCN-LABEL: {{^}}smrd_uniform_loop: 569; 570; TODO: we should keep the loop counter in an SGPR 571; 572; GCN: v_readfirstlane_b32 573; GCN: s_buffer_load_dword 574define amdgpu_ps float @smrd_uniform_loop(<4 x i32> inreg %desc, i32 %bound) #0 { 575main_body: 576 br label %loop 577 578loop: 579 %counter = phi i32 [ 0, %main_body ], [ %counter.next, %loop ] 580 %sum = phi float [ 0.0, %main_body ], [ %sum.next, %loop ] 581 %offset = shl i32 %counter, 2 582 %v = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %offset) 583 %sum.next = fadd float %sum, %v 584 %counter.next = add i32 %counter, 1 585 %cc = icmp uge i32 %counter.next, %bound 586 br i1 %cc, label %exit, label %loop 587 588exit: 589 ret float %sum.next 590} 591 592 593; GCN-LABEL: {{^}}smrd_uniform_loop2: 594; (this test differs from smrd_uniform_loop by the more complex structure of phis, 595; which used to confuse the DivergenceAnalysis after structurization) 596; 597; TODO: we should keep the loop counter in an SGPR 598; 599; GCN: v_readfirstlane_b32 600; GCN: s_buffer_load_dword 601define amdgpu_ps float @smrd_uniform_loop2(<4 x i32> inreg %desc, i32 %bound, i32 %bound.a) #0 { 602main_body: 603 br label %loop 604 605loop: 606 %counter = phi i32 [ 0, %main_body ], [ %counter.next, %loop.a ], [ %counter.next, %loop.b ] 607 %sum = phi float [ 0.0, %main_body ], [ %sum.next, %loop.a ], [ %sum.next.b, %loop.b ] 608 %offset = shl i32 %counter, 2 609 %v = call float @llvm.SI.load.const.v4i32(<4 x i32> %desc, i32 %offset) 610 %sum.next = fadd float %sum, %v 611 %counter.next = add i32 %counter, 1 612 %cc = icmp uge i32 %counter.next, %bound 613 br i1 %cc, label %exit, label %loop.a 614 615loop.a: 616 %cc.a = icmp uge i32 %counter.next, %bound.a 617 br i1 %cc, label %loop, label %loop.b 618 619loop.b: 620 %sum.next.b = fadd float %sum.next, 1.0 621 br label %loop 622 623exit: 624 ret float %sum.next 625} 626 627 628declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0 629declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #1 630declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #2 631declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #2 632declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32) 633declare <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32>, i32, i32) 634declare <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32>, i32, i32) 635declare <8 x i32> @llvm.amdgcn.s.buffer.load.v8i32(<4 x i32>, i32, i32) 636declare <16 x i32> @llvm.amdgcn.s.buffer.load.v16i32(<4 x i32>, i32, i32) 637 638attributes #0 = { nounwind } 639attributes #1 = { nounwind readnone } 640attributes #2 = { nounwind readnone speculatable } 641 642!0 = !{} 643