1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,WAVE64,SI %s
3; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,WAVE64,GFX10-WAVE64 %s
4; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,GFX10-WAVE32 %s
5
6define amdgpu_ps void @test_kill_depth_0_imm_pos() #0 {
7; GCN-LABEL: test_kill_depth_0_imm_pos:
8; GCN:       ; %bb.0:
9; GCN-NEXT:    s_endpgm
10  call void @llvm.amdgcn.kill(i1 true)
11  ret void
12}
13
14define amdgpu_ps void @test_kill_depth_0_imm_neg() #0 {
15; WAVE64-LABEL: test_kill_depth_0_imm_neg:
16; WAVE64:       ; %bb.0:
17; WAVE64-NEXT:    s_andn2_b64 exec, exec, exec
18; WAVE64-NEXT:    s_cbranch_scc0 .LBB1_1
19; WAVE64-NEXT:    s_endpgm
20; WAVE64-NEXT:  .LBB1_1:
21; WAVE64-NEXT:    s_mov_b64 exec, 0
22; WAVE64-NEXT:    exp null off, off, off, off done vm
23; WAVE64-NEXT:    s_endpgm
24;
25; GFX10-WAVE32-LABEL: test_kill_depth_0_imm_neg:
26; GFX10-WAVE32:       ; %bb.0:
27; GFX10-WAVE32-NEXT:    s_andn2_b32 exec_lo, exec_lo, exec_lo
28; GFX10-WAVE32-NEXT:    s_cbranch_scc0 .LBB1_1
29; GFX10-WAVE32-NEXT:    s_endpgm
30; GFX10-WAVE32-NEXT:  .LBB1_1:
31; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
32; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
33; GFX10-WAVE32-NEXT:    s_endpgm
34  call void @llvm.amdgcn.kill(i1 false)
35  ret void
36}
37
38; FIXME: Ideally only one early-exit would be emitted
39define amdgpu_ps void @test_kill_depth_0_imm_neg_x2() #0 {
40; WAVE64-LABEL: test_kill_depth_0_imm_neg_x2:
41; WAVE64:       ; %bb.0:
42; WAVE64-NEXT:    s_mov_b64 s[0:1], exec
43; WAVE64-NEXT:    s_andn2_b64 s[0:1], s[0:1], exec
44; WAVE64-NEXT:    s_cbranch_scc0 .LBB2_2
45; WAVE64-NEXT:  ; %bb.1:
46; WAVE64-NEXT:    s_mov_b64 exec, 0
47; WAVE64-NEXT:    s_andn2_b64 s[0:1], s[0:1], exec
48; WAVE64-NEXT:    s_cbranch_scc0 .LBB2_2
49; WAVE64-NEXT:    s_endpgm
50; WAVE64-NEXT:  .LBB2_2:
51; WAVE64-NEXT:    s_mov_b64 exec, 0
52; WAVE64-NEXT:    exp null off, off, off, off done vm
53; WAVE64-NEXT:    s_endpgm
54;
55; GFX10-WAVE32-LABEL: test_kill_depth_0_imm_neg_x2:
56; GFX10-WAVE32:       ; %bb.0:
57; GFX10-WAVE32-NEXT:    s_mov_b32 s0, exec_lo
58; GFX10-WAVE32-NEXT:    s_andn2_b32 s0, s0, exec_lo
59; GFX10-WAVE32-NEXT:    s_cbranch_scc0 .LBB2_2
60; GFX10-WAVE32-NEXT:  ; %bb.1:
61; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
62; GFX10-WAVE32-NEXT:    s_andn2_b32 s0, s0, exec_lo
63; GFX10-WAVE32-NEXT:    s_cbranch_scc0 .LBB2_2
64; GFX10-WAVE32-NEXT:    s_endpgm
65; GFX10-WAVE32-NEXT:  .LBB2_2:
66; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
67; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
68; GFX10-WAVE32-NEXT:    s_endpgm
69  call void @llvm.amdgcn.kill(i1 false)
70  call void @llvm.amdgcn.kill(i1 false)
71  ret void
72}
73
74define amdgpu_ps void @test_kill_depth_var(float %x) #0 {
75; WAVE64-LABEL: test_kill_depth_var:
76; WAVE64:       ; %bb.0:
77; WAVE64-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v0
78; WAVE64-NEXT:    s_andn2_b64 exec, exec, vcc
79; WAVE64-NEXT:    s_cbranch_scc0 .LBB3_1
80; WAVE64-NEXT:    s_endpgm
81; WAVE64-NEXT:  .LBB3_1:
82; WAVE64-NEXT:    s_mov_b64 exec, 0
83; WAVE64-NEXT:    exp null off, off, off, off done vm
84; WAVE64-NEXT:    s_endpgm
85;
86; GFX10-WAVE32-LABEL: test_kill_depth_var:
87; GFX10-WAVE32:       ; %bb.0:
88; GFX10-WAVE32-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, 0, v0
89; GFX10-WAVE32-NEXT:    s_andn2_b32 exec_lo, exec_lo, vcc_lo
90; GFX10-WAVE32-NEXT:    s_cbranch_scc0 .LBB3_1
91; GFX10-WAVE32-NEXT:    s_endpgm
92; GFX10-WAVE32-NEXT:  .LBB3_1:
93; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
94; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
95; GFX10-WAVE32-NEXT:    s_endpgm
96  %cmp = fcmp olt float %x, 0.0
97  call void @llvm.amdgcn.kill(i1 %cmp)
98  ret void
99}
100
101; FIXME: Ideally only one early-exit would be emitted
102define amdgpu_ps void @test_kill_depth_var_x2_same(float %x) #0 {
103; SI-LABEL: test_kill_depth_var_x2_same:
104; SI:       ; %bb.0:
105; SI-NEXT:    s_mov_b64 s[0:1], exec
106; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v0
107; SI-NEXT:    s_andn2_b64 s[0:1], s[0:1], vcc
108; SI-NEXT:    s_cbranch_scc0 .LBB4_2
109; SI-NEXT:  ; %bb.1:
110; SI-NEXT:    s_andn2_b64 exec, exec, vcc
111; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v0
112; SI-NEXT:    s_andn2_b64 s[0:1], s[0:1], vcc
113; SI-NEXT:    s_cbranch_scc0 .LBB4_2
114; SI-NEXT:    s_endpgm
115; SI-NEXT:  .LBB4_2:
116; SI-NEXT:    s_mov_b64 exec, 0
117; SI-NEXT:    exp null off, off, off, off done vm
118; SI-NEXT:    s_endpgm
119;
120; GFX10-WAVE64-LABEL: test_kill_depth_var_x2_same:
121; GFX10-WAVE64:       ; %bb.0:
122; GFX10-WAVE64-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v0
123; GFX10-WAVE64-NEXT:    s_mov_b64 s[0:1], exec
124; GFX10-WAVE64-NEXT:    s_andn2_b64 s[0:1], s[0:1], vcc
125; GFX10-WAVE64-NEXT:    s_cbranch_scc0 .LBB4_2
126; GFX10-WAVE64-NEXT:  ; %bb.1:
127; GFX10-WAVE64-NEXT:    s_andn2_b64 exec, exec, vcc
128; GFX10-WAVE64-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v0
129; GFX10-WAVE64-NEXT:    s_andn2_b64 s[0:1], s[0:1], vcc
130; GFX10-WAVE64-NEXT:    s_cbranch_scc0 .LBB4_2
131; GFX10-WAVE64-NEXT:    s_endpgm
132; GFX10-WAVE64-NEXT:  .LBB4_2:
133; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
134; GFX10-WAVE64-NEXT:    exp null off, off, off, off done vm
135; GFX10-WAVE64-NEXT:    s_endpgm
136;
137; GFX10-WAVE32-LABEL: test_kill_depth_var_x2_same:
138; GFX10-WAVE32:       ; %bb.0:
139; GFX10-WAVE32-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, 0, v0
140; GFX10-WAVE32-NEXT:    s_mov_b32 s0, exec_lo
141; GFX10-WAVE32-NEXT:    s_andn2_b32 s0, s0, vcc_lo
142; GFX10-WAVE32-NEXT:    s_cbranch_scc0 .LBB4_2
143; GFX10-WAVE32-NEXT:  ; %bb.1:
144; GFX10-WAVE32-NEXT:    s_andn2_b32 exec_lo, exec_lo, vcc_lo
145; GFX10-WAVE32-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, 0, v0
146; GFX10-WAVE32-NEXT:    s_andn2_b32 s0, s0, vcc_lo
147; GFX10-WAVE32-NEXT:    s_cbranch_scc0 .LBB4_2
148; GFX10-WAVE32-NEXT:    s_endpgm
149; GFX10-WAVE32-NEXT:  .LBB4_2:
150; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
151; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
152; GFX10-WAVE32-NEXT:    s_endpgm
153  %cmp = fcmp olt float %x, 0.0
154  call void @llvm.amdgcn.kill(i1 %cmp)
155  call void @llvm.amdgcn.kill(i1 %cmp)
156  ret void
157}
158
159; FIXME: Ideally only one early-exit would be emitted
160define amdgpu_ps void @test_kill_depth_var_x2(float %x, float %y) #0 {
161; SI-LABEL: test_kill_depth_var_x2:
162; SI:       ; %bb.0:
163; SI-NEXT:    s_mov_b64 s[0:1], exec
164; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v0
165; SI-NEXT:    s_andn2_b64 s[0:1], s[0:1], vcc
166; SI-NEXT:    s_cbranch_scc0 .LBB5_2
167; SI-NEXT:  ; %bb.1:
168; SI-NEXT:    s_andn2_b64 exec, exec, vcc
169; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v1
170; SI-NEXT:    s_andn2_b64 s[0:1], s[0:1], vcc
171; SI-NEXT:    s_cbranch_scc0 .LBB5_2
172; SI-NEXT:    s_endpgm
173; SI-NEXT:  .LBB5_2:
174; SI-NEXT:    s_mov_b64 exec, 0
175; SI-NEXT:    exp null off, off, off, off done vm
176; SI-NEXT:    s_endpgm
177;
178; GFX10-WAVE64-LABEL: test_kill_depth_var_x2:
179; GFX10-WAVE64:       ; %bb.0:
180; GFX10-WAVE64-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v0
181; GFX10-WAVE64-NEXT:    s_mov_b64 s[0:1], exec
182; GFX10-WAVE64-NEXT:    s_andn2_b64 s[0:1], s[0:1], vcc
183; GFX10-WAVE64-NEXT:    s_cbranch_scc0 .LBB5_2
184; GFX10-WAVE64-NEXT:  ; %bb.1:
185; GFX10-WAVE64-NEXT:    s_andn2_b64 exec, exec, vcc
186; GFX10-WAVE64-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v1
187; GFX10-WAVE64-NEXT:    s_andn2_b64 s[0:1], s[0:1], vcc
188; GFX10-WAVE64-NEXT:    s_cbranch_scc0 .LBB5_2
189; GFX10-WAVE64-NEXT:    s_endpgm
190; GFX10-WAVE64-NEXT:  .LBB5_2:
191; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
192; GFX10-WAVE64-NEXT:    exp null off, off, off, off done vm
193; GFX10-WAVE64-NEXT:    s_endpgm
194;
195; GFX10-WAVE32-LABEL: test_kill_depth_var_x2:
196; GFX10-WAVE32:       ; %bb.0:
197; GFX10-WAVE32-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, 0, v0
198; GFX10-WAVE32-NEXT:    s_mov_b32 s0, exec_lo
199; GFX10-WAVE32-NEXT:    s_andn2_b32 s0, s0, vcc_lo
200; GFX10-WAVE32-NEXT:    s_cbranch_scc0 .LBB5_2
201; GFX10-WAVE32-NEXT:  ; %bb.1:
202; GFX10-WAVE32-NEXT:    s_andn2_b32 exec_lo, exec_lo, vcc_lo
203; GFX10-WAVE32-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, 0, v1
204; GFX10-WAVE32-NEXT:    s_andn2_b32 s0, s0, vcc_lo
205; GFX10-WAVE32-NEXT:    s_cbranch_scc0 .LBB5_2
206; GFX10-WAVE32-NEXT:    s_endpgm
207; GFX10-WAVE32-NEXT:  .LBB5_2:
208; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
209; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
210; GFX10-WAVE32-NEXT:    s_endpgm
211  %cmp.x = fcmp olt float %x, 0.0
212  call void @llvm.amdgcn.kill(i1 %cmp.x)
213  %cmp.y = fcmp olt float %y, 0.0
214  call void @llvm.amdgcn.kill(i1 %cmp.y)
215  ret void
216}
217
218define amdgpu_ps void @test_kill_depth_var_x2_instructions(float %x) #0 {
219; SI-LABEL: test_kill_depth_var_x2_instructions:
220; SI:       ; %bb.0:
221; SI-NEXT:    s_mov_b64 s[0:1], exec
222; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v0
223; SI-NEXT:    s_andn2_b64 s[0:1], s[0:1], vcc
224; SI-NEXT:    s_cbranch_scc0 .LBB6_2
225; SI-NEXT:  ; %bb.1:
226; SI-NEXT:    s_andn2_b64 exec, exec, vcc
227; SI-NEXT:    ;;#ASMSTART
228; SI-NEXT:    v_mov_b32_e64 v7, -1
229; SI-NEXT:    ;;#ASMEND
230; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v7
231; SI-NEXT:    s_andn2_b64 s[0:1], s[0:1], vcc
232; SI-NEXT:    s_cbranch_scc0 .LBB6_2
233; SI-NEXT:    s_endpgm
234; SI-NEXT:  .LBB6_2:
235; SI-NEXT:    s_mov_b64 exec, 0
236; SI-NEXT:    exp null off, off, off, off done vm
237; SI-NEXT:    s_endpgm
238;
239; GFX10-WAVE64-LABEL: test_kill_depth_var_x2_instructions:
240; GFX10-WAVE64:       ; %bb.0:
241; GFX10-WAVE64-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v0
242; GFX10-WAVE64-NEXT:    s_mov_b64 s[0:1], exec
243; GFX10-WAVE64-NEXT:    s_andn2_b64 s[0:1], s[0:1], vcc
244; GFX10-WAVE64-NEXT:    s_cbranch_scc0 .LBB6_2
245; GFX10-WAVE64-NEXT:  ; %bb.1:
246; GFX10-WAVE64-NEXT:    s_andn2_b64 exec, exec, vcc
247; GFX10-WAVE64-NEXT:    ;;#ASMSTART
248; GFX10-WAVE64-NEXT:    v_mov_b32_e64 v7, -1
249; GFX10-WAVE64-NEXT:    ;;#ASMEND
250; GFX10-WAVE64-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v7
251; GFX10-WAVE64-NEXT:    s_andn2_b64 s[0:1], s[0:1], vcc
252; GFX10-WAVE64-NEXT:    s_cbranch_scc0 .LBB6_2
253; GFX10-WAVE64-NEXT:    s_endpgm
254; GFX10-WAVE64-NEXT:  .LBB6_2:
255; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
256; GFX10-WAVE64-NEXT:    exp null off, off, off, off done vm
257; GFX10-WAVE64-NEXT:    s_endpgm
258;
259; GFX10-WAVE32-LABEL: test_kill_depth_var_x2_instructions:
260; GFX10-WAVE32:       ; %bb.0:
261; GFX10-WAVE32-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, 0, v0
262; GFX10-WAVE32-NEXT:    s_mov_b32 s0, exec_lo
263; GFX10-WAVE32-NEXT:    s_andn2_b32 s0, s0, vcc_lo
264; GFX10-WAVE32-NEXT:    s_cbranch_scc0 .LBB6_2
265; GFX10-WAVE32-NEXT:  ; %bb.1:
266; GFX10-WAVE32-NEXT:    s_andn2_b32 exec_lo, exec_lo, vcc_lo
267; GFX10-WAVE32-NEXT:    ;;#ASMSTART
268; GFX10-WAVE32-NEXT:    v_mov_b32_e64 v7, -1
269; GFX10-WAVE32-NEXT:    ;;#ASMEND
270; GFX10-WAVE32-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, 0, v7
271; GFX10-WAVE32-NEXT:    s_andn2_b32 s0, s0, vcc_lo
272; GFX10-WAVE32-NEXT:    s_cbranch_scc0 .LBB6_2
273; GFX10-WAVE32-NEXT:    s_endpgm
274; GFX10-WAVE32-NEXT:  .LBB6_2:
275; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
276; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
277; GFX10-WAVE32-NEXT:    s_endpgm
278  %cmp.x = fcmp olt float %x, 0.0
279  call void @llvm.amdgcn.kill(i1 %cmp.x)
280  %y = call float asm sideeffect "v_mov_b32_e64 v7, -1", "={v7}"()
281  %cmp.y = fcmp olt float %y, 0.0
282  call void @llvm.amdgcn.kill(i1 %cmp.y)
283  ret void
284}
285
286; FIXME: why does the skip depend on the asm length in the same block?
287define amdgpu_ps float @test_kill_control_flow(i32 inreg %arg) #0 {
288; SI-LABEL: test_kill_control_flow:
289; SI:       ; %bb.0: ; %entry
290; SI-NEXT:    s_cmp_lg_u32 s0, 0
291; SI-NEXT:    s_cbranch_scc0 .LBB7_2
292; SI-NEXT:  ; %bb.1: ; %exit
293; SI-NEXT:    v_mov_b32_e32 v0, 1.0
294; SI-NEXT:    s_branch .LBB7_5
295; SI-NEXT:  .LBB7_2: ; %bb
296; SI-NEXT:    s_mov_b64 s[2:3], exec
297; SI-NEXT:    ;;#ASMSTART
298; SI-NEXT:    v_mov_b32_e64 v7, -1
299; SI-NEXT:    v_nop_e64
300; SI-NEXT:    v_nop_e64
301; SI-NEXT:    v_nop_e64
302; SI-NEXT:    v_nop_e64
303; SI-NEXT:    v_nop_e64
304; SI-NEXT:    v_nop_e64
305; SI-NEXT:    v_nop_e64
306; SI-NEXT:    v_nop_e64
307; SI-NEXT:    v_nop_e64
308; SI-NEXT:    v_nop_e64
309; SI-NEXT:    ;;#ASMEND
310; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v7
311; SI-NEXT:    s_andn2_b64 s[2:3], s[2:3], vcc
312; SI-NEXT:    s_cbranch_scc0 .LBB7_4
313; SI-NEXT:  ; %bb.3: ; %bb
314; SI-NEXT:    s_andn2_b64 exec, exec, vcc
315; SI-NEXT:    v_mov_b32_e32 v0, 1.0
316; SI-NEXT:    s_branch .LBB7_5
317; SI-NEXT:  .LBB7_4:
318; SI-NEXT:    s_mov_b64 exec, 0
319; SI-NEXT:    exp null off, off, off, off done vm
320; SI-NEXT:    s_endpgm
321; SI-NEXT:  .LBB7_5:
322;
323; GFX10-WAVE64-LABEL: test_kill_control_flow:
324; GFX10-WAVE64:       ; %bb.0: ; %entry
325; GFX10-WAVE64-NEXT:    s_cmp_lg_u32 s0, 0
326; GFX10-WAVE64-NEXT:    s_cbranch_scc0 .LBB7_2
327; GFX10-WAVE64-NEXT:  ; %bb.1: ; %exit
328; GFX10-WAVE64-NEXT:    v_mov_b32_e32 v0, 1.0
329; GFX10-WAVE64-NEXT:    s_branch .LBB7_5
330; GFX10-WAVE64-NEXT:  .LBB7_2: ; %bb
331; GFX10-WAVE64-NEXT:    ;;#ASMSTART
332; GFX10-WAVE64-NEXT:    v_mov_b32_e64 v7, -1
333; GFX10-WAVE64-NEXT:    v_nop_e64
334; GFX10-WAVE64-NEXT:    v_nop_e64
335; GFX10-WAVE64-NEXT:    v_nop_e64
336; GFX10-WAVE64-NEXT:    v_nop_e64
337; GFX10-WAVE64-NEXT:    v_nop_e64
338; GFX10-WAVE64-NEXT:    v_nop_e64
339; GFX10-WAVE64-NEXT:    v_nop_e64
340; GFX10-WAVE64-NEXT:    v_nop_e64
341; GFX10-WAVE64-NEXT:    v_nop_e64
342; GFX10-WAVE64-NEXT:    v_nop_e64
343; GFX10-WAVE64-NEXT:    ;;#ASMEND
344; GFX10-WAVE64-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v7
345; GFX10-WAVE64-NEXT:    s_mov_b64 s[2:3], exec
346; GFX10-WAVE64-NEXT:    s_andn2_b64 s[2:3], s[2:3], vcc
347; GFX10-WAVE64-NEXT:    s_cbranch_scc0 .LBB7_4
348; GFX10-WAVE64-NEXT:  ; %bb.3: ; %bb
349; GFX10-WAVE64-NEXT:    s_andn2_b64 exec, exec, vcc
350; GFX10-WAVE64-NEXT:    v_mov_b32_e32 v0, 1.0
351; GFX10-WAVE64-NEXT:    s_branch .LBB7_5
352; GFX10-WAVE64-NEXT:  .LBB7_4:
353; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
354; GFX10-WAVE64-NEXT:    exp null off, off, off, off done vm
355; GFX10-WAVE64-NEXT:    s_endpgm
356; GFX10-WAVE64-NEXT:  .LBB7_5:
357;
358; GFX10-WAVE32-LABEL: test_kill_control_flow:
359; GFX10-WAVE32:       ; %bb.0: ; %entry
360; GFX10-WAVE32-NEXT:    s_cmp_lg_u32 s0, 0
361; GFX10-WAVE32-NEXT:    s_cbranch_scc0 .LBB7_2
362; GFX10-WAVE32-NEXT:  ; %bb.1: ; %exit
363; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v0, 1.0
364; GFX10-WAVE32-NEXT:    s_branch .LBB7_5
365; GFX10-WAVE32-NEXT:  .LBB7_2: ; %bb
366; GFX10-WAVE32-NEXT:    ;;#ASMSTART
367; GFX10-WAVE32-NEXT:    v_mov_b32_e64 v7, -1
368; GFX10-WAVE32-NEXT:    v_nop_e64
369; GFX10-WAVE32-NEXT:    v_nop_e64
370; GFX10-WAVE32-NEXT:    v_nop_e64
371; GFX10-WAVE32-NEXT:    v_nop_e64
372; GFX10-WAVE32-NEXT:    v_nop_e64
373; GFX10-WAVE32-NEXT:    v_nop_e64
374; GFX10-WAVE32-NEXT:    v_nop_e64
375; GFX10-WAVE32-NEXT:    v_nop_e64
376; GFX10-WAVE32-NEXT:    v_nop_e64
377; GFX10-WAVE32-NEXT:    v_nop_e64
378; GFX10-WAVE32-NEXT:    ;;#ASMEND
379; GFX10-WAVE32-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, 0, v7
380; GFX10-WAVE32-NEXT:    s_mov_b32 s1, exec_lo
381; GFX10-WAVE32-NEXT:    s_andn2_b32 s1, s1, vcc_lo
382; GFX10-WAVE32-NEXT:    s_cbranch_scc0 .LBB7_4
383; GFX10-WAVE32-NEXT:  ; %bb.3: ; %bb
384; GFX10-WAVE32-NEXT:    s_andn2_b32 exec_lo, exec_lo, vcc_lo
385; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v0, 1.0
386; GFX10-WAVE32-NEXT:    s_branch .LBB7_5
387; GFX10-WAVE32-NEXT:  .LBB7_4:
388; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
389; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
390; GFX10-WAVE32-NEXT:    s_endpgm
391; GFX10-WAVE32-NEXT:  .LBB7_5:
392entry:
393  %cmp = icmp eq i32 %arg, 0
394  br i1 %cmp, label %bb, label %exit
395
396bb:
397  %var = call float asm sideeffect "v_mov_b32_e64 v7, -1
398    v_nop_e64
399    v_nop_e64
400    v_nop_e64
401    v_nop_e64
402    v_nop_e64
403    v_nop_e64
404    v_nop_e64
405    v_nop_e64
406    v_nop_e64
407    v_nop_e64", "={v7}"()
408  %cmp.var = fcmp olt float %var, 0.0
409  ; TODO: We could do an early-exit here (the branch above is uniform!)
410  call void @llvm.amdgcn.kill(i1 %cmp.var)
411  br label %exit
412
413exit:
414  ret float 1.0
415}
416
417define amdgpu_ps void @test_kill_control_flow_remainder(i32 inreg %arg) #0 {
418; SI-LABEL: test_kill_control_flow_remainder:
419; SI:       ; %bb.0: ; %entry
420; SI-NEXT:    s_cmp_lg_u32 s0, 0
421; SI-NEXT:    v_mov_b32_e32 v9, 0
422; SI-NEXT:    s_cbranch_scc1 .LBB8_3
423; SI-NEXT:  ; %bb.1: ; %bb
424; SI-NEXT:    s_mov_b64 s[2:3], exec
425; SI-NEXT:    ;;#ASMSTART
426; SI-NEXT:    v_mov_b32_e64 v7, -1
427; SI-NEXT:    v_nop_e64
428; SI-NEXT:    v_nop_e64
429; SI-NEXT:    v_nop_e64
430; SI-NEXT:    v_nop_e64
431; SI-NEXT:    v_nop_e64
432; SI-NEXT:    v_nop_e64
433; SI-NEXT:    v_nop_e64
434; SI-NEXT:    v_nop_e64
435; SI-NEXT:    v_nop_e64
436; SI-NEXT:    v_nop_e64
437; SI-NEXT:    v_nop_e64
438; SI-NEXT:    ;;#ASMEND
439; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v7
440; SI-NEXT:    s_andn2_b64 s[2:3], s[2:3], vcc
441; SI-NEXT:    ;;#ASMSTART
442; SI-NEXT:    v_mov_b32_e64 v8, -1
443; SI-NEXT:    ;;#ASMEND
444; SI-NEXT:    s_cbranch_scc0 .LBB8_4
445; SI-NEXT:  ; %bb.2: ; %bb
446; SI-NEXT:    s_andn2_b64 exec, exec, vcc
447; SI-NEXT:    s_mov_b32 s3, 0xf000
448; SI-NEXT:    s_mov_b32 s2, -1
449; SI-NEXT:    buffer_store_dword v8, off, s[0:3], 0
450; SI-NEXT:    s_waitcnt vmcnt(0)
451; SI-NEXT:    ;;#ASMSTART
452; SI-NEXT:    v_mov_b32_e64 v9, -2
453; SI-NEXT:    ;;#ASMEND
454; SI-NEXT:  .LBB8_3: ; %exit
455; SI-NEXT:    s_mov_b32 s3, 0xf000
456; SI-NEXT:    s_mov_b32 s2, -1
457; SI-NEXT:    buffer_store_dword v9, off, s[0:3], 0
458; SI-NEXT:    s_endpgm
459; SI-NEXT:  .LBB8_4:
460; SI-NEXT:    s_mov_b64 exec, 0
461; SI-NEXT:    exp null off, off, off, off done vm
462; SI-NEXT:    s_endpgm
463;
464; GFX10-WAVE64-LABEL: test_kill_control_flow_remainder:
465; GFX10-WAVE64:       ; %bb.0: ; %entry
466; GFX10-WAVE64-NEXT:    v_mov_b32_e32 v9, 0
467; GFX10-WAVE64-NEXT:    s_cmp_lg_u32 s0, 0
468; GFX10-WAVE64-NEXT:    s_cbranch_scc0 .LBB8_2
469; GFX10-WAVE64-NEXT:  ; %bb.1: ; %exit
470; GFX10-WAVE64-NEXT:    global_store_dword v[0:1], v9, off
471; GFX10-WAVE64-NEXT:    s_endpgm
472; GFX10-WAVE64-NEXT:  .LBB8_2: ; %bb
473; GFX10-WAVE64-NEXT:    ;;#ASMSTART
474; GFX10-WAVE64-NEXT:    v_mov_b32_e64 v7, -1
475; GFX10-WAVE64-NEXT:    v_nop_e64
476; GFX10-WAVE64-NEXT:    v_nop_e64
477; GFX10-WAVE64-NEXT:    v_nop_e64
478; GFX10-WAVE64-NEXT:    v_nop_e64
479; GFX10-WAVE64-NEXT:    v_nop_e64
480; GFX10-WAVE64-NEXT:    v_nop_e64
481; GFX10-WAVE64-NEXT:    v_nop_e64
482; GFX10-WAVE64-NEXT:    v_nop_e64
483; GFX10-WAVE64-NEXT:    v_nop_e64
484; GFX10-WAVE64-NEXT:    v_nop_e64
485; GFX10-WAVE64-NEXT:    v_nop_e64
486; GFX10-WAVE64-NEXT:    ;;#ASMEND
487; GFX10-WAVE64-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v7
488; GFX10-WAVE64-NEXT:    s_mov_b64 s[2:3], exec
489; GFX10-WAVE64-NEXT:    ;;#ASMSTART
490; GFX10-WAVE64-NEXT:    v_mov_b32_e64 v8, -1
491; GFX10-WAVE64-NEXT:    ;;#ASMEND
492; GFX10-WAVE64-NEXT:    s_andn2_b64 s[2:3], s[2:3], vcc
493; GFX10-WAVE64-NEXT:    s_cbranch_scc0 .LBB8_4
494; GFX10-WAVE64-NEXT:  ; %bb.3: ; %bb
495; GFX10-WAVE64-NEXT:    s_andn2_b64 exec, exec, vcc
496; GFX10-WAVE64-NEXT:    global_store_dword v[0:1], v8, off
497; GFX10-WAVE64-NEXT:    s_waitcnt_vscnt null, 0x0
498; GFX10-WAVE64-NEXT:    ;;#ASMSTART
499; GFX10-WAVE64-NEXT:    v_mov_b32_e64 v9, -2
500; GFX10-WAVE64-NEXT:    ;;#ASMEND
501; GFX10-WAVE64-NEXT:    global_store_dword v[0:1], v9, off
502; GFX10-WAVE64-NEXT:    s_endpgm
503; GFX10-WAVE64-NEXT:  .LBB8_4:
504; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
505; GFX10-WAVE64-NEXT:    exp null off, off, off, off done vm
506; GFX10-WAVE64-NEXT:    s_endpgm
507;
508; GFX10-WAVE32-LABEL: test_kill_control_flow_remainder:
509; GFX10-WAVE32:       ; %bb.0: ; %entry
510; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v9, 0
511; GFX10-WAVE32-NEXT:    s_cmp_lg_u32 s0, 0
512; GFX10-WAVE32-NEXT:    s_cbranch_scc0 .LBB8_2
513; GFX10-WAVE32-NEXT:  ; %bb.1: ; %exit
514; GFX10-WAVE32-NEXT:    global_store_dword v[0:1], v9, off
515; GFX10-WAVE32-NEXT:    s_endpgm
516; GFX10-WAVE32-NEXT:  .LBB8_2: ; %bb
517; GFX10-WAVE32-NEXT:    ;;#ASMSTART
518; GFX10-WAVE32-NEXT:    v_mov_b32_e64 v7, -1
519; GFX10-WAVE32-NEXT:    v_nop_e64
520; GFX10-WAVE32-NEXT:    v_nop_e64
521; GFX10-WAVE32-NEXT:    v_nop_e64
522; GFX10-WAVE32-NEXT:    v_nop_e64
523; GFX10-WAVE32-NEXT:    v_nop_e64
524; GFX10-WAVE32-NEXT:    v_nop_e64
525; GFX10-WAVE32-NEXT:    v_nop_e64
526; GFX10-WAVE32-NEXT:    v_nop_e64
527; GFX10-WAVE32-NEXT:    v_nop_e64
528; GFX10-WAVE32-NEXT:    v_nop_e64
529; GFX10-WAVE32-NEXT:    v_nop_e64
530; GFX10-WAVE32-NEXT:    ;;#ASMEND
531; GFX10-WAVE32-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, 0, v7
532; GFX10-WAVE32-NEXT:    s_mov_b32 s1, exec_lo
533; GFX10-WAVE32-NEXT:    ;;#ASMSTART
534; GFX10-WAVE32-NEXT:    v_mov_b32_e64 v8, -1
535; GFX10-WAVE32-NEXT:    ;;#ASMEND
536; GFX10-WAVE32-NEXT:    s_andn2_b32 s1, s1, vcc_lo
537; GFX10-WAVE32-NEXT:    s_cbranch_scc0 .LBB8_4
538; GFX10-WAVE32-NEXT:  ; %bb.3: ; %bb
539; GFX10-WAVE32-NEXT:    s_andn2_b32 exec_lo, exec_lo, vcc_lo
540; GFX10-WAVE32-NEXT:    global_store_dword v[0:1], v8, off
541; GFX10-WAVE32-NEXT:    s_waitcnt_vscnt null, 0x0
542; GFX10-WAVE32-NEXT:    ;;#ASMSTART
543; GFX10-WAVE32-NEXT:    v_mov_b32_e64 v9, -2
544; GFX10-WAVE32-NEXT:    ;;#ASMEND
545; GFX10-WAVE32-NEXT:    global_store_dword v[0:1], v9, off
546; GFX10-WAVE32-NEXT:    s_endpgm
547; GFX10-WAVE32-NEXT:  .LBB8_4:
548; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
549; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
550; GFX10-WAVE32-NEXT:    s_endpgm
551entry:
552  %cmp = icmp eq i32 %arg, 0
553  br i1 %cmp, label %bb, label %exit
554
555bb:
556  %var = call float asm sideeffect "v_mov_b32_e64 v7, -1
557    v_nop_e64
558    v_nop_e64
559    v_nop_e64
560    v_nop_e64
561    v_nop_e64
562    v_nop_e64
563    v_nop_e64
564    v_nop_e64
565    v_nop_e64
566    v_nop_e64
567    v_nop_e64", "={v7}"()
568  %live.across = call float asm sideeffect "v_mov_b32_e64 v8, -1", "={v8}"()
569  %cmp.var = fcmp olt float %var, 0.0
570  ; TODO: We could do an early-exit here (the branch above is uniform!)
571  call void @llvm.amdgcn.kill(i1 %cmp.var)
572  store volatile float %live.across, float addrspace(1)* undef
573  %live.out = call float asm sideeffect "v_mov_b32_e64 v9, -2", "={v9}"()
574  br label %exit
575
576exit:
577  %phi = phi float [ 0.0, %entry ], [ %live.out, %bb ]
578  store float %phi, float addrspace(1)* undef
579  ret void
580}
581
582define amdgpu_ps float @test_kill_control_flow_return(i32 inreg %arg) #0 {
583; SI-LABEL: test_kill_control_flow_return:
584; SI:       ; %bb.0: ; %entry
585; SI-NEXT:    s_cmp_eq_u32 s0, 1
586; SI-NEXT:    s_cselect_b64 s[4:5], -1, 0
587; SI-NEXT:    s_mov_b64 s[2:3], exec
588; SI-NEXT:    s_xor_b64 s[4:5], s[4:5], exec
589; SI-NEXT:    s_andn2_b64 s[2:3], s[2:3], s[4:5]
590; SI-NEXT:    s_cbranch_scc0 .LBB9_4
591; SI-NEXT:  ; %bb.1: ; %entry
592; SI-NEXT:    s_and_b64 exec, exec, s[2:3]
593; SI-NEXT:    s_cmp_lg_u32 s0, 0
594; SI-NEXT:    v_mov_b32_e32 v0, 0
595; SI-NEXT:    s_cbranch_scc0 .LBB9_3
596; SI-NEXT:  ; %bb.2: ; %exit
597; SI-NEXT:    s_branch .LBB9_5
598; SI-NEXT:  .LBB9_3: ; %bb
599; SI-NEXT:    ;;#ASMSTART
600; SI-NEXT:    v_mov_b32_e64 v7, -1
601; SI-NEXT:    v_nop_e64
602; SI-NEXT:    v_nop_e64
603; SI-NEXT:    v_nop_e64
604; SI-NEXT:    v_nop_e64
605; SI-NEXT:    v_nop_e64
606; SI-NEXT:    v_nop_e64
607; SI-NEXT:    v_nop_e64
608; SI-NEXT:    v_nop_e64
609; SI-NEXT:    v_nop_e64
610; SI-NEXT:    v_nop_e64
611; SI-NEXT:    ;;#ASMEND
612; SI-NEXT:    v_mov_b32_e32 v0, v7
613; SI-NEXT:    s_branch .LBB9_5
614; SI-NEXT:  .LBB9_4:
615; SI-NEXT:    s_mov_b64 exec, 0
616; SI-NEXT:    exp null off, off, off, off done vm
617; SI-NEXT:    s_endpgm
618; SI-NEXT:  .LBB9_5:
619;
620; GFX10-WAVE64-LABEL: test_kill_control_flow_return:
621; GFX10-WAVE64:       ; %bb.0: ; %entry
622; GFX10-WAVE64-NEXT:    s_cmp_eq_u32 s0, 1
623; GFX10-WAVE64-NEXT:    s_mov_b64 s[2:3], exec
624; GFX10-WAVE64-NEXT:    s_cselect_b64 s[4:5], -1, 0
625; GFX10-WAVE64-NEXT:    s_xor_b64 s[4:5], s[4:5], exec
626; GFX10-WAVE64-NEXT:    s_andn2_b64 s[2:3], s[2:3], s[4:5]
627; GFX10-WAVE64-NEXT:    s_cbranch_scc0 .LBB9_4
628; GFX10-WAVE64-NEXT:  ; %bb.1: ; %entry
629; GFX10-WAVE64-NEXT:    s_and_b64 exec, exec, s[2:3]
630; GFX10-WAVE64-NEXT:    v_mov_b32_e32 v0, 0
631; GFX10-WAVE64-NEXT:    s_cmp_lg_u32 s0, 0
632; GFX10-WAVE64-NEXT:    s_cbranch_scc0 .LBB9_3
633; GFX10-WAVE64-NEXT:  ; %bb.2: ; %exit
634; GFX10-WAVE64-NEXT:    s_branch .LBB9_5
635; GFX10-WAVE64-NEXT:  .LBB9_3: ; %bb
636; GFX10-WAVE64-NEXT:    ;;#ASMSTART
637; GFX10-WAVE64-NEXT:    v_mov_b32_e64 v7, -1
638; GFX10-WAVE64-NEXT:    v_nop_e64
639; GFX10-WAVE64-NEXT:    v_nop_e64
640; GFX10-WAVE64-NEXT:    v_nop_e64
641; GFX10-WAVE64-NEXT:    v_nop_e64
642; GFX10-WAVE64-NEXT:    v_nop_e64
643; GFX10-WAVE64-NEXT:    v_nop_e64
644; GFX10-WAVE64-NEXT:    v_nop_e64
645; GFX10-WAVE64-NEXT:    v_nop_e64
646; GFX10-WAVE64-NEXT:    v_nop_e64
647; GFX10-WAVE64-NEXT:    v_nop_e64
648; GFX10-WAVE64-NEXT:    ;;#ASMEND
649; GFX10-WAVE64-NEXT:    v_mov_b32_e32 v0, v7
650; GFX10-WAVE64-NEXT:    s_branch .LBB9_5
651; GFX10-WAVE64-NEXT:  .LBB9_4:
652; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
653; GFX10-WAVE64-NEXT:    exp null off, off, off, off done vm
654; GFX10-WAVE64-NEXT:    s_endpgm
655; GFX10-WAVE64-NEXT:  .LBB9_5:
656;
657; GFX10-WAVE32-LABEL: test_kill_control_flow_return:
658; GFX10-WAVE32:       ; %bb.0: ; %entry
659; GFX10-WAVE32-NEXT:    s_cmp_eq_u32 s0, 1
660; GFX10-WAVE32-NEXT:    s_mov_b32 s1, exec_lo
661; GFX10-WAVE32-NEXT:    s_cselect_b32 s2, -1, 0
662; GFX10-WAVE32-NEXT:    s_xor_b32 s2, s2, exec_lo
663; GFX10-WAVE32-NEXT:    s_andn2_b32 s1, s1, s2
664; GFX10-WAVE32-NEXT:    s_cbranch_scc0 .LBB9_4
665; GFX10-WAVE32-NEXT:  ; %bb.1: ; %entry
666; GFX10-WAVE32-NEXT:    s_and_b32 exec_lo, exec_lo, s1
667; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v0, 0
668; GFX10-WAVE32-NEXT:    s_cmp_lg_u32 s0, 0
669; GFX10-WAVE32-NEXT:    s_cbranch_scc0 .LBB9_3
670; GFX10-WAVE32-NEXT:  ; %bb.2: ; %exit
671; GFX10-WAVE32-NEXT:    s_branch .LBB9_5
672; GFX10-WAVE32-NEXT:  .LBB9_3: ; %bb
673; GFX10-WAVE32-NEXT:    ;;#ASMSTART
674; GFX10-WAVE32-NEXT:    v_mov_b32_e64 v7, -1
675; GFX10-WAVE32-NEXT:    v_nop_e64
676; GFX10-WAVE32-NEXT:    v_nop_e64
677; GFX10-WAVE32-NEXT:    v_nop_e64
678; GFX10-WAVE32-NEXT:    v_nop_e64
679; GFX10-WAVE32-NEXT:    v_nop_e64
680; GFX10-WAVE32-NEXT:    v_nop_e64
681; GFX10-WAVE32-NEXT:    v_nop_e64
682; GFX10-WAVE32-NEXT:    v_nop_e64
683; GFX10-WAVE32-NEXT:    v_nop_e64
684; GFX10-WAVE32-NEXT:    v_nop_e64
685; GFX10-WAVE32-NEXT:    ;;#ASMEND
686; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v0, v7
687; GFX10-WAVE32-NEXT:    s_branch .LBB9_5
688; GFX10-WAVE32-NEXT:  .LBB9_4:
689; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
690; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
691; GFX10-WAVE32-NEXT:    s_endpgm
692; GFX10-WAVE32-NEXT:  .LBB9_5:
693entry:
694  %kill = icmp eq i32 %arg, 1
695  %cmp = icmp eq i32 %arg, 0
696  call void @llvm.amdgcn.kill(i1 %kill)
697  br i1 %cmp, label %bb, label %exit
698
699bb:
700  %var = call float asm sideeffect "v_mov_b32_e64 v7, -1
701    v_nop_e64
702    v_nop_e64
703    v_nop_e64
704    v_nop_e64
705    v_nop_e64
706    v_nop_e64
707    v_nop_e64
708    v_nop_e64
709    v_nop_e64
710    v_nop_e64", "={v7}"()
711  br label %exit
712
713exit:
714  %ret = phi float [ %var, %bb ], [ 0.0, %entry ]
715  ret float %ret
716}
717
718define amdgpu_ps void @test_kill_divergent_loop(i32 %arg) #0 {
719; SI-LABEL: test_kill_divergent_loop:
720; SI:       ; %bb.0: ; %entry
721; SI-NEXT:    s_mov_b64 s[0:1], exec
722; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
723; SI-NEXT:    s_and_saveexec_b64 s[2:3], vcc
724; SI-NEXT:    s_xor_b64 s[4:5], exec, s[2:3]
725; SI-NEXT:    s_cbranch_execz .LBB10_4
726; SI-NEXT:  ; %bb.1: ; %bb.preheader
727; SI-NEXT:    s_mov_b32 s3, 0xf000
728; SI-NEXT:    s_mov_b32 s2, -1
729; SI-NEXT:  .LBB10_2: ; %bb
730; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
731; SI-NEXT:    ;;#ASMSTART
732; SI-NEXT:    v_mov_b32_e64 v7, -1
733; SI-NEXT:    v_nop_e64
734; SI-NEXT:    v_nop_e64
735; SI-NEXT:    v_nop_e64
736; SI-NEXT:    v_nop_e64
737; SI-NEXT:    v_nop_e64
738; SI-NEXT:    v_nop_e64
739; SI-NEXT:    v_nop_e64
740; SI-NEXT:    v_nop_e64
741; SI-NEXT:    v_nop_e64
742; SI-NEXT:    v_nop_e64
743; SI-NEXT:    ;;#ASMEND
744; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v7
745; SI-NEXT:    s_andn2_b64 s[0:1], s[0:1], vcc
746; SI-NEXT:    s_cbranch_scc0 .LBB10_5
747; SI-NEXT:  ; %bb.3: ; %bb
748; SI-NEXT:    ; in Loop: Header=BB10_2 Depth=1
749; SI-NEXT:    s_andn2_b64 exec, exec, vcc
750; SI-NEXT:    buffer_load_dword v0, off, s[0:3], 0 glc
751; SI-NEXT:    s_waitcnt vmcnt(0)
752; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
753; SI-NEXT:    s_cbranch_vccnz .LBB10_2
754; SI-NEXT:  .LBB10_4: ; %Flow1
755; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
756; SI-NEXT:    s_mov_b32 s3, 0xf000
757; SI-NEXT:    s_mov_b32 s2, -1
758; SI-NEXT:    v_mov_b32_e32 v0, 8
759; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
760; SI-NEXT:    s_waitcnt vmcnt(0)
761; SI-NEXT:    s_endpgm
762; SI-NEXT:  .LBB10_5:
763; SI-NEXT:    s_mov_b64 exec, 0
764; SI-NEXT:    exp null off, off, off, off done vm
765; SI-NEXT:    s_endpgm
766;
767; GFX10-WAVE64-LABEL: test_kill_divergent_loop:
768; GFX10-WAVE64:       ; %bb.0: ; %entry
769; GFX10-WAVE64-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
770; GFX10-WAVE64-NEXT:    s_mov_b64 s[0:1], exec
771; GFX10-WAVE64-NEXT:    s_and_saveexec_b64 s[2:3], vcc
772; GFX10-WAVE64-NEXT:    s_xor_b64 s[2:3], exec, s[2:3]
773; GFX10-WAVE64-NEXT:    s_cbranch_execz .LBB10_3
774; GFX10-WAVE64-NEXT:  .LBB10_1: ; %bb
775; GFX10-WAVE64-NEXT:    ; =>This Inner Loop Header: Depth=1
776; GFX10-WAVE64-NEXT:    ;;#ASMSTART
777; GFX10-WAVE64-NEXT:    v_mov_b32_e64 v7, -1
778; GFX10-WAVE64-NEXT:    v_nop_e64
779; GFX10-WAVE64-NEXT:    v_nop_e64
780; GFX10-WAVE64-NEXT:    v_nop_e64
781; GFX10-WAVE64-NEXT:    v_nop_e64
782; GFX10-WAVE64-NEXT:    v_nop_e64
783; GFX10-WAVE64-NEXT:    v_nop_e64
784; GFX10-WAVE64-NEXT:    v_nop_e64
785; GFX10-WAVE64-NEXT:    v_nop_e64
786; GFX10-WAVE64-NEXT:    v_nop_e64
787; GFX10-WAVE64-NEXT:    v_nop_e64
788; GFX10-WAVE64-NEXT:    ;;#ASMEND
789; GFX10-WAVE64-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v7
790; GFX10-WAVE64-NEXT:    s_andn2_b64 s[0:1], s[0:1], vcc
791; GFX10-WAVE64-NEXT:    s_cbranch_scc0 .LBB10_4
792; GFX10-WAVE64-NEXT:  ; %bb.2: ; %bb
793; GFX10-WAVE64-NEXT:    ; in Loop: Header=BB10_1 Depth=1
794; GFX10-WAVE64-NEXT:    s_andn2_b64 exec, exec, vcc
795; GFX10-WAVE64-NEXT:    global_load_dword v0, v[0:1], off glc dlc
796; GFX10-WAVE64-NEXT:    s_waitcnt vmcnt(0)
797; GFX10-WAVE64-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
798; GFX10-WAVE64-NEXT:    s_cbranch_vccnz .LBB10_1
799; GFX10-WAVE64-NEXT:  .LBB10_3: ; %Flow1
800; GFX10-WAVE64-NEXT:    s_or_b64 exec, exec, s[2:3]
801; GFX10-WAVE64-NEXT:    v_mov_b32_e32 v0, 8
802; GFX10-WAVE64-NEXT:    global_store_dword v[0:1], v0, off
803; GFX10-WAVE64-NEXT:    s_waitcnt_vscnt null, 0x0
804; GFX10-WAVE64-NEXT:    s_endpgm
805; GFX10-WAVE64-NEXT:  .LBB10_4:
806; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
807; GFX10-WAVE64-NEXT:    exp null off, off, off, off done vm
808; GFX10-WAVE64-NEXT:    s_endpgm
809;
810; GFX10-WAVE32-LABEL: test_kill_divergent_loop:
811; GFX10-WAVE32:       ; %bb.0: ; %entry
812; GFX10-WAVE32-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
813; GFX10-WAVE32-NEXT:    s_mov_b32 s0, exec_lo
814; GFX10-WAVE32-NEXT:    s_and_saveexec_b32 s1, vcc_lo
815; GFX10-WAVE32-NEXT:    s_xor_b32 s1, exec_lo, s1
816; GFX10-WAVE32-NEXT:    s_cbranch_execz .LBB10_3
817; GFX10-WAVE32-NEXT:  .LBB10_1: ; %bb
818; GFX10-WAVE32-NEXT:    ; =>This Inner Loop Header: Depth=1
819; GFX10-WAVE32-NEXT:    ;;#ASMSTART
820; GFX10-WAVE32-NEXT:    v_mov_b32_e64 v7, -1
821; GFX10-WAVE32-NEXT:    v_nop_e64
822; GFX10-WAVE32-NEXT:    v_nop_e64
823; GFX10-WAVE32-NEXT:    v_nop_e64
824; GFX10-WAVE32-NEXT:    v_nop_e64
825; GFX10-WAVE32-NEXT:    v_nop_e64
826; GFX10-WAVE32-NEXT:    v_nop_e64
827; GFX10-WAVE32-NEXT:    v_nop_e64
828; GFX10-WAVE32-NEXT:    v_nop_e64
829; GFX10-WAVE32-NEXT:    v_nop_e64
830; GFX10-WAVE32-NEXT:    v_nop_e64
831; GFX10-WAVE32-NEXT:    ;;#ASMEND
832; GFX10-WAVE32-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, 0, v7
833; GFX10-WAVE32-NEXT:    s_andn2_b32 s0, s0, vcc_lo
834; GFX10-WAVE32-NEXT:    s_cbranch_scc0 .LBB10_4
835; GFX10-WAVE32-NEXT:  ; %bb.2: ; %bb
836; GFX10-WAVE32-NEXT:    ; in Loop: Header=BB10_1 Depth=1
837; GFX10-WAVE32-NEXT:    s_andn2_b32 exec_lo, exec_lo, vcc_lo
838; GFX10-WAVE32-NEXT:    global_load_dword v0, v[0:1], off glc dlc
839; GFX10-WAVE32-NEXT:    s_waitcnt vmcnt(0)
840; GFX10-WAVE32-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
841; GFX10-WAVE32-NEXT:    s_cbranch_vccnz .LBB10_1
842; GFX10-WAVE32-NEXT:  .LBB10_3: ; %Flow1
843; GFX10-WAVE32-NEXT:    s_or_b32 exec_lo, exec_lo, s1
844; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v0, 8
845; GFX10-WAVE32-NEXT:    global_store_dword v[0:1], v0, off
846; GFX10-WAVE32-NEXT:    s_waitcnt_vscnt null, 0x0
847; GFX10-WAVE32-NEXT:    s_endpgm
848; GFX10-WAVE32-NEXT:  .LBB10_4:
849; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
850; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
851; GFX10-WAVE32-NEXT:    s_endpgm
852entry:
853  %cmp = icmp eq i32 %arg, 0
854  br i1 %cmp, label %bb, label %exit
855
856bb:
857  %var = call float asm sideeffect "v_mov_b32_e64 v7, -1
858    v_nop_e64
859    v_nop_e64
860    v_nop_e64
861    v_nop_e64
862    v_nop_e64
863    v_nop_e64
864    v_nop_e64
865    v_nop_e64
866    v_nop_e64
867    v_nop_e64", "={v7}"()
868  %cmp.var = fcmp olt float %var, 0.0
869  call void @llvm.amdgcn.kill(i1 %cmp.var)
870  %vgpr = load volatile i32, i32 addrspace(1)* undef
871  %loop.cond = icmp eq i32 %vgpr, 0
872  br i1 %loop.cond, label %bb, label %exit
873
874exit:
875  store volatile i32 8, i32 addrspace(1)* undef
876  ret void
877}
878
879; bug 28550
880define amdgpu_ps void @phi_use_def_before_kill(float inreg %x) #0 {
881; SI-LABEL: phi_use_def_before_kill:
882; SI:       ; %bb.0: ; %bb
883; SI-NEXT:    v_add_f32_e64 v1, s0, 1.0
884; SI-NEXT:    v_cmp_lt_f32_e32 vcc, 0, v1
885; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1.0, vcc
886; SI-NEXT:    v_cmp_nlt_f32_e32 vcc, 0, v1
887; SI-NEXT:    s_andn2_b64 exec, exec, vcc
888; SI-NEXT:    s_cbranch_scc0 .LBB11_6
889; SI-NEXT:  ; %bb.1: ; %bb
890; SI-NEXT:    s_andn2_b64 exec, exec, vcc
891; SI-NEXT:    s_cbranch_scc0 .LBB11_3
892; SI-NEXT:  ; %bb.2: ; %bb8
893; SI-NEXT:    s_mov_b32 s3, 0xf000
894; SI-NEXT:    s_mov_b32 s2, -1
895; SI-NEXT:    v_mov_b32_e32 v0, 8
896; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
897; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
898; SI-NEXT:    v_mov_b32_e32 v0, 4.0
899; SI-NEXT:  .LBB11_3: ; %phibb
900; SI-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v0
901; SI-NEXT:    s_cbranch_vccz .LBB11_5
902; SI-NEXT:  ; %bb.4: ; %bb10
903; SI-NEXT:    s_mov_b32 s3, 0xf000
904; SI-NEXT:    s_mov_b32 s2, -1
905; SI-NEXT:    v_mov_b32_e32 v0, 9
906; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
907; SI-NEXT:    s_waitcnt vmcnt(0)
908; SI-NEXT:  .LBB11_5: ; %end
909; SI-NEXT:    s_endpgm
910; SI-NEXT:  .LBB11_6:
911; SI-NEXT:    s_mov_b64 exec, 0
912; SI-NEXT:    exp null off, off, off, off done vm
913; SI-NEXT:    s_endpgm
914;
915; GFX10-WAVE64-LABEL: phi_use_def_before_kill:
916; GFX10-WAVE64:       ; %bb.0: ; %bb
917; GFX10-WAVE64-NEXT:    v_add_f32_e64 v1, s0, 1.0
918; GFX10-WAVE64-NEXT:    v_cmp_lt_f32_e32 vcc, 0, v1
919; GFX10-WAVE64-NEXT:    v_cndmask_b32_e64 v0, 0, -1.0, vcc
920; GFX10-WAVE64-NEXT:    v_cmp_nlt_f32_e32 vcc, 0, v1
921; GFX10-WAVE64-NEXT:    s_andn2_b64 exec, exec, vcc
922; GFX10-WAVE64-NEXT:    s_cbranch_scc0 .LBB11_6
923; GFX10-WAVE64-NEXT:  ; %bb.1: ; %bb
924; GFX10-WAVE64-NEXT:    s_andn2_b64 exec, exec, vcc
925; GFX10-WAVE64-NEXT:    s_cbranch_scc0 .LBB11_3
926; GFX10-WAVE64-NEXT:  ; %bb.2: ; %bb8
927; GFX10-WAVE64-NEXT:    v_mov_b32_e32 v1, 8
928; GFX10-WAVE64-NEXT:    v_mov_b32_e32 v0, 4.0
929; GFX10-WAVE64-NEXT:    global_store_dword v[0:1], v1, off
930; GFX10-WAVE64-NEXT:    s_waitcnt_vscnt null, 0x0
931; GFX10-WAVE64-NEXT:  .LBB11_3: ; %phibb
932; GFX10-WAVE64-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v0
933; GFX10-WAVE64-NEXT:    s_cbranch_vccz .LBB11_5
934; GFX10-WAVE64-NEXT:  ; %bb.4: ; %bb10
935; GFX10-WAVE64-NEXT:    v_mov_b32_e32 v0, 9
936; GFX10-WAVE64-NEXT:    global_store_dword v[0:1], v0, off
937; GFX10-WAVE64-NEXT:    s_waitcnt_vscnt null, 0x0
938; GFX10-WAVE64-NEXT:  .LBB11_5: ; %end
939; GFX10-WAVE64-NEXT:    s_endpgm
940; GFX10-WAVE64-NEXT:  .LBB11_6:
941; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
942; GFX10-WAVE64-NEXT:    exp null off, off, off, off done vm
943; GFX10-WAVE64-NEXT:    s_endpgm
944;
945; GFX10-WAVE32-LABEL: phi_use_def_before_kill:
946; GFX10-WAVE32:       ; %bb.0: ; %bb
947; GFX10-WAVE32-NEXT:    v_add_f32_e64 v1, s0, 1.0
948; GFX10-WAVE32-NEXT:    v_cmp_lt_f32_e32 vcc_lo, 0, v1
949; GFX10-WAVE32-NEXT:    v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
950; GFX10-WAVE32-NEXT:    v_cmp_nlt_f32_e32 vcc_lo, 0, v1
951; GFX10-WAVE32-NEXT:    s_andn2_b32 exec_lo, exec_lo, vcc_lo
952; GFX10-WAVE32-NEXT:    s_cbranch_scc0 .LBB11_6
953; GFX10-WAVE32-NEXT:  ; %bb.1: ; %bb
954; GFX10-WAVE32-NEXT:    s_andn2_b32 exec_lo, exec_lo, vcc_lo
955; GFX10-WAVE32-NEXT:    s_cbranch_scc0 .LBB11_3
956; GFX10-WAVE32-NEXT:  ; %bb.2: ; %bb8
957; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v1, 8
958; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v0, 4.0
959; GFX10-WAVE32-NEXT:    global_store_dword v[0:1], v1, off
960; GFX10-WAVE32-NEXT:    s_waitcnt_vscnt null, 0x0
961; GFX10-WAVE32-NEXT:  .LBB11_3: ; %phibb
962; GFX10-WAVE32-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v0
963; GFX10-WAVE32-NEXT:    s_cbranch_vccz .LBB11_5
964; GFX10-WAVE32-NEXT:  ; %bb.4: ; %bb10
965; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v0, 9
966; GFX10-WAVE32-NEXT:    global_store_dword v[0:1], v0, off
967; GFX10-WAVE32-NEXT:    s_waitcnt_vscnt null, 0x0
968; GFX10-WAVE32-NEXT:  .LBB11_5: ; %end
969; GFX10-WAVE32-NEXT:    s_endpgm
970; GFX10-WAVE32-NEXT:  .LBB11_6:
971; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
972; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
973; GFX10-WAVE32-NEXT:    s_endpgm
974bb:
975  %tmp = fadd float %x, 1.000000e+00
976  %tmp1 = fcmp olt float 0.000000e+00, %tmp
977  %tmp2 = select i1 %tmp1, float -1.000000e+00, float 0.000000e+00
978  %cmp.tmp2 = fcmp olt float %tmp2, 0.0
979  call void @llvm.amdgcn.kill(i1 %cmp.tmp2)
980  br i1 undef, label %phibb, label %bb8
981
982phibb:
983  %tmp5 = phi float [ %tmp2, %bb ], [ 4.0, %bb8 ]
984  %tmp6 = fcmp oeq float %tmp5, 0.000000e+00
985  br i1 %tmp6, label %bb10, label %end
986
987bb8:
988  store volatile i32 8, i32 addrspace(1)* undef
989  br label %phibb
990
991bb10:
992  store volatile i32 9, i32 addrspace(1)* undef
993  br label %end
994
995end:
996  ret void
997}
998
999define amdgpu_ps void @no_skip_no_successors(float inreg %arg, float inreg %arg1) #0 {
1000; SI-LABEL: no_skip_no_successors:
1001; SI:       ; %bb.0: ; %bb
1002; SI-NEXT:    v_cmp_nge_f32_e64 s[4:5], s1, 0
1003; SI-NEXT:    s_and_b64 vcc, exec, s[4:5]
1004; SI-NEXT:    s_cbranch_vccz .LBB12_3
1005; SI-NEXT:  ; %bb.1: ; %bb6
1006; SI-NEXT:    s_mov_b64 s[2:3], exec
1007; SI-NEXT:    s_andn2_b64 s[2:3], s[2:3], exec
1008; SI-NEXT:    s_cbranch_scc0 .LBB12_5
1009; SI-NEXT:  ; %bb.2: ; %bb6
1010; SI-NEXT:    s_mov_b64 exec, 0
1011; SI-NEXT:  .LBB12_3: ; %bb3
1012; SI-NEXT:    v_mov_b32_e32 v0, 0x3e7ae148
1013; SI-NEXT:    v_cmp_nge_f32_e32 vcc, s0, v0
1014; SI-NEXT:    s_and_b64 vcc, exec, vcc
1015; SI-NEXT:  ; %bb.4: ; %bb5
1016; SI-NEXT:  .LBB12_5:
1017; SI-NEXT:    s_mov_b64 exec, 0
1018; SI-NEXT:    exp null off, off, off, off done vm
1019; SI-NEXT:    s_endpgm
1020;
1021; GFX10-WAVE64-LABEL: no_skip_no_successors:
1022; GFX10-WAVE64:       ; %bb.0: ; %bb
1023; GFX10-WAVE64-NEXT:    v_cmp_nge_f32_e64 s[4:5], s1, 0
1024; GFX10-WAVE64-NEXT:    s_and_b64 vcc, exec, s[4:5]
1025; GFX10-WAVE64-NEXT:    s_cbranch_vccz .LBB12_3
1026; GFX10-WAVE64-NEXT:  ; %bb.1: ; %bb6
1027; GFX10-WAVE64-NEXT:    s_mov_b64 s[2:3], exec
1028; GFX10-WAVE64-NEXT:    s_andn2_b64 s[2:3], s[2:3], exec
1029; GFX10-WAVE64-NEXT:    s_cbranch_scc0 .LBB12_5
1030; GFX10-WAVE64-NEXT:  ; %bb.2: ; %bb6
1031; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
1032; GFX10-WAVE64-NEXT:  .LBB12_3: ; %bb3
1033; GFX10-WAVE64-NEXT:    v_cmp_nle_f32_e64 s[0:1], 0x3e7ae148, s0
1034; GFX10-WAVE64-NEXT:    s_and_b64 vcc, exec, s[0:1]
1035; GFX10-WAVE64-NEXT:  ; %bb.4: ; %bb5
1036; GFX10-WAVE64-NEXT:  .LBB12_5:
1037; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
1038; GFX10-WAVE64-NEXT:    exp null off, off, off, off done vm
1039; GFX10-WAVE64-NEXT:    s_endpgm
1040;
1041; GFX10-WAVE32-LABEL: no_skip_no_successors:
1042; GFX10-WAVE32:       ; %bb.0: ; %bb
1043; GFX10-WAVE32-NEXT:    v_cmp_nge_f32_e64 s1, s1, 0
1044; GFX10-WAVE32-NEXT:    s_and_b32 vcc_lo, exec_lo, s1
1045; GFX10-WAVE32-NEXT:    s_cbranch_vccz .LBB12_3
1046; GFX10-WAVE32-NEXT:  ; %bb.1: ; %bb6
1047; GFX10-WAVE32-NEXT:    s_mov_b32 s2, exec_lo
1048; GFX10-WAVE32-NEXT:    s_andn2_b32 s2, s2, exec_lo
1049; GFX10-WAVE32-NEXT:    s_cbranch_scc0 .LBB12_5
1050; GFX10-WAVE32-NEXT:  ; %bb.2: ; %bb6
1051; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
1052; GFX10-WAVE32-NEXT:  .LBB12_3: ; %bb3
1053; GFX10-WAVE32-NEXT:    v_cmp_nle_f32_e64 s0, 0x3e7ae148, s0
1054; GFX10-WAVE32-NEXT:    s_and_b32 vcc_lo, exec_lo, s0
1055; GFX10-WAVE32-NEXT:  ; %bb.4: ; %bb5
1056; GFX10-WAVE32-NEXT:  .LBB12_5:
1057; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
1058; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
1059; GFX10-WAVE32-NEXT:    s_endpgm
1060bb:
1061  %tmp = fcmp ult float %arg1, 0.000000e+00
1062  %tmp2 = fcmp ult float %arg, 0x3FCF5C2900000000
1063  br i1 %tmp, label %bb6, label %bb3
1064
1065bb3:                                              ; preds = %bb
1066  br i1 %tmp2, label %bb5, label %bb4
1067
1068bb4:                                              ; preds = %bb3
1069  br i1 true, label %bb5, label %bb7
1070
1071bb5:                                              ; preds = %bb4, %bb3
1072  unreachable
1073
1074bb6:                                              ; preds = %bb
1075  call void @llvm.amdgcn.kill(i1 false)
1076  unreachable
1077
1078bb7:                                              ; preds = %bb4
1079  ret void
1080}
1081
1082define amdgpu_ps void @if_after_kill_block(float %arg, float %arg1, float %arg2, float %arg3) #0 {
1083; SI-LABEL: if_after_kill_block:
1084; SI:       ; %bb.0: ; %bb
1085; SI-NEXT:    s_mov_b64 s[2:3], exec
1086; SI-NEXT:    s_wqm_b64 exec, exec
1087; SI-NEXT:    s_mov_b32 s0, 0
1088; SI-NEXT:    v_cmp_nle_f32_e32 vcc, 0, v1
1089; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1090; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
1091; SI-NEXT:    s_cbranch_execz .LBB13_3
1092; SI-NEXT:  ; %bb.1: ; %bb3
1093; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v0
1094; SI-NEXT:    s_andn2_b64 s[2:3], s[2:3], vcc
1095; SI-NEXT:    s_cbranch_scc0 .LBB13_6
1096; SI-NEXT:  ; %bb.2: ; %bb3
1097; SI-NEXT:    s_andn2_b64 exec, exec, vcc
1098; SI-NEXT:  .LBB13_3: ; %bb4
1099; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
1100; SI-NEXT:    s_mov_b32 s1, s0
1101; SI-NEXT:    s_mov_b32 s2, s0
1102; SI-NEXT:    s_mov_b32 s3, s0
1103; SI-NEXT:    s_mov_b32 s4, s0
1104; SI-NEXT:    s_mov_b32 s5, s0
1105; SI-NEXT:    s_mov_b32 s6, s0
1106; SI-NEXT:    s_mov_b32 s7, s0
1107; SI-NEXT:    image_sample_c v0, v[2:3], s[0:7], s[0:3] dmask:0x10
1108; SI-NEXT:    s_waitcnt vmcnt(0)
1109; SI-NEXT:    v_cmp_neq_f32_e32 vcc, 0, v0
1110; SI-NEXT:    s_and_saveexec_b64 s[0:1], vcc
1111; SI-NEXT:    s_cbranch_execz .LBB13_5
1112; SI-NEXT:  ; %bb.4: ; %bb8
1113; SI-NEXT:    s_mov_b32 s3, 0xf000
1114; SI-NEXT:    s_mov_b32 s2, -1
1115; SI-NEXT:    v_mov_b32_e32 v0, 9
1116; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
1117; SI-NEXT:    s_waitcnt vmcnt(0)
1118; SI-NEXT:  .LBB13_5: ; %UnifiedReturnBlock
1119; SI-NEXT:    s_endpgm
1120; SI-NEXT:  .LBB13_6:
1121; SI-NEXT:    s_mov_b64 exec, 0
1122; SI-NEXT:    exp null off, off, off, off done vm
1123; SI-NEXT:    s_endpgm
1124;
1125; GFX10-WAVE64-LABEL: if_after_kill_block:
1126; GFX10-WAVE64:       ; %bb.0: ; %bb
1127; GFX10-WAVE64-NEXT:    s_mov_b64 s[2:3], exec
1128; GFX10-WAVE64-NEXT:    s_wqm_b64 exec, exec
1129; GFX10-WAVE64-NEXT:    v_cmp_nle_f32_e32 vcc, 0, v1
1130; GFX10-WAVE64-NEXT:    s_mov_b32 s0, 0
1131; GFX10-WAVE64-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1132; GFX10-WAVE64-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
1133; GFX10-WAVE64-NEXT:    s_cbranch_execz .LBB13_3
1134; GFX10-WAVE64-NEXT:  ; %bb.1: ; %bb3
1135; GFX10-WAVE64-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v0
1136; GFX10-WAVE64-NEXT:    s_andn2_b64 s[2:3], s[2:3], vcc
1137; GFX10-WAVE64-NEXT:    s_cbranch_scc0 .LBB13_6
1138; GFX10-WAVE64-NEXT:  ; %bb.2: ; %bb3
1139; GFX10-WAVE64-NEXT:    s_andn2_b64 exec, exec, vcc
1140; GFX10-WAVE64-NEXT:  .LBB13_3: ; %bb4
1141; GFX10-WAVE64-NEXT:    s_or_b64 exec, exec, s[4:5]
1142; GFX10-WAVE64-NEXT:    s_mov_b32 s1, s0
1143; GFX10-WAVE64-NEXT:    s_mov_b32 s2, s0
1144; GFX10-WAVE64-NEXT:    s_mov_b32 s3, s0
1145; GFX10-WAVE64-NEXT:    s_mov_b32 s4, s0
1146; GFX10-WAVE64-NEXT:    s_mov_b32 s5, s0
1147; GFX10-WAVE64-NEXT:    s_mov_b32 s6, s0
1148; GFX10-WAVE64-NEXT:    s_mov_b32 s7, s0
1149; GFX10-WAVE64-NEXT:    image_sample_c v0, v[2:3], s[0:7], s[0:3] dmask:0x10 dim:SQ_RSRC_IMG_1D
1150; GFX10-WAVE64-NEXT:    s_waitcnt vmcnt(0)
1151; GFX10-WAVE64-NEXT:    v_cmp_neq_f32_e32 vcc, 0, v0
1152; GFX10-WAVE64-NEXT:    s_and_saveexec_b64 s[0:1], vcc
1153; GFX10-WAVE64-NEXT:    s_cbranch_execz .LBB13_5
1154; GFX10-WAVE64-NEXT:  ; %bb.4: ; %bb8
1155; GFX10-WAVE64-NEXT:    v_mov_b32_e32 v0, 9
1156; GFX10-WAVE64-NEXT:    global_store_dword v[0:1], v0, off
1157; GFX10-WAVE64-NEXT:    s_waitcnt_vscnt null, 0x0
1158; GFX10-WAVE64-NEXT:  .LBB13_5: ; %UnifiedReturnBlock
1159; GFX10-WAVE64-NEXT:    s_endpgm
1160; GFX10-WAVE64-NEXT:  .LBB13_6:
1161; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
1162; GFX10-WAVE64-NEXT:    exp null off, off, off, off done vm
1163; GFX10-WAVE64-NEXT:    s_endpgm
1164;
1165; GFX10-WAVE32-LABEL: if_after_kill_block:
1166; GFX10-WAVE32:       ; %bb.0: ; %bb
1167; GFX10-WAVE32-NEXT:    s_mov_b32 s1, exec_lo
1168; GFX10-WAVE32-NEXT:    s_wqm_b32 exec_lo, exec_lo
1169; GFX10-WAVE32-NEXT:    v_cmp_nle_f32_e32 vcc_lo, 0, v1
1170; GFX10-WAVE32-NEXT:    s_mov_b32 s0, 0
1171; GFX10-WAVE32-NEXT:    s_and_saveexec_b32 s2, vcc_lo
1172; GFX10-WAVE32-NEXT:    s_xor_b32 s2, exec_lo, s2
1173; GFX10-WAVE32-NEXT:    s_cbranch_execz .LBB13_3
1174; GFX10-WAVE32-NEXT:  ; %bb.1: ; %bb3
1175; GFX10-WAVE32-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, 0, v0
1176; GFX10-WAVE32-NEXT:    s_andn2_b32 s1, s1, vcc_lo
1177; GFX10-WAVE32-NEXT:    s_cbranch_scc0 .LBB13_6
1178; GFX10-WAVE32-NEXT:  ; %bb.2: ; %bb3
1179; GFX10-WAVE32-NEXT:    s_andn2_b32 exec_lo, exec_lo, vcc_lo
1180; GFX10-WAVE32-NEXT:  .LBB13_3: ; %bb4
1181; GFX10-WAVE32-NEXT:    s_or_b32 exec_lo, exec_lo, s2
1182; GFX10-WAVE32-NEXT:    s_mov_b32 s1, s0
1183; GFX10-WAVE32-NEXT:    s_mov_b32 s2, s0
1184; GFX10-WAVE32-NEXT:    s_mov_b32 s3, s0
1185; GFX10-WAVE32-NEXT:    s_mov_b32 s4, s0
1186; GFX10-WAVE32-NEXT:    s_mov_b32 s5, s0
1187; GFX10-WAVE32-NEXT:    s_mov_b32 s6, s0
1188; GFX10-WAVE32-NEXT:    s_mov_b32 s7, s0
1189; GFX10-WAVE32-NEXT:    image_sample_c v0, v[2:3], s[0:7], s[0:3] dmask:0x10 dim:SQ_RSRC_IMG_1D
1190; GFX10-WAVE32-NEXT:    s_waitcnt vmcnt(0)
1191; GFX10-WAVE32-NEXT:    v_cmp_neq_f32_e32 vcc_lo, 0, v0
1192; GFX10-WAVE32-NEXT:    s_and_saveexec_b32 s0, vcc_lo
1193; GFX10-WAVE32-NEXT:    s_cbranch_execz .LBB13_5
1194; GFX10-WAVE32-NEXT:  ; %bb.4: ; %bb8
1195; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v0, 9
1196; GFX10-WAVE32-NEXT:    global_store_dword v[0:1], v0, off
1197; GFX10-WAVE32-NEXT:    s_waitcnt_vscnt null, 0x0
1198; GFX10-WAVE32-NEXT:  .LBB13_5: ; %UnifiedReturnBlock
1199; GFX10-WAVE32-NEXT:    s_endpgm
1200; GFX10-WAVE32-NEXT:  .LBB13_6:
1201; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
1202; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
1203; GFX10-WAVE32-NEXT:    s_endpgm
1204bb:
1205  %tmp = fcmp ult float %arg1, 0.000000e+00
1206  br i1 %tmp, label %bb3, label %bb4
1207
1208bb3:                                              ; preds = %bb
1209  %cmp.arg = fcmp olt float %arg, 0.0
1210  call void @llvm.amdgcn.kill(i1 %cmp.arg)
1211  br label %bb4
1212
1213bb4:                                              ; preds = %bb3, %bb
1214  %tmp5 = call <4 x float> @llvm.amdgcn.image.sample.c.1d.v4f32.f32(i32 16, float %arg2, float %arg3, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
1215  %tmp6 = extractelement <4 x float> %tmp5, i32 0
1216  %tmp7 = fcmp une float %tmp6, 0.000000e+00
1217  br i1 %tmp7, label %bb8, label %bb9
1218
1219bb8:                                              ; preds = %bb9, %bb4
1220  store volatile i32 9, i32 addrspace(1)* undef
1221  ret void
1222
1223bb9:                                              ; preds = %bb4
1224  ret void
1225}
1226
1227define amdgpu_ps void @cbranch_kill(i32 inreg %0, float %val0, float %val1) {
1228; SI-LABEL: cbranch_kill:
1229; SI:       ; %bb.0: ; %.entry
1230; SI-NEXT:    s_mov_b32 s4, 0
1231; SI-NEXT:    s_mov_b64 s[0:1], exec
1232; SI-NEXT:    v_mov_b32_e32 v4, 0
1233; SI-NEXT:    v_mov_b32_e32 v2, v1
1234; SI-NEXT:    v_mov_b32_e32 v3, v1
1235; SI-NEXT:    s_mov_b32 s5, s4
1236; SI-NEXT:    s_mov_b32 s6, s4
1237; SI-NEXT:    s_mov_b32 s7, s4
1238; SI-NEXT:    s_mov_b32 s8, s4
1239; SI-NEXT:    s_mov_b32 s9, s4
1240; SI-NEXT:    s_mov_b32 s10, s4
1241; SI-NEXT:    s_mov_b32 s11, s4
1242; SI-NEXT:    image_sample_l v1, v[1:4], s[4:11], s[0:3] dmask:0x1 da
1243; SI-NEXT:    s_waitcnt vmcnt(0)
1244; SI-NEXT:    v_cmp_ge_f32_e32 vcc, 0, v1
1245; SI-NEXT:    s_and_saveexec_b64 s[2:3], vcc
1246; SI-NEXT:    s_xor_b64 s[2:3], exec, s[2:3]
1247; SI-NEXT:    s_cbranch_execz .LBB14_3
1248; SI-NEXT:  ; %bb.1: ; %kill
1249; SI-NEXT:    s_andn2_b64 s[0:1], s[0:1], exec
1250; SI-NEXT:    ; implicit-def: $vgpr0
1251; SI-NEXT:    ; implicit-def: $vgpr1
1252; SI-NEXT:    s_cbranch_scc0 .LBB14_6
1253; SI-NEXT:  ; %bb.2: ; %kill
1254; SI-NEXT:    s_mov_b64 exec, 0
1255; SI-NEXT:  .LBB14_3: ; %Flow
1256; SI-NEXT:    s_or_saveexec_b64 s[0:1], s[2:3]
1257; SI-NEXT:    ; implicit-def: $vgpr2
1258; SI-NEXT:    s_xor_b64 exec, exec, s[0:1]
1259; SI-NEXT:  ; %bb.4: ; %live
1260; SI-NEXT:    v_mul_f32_e32 v2, v0, v1
1261; SI-NEXT:  ; %bb.5: ; %export
1262; SI-NEXT:    s_or_b64 exec, exec, s[0:1]
1263; SI-NEXT:    exp mrt0 v2, v2, v2, v2 done vm
1264; SI-NEXT:    s_endpgm
1265; SI-NEXT:  .LBB14_6:
1266; SI-NEXT:    s_mov_b64 exec, 0
1267; SI-NEXT:    exp null off, off, off, off done vm
1268; SI-NEXT:    s_endpgm
1269;
1270; GFX10-WAVE64-LABEL: cbranch_kill:
1271; GFX10-WAVE64:       ; %bb.0: ; %.entry
1272; GFX10-WAVE64-NEXT:    v_mov_b32_e32 v2, 0
1273; GFX10-WAVE64-NEXT:    s_mov_b32 s4, 0
1274; GFX10-WAVE64-NEXT:    s_mov_b64 s[0:1], exec
1275; GFX10-WAVE64-NEXT:    s_mov_b32 s5, s4
1276; GFX10-WAVE64-NEXT:    s_mov_b32 s6, s4
1277; GFX10-WAVE64-NEXT:    s_mov_b32 s7, s4
1278; GFX10-WAVE64-NEXT:    s_mov_b32 s8, s4
1279; GFX10-WAVE64-NEXT:    s_mov_b32 s9, s4
1280; GFX10-WAVE64-NEXT:    s_mov_b32 s10, s4
1281; GFX10-WAVE64-NEXT:    s_mov_b32 s11, s4
1282; GFX10-WAVE64-NEXT:    image_sample_l v1, [v1, v1, v1, v2], s[4:11], s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
1283; GFX10-WAVE64-NEXT:    s_waitcnt vmcnt(0)
1284; GFX10-WAVE64-NEXT:    v_cmp_ge_f32_e32 vcc, 0, v1
1285; GFX10-WAVE64-NEXT:    s_and_saveexec_b64 s[2:3], vcc
1286; GFX10-WAVE64-NEXT:    s_xor_b64 s[2:3], exec, s[2:3]
1287; GFX10-WAVE64-NEXT:    s_cbranch_execz .LBB14_3
1288; GFX10-WAVE64-NEXT:  ; %bb.1: ; %kill
1289; GFX10-WAVE64-NEXT:    s_andn2_b64 s[0:1], s[0:1], exec
1290; GFX10-WAVE64-NEXT:    ; implicit-def: $vgpr0
1291; GFX10-WAVE64-NEXT:    ; implicit-def: $vgpr1
1292; GFX10-WAVE64-NEXT:    s_cbranch_scc0 .LBB14_6
1293; GFX10-WAVE64-NEXT:  ; %bb.2: ; %kill
1294; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
1295; GFX10-WAVE64-NEXT:  .LBB14_3: ; %Flow
1296; GFX10-WAVE64-NEXT:    s_or_saveexec_b64 s[0:1], s[2:3]
1297; GFX10-WAVE64-NEXT:    ; implicit-def: $vgpr2
1298; GFX10-WAVE64-NEXT:    s_xor_b64 exec, exec, s[0:1]
1299; GFX10-WAVE64-NEXT:  ; %bb.4: ; %live
1300; GFX10-WAVE64-NEXT:    v_mul_f32_e32 v2, v0, v1
1301; GFX10-WAVE64-NEXT:  ; %bb.5: ; %export
1302; GFX10-WAVE64-NEXT:    s_or_b64 exec, exec, s[0:1]
1303; GFX10-WAVE64-NEXT:    exp mrt0 v2, v2, v2, v2 done vm
1304; GFX10-WAVE64-NEXT:    s_endpgm
1305; GFX10-WAVE64-NEXT:  .LBB14_6:
1306; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
1307; GFX10-WAVE64-NEXT:    exp null off, off, off, off done vm
1308; GFX10-WAVE64-NEXT:    s_endpgm
1309;
1310; GFX10-WAVE32-LABEL: cbranch_kill:
1311; GFX10-WAVE32:       ; %bb.0: ; %.entry
1312; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v2, 0
1313; GFX10-WAVE32-NEXT:    s_mov_b32 s4, 0
1314; GFX10-WAVE32-NEXT:    s_mov_b32 s0, exec_lo
1315; GFX10-WAVE32-NEXT:    s_mov_b32 s5, s4
1316; GFX10-WAVE32-NEXT:    s_mov_b32 s6, s4
1317; GFX10-WAVE32-NEXT:    s_mov_b32 s7, s4
1318; GFX10-WAVE32-NEXT:    s_mov_b32 s8, s4
1319; GFX10-WAVE32-NEXT:    s_mov_b32 s9, s4
1320; GFX10-WAVE32-NEXT:    s_mov_b32 s10, s4
1321; GFX10-WAVE32-NEXT:    s_mov_b32 s11, s4
1322; GFX10-WAVE32-NEXT:    image_sample_l v1, [v1, v1, v1, v2], s[4:11], s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
1323; GFX10-WAVE32-NEXT:    s_waitcnt vmcnt(0)
1324; GFX10-WAVE32-NEXT:    v_cmp_ge_f32_e32 vcc_lo, 0, v1
1325; GFX10-WAVE32-NEXT:    s_and_saveexec_b32 s1, vcc_lo
1326; GFX10-WAVE32-NEXT:    s_xor_b32 s1, exec_lo, s1
1327; GFX10-WAVE32-NEXT:    s_cbranch_execz .LBB14_3
1328; GFX10-WAVE32-NEXT:  ; %bb.1: ; %kill
1329; GFX10-WAVE32-NEXT:    s_andn2_b32 s0, s0, exec_lo
1330; GFX10-WAVE32-NEXT:    ; implicit-def: $vgpr0
1331; GFX10-WAVE32-NEXT:    ; implicit-def: $vgpr1
1332; GFX10-WAVE32-NEXT:    s_cbranch_scc0 .LBB14_6
1333; GFX10-WAVE32-NEXT:  ; %bb.2: ; %kill
1334; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
1335; GFX10-WAVE32-NEXT:  .LBB14_3: ; %Flow
1336; GFX10-WAVE32-NEXT:    s_or_saveexec_b32 s0, s1
1337; GFX10-WAVE32-NEXT:    ; implicit-def: $vgpr2
1338; GFX10-WAVE32-NEXT:    s_xor_b32 exec_lo, exec_lo, s0
1339; GFX10-WAVE32-NEXT:  ; %bb.4: ; %live
1340; GFX10-WAVE32-NEXT:    v_mul_f32_e32 v2, v0, v1
1341; GFX10-WAVE32-NEXT:  ; %bb.5: ; %export
1342; GFX10-WAVE32-NEXT:    s_or_b32 exec_lo, exec_lo, s0
1343; GFX10-WAVE32-NEXT:    exp mrt0 v2, v2, v2, v2 done vm
1344; GFX10-WAVE32-NEXT:    s_endpgm
1345; GFX10-WAVE32-NEXT:  .LBB14_6:
1346; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
1347; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
1348; GFX10-WAVE32-NEXT:    s_endpgm
1349.entry:
1350  %sample = call float @llvm.amdgcn.image.sample.l.2darray.f32.f32(i32 1, float %val1, float %val1, float %val1, float 0.000000e+00, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
1351  %cond0 = fcmp ugt float %sample, 0.000000e+00
1352  br i1 %cond0, label %live, label %kill
1353
1354kill:
1355  call void @llvm.amdgcn.kill(i1 false)
1356  br label %export
1357
1358live:
1359  %scale = fmul reassoc nnan nsz arcp contract float %val0, %sample
1360  br label %export
1361
1362export:
1363  %proxy = phi float [ undef, %kill ], [ %scale, %live ]
1364  call void @llvm.amdgcn.exp.f32(i32 immarg 0, i32 immarg 15, float %proxy, float %proxy, float %proxy, float %proxy, i1 immarg true, i1 immarg true) #3
1365  ret void
1366}
1367
1368
1369define amdgpu_ps void @complex_loop(i32 inreg %cmpa, i32 %cmpb, i32 %cmpc) {
1370; SI-LABEL: complex_loop:
1371; SI:       ; %bb.0: ; %.entry
1372; SI-NEXT:    s_cmp_lt_i32 s0, 1
1373; SI-NEXT:    s_cbranch_scc1 .LBB15_7
1374; SI-NEXT:  ; %bb.1: ; %.lr.ph
1375; SI-NEXT:    s_mov_b64 s[2:3], exec
1376; SI-NEXT:    s_mov_b32 s6, 0
1377; SI-NEXT:    s_mov_b64 s[0:1], 0
1378; SI-NEXT:    s_branch .LBB15_3
1379; SI-NEXT:  .LBB15_2: ; %latch
1380; SI-NEXT:    ; in Loop: Header=BB15_3 Depth=1
1381; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
1382; SI-NEXT:    s_add_i32 s6, s6, 1
1383; SI-NEXT:    v_cmp_ge_i32_e32 vcc, s6, v1
1384; SI-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
1385; SI-NEXT:    v_mov_b32_e32 v2, s6
1386; SI-NEXT:    s_andn2_b64 exec, exec, s[0:1]
1387; SI-NEXT:    s_cbranch_execz .LBB15_6
1388; SI-NEXT:  .LBB15_3: ; %hdr
1389; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
1390; SI-NEXT:    v_cmp_gt_u32_e32 vcc, s6, v0
1391; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1392; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
1393; SI-NEXT:    s_cbranch_execz .LBB15_2
1394; SI-NEXT:  ; %bb.4: ; %kill
1395; SI-NEXT:    ; in Loop: Header=BB15_3 Depth=1
1396; SI-NEXT:    s_andn2_b64 s[2:3], s[2:3], exec
1397; SI-NEXT:    s_cbranch_scc0 .LBB15_8
1398; SI-NEXT:  ; %bb.5: ; %kill
1399; SI-NEXT:    ; in Loop: Header=BB15_3 Depth=1
1400; SI-NEXT:    s_mov_b64 exec, 0
1401; SI-NEXT:    s_branch .LBB15_2
1402; SI-NEXT:  .LBB15_6: ; %Flow
1403; SI-NEXT:    s_or_b64 exec, exec, s[0:1]
1404; SI-NEXT:    exp mrt0 v2, v2, v0, v0 done vm
1405; SI-NEXT:    s_endpgm
1406; SI-NEXT:  .LBB15_7:
1407; SI-NEXT:    v_mov_b32_e32 v2, -1
1408; SI-NEXT:    exp mrt0 v2, v2, v0, v0 done vm
1409; SI-NEXT:    s_endpgm
1410; SI-NEXT:  .LBB15_8:
1411; SI-NEXT:    s_mov_b64 exec, 0
1412; SI-NEXT:    exp null off, off, off, off done vm
1413; SI-NEXT:    s_endpgm
1414;
1415; GFX10-WAVE64-LABEL: complex_loop:
1416; GFX10-WAVE64:       ; %bb.0: ; %.entry
1417; GFX10-WAVE64-NEXT:    s_cmp_lt_i32 s0, 1
1418; GFX10-WAVE64-NEXT:    s_cbranch_scc1 .LBB15_7
1419; GFX10-WAVE64-NEXT:  ; %bb.1: ; %.lr.ph
1420; GFX10-WAVE64-NEXT:    s_mov_b64 s[2:3], exec
1421; GFX10-WAVE64-NEXT:    s_mov_b32 s6, 0
1422; GFX10-WAVE64-NEXT:    s_mov_b64 s[0:1], 0
1423; GFX10-WAVE64-NEXT:    s_branch .LBB15_3
1424; GFX10-WAVE64-NEXT:  .LBB15_2: ; %latch
1425; GFX10-WAVE64-NEXT:    ; in Loop: Header=BB15_3 Depth=1
1426; GFX10-WAVE64-NEXT:    s_or_b64 exec, exec, s[4:5]
1427; GFX10-WAVE64-NEXT:    s_add_i32 s6, s6, 1
1428; GFX10-WAVE64-NEXT:    v_cmp_ge_i32_e32 vcc, s6, v1
1429; GFX10-WAVE64-NEXT:    v_mov_b32_e32 v2, s6
1430; GFX10-WAVE64-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
1431; GFX10-WAVE64-NEXT:    s_andn2_b64 exec, exec, s[0:1]
1432; GFX10-WAVE64-NEXT:    s_cbranch_execz .LBB15_6
1433; GFX10-WAVE64-NEXT:  .LBB15_3: ; %hdr
1434; GFX10-WAVE64-NEXT:    ; =>This Inner Loop Header: Depth=1
1435; GFX10-WAVE64-NEXT:    v_cmp_gt_u32_e32 vcc, s6, v0
1436; GFX10-WAVE64-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1437; GFX10-WAVE64-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
1438; GFX10-WAVE64-NEXT:    s_cbranch_execz .LBB15_2
1439; GFX10-WAVE64-NEXT:  ; %bb.4: ; %kill
1440; GFX10-WAVE64-NEXT:    ; in Loop: Header=BB15_3 Depth=1
1441; GFX10-WAVE64-NEXT:    s_andn2_b64 s[2:3], s[2:3], exec
1442; GFX10-WAVE64-NEXT:    s_cbranch_scc0 .LBB15_8
1443; GFX10-WAVE64-NEXT:  ; %bb.5: ; %kill
1444; GFX10-WAVE64-NEXT:    ; in Loop: Header=BB15_3 Depth=1
1445; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
1446; GFX10-WAVE64-NEXT:    s_branch .LBB15_2
1447; GFX10-WAVE64-NEXT:  .LBB15_6: ; %Flow
1448; GFX10-WAVE64-NEXT:    s_or_b64 exec, exec, s[0:1]
1449; GFX10-WAVE64-NEXT:    exp mrt0 v2, v2, v0, v0 done vm
1450; GFX10-WAVE64-NEXT:    s_endpgm
1451; GFX10-WAVE64-NEXT:  .LBB15_7:
1452; GFX10-WAVE64-NEXT:    v_mov_b32_e32 v2, -1
1453; GFX10-WAVE64-NEXT:    exp mrt0 v2, v2, v0, v0 done vm
1454; GFX10-WAVE64-NEXT:    s_endpgm
1455; GFX10-WAVE64-NEXT:  .LBB15_8:
1456; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
1457; GFX10-WAVE64-NEXT:    exp null off, off, off, off done vm
1458; GFX10-WAVE64-NEXT:    s_endpgm
1459;
1460; GFX10-WAVE32-LABEL: complex_loop:
1461; GFX10-WAVE32:       ; %bb.0: ; %.entry
1462; GFX10-WAVE32-NEXT:    s_cmp_lt_i32 s0, 1
1463; GFX10-WAVE32-NEXT:    s_cbranch_scc1 .LBB15_7
1464; GFX10-WAVE32-NEXT:  ; %bb.1: ; %.lr.ph
1465; GFX10-WAVE32-NEXT:    s_mov_b32 s1, exec_lo
1466; GFX10-WAVE32-NEXT:    s_mov_b32 s0, 0
1467; GFX10-WAVE32-NEXT:    s_mov_b32 s2, 0
1468; GFX10-WAVE32-NEXT:    s_branch .LBB15_3
1469; GFX10-WAVE32-NEXT:  .LBB15_2: ; %latch
1470; GFX10-WAVE32-NEXT:    ; in Loop: Header=BB15_3 Depth=1
1471; GFX10-WAVE32-NEXT:    s_or_b32 exec_lo, exec_lo, s3
1472; GFX10-WAVE32-NEXT:    s_add_i32 s2, s2, 1
1473; GFX10-WAVE32-NEXT:    v_cmp_ge_i32_e32 vcc_lo, s2, v1
1474; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v2, s2
1475; GFX10-WAVE32-NEXT:    s_or_b32 s0, vcc_lo, s0
1476; GFX10-WAVE32-NEXT:    s_andn2_b32 exec_lo, exec_lo, s0
1477; GFX10-WAVE32-NEXT:    s_cbranch_execz .LBB15_6
1478; GFX10-WAVE32-NEXT:  .LBB15_3: ; %hdr
1479; GFX10-WAVE32-NEXT:    ; =>This Inner Loop Header: Depth=1
1480; GFX10-WAVE32-NEXT:    v_cmp_gt_u32_e32 vcc_lo, s2, v0
1481; GFX10-WAVE32-NEXT:    s_and_saveexec_b32 s3, vcc_lo
1482; GFX10-WAVE32-NEXT:    s_xor_b32 s3, exec_lo, s3
1483; GFX10-WAVE32-NEXT:    s_cbranch_execz .LBB15_2
1484; GFX10-WAVE32-NEXT:  ; %bb.4: ; %kill
1485; GFX10-WAVE32-NEXT:    ; in Loop: Header=BB15_3 Depth=1
1486; GFX10-WAVE32-NEXT:    s_andn2_b32 s1, s1, exec_lo
1487; GFX10-WAVE32-NEXT:    s_cbranch_scc0 .LBB15_8
1488; GFX10-WAVE32-NEXT:  ; %bb.5: ; %kill
1489; GFX10-WAVE32-NEXT:    ; in Loop: Header=BB15_3 Depth=1
1490; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
1491; GFX10-WAVE32-NEXT:    s_branch .LBB15_2
1492; GFX10-WAVE32-NEXT:  .LBB15_6: ; %Flow
1493; GFX10-WAVE32-NEXT:    s_or_b32 exec_lo, exec_lo, s0
1494; GFX10-WAVE32-NEXT:    exp mrt0 v2, v2, v0, v0 done vm
1495; GFX10-WAVE32-NEXT:    s_endpgm
1496; GFX10-WAVE32-NEXT:  .LBB15_7:
1497; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v2, -1
1498; GFX10-WAVE32-NEXT:    exp mrt0 v2, v2, v0, v0 done vm
1499; GFX10-WAVE32-NEXT:    s_endpgm
1500; GFX10-WAVE32-NEXT:  .LBB15_8:
1501; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
1502; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
1503; GFX10-WAVE32-NEXT:    s_endpgm
1504.entry:
1505  %flaga = icmp sgt i32 %cmpa, 0
1506  br i1 %flaga, label %.lr.ph, label %._crit_edge
1507
1508.lr.ph:
1509  br label %hdr
1510
1511hdr:
1512  %ctr = phi i32 [ 0, %.lr.ph ], [ %ctr.next, %latch ]
1513  %flagb = icmp ugt i32 %ctr, %cmpb
1514  br i1 %flagb, label %kill, label %latch
1515
1516kill:
1517  call void @llvm.amdgcn.kill(i1 false)
1518  br label %latch
1519
1520latch:
1521  %ctr.next = add nuw nsw i32 %ctr, 1
1522  %flagc = icmp slt i32 %ctr.next, %cmpc
1523  br i1 %flagc, label %hdr, label %._crit_edge
1524
1525._crit_edge:
1526  %tmp = phi i32 [ -1, %.entry ], [ %ctr.next, %latch ]
1527  %out = bitcast i32 %tmp to float
1528  call void @llvm.amdgcn.exp.f32(i32 immarg 0, i32 immarg 15, float %out, float %out, float undef, float undef, i1 immarg true, i1 immarg true)
1529  ret void
1530}
1531
1532define void @skip_mode_switch(i32 %arg) {
1533; SI-LABEL: skip_mode_switch:
1534; SI:       ; %bb.0: ; %entry
1535; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1536; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
1537; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1538; SI-NEXT:    s_cbranch_execz .LBB16_2
1539; SI-NEXT:  ; %bb.1: ; %bb.0
1540; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3
1541; SI-NEXT:  .LBB16_2: ; %bb.1
1542; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
1543; SI-NEXT:    s_setpc_b64 s[30:31]
1544;
1545; GFX10-WAVE64-LABEL: skip_mode_switch:
1546; GFX10-WAVE64:       ; %bb.0: ; %entry
1547; GFX10-WAVE64-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1548; GFX10-WAVE64-NEXT:    s_waitcnt_vscnt null, 0x0
1549; GFX10-WAVE64-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
1550; GFX10-WAVE64-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1551; GFX10-WAVE64-NEXT:    s_cbranch_execz .LBB16_2
1552; GFX10-WAVE64-NEXT:  ; %bb.1: ; %bb.0
1553; GFX10-WAVE64-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3
1554; GFX10-WAVE64-NEXT:  .LBB16_2: ; %bb.1
1555; GFX10-WAVE64-NEXT:    s_or_b64 exec, exec, s[4:5]
1556; GFX10-WAVE64-NEXT:    s_setpc_b64 s[30:31]
1557;
1558; GFX10-WAVE32-LABEL: skip_mode_switch:
1559; GFX10-WAVE32:       ; %bb.0: ; %entry
1560; GFX10-WAVE32-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1561; GFX10-WAVE32-NEXT:    s_waitcnt_vscnt null, 0x0
1562; GFX10-WAVE32-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
1563; GFX10-WAVE32-NEXT:    s_and_saveexec_b32 s4, vcc_lo
1564; GFX10-WAVE32-NEXT:    s_cbranch_execz .LBB16_2
1565; GFX10-WAVE32-NEXT:  ; %bb.1: ; %bb.0
1566; GFX10-WAVE32-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3
1567; GFX10-WAVE32-NEXT:  .LBB16_2: ; %bb.1
1568; GFX10-WAVE32-NEXT:    s_or_b32 exec_lo, exec_lo, s4
1569; GFX10-WAVE32-NEXT:    s_setpc_b64 s[30:31]
1570entry:
1571  %cmp = icmp eq i32 %arg, 0
1572  br i1 %cmp, label %bb.0, label %bb.1
1573
1574bb.0:
1575  call void @llvm.amdgcn.s.setreg(i32 2049, i32 3)
1576  br label %bb.1
1577
1578bb.1:
1579  ret void
1580}
1581
1582declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg) #3
1583declare float @llvm.amdgcn.image.sample.l.2darray.f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1
1584declare <4 x float> @llvm.amdgcn.image.sample.c.1d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
1585declare void @llvm.amdgcn.kill(i1) #0
1586
1587declare void @llvm.amdgcn.s.setreg(i32 immarg, i32)
1588
1589attributes #0 = { nounwind }
1590attributes #1 = { nounwind readonly }
1591attributes #2 = { nounwind readnone speculatable }
1592attributes #3 = { inaccessiblememonly nounwind writeonly }
1593