1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,WAVE64,SI %s
3; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,WAVE64,GFX10-WAVE64 %s
4; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,GFX10-WAVE32 %s
5
6define amdgpu_ps void @test_kill_depth_0_imm_pos() #0 {
7; GCN-LABEL: test_kill_depth_0_imm_pos:
8; GCN:       ; %bb.0:
9; GCN-NEXT:    s_endpgm
10  call void @llvm.amdgcn.kill(i1 true)
11  ret void
12}
13
14define amdgpu_ps void @test_kill_depth_0_imm_neg() #0 {
15; WAVE64-LABEL: test_kill_depth_0_imm_neg:
16; WAVE64:       ; %bb.0:
17; WAVE64-NEXT:    s_andn2_b64 exec, exec, exec
18; WAVE64-NEXT:    s_cbranch_scc0 BB1_1
19; WAVE64-NEXT:    s_endpgm
20; WAVE64-NEXT:  BB1_1:
21; WAVE64-NEXT:    s_mov_b64 exec, 0
22; WAVE64-NEXT:    exp null off, off, off, off done vm
23; WAVE64-NEXT:    s_endpgm
24;
25; GFX10-WAVE32-LABEL: test_kill_depth_0_imm_neg:
26; GFX10-WAVE32:       ; %bb.0:
27; GFX10-WAVE32-NEXT:    s_andn2_b32 exec_lo, exec_lo, exec_lo
28; GFX10-WAVE32-NEXT:    s_cbranch_scc0 BB1_1
29; GFX10-WAVE32-NEXT:    s_endpgm
30; GFX10-WAVE32-NEXT:  BB1_1:
31; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
32; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
33; GFX10-WAVE32-NEXT:    s_endpgm
34  call void @llvm.amdgcn.kill(i1 false)
35  ret void
36}
37
38; FIXME: Ideally only one early-exit would be emitted
39define amdgpu_ps void @test_kill_depth_0_imm_neg_x2() #0 {
40; WAVE64-LABEL: test_kill_depth_0_imm_neg_x2:
41; WAVE64:       ; %bb.0:
42; WAVE64-NEXT:    s_mov_b64 s[0:1], exec
43; WAVE64-NEXT:    s_andn2_b64 s[0:1], s[0:1], exec
44; WAVE64-NEXT:    s_cbranch_scc0 BB2_2
45; WAVE64-NEXT:  ; %bb.1:
46; WAVE64-NEXT:    s_mov_b64 exec, 0
47; WAVE64-NEXT:    s_andn2_b64 s[0:1], s[0:1], exec
48; WAVE64-NEXT:    s_cbranch_scc0 BB2_2
49; WAVE64-NEXT:    s_endpgm
50; WAVE64-NEXT:  BB2_2:
51; WAVE64-NEXT:    s_mov_b64 exec, 0
52; WAVE64-NEXT:    exp null off, off, off, off done vm
53; WAVE64-NEXT:    s_endpgm
54;
55; GFX10-WAVE32-LABEL: test_kill_depth_0_imm_neg_x2:
56; GFX10-WAVE32:       ; %bb.0:
57; GFX10-WAVE32-NEXT:    s_mov_b32 s0, exec_lo
58; GFX10-WAVE32-NEXT:    s_andn2_b32 s0, s0, exec_lo
59; GFX10-WAVE32-NEXT:    s_cbranch_scc0 BB2_2
60; GFX10-WAVE32-NEXT:  ; %bb.1:
61; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
62; GFX10-WAVE32-NEXT:    s_andn2_b32 s0, s0, exec_lo
63; GFX10-WAVE32-NEXT:    s_cbranch_scc0 BB2_2
64; GFX10-WAVE32-NEXT:    s_endpgm
65; GFX10-WAVE32-NEXT:  BB2_2:
66; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
67; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
68; GFX10-WAVE32-NEXT:    s_endpgm
69  call void @llvm.amdgcn.kill(i1 false)
70  call void @llvm.amdgcn.kill(i1 false)
71  ret void
72}
73
74define amdgpu_ps void @test_kill_depth_var(float %x) #0 {
75; WAVE64-LABEL: test_kill_depth_var:
76; WAVE64:       ; %bb.0:
77; WAVE64-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v0
78; WAVE64-NEXT:    s_andn2_b64 exec, exec, vcc
79; WAVE64-NEXT:    s_cbranch_scc0 BB3_1
80; WAVE64-NEXT:    s_endpgm
81; WAVE64-NEXT:  BB3_1:
82; WAVE64-NEXT:    s_mov_b64 exec, 0
83; WAVE64-NEXT:    exp null off, off, off, off done vm
84; WAVE64-NEXT:    s_endpgm
85;
86; GFX10-WAVE32-LABEL: test_kill_depth_var:
87; GFX10-WAVE32:       ; %bb.0:
88; GFX10-WAVE32-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, 0, v0
89; GFX10-WAVE32-NEXT:    s_andn2_b32 exec_lo, exec_lo, vcc_lo
90; GFX10-WAVE32-NEXT:    s_cbranch_scc0 BB3_1
91; GFX10-WAVE32-NEXT:    s_endpgm
92; GFX10-WAVE32-NEXT:  BB3_1:
93; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
94; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
95; GFX10-WAVE32-NEXT:    s_endpgm
96  %cmp = fcmp olt float %x, 0.0
97  call void @llvm.amdgcn.kill(i1 %cmp)
98  ret void
99}
100
101; FIXME: Ideally only one early-exit would be emitted
102define amdgpu_ps void @test_kill_depth_var_x2_same(float %x) #0 {
103; WAVE64-LABEL: test_kill_depth_var_x2_same:
104; WAVE64:       ; %bb.0:
105; WAVE64-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v0
106; WAVE64-NEXT:    s_mov_b64 s[0:1], exec
107; WAVE64-NEXT:    s_andn2_b64 s[0:1], s[0:1], vcc
108; WAVE64-NEXT:    s_cbranch_scc0 BB4_2
109; WAVE64-NEXT:  ; %bb.1:
110; WAVE64-NEXT:    s_andn2_b64 exec, exec, vcc
111; WAVE64-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v0
112; WAVE64-NEXT:    s_andn2_b64 s[0:1], s[0:1], vcc
113; WAVE64-NEXT:    s_cbranch_scc0 BB4_2
114; WAVE64-NEXT:    s_endpgm
115; WAVE64-NEXT:  BB4_2:
116; WAVE64-NEXT:    s_mov_b64 exec, 0
117; WAVE64-NEXT:    exp null off, off, off, off done vm
118; WAVE64-NEXT:    s_endpgm
119;
120; GFX10-WAVE32-LABEL: test_kill_depth_var_x2_same:
121; GFX10-WAVE32:       ; %bb.0:
122; GFX10-WAVE32-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, 0, v0
123; GFX10-WAVE32-NEXT:    s_mov_b32 s0, exec_lo
124; GFX10-WAVE32-NEXT:    s_andn2_b32 s0, s0, vcc_lo
125; GFX10-WAVE32-NEXT:    s_cbranch_scc0 BB4_2
126; GFX10-WAVE32-NEXT:  ; %bb.1:
127; GFX10-WAVE32-NEXT:    s_andn2_b32 exec_lo, exec_lo, vcc_lo
128; GFX10-WAVE32-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, 0, v0
129; GFX10-WAVE32-NEXT:    s_andn2_b32 s0, s0, vcc_lo
130; GFX10-WAVE32-NEXT:    s_cbranch_scc0 BB4_2
131; GFX10-WAVE32-NEXT:    s_endpgm
132; GFX10-WAVE32-NEXT:  BB4_2:
133; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
134; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
135; GFX10-WAVE32-NEXT:    s_endpgm
136  %cmp = fcmp olt float %x, 0.0
137  call void @llvm.amdgcn.kill(i1 %cmp)
138  call void @llvm.amdgcn.kill(i1 %cmp)
139  ret void
140}
141
142; FIXME: Ideally only one early-exit would be emitted
143define amdgpu_ps void @test_kill_depth_var_x2(float %x, float %y) #0 {
144; WAVE64-LABEL: test_kill_depth_var_x2:
145; WAVE64:       ; %bb.0:
146; WAVE64-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v0
147; WAVE64-NEXT:    s_mov_b64 s[0:1], exec
148; WAVE64-NEXT:    s_andn2_b64 s[0:1], s[0:1], vcc
149; WAVE64-NEXT:    s_cbranch_scc0 BB5_2
150; WAVE64-NEXT:  ; %bb.1:
151; WAVE64-NEXT:    s_andn2_b64 exec, exec, vcc
152; WAVE64-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v1
153; WAVE64-NEXT:    s_andn2_b64 s[0:1], s[0:1], vcc
154; WAVE64-NEXT:    s_cbranch_scc0 BB5_2
155; WAVE64-NEXT:    s_endpgm
156; WAVE64-NEXT:  BB5_2:
157; WAVE64-NEXT:    s_mov_b64 exec, 0
158; WAVE64-NEXT:    exp null off, off, off, off done vm
159; WAVE64-NEXT:    s_endpgm
160;
161; GFX10-WAVE32-LABEL: test_kill_depth_var_x2:
162; GFX10-WAVE32:       ; %bb.0:
163; GFX10-WAVE32-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, 0, v0
164; GFX10-WAVE32-NEXT:    s_mov_b32 s0, exec_lo
165; GFX10-WAVE32-NEXT:    s_andn2_b32 s0, s0, vcc_lo
166; GFX10-WAVE32-NEXT:    s_cbranch_scc0 BB5_2
167; GFX10-WAVE32-NEXT:  ; %bb.1:
168; GFX10-WAVE32-NEXT:    s_andn2_b32 exec_lo, exec_lo, vcc_lo
169; GFX10-WAVE32-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, 0, v1
170; GFX10-WAVE32-NEXT:    s_andn2_b32 s0, s0, vcc_lo
171; GFX10-WAVE32-NEXT:    s_cbranch_scc0 BB5_2
172; GFX10-WAVE32-NEXT:    s_endpgm
173; GFX10-WAVE32-NEXT:  BB5_2:
174; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
175; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
176; GFX10-WAVE32-NEXT:    s_endpgm
177  %cmp.x = fcmp olt float %x, 0.0
178  call void @llvm.amdgcn.kill(i1 %cmp.x)
179  %cmp.y = fcmp olt float %y, 0.0
180  call void @llvm.amdgcn.kill(i1 %cmp.y)
181  ret void
182}
183
184define amdgpu_ps void @test_kill_depth_var_x2_instructions(float %x) #0 {
185; WAVE64-LABEL: test_kill_depth_var_x2_instructions:
186; WAVE64:       ; %bb.0:
187; WAVE64-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v0
188; WAVE64-NEXT:    s_mov_b64 s[0:1], exec
189; WAVE64-NEXT:    s_andn2_b64 s[0:1], s[0:1], vcc
190; WAVE64-NEXT:    s_cbranch_scc0 BB6_2
191; WAVE64-NEXT:  ; %bb.1:
192; WAVE64-NEXT:    s_andn2_b64 exec, exec, vcc
193; WAVE64-NEXT:    ;;#ASMSTART
194; WAVE64-NEXT:    v_mov_b32_e64 v7, -1
195; WAVE64-NEXT:    ;;#ASMEND
196; WAVE64-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v7
197; WAVE64-NEXT:    s_andn2_b64 s[0:1], s[0:1], vcc
198; WAVE64-NEXT:    s_cbranch_scc0 BB6_2
199; WAVE64-NEXT:    s_endpgm
200; WAVE64-NEXT:  BB6_2:
201; WAVE64-NEXT:    s_mov_b64 exec, 0
202; WAVE64-NEXT:    exp null off, off, off, off done vm
203; WAVE64-NEXT:    s_endpgm
204;
205; GFX10-WAVE32-LABEL: test_kill_depth_var_x2_instructions:
206; GFX10-WAVE32:       ; %bb.0:
207; GFX10-WAVE32-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, 0, v0
208; GFX10-WAVE32-NEXT:    s_mov_b32 s0, exec_lo
209; GFX10-WAVE32-NEXT:    s_andn2_b32 s0, s0, vcc_lo
210; GFX10-WAVE32-NEXT:    s_cbranch_scc0 BB6_2
211; GFX10-WAVE32-NEXT:  ; %bb.1:
212; GFX10-WAVE32-NEXT:    s_andn2_b32 exec_lo, exec_lo, vcc_lo
213; GFX10-WAVE32-NEXT:    ;;#ASMSTART
214; GFX10-WAVE32-NEXT:    v_mov_b32_e64 v7, -1
215; GFX10-WAVE32-NEXT:    ;;#ASMEND
216; GFX10-WAVE32-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, 0, v7
217; GFX10-WAVE32-NEXT:    s_andn2_b32 s0, s0, vcc_lo
218; GFX10-WAVE32-NEXT:    s_cbranch_scc0 BB6_2
219; GFX10-WAVE32-NEXT:    s_endpgm
220; GFX10-WAVE32-NEXT:  BB6_2:
221; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
222; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
223; GFX10-WAVE32-NEXT:    s_endpgm
224  %cmp.x = fcmp olt float %x, 0.0
225  call void @llvm.amdgcn.kill(i1 %cmp.x)
226  %y = call float asm sideeffect "v_mov_b32_e64 v7, -1", "={v7}"()
227  %cmp.y = fcmp olt float %y, 0.0
228  call void @llvm.amdgcn.kill(i1 %cmp.y)
229  ret void
230}
231
232; FIXME: why does the skip depend on the asm length in the same block?
233define amdgpu_ps float @test_kill_control_flow(i32 inreg %arg) #0 {
234; WAVE64-LABEL: test_kill_control_flow:
235; WAVE64:       ; %bb.0: ; %entry
236; WAVE64-NEXT:    s_cmp_lg_u32 s0, 0
237; WAVE64-NEXT:    s_cbranch_scc0 BB7_2
238; WAVE64-NEXT:  ; %bb.1: ; %exit
239; WAVE64-NEXT:    v_mov_b32_e32 v0, 1.0
240; WAVE64-NEXT:    s_branch BB7_5
241; WAVE64-NEXT:  BB7_2: ; %bb
242; WAVE64-NEXT:    ;;#ASMSTART
243; WAVE64-NEXT:    v_mov_b32_e64 v7, -1
244; WAVE64-NEXT:    v_nop_e64
245; WAVE64-NEXT:    v_nop_e64
246; WAVE64-NEXT:    v_nop_e64
247; WAVE64-NEXT:    v_nop_e64
248; WAVE64-NEXT:    v_nop_e64
249; WAVE64-NEXT:    v_nop_e64
250; WAVE64-NEXT:    v_nop_e64
251; WAVE64-NEXT:    v_nop_e64
252; WAVE64-NEXT:    v_nop_e64
253; WAVE64-NEXT:    v_nop_e64
254; WAVE64-NEXT:    ;;#ASMEND
255; WAVE64-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v7
256; WAVE64-NEXT:    s_mov_b64 s[2:3], exec
257; WAVE64-NEXT:    s_andn2_b64 s[2:3], s[2:3], vcc
258; WAVE64-NEXT:    s_cbranch_scc0 BB7_4
259; WAVE64-NEXT:  ; %bb.3: ; %bb
260; WAVE64-NEXT:    s_andn2_b64 exec, exec, vcc
261; WAVE64-NEXT:    v_mov_b32_e32 v0, 1.0
262; WAVE64-NEXT:    s_branch BB7_5
263; WAVE64-NEXT:  BB7_4:
264; WAVE64-NEXT:    s_mov_b64 exec, 0
265; WAVE64-NEXT:    exp null off, off, off, off done vm
266; WAVE64-NEXT:    s_endpgm
267; WAVE64-NEXT:  BB7_5:
268;
269; GFX10-WAVE32-LABEL: test_kill_control_flow:
270; GFX10-WAVE32:       ; %bb.0: ; %entry
271; GFX10-WAVE32-NEXT:    s_cmp_lg_u32 s0, 0
272; GFX10-WAVE32-NEXT:    s_cbranch_scc0 BB7_2
273; GFX10-WAVE32-NEXT:  ; %bb.1: ; %exit
274; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v0, 1.0
275; GFX10-WAVE32-NEXT:    s_branch BB7_5
276; GFX10-WAVE32-NEXT:  BB7_2: ; %bb
277; GFX10-WAVE32-NEXT:    ;;#ASMSTART
278; GFX10-WAVE32-NEXT:    v_mov_b32_e64 v7, -1
279; GFX10-WAVE32-NEXT:    v_nop_e64
280; GFX10-WAVE32-NEXT:    v_nop_e64
281; GFX10-WAVE32-NEXT:    v_nop_e64
282; GFX10-WAVE32-NEXT:    v_nop_e64
283; GFX10-WAVE32-NEXT:    v_nop_e64
284; GFX10-WAVE32-NEXT:    v_nop_e64
285; GFX10-WAVE32-NEXT:    v_nop_e64
286; GFX10-WAVE32-NEXT:    v_nop_e64
287; GFX10-WAVE32-NEXT:    v_nop_e64
288; GFX10-WAVE32-NEXT:    v_nop_e64
289; GFX10-WAVE32-NEXT:    ;;#ASMEND
290; GFX10-WAVE32-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, 0, v7
291; GFX10-WAVE32-NEXT:    s_mov_b32 s1, exec_lo
292; GFX10-WAVE32-NEXT:    s_andn2_b32 s1, s1, vcc_lo
293; GFX10-WAVE32-NEXT:    s_cbranch_scc0 BB7_4
294; GFX10-WAVE32-NEXT:  ; %bb.3: ; %bb
295; GFX10-WAVE32-NEXT:    s_andn2_b32 exec_lo, exec_lo, vcc_lo
296; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v0, 1.0
297; GFX10-WAVE32-NEXT:    s_branch BB7_5
298; GFX10-WAVE32-NEXT:  BB7_4:
299; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
300; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
301; GFX10-WAVE32-NEXT:    s_endpgm
302; GFX10-WAVE32-NEXT:  BB7_5:
303entry:
304  %cmp = icmp eq i32 %arg, 0
305  br i1 %cmp, label %bb, label %exit
306
307bb:
308  %var = call float asm sideeffect "v_mov_b32_e64 v7, -1
309    v_nop_e64
310    v_nop_e64
311    v_nop_e64
312    v_nop_e64
313    v_nop_e64
314    v_nop_e64
315    v_nop_e64
316    v_nop_e64
317    v_nop_e64
318    v_nop_e64", "={v7}"()
319  %cmp.var = fcmp olt float %var, 0.0
320  ; TODO: We could do an early-exit here (the branch above is uniform!)
321  call void @llvm.amdgcn.kill(i1 %cmp.var)
322  br label %exit
323
324exit:
325  ret float 1.0
326}
327
328define amdgpu_ps void @test_kill_control_flow_remainder(i32 inreg %arg) #0 {
329; SI-LABEL: test_kill_control_flow_remainder:
330; SI:       ; %bb.0: ; %entry
331; SI-NEXT:    s_cmp_lg_u32 s0, 0
332; SI-NEXT:    v_mov_b32_e32 v9, 0
333; SI-NEXT:    s_cbranch_scc1 BB8_3
334; SI-NEXT:  ; %bb.1: ; %bb
335; SI-NEXT:    ;;#ASMSTART
336; SI-NEXT:    v_mov_b32_e64 v7, -1
337; SI-NEXT:    v_nop_e64
338; SI-NEXT:    v_nop_e64
339; SI-NEXT:    v_nop_e64
340; SI-NEXT:    v_nop_e64
341; SI-NEXT:    v_nop_e64
342; SI-NEXT:    v_nop_e64
343; SI-NEXT:    v_nop_e64
344; SI-NEXT:    v_nop_e64
345; SI-NEXT:    v_nop_e64
346; SI-NEXT:    v_nop_e64
347; SI-NEXT:    v_nop_e64
348; SI-NEXT:    ;;#ASMEND
349; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v7
350; SI-NEXT:    s_mov_b64 s[2:3], exec
351; SI-NEXT:    s_andn2_b64 s[2:3], s[2:3], vcc
352; SI-NEXT:    ;;#ASMSTART
353; SI-NEXT:    v_mov_b32_e64 v8, -1
354; SI-NEXT:    ;;#ASMEND
355; SI-NEXT:    s_cbranch_scc0 BB8_4
356; SI-NEXT:  ; %bb.2: ; %bb
357; SI-NEXT:    s_andn2_b64 exec, exec, vcc
358; SI-NEXT:    s_mov_b32 s3, 0xf000
359; SI-NEXT:    s_mov_b32 s2, -1
360; SI-NEXT:    buffer_store_dword v8, off, s[0:3], 0
361; SI-NEXT:    s_waitcnt vmcnt(0)
362; SI-NEXT:    ;;#ASMSTART
363; SI-NEXT:    v_mov_b32_e64 v9, -2
364; SI-NEXT:    ;;#ASMEND
365; SI-NEXT:  BB8_3: ; %exit
366; SI-NEXT:    s_mov_b32 s3, 0xf000
367; SI-NEXT:    s_mov_b32 s2, -1
368; SI-NEXT:    buffer_store_dword v9, off, s[0:3], 0
369; SI-NEXT:    s_endpgm
370; SI-NEXT:  BB8_4:
371; SI-NEXT:    s_mov_b64 exec, 0
372; SI-NEXT:    exp null off, off, off, off done vm
373; SI-NEXT:    s_endpgm
374;
375; GFX10-WAVE64-LABEL: test_kill_control_flow_remainder:
376; GFX10-WAVE64:       ; %bb.0: ; %entry
377; GFX10-WAVE64-NEXT:    v_mov_b32_e32 v9, 0
378; GFX10-WAVE64-NEXT:    s_cmp_lg_u32 s0, 0
379; GFX10-WAVE64-NEXT:    s_cbranch_scc0 BB8_2
380; GFX10-WAVE64-NEXT:  ; %bb.1: ; %exit
381; GFX10-WAVE64-NEXT:    global_store_dword v[0:1], v9, off
382; GFX10-WAVE64-NEXT:    s_endpgm
383; GFX10-WAVE64-NEXT:  BB8_2: ; %bb
384; GFX10-WAVE64-NEXT:    ;;#ASMSTART
385; GFX10-WAVE64-NEXT:    v_mov_b32_e64 v7, -1
386; GFX10-WAVE64-NEXT:    v_nop_e64
387; GFX10-WAVE64-NEXT:    v_nop_e64
388; GFX10-WAVE64-NEXT:    v_nop_e64
389; GFX10-WAVE64-NEXT:    v_nop_e64
390; GFX10-WAVE64-NEXT:    v_nop_e64
391; GFX10-WAVE64-NEXT:    v_nop_e64
392; GFX10-WAVE64-NEXT:    v_nop_e64
393; GFX10-WAVE64-NEXT:    v_nop_e64
394; GFX10-WAVE64-NEXT:    v_nop_e64
395; GFX10-WAVE64-NEXT:    v_nop_e64
396; GFX10-WAVE64-NEXT:    v_nop_e64
397; GFX10-WAVE64-NEXT:    ;;#ASMEND
398; GFX10-WAVE64-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v7
399; GFX10-WAVE64-NEXT:    s_mov_b64 s[2:3], exec
400; GFX10-WAVE64-NEXT:    ;;#ASMSTART
401; GFX10-WAVE64-NEXT:    v_mov_b32_e64 v8, -1
402; GFX10-WAVE64-NEXT:    ;;#ASMEND
403; GFX10-WAVE64-NEXT:    s_andn2_b64 s[2:3], s[2:3], vcc
404; GFX10-WAVE64-NEXT:    s_cbranch_scc0 BB8_4
405; GFX10-WAVE64-NEXT:  ; %bb.3: ; %bb
406; GFX10-WAVE64-NEXT:    s_andn2_b64 exec, exec, vcc
407; GFX10-WAVE64-NEXT:    global_store_dword v[0:1], v8, off
408; GFX10-WAVE64-NEXT:    s_waitcnt_vscnt null, 0x0
409; GFX10-WAVE64-NEXT:    ;;#ASMSTART
410; GFX10-WAVE64-NEXT:    v_mov_b32_e64 v9, -2
411; GFX10-WAVE64-NEXT:    ;;#ASMEND
412; GFX10-WAVE64-NEXT:    global_store_dword v[0:1], v9, off
413; GFX10-WAVE64-NEXT:    s_endpgm
414; GFX10-WAVE64-NEXT:  BB8_4:
415; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
416; GFX10-WAVE64-NEXT:    exp null off, off, off, off done vm
417; GFX10-WAVE64-NEXT:    s_endpgm
418;
419; GFX10-WAVE32-LABEL: test_kill_control_flow_remainder:
420; GFX10-WAVE32:       ; %bb.0: ; %entry
421; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v9, 0
422; GFX10-WAVE32-NEXT:    s_cmp_lg_u32 s0, 0
423; GFX10-WAVE32-NEXT:    s_cbranch_scc0 BB8_2
424; GFX10-WAVE32-NEXT:  ; %bb.1: ; %exit
425; GFX10-WAVE32-NEXT:    global_store_dword v[0:1], v9, off
426; GFX10-WAVE32-NEXT:    s_endpgm
427; GFX10-WAVE32-NEXT:  BB8_2: ; %bb
428; GFX10-WAVE32-NEXT:    ;;#ASMSTART
429; GFX10-WAVE32-NEXT:    v_mov_b32_e64 v7, -1
430; GFX10-WAVE32-NEXT:    v_nop_e64
431; GFX10-WAVE32-NEXT:    v_nop_e64
432; GFX10-WAVE32-NEXT:    v_nop_e64
433; GFX10-WAVE32-NEXT:    v_nop_e64
434; GFX10-WAVE32-NEXT:    v_nop_e64
435; GFX10-WAVE32-NEXT:    v_nop_e64
436; GFX10-WAVE32-NEXT:    v_nop_e64
437; GFX10-WAVE32-NEXT:    v_nop_e64
438; GFX10-WAVE32-NEXT:    v_nop_e64
439; GFX10-WAVE32-NEXT:    v_nop_e64
440; GFX10-WAVE32-NEXT:    v_nop_e64
441; GFX10-WAVE32-NEXT:    ;;#ASMEND
442; GFX10-WAVE32-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, 0, v7
443; GFX10-WAVE32-NEXT:    s_mov_b32 s1, exec_lo
444; GFX10-WAVE32-NEXT:    ;;#ASMSTART
445; GFX10-WAVE32-NEXT:    v_mov_b32_e64 v8, -1
446; GFX10-WAVE32-NEXT:    ;;#ASMEND
447; GFX10-WAVE32-NEXT:    s_andn2_b32 s1, s1, vcc_lo
448; GFX10-WAVE32-NEXT:    s_cbranch_scc0 BB8_4
449; GFX10-WAVE32-NEXT:  ; %bb.3: ; %bb
450; GFX10-WAVE32-NEXT:    s_andn2_b32 exec_lo, exec_lo, vcc_lo
451; GFX10-WAVE32-NEXT:    global_store_dword v[0:1], v8, off
452; GFX10-WAVE32-NEXT:    s_waitcnt_vscnt null, 0x0
453; GFX10-WAVE32-NEXT:    ;;#ASMSTART
454; GFX10-WAVE32-NEXT:    v_mov_b32_e64 v9, -2
455; GFX10-WAVE32-NEXT:    ;;#ASMEND
456; GFX10-WAVE32-NEXT:    global_store_dword v[0:1], v9, off
457; GFX10-WAVE32-NEXT:    s_endpgm
458; GFX10-WAVE32-NEXT:  BB8_4:
459; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
460; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
461; GFX10-WAVE32-NEXT:    s_endpgm
462entry:
463  %cmp = icmp eq i32 %arg, 0
464  br i1 %cmp, label %bb, label %exit
465
466bb:
467  %var = call float asm sideeffect "v_mov_b32_e64 v7, -1
468    v_nop_e64
469    v_nop_e64
470    v_nop_e64
471    v_nop_e64
472    v_nop_e64
473    v_nop_e64
474    v_nop_e64
475    v_nop_e64
476    v_nop_e64
477    v_nop_e64
478    v_nop_e64", "={v7}"()
479  %live.across = call float asm sideeffect "v_mov_b32_e64 v8, -1", "={v8}"()
480  %cmp.var = fcmp olt float %var, 0.0
481  ; TODO: We could do an early-exit here (the branch above is uniform!)
482  call void @llvm.amdgcn.kill(i1 %cmp.var)
483  store volatile float %live.across, float addrspace(1)* undef
484  %live.out = call float asm sideeffect "v_mov_b32_e64 v9, -2", "={v9}"()
485  br label %exit
486
487exit:
488  %phi = phi float [ 0.0, %entry ], [ %live.out, %bb ]
489  store float %phi, float addrspace(1)* undef
490  ret void
491}
492
493define amdgpu_ps float @test_kill_control_flow_return(i32 inreg %arg) #0 {
494; SI-LABEL: test_kill_control_flow_return:
495; SI:       ; %bb.0: ; %entry
496; SI-NEXT:    v_cmp_eq_u32_e64 s[4:5], s0, 1
497; SI-NEXT:    s_mov_b64 s[2:3], exec
498; SI-NEXT:    s_xor_b64 s[4:5], s[4:5], exec
499; SI-NEXT:    s_andn2_b64 s[2:3], s[2:3], s[4:5]
500; SI-NEXT:    s_cbranch_scc0 BB9_4
501; SI-NEXT:  ; %bb.1: ; %entry
502; SI-NEXT:    s_and_b64 exec, exec, s[2:3]
503; SI-NEXT:    s_cmp_lg_u32 s0, 0
504; SI-NEXT:    v_mov_b32_e32 v0, 0
505; SI-NEXT:    s_cbranch_scc0 BB9_3
506; SI-NEXT:  ; %bb.2: ; %exit
507; SI-NEXT:    s_branch BB9_5
508; SI-NEXT:  BB9_3: ; %bb
509; SI-NEXT:    ;;#ASMSTART
510; SI-NEXT:    v_mov_b32_e64 v7, -1
511; SI-NEXT:    v_nop_e64
512; SI-NEXT:    v_nop_e64
513; SI-NEXT:    v_nop_e64
514; SI-NEXT:    v_nop_e64
515; SI-NEXT:    v_nop_e64
516; SI-NEXT:    v_nop_e64
517; SI-NEXT:    v_nop_e64
518; SI-NEXT:    v_nop_e64
519; SI-NEXT:    v_nop_e64
520; SI-NEXT:    v_nop_e64
521; SI-NEXT:    ;;#ASMEND
522; SI-NEXT:    v_mov_b32_e32 v0, v7
523; SI-NEXT:    s_branch BB9_5
524; SI-NEXT:  BB9_4:
525; SI-NEXT:    s_mov_b64 exec, 0
526; SI-NEXT:    exp null off, off, off, off done vm
527; SI-NEXT:    s_endpgm
528; SI-NEXT:  BB9_5:
529;
530; GFX10-WAVE64-LABEL: test_kill_control_flow_return:
531; GFX10-WAVE64:       ; %bb.0: ; %entry
532; GFX10-WAVE64-NEXT:    v_cmp_eq_u32_e64 s[4:5], s0, 1
533; GFX10-WAVE64-NEXT:    s_mov_b64 s[2:3], exec
534; GFX10-WAVE64-NEXT:    s_xor_b64 s[4:5], s[4:5], exec
535; GFX10-WAVE64-NEXT:    s_andn2_b64 s[2:3], s[2:3], s[4:5]
536; GFX10-WAVE64-NEXT:    s_cbranch_scc0 BB9_4
537; GFX10-WAVE64-NEXT:  ; %bb.1: ; %entry
538; GFX10-WAVE64-NEXT:    s_and_b64 exec, exec, s[2:3]
539; GFX10-WAVE64-NEXT:    v_mov_b32_e32 v0, 0
540; GFX10-WAVE64-NEXT:    s_cmp_lg_u32 s0, 0
541; GFX10-WAVE64-NEXT:    s_cbranch_scc0 BB9_3
542; GFX10-WAVE64-NEXT:  ; %bb.2: ; %exit
543; GFX10-WAVE64-NEXT:    s_branch BB9_5
544; GFX10-WAVE64-NEXT:  BB9_3: ; %bb
545; GFX10-WAVE64-NEXT:    ;;#ASMSTART
546; GFX10-WAVE64-NEXT:    v_mov_b32_e64 v7, -1
547; GFX10-WAVE64-NEXT:    v_nop_e64
548; GFX10-WAVE64-NEXT:    v_nop_e64
549; GFX10-WAVE64-NEXT:    v_nop_e64
550; GFX10-WAVE64-NEXT:    v_nop_e64
551; GFX10-WAVE64-NEXT:    v_nop_e64
552; GFX10-WAVE64-NEXT:    v_nop_e64
553; GFX10-WAVE64-NEXT:    v_nop_e64
554; GFX10-WAVE64-NEXT:    v_nop_e64
555; GFX10-WAVE64-NEXT:    v_nop_e64
556; GFX10-WAVE64-NEXT:    v_nop_e64
557; GFX10-WAVE64-NEXT:    ;;#ASMEND
558; GFX10-WAVE64-NEXT:    v_mov_b32_e32 v0, v7
559; GFX10-WAVE64-NEXT:    s_branch BB9_5
560; GFX10-WAVE64-NEXT:  BB9_4:
561; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
562; GFX10-WAVE64-NEXT:    exp null off, off, off, off done vm
563; GFX10-WAVE64-NEXT:    s_endpgm
564; GFX10-WAVE64-NEXT:  BB9_5:
565;
566; GFX10-WAVE32-LABEL: test_kill_control_flow_return:
567; GFX10-WAVE32:       ; %bb.0: ; %entry
568; GFX10-WAVE32-NEXT:    v_cmp_eq_u32_e64 s2, s0, 1
569; GFX10-WAVE32-NEXT:    s_mov_b32 s1, exec_lo
570; GFX10-WAVE32-NEXT:    s_xor_b32 s2, s2, exec_lo
571; GFX10-WAVE32-NEXT:    s_andn2_b32 s1, s1, s2
572; GFX10-WAVE32-NEXT:    s_cbranch_scc0 BB9_4
573; GFX10-WAVE32-NEXT:  ; %bb.1: ; %entry
574; GFX10-WAVE32-NEXT:    s_and_b32 exec_lo, exec_lo, s1
575; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v0, 0
576; GFX10-WAVE32-NEXT:    s_cmp_lg_u32 s0, 0
577; GFX10-WAVE32-NEXT:    s_cbranch_scc0 BB9_3
578; GFX10-WAVE32-NEXT:  ; %bb.2: ; %exit
579; GFX10-WAVE32-NEXT:    s_branch BB9_5
580; GFX10-WAVE32-NEXT:  BB9_3: ; %bb
581; GFX10-WAVE32-NEXT:    ;;#ASMSTART
582; GFX10-WAVE32-NEXT:    v_mov_b32_e64 v7, -1
583; GFX10-WAVE32-NEXT:    v_nop_e64
584; GFX10-WAVE32-NEXT:    v_nop_e64
585; GFX10-WAVE32-NEXT:    v_nop_e64
586; GFX10-WAVE32-NEXT:    v_nop_e64
587; GFX10-WAVE32-NEXT:    v_nop_e64
588; GFX10-WAVE32-NEXT:    v_nop_e64
589; GFX10-WAVE32-NEXT:    v_nop_e64
590; GFX10-WAVE32-NEXT:    v_nop_e64
591; GFX10-WAVE32-NEXT:    v_nop_e64
592; GFX10-WAVE32-NEXT:    v_nop_e64
593; GFX10-WAVE32-NEXT:    ;;#ASMEND
594; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v0, v7
595; GFX10-WAVE32-NEXT:    s_branch BB9_5
596; GFX10-WAVE32-NEXT:  BB9_4:
597; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
598; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
599; GFX10-WAVE32-NEXT:    s_endpgm
600; GFX10-WAVE32-NEXT:  BB9_5:
601entry:
602  %kill = icmp eq i32 %arg, 1
603  %cmp = icmp eq i32 %arg, 0
604  call void @llvm.amdgcn.kill(i1 %kill)
605  br i1 %cmp, label %bb, label %exit
606
607bb:
608  %var = call float asm sideeffect "v_mov_b32_e64 v7, -1
609    v_nop_e64
610    v_nop_e64
611    v_nop_e64
612    v_nop_e64
613    v_nop_e64
614    v_nop_e64
615    v_nop_e64
616    v_nop_e64
617    v_nop_e64
618    v_nop_e64", "={v7}"()
619  br label %exit
620
621exit:
622  %ret = phi float [ %var, %bb ], [ 0.0, %entry ]
623  ret float %ret
624}
625
626define amdgpu_ps void @test_kill_divergent_loop(i32 %arg) #0 {
627; SI-LABEL: test_kill_divergent_loop:
628; SI:       ; %bb.0: ; %entry
629; SI-NEXT:    s_mov_b64 s[0:1], exec
630; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
631; SI-NEXT:    s_and_saveexec_b64 s[2:3], vcc
632; SI-NEXT:    s_xor_b64 s[2:3], exec, s[2:3]
633; SI-NEXT:    s_cbranch_execz BB10_4
634; SI-NEXT:  ; %bb.1: ; %bb.preheader
635; SI-NEXT:    s_mov_b32 s7, 0xf000
636; SI-NEXT:    s_mov_b32 s6, -1
637; SI-NEXT:  BB10_2: ; %bb
638; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
639; SI-NEXT:    ;;#ASMSTART
640; SI-NEXT:    v_mov_b32_e64 v7, -1
641; SI-NEXT:    v_nop_e64
642; SI-NEXT:    v_nop_e64
643; SI-NEXT:    v_nop_e64
644; SI-NEXT:    v_nop_e64
645; SI-NEXT:    v_nop_e64
646; SI-NEXT:    v_nop_e64
647; SI-NEXT:    v_nop_e64
648; SI-NEXT:    v_nop_e64
649; SI-NEXT:    v_nop_e64
650; SI-NEXT:    v_nop_e64
651; SI-NEXT:    ;;#ASMEND
652; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v7
653; SI-NEXT:    s_andn2_b64 s[0:1], s[0:1], vcc
654; SI-NEXT:    s_cbranch_scc0 BB10_5
655; SI-NEXT:  ; %bb.3: ; %bb
656; SI-NEXT:    ; in Loop: Header=BB10_2 Depth=1
657; SI-NEXT:    s_andn2_b64 exec, exec, vcc
658; SI-NEXT:    buffer_load_dword v0, off, s[4:7], 0 glc
659; SI-NEXT:    s_waitcnt vmcnt(0)
660; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
661; SI-NEXT:    s_and_b64 vcc, exec, vcc
662; SI-NEXT:    s_cbranch_vccnz BB10_2
663; SI-NEXT:  BB10_4: ; %Flow1
664; SI-NEXT:    s_or_b64 exec, exec, s[2:3]
665; SI-NEXT:    s_mov_b32 s3, 0xf000
666; SI-NEXT:    s_mov_b32 s2, -1
667; SI-NEXT:    v_mov_b32_e32 v0, 8
668; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
669; SI-NEXT:    s_waitcnt vmcnt(0)
670; SI-NEXT:    s_endpgm
671; SI-NEXT:  BB10_5:
672; SI-NEXT:    s_mov_b64 exec, 0
673; SI-NEXT:    exp null off, off, off, off done vm
674; SI-NEXT:    s_endpgm
675;
676; GFX10-WAVE64-LABEL: test_kill_divergent_loop:
677; GFX10-WAVE64:       ; %bb.0: ; %entry
678; GFX10-WAVE64-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
679; GFX10-WAVE64-NEXT:    s_mov_b64 s[0:1], exec
680; GFX10-WAVE64-NEXT:    s_and_saveexec_b64 s[2:3], vcc
681; GFX10-WAVE64-NEXT:    s_xor_b64 s[2:3], exec, s[2:3]
682; GFX10-WAVE64-NEXT:    s_cbranch_execz BB10_3
683; GFX10-WAVE64-NEXT:  BB10_1: ; %bb
684; GFX10-WAVE64-NEXT:    ; =>This Inner Loop Header: Depth=1
685; GFX10-WAVE64-NEXT:    ;;#ASMSTART
686; GFX10-WAVE64-NEXT:    v_mov_b32_e64 v7, -1
687; GFX10-WAVE64-NEXT:    v_nop_e64
688; GFX10-WAVE64-NEXT:    v_nop_e64
689; GFX10-WAVE64-NEXT:    v_nop_e64
690; GFX10-WAVE64-NEXT:    v_nop_e64
691; GFX10-WAVE64-NEXT:    v_nop_e64
692; GFX10-WAVE64-NEXT:    v_nop_e64
693; GFX10-WAVE64-NEXT:    v_nop_e64
694; GFX10-WAVE64-NEXT:    v_nop_e64
695; GFX10-WAVE64-NEXT:    v_nop_e64
696; GFX10-WAVE64-NEXT:    v_nop_e64
697; GFX10-WAVE64-NEXT:    ;;#ASMEND
698; GFX10-WAVE64-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v7
699; GFX10-WAVE64-NEXT:    s_andn2_b64 s[0:1], s[0:1], vcc
700; GFX10-WAVE64-NEXT:    s_cbranch_scc0 BB10_4
701; GFX10-WAVE64-NEXT:  ; %bb.2: ; %bb
702; GFX10-WAVE64-NEXT:    ; in Loop: Header=BB10_1 Depth=1
703; GFX10-WAVE64-NEXT:    s_andn2_b64 exec, exec, vcc
704; GFX10-WAVE64-NEXT:    global_load_dword v0, v[0:1], off glc dlc
705; GFX10-WAVE64-NEXT:    s_waitcnt vmcnt(0)
706; GFX10-WAVE64-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
707; GFX10-WAVE64-NEXT:    s_and_b64 vcc, exec, vcc
708; GFX10-WAVE64-NEXT:    s_cbranch_vccnz BB10_1
709; GFX10-WAVE64-NEXT:  BB10_3: ; %Flow1
710; GFX10-WAVE64-NEXT:    s_or_b64 exec, exec, s[2:3]
711; GFX10-WAVE64-NEXT:    v_mov_b32_e32 v0, 8
712; GFX10-WAVE64-NEXT:    global_store_dword v[0:1], v0, off
713; GFX10-WAVE64-NEXT:    s_waitcnt_vscnt null, 0x0
714; GFX10-WAVE64-NEXT:    s_endpgm
715; GFX10-WAVE64-NEXT:  BB10_4:
716; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
717; GFX10-WAVE64-NEXT:    exp null off, off, off, off done vm
718; GFX10-WAVE64-NEXT:    s_endpgm
719;
720; GFX10-WAVE32-LABEL: test_kill_divergent_loop:
721; GFX10-WAVE32:       ; %bb.0: ; %entry
722; GFX10-WAVE32-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
723; GFX10-WAVE32-NEXT:    s_mov_b32 s0, exec_lo
724; GFX10-WAVE32-NEXT:    s_and_saveexec_b32 s1, vcc_lo
725; GFX10-WAVE32-NEXT:    s_xor_b32 s1, exec_lo, s1
726; GFX10-WAVE32-NEXT:    s_cbranch_execz BB10_3
727; GFX10-WAVE32-NEXT:  BB10_1: ; %bb
728; GFX10-WAVE32-NEXT:    ; =>This Inner Loop Header: Depth=1
729; GFX10-WAVE32-NEXT:    ;;#ASMSTART
730; GFX10-WAVE32-NEXT:    v_mov_b32_e64 v7, -1
731; GFX10-WAVE32-NEXT:    v_nop_e64
732; GFX10-WAVE32-NEXT:    v_nop_e64
733; GFX10-WAVE32-NEXT:    v_nop_e64
734; GFX10-WAVE32-NEXT:    v_nop_e64
735; GFX10-WAVE32-NEXT:    v_nop_e64
736; GFX10-WAVE32-NEXT:    v_nop_e64
737; GFX10-WAVE32-NEXT:    v_nop_e64
738; GFX10-WAVE32-NEXT:    v_nop_e64
739; GFX10-WAVE32-NEXT:    v_nop_e64
740; GFX10-WAVE32-NEXT:    v_nop_e64
741; GFX10-WAVE32-NEXT:    ;;#ASMEND
742; GFX10-WAVE32-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, 0, v7
743; GFX10-WAVE32-NEXT:    s_andn2_b32 s0, s0, vcc_lo
744; GFX10-WAVE32-NEXT:    s_cbranch_scc0 BB10_4
745; GFX10-WAVE32-NEXT:  ; %bb.2: ; %bb
746; GFX10-WAVE32-NEXT:    ; in Loop: Header=BB10_1 Depth=1
747; GFX10-WAVE32-NEXT:    s_andn2_b32 exec_lo, exec_lo, vcc_lo
748; GFX10-WAVE32-NEXT:    global_load_dword v0, v[0:1], off glc dlc
749; GFX10-WAVE32-NEXT:    s_waitcnt vmcnt(0)
750; GFX10-WAVE32-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
751; GFX10-WAVE32-NEXT:    s_and_b32 vcc_lo, exec_lo, vcc_lo
752; GFX10-WAVE32-NEXT:    s_cbranch_vccnz BB10_1
753; GFX10-WAVE32-NEXT:  BB10_3: ; %Flow1
754; GFX10-WAVE32-NEXT:    s_or_b32 exec_lo, exec_lo, s1
755; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v0, 8
756; GFX10-WAVE32-NEXT:    global_store_dword v[0:1], v0, off
757; GFX10-WAVE32-NEXT:    s_waitcnt_vscnt null, 0x0
758; GFX10-WAVE32-NEXT:    s_endpgm
759; GFX10-WAVE32-NEXT:  BB10_4:
760; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
761; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
762; GFX10-WAVE32-NEXT:    s_endpgm
763entry:
764  %cmp = icmp eq i32 %arg, 0
765  br i1 %cmp, label %bb, label %exit
766
767bb:
768  %var = call float asm sideeffect "v_mov_b32_e64 v7, -1
769    v_nop_e64
770    v_nop_e64
771    v_nop_e64
772    v_nop_e64
773    v_nop_e64
774    v_nop_e64
775    v_nop_e64
776    v_nop_e64
777    v_nop_e64
778    v_nop_e64", "={v7}"()
779  %cmp.var = fcmp olt float %var, 0.0
780  call void @llvm.amdgcn.kill(i1 %cmp.var)
781  %vgpr = load volatile i32, i32 addrspace(1)* undef
782  %loop.cond = icmp eq i32 %vgpr, 0
783  br i1 %loop.cond, label %bb, label %exit
784
785exit:
786  store volatile i32 8, i32 addrspace(1)* undef
787  ret void
788}
789
790; bug 28550
791define amdgpu_ps void @phi_use_def_before_kill(float inreg %x) #0 {
792; SI-LABEL: phi_use_def_before_kill:
793; SI:       ; %bb.0: ; %bb
794; SI-NEXT:    v_add_f32_e64 v1, s0, 1.0
795; SI-NEXT:    v_cmp_lt_f32_e32 vcc, 0, v1
796; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1.0, vcc
797; SI-NEXT:    v_cmp_nlt_f32_e32 vcc, 0, v1
798; SI-NEXT:    s_andn2_b64 exec, exec, vcc
799; SI-NEXT:    s_cbranch_scc0 BB11_6
800; SI-NEXT:  ; %bb.1: ; %bb
801; SI-NEXT:    s_andn2_b64 exec, exec, vcc
802; SI-NEXT:    s_cbranch_scc0 BB11_3
803; SI-NEXT:  ; %bb.2: ; %bb8
804; SI-NEXT:    s_mov_b32 s3, 0xf000
805; SI-NEXT:    s_mov_b32 s2, -1
806; SI-NEXT:    v_mov_b32_e32 v0, 8
807; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
808; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
809; SI-NEXT:    v_mov_b32_e32 v0, 4.0
810; SI-NEXT:  BB11_3: ; %phibb
811; SI-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v0
812; SI-NEXT:    s_and_b64 vcc, exec, vcc
813; SI-NEXT:    s_cbranch_vccz BB11_5
814; SI-NEXT:  ; %bb.4: ; %bb10
815; SI-NEXT:    s_mov_b32 s3, 0xf000
816; SI-NEXT:    s_mov_b32 s2, -1
817; SI-NEXT:    v_mov_b32_e32 v0, 9
818; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
819; SI-NEXT:    s_waitcnt vmcnt(0)
820; SI-NEXT:  BB11_5: ; %end
821; SI-NEXT:    s_endpgm
822; SI-NEXT:  BB11_6:
823; SI-NEXT:    s_mov_b64 exec, 0
824; SI-NEXT:    exp null off, off, off, off done vm
825; SI-NEXT:    s_endpgm
826;
827; GFX10-WAVE64-LABEL: phi_use_def_before_kill:
828; GFX10-WAVE64:       ; %bb.0: ; %bb
829; GFX10-WAVE64-NEXT:    v_add_f32_e64 v1, s0, 1.0
830; GFX10-WAVE64-NEXT:    v_cmp_lt_f32_e32 vcc, 0, v1
831; GFX10-WAVE64-NEXT:    v_cndmask_b32_e64 v0, 0, -1.0, vcc
832; GFX10-WAVE64-NEXT:    v_cmp_nlt_f32_e32 vcc, 0, v1
833; GFX10-WAVE64-NEXT:    s_andn2_b64 exec, exec, vcc
834; GFX10-WAVE64-NEXT:    s_cbranch_scc0 BB11_6
835; GFX10-WAVE64-NEXT:  ; %bb.1: ; %bb
836; GFX10-WAVE64-NEXT:    s_andn2_b64 exec, exec, vcc
837; GFX10-WAVE64-NEXT:    s_cbranch_scc0 BB11_3
838; GFX10-WAVE64-NEXT:  ; %bb.2: ; %bb8
839; GFX10-WAVE64-NEXT:    v_mov_b32_e32 v1, 8
840; GFX10-WAVE64-NEXT:    v_mov_b32_e32 v0, 4.0
841; GFX10-WAVE64-NEXT:    global_store_dword v[0:1], v1, off
842; GFX10-WAVE64-NEXT:    s_waitcnt_vscnt null, 0x0
843; GFX10-WAVE64-NEXT:  BB11_3: ; %phibb
844; GFX10-WAVE64-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v0
845; GFX10-WAVE64-NEXT:    s_and_b64 vcc, exec, vcc
846; GFX10-WAVE64-NEXT:    s_cbranch_vccz BB11_5
847; GFX10-WAVE64-NEXT:  ; %bb.4: ; %bb10
848; GFX10-WAVE64-NEXT:    v_mov_b32_e32 v0, 9
849; GFX10-WAVE64-NEXT:    global_store_dword v[0:1], v0, off
850; GFX10-WAVE64-NEXT:    s_waitcnt_vscnt null, 0x0
851; GFX10-WAVE64-NEXT:  BB11_5: ; %end
852; GFX10-WAVE64-NEXT:    s_endpgm
853; GFX10-WAVE64-NEXT:  BB11_6:
854; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
855; GFX10-WAVE64-NEXT:    exp null off, off, off, off done vm
856; GFX10-WAVE64-NEXT:    s_endpgm
857;
858; GFX10-WAVE32-LABEL: phi_use_def_before_kill:
859; GFX10-WAVE32:       ; %bb.0: ; %bb
860; GFX10-WAVE32-NEXT:    v_add_f32_e64 v1, s0, 1.0
861; GFX10-WAVE32-NEXT:    v_cmp_lt_f32_e32 vcc_lo, 0, v1
862; GFX10-WAVE32-NEXT:    v_cndmask_b32_e64 v0, 0, -1.0, vcc_lo
863; GFX10-WAVE32-NEXT:    v_cmp_nlt_f32_e32 vcc_lo, 0, v1
864; GFX10-WAVE32-NEXT:    s_andn2_b32 exec_lo, exec_lo, vcc_lo
865; GFX10-WAVE32-NEXT:    s_cbranch_scc0 BB11_6
866; GFX10-WAVE32-NEXT:  ; %bb.1: ; %bb
867; GFX10-WAVE32-NEXT:    s_andn2_b32 exec_lo, exec_lo, vcc_lo
868; GFX10-WAVE32-NEXT:    s_cbranch_scc0 BB11_3
869; GFX10-WAVE32-NEXT:  ; %bb.2: ; %bb8
870; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v1, 8
871; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v0, 4.0
872; GFX10-WAVE32-NEXT:    global_store_dword v[0:1], v1, off
873; GFX10-WAVE32-NEXT:    s_waitcnt_vscnt null, 0x0
874; GFX10-WAVE32-NEXT:  BB11_3: ; %phibb
875; GFX10-WAVE32-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v0
876; GFX10-WAVE32-NEXT:    s_and_b32 vcc_lo, exec_lo, vcc_lo
877; GFX10-WAVE32-NEXT:    s_cbranch_vccz BB11_5
878; GFX10-WAVE32-NEXT:  ; %bb.4: ; %bb10
879; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v0, 9
880; GFX10-WAVE32-NEXT:    global_store_dword v[0:1], v0, off
881; GFX10-WAVE32-NEXT:    s_waitcnt_vscnt null, 0x0
882; GFX10-WAVE32-NEXT:  BB11_5: ; %end
883; GFX10-WAVE32-NEXT:    s_endpgm
884; GFX10-WAVE32-NEXT:  BB11_6:
885; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
886; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
887; GFX10-WAVE32-NEXT:    s_endpgm
888bb:
889  %tmp = fadd float %x, 1.000000e+00
890  %tmp1 = fcmp olt float 0.000000e+00, %tmp
891  %tmp2 = select i1 %tmp1, float -1.000000e+00, float 0.000000e+00
892  %cmp.tmp2 = fcmp olt float %tmp2, 0.0
893  call void @llvm.amdgcn.kill(i1 %cmp.tmp2)
894  br i1 undef, label %phibb, label %bb8
895
896phibb:
897  %tmp5 = phi float [ %tmp2, %bb ], [ 4.0, %bb8 ]
898  %tmp6 = fcmp oeq float %tmp5, 0.000000e+00
899  br i1 %tmp6, label %bb10, label %end
900
901bb8:
902  store volatile i32 8, i32 addrspace(1)* undef
903  br label %phibb
904
905bb10:
906  store volatile i32 9, i32 addrspace(1)* undef
907  br label %end
908
909end:
910  ret void
911}
912
913define amdgpu_ps void @no_skip_no_successors(float inreg %arg, float inreg %arg1) #0 {
914; SI-LABEL: no_skip_no_successors:
915; SI:       ; %bb.0: ; %bb
916; SI-NEXT:    v_cmp_nge_f32_e64 s[4:5], s1, 0
917; SI-NEXT:    s_and_b64 vcc, exec, s[4:5]
918; SI-NEXT:    s_cbranch_vccz BB12_3
919; SI-NEXT:  ; %bb.1: ; %bb6
920; SI-NEXT:    s_mov_b64 s[2:3], exec
921; SI-NEXT:    s_andn2_b64 s[2:3], s[2:3], exec
922; SI-NEXT:    s_cbranch_scc0 BB12_5
923; SI-NEXT:  ; %bb.2: ; %bb6
924; SI-NEXT:    s_mov_b64 exec, 0
925; SI-NEXT:  BB12_3: ; %bb3
926; SI-NEXT:    v_mov_b32_e32 v0, 0x3e7ae148
927; SI-NEXT:    v_cmp_nge_f32_e32 vcc, s0, v0
928; SI-NEXT:    s_and_b64 vcc, exec, vcc
929; SI-NEXT:  ; %bb.4: ; %bb5
930; SI-NEXT:  BB12_5:
931; SI-NEXT:    s_mov_b64 exec, 0
932; SI-NEXT:    exp null off, off, off, off done vm
933; SI-NEXT:    s_endpgm
934;
935; GFX10-WAVE64-LABEL: no_skip_no_successors:
936; GFX10-WAVE64:       ; %bb.0: ; %bb
937; GFX10-WAVE64-NEXT:    v_cmp_nge_f32_e64 s[4:5], s1, 0
938; GFX10-WAVE64-NEXT:    s_and_b64 vcc, exec, s[4:5]
939; GFX10-WAVE64-NEXT:    s_cbranch_vccz BB12_3
940; GFX10-WAVE64-NEXT:  ; %bb.1: ; %bb6
941; GFX10-WAVE64-NEXT:    s_mov_b64 s[2:3], exec
942; GFX10-WAVE64-NEXT:    s_andn2_b64 s[2:3], s[2:3], exec
943; GFX10-WAVE64-NEXT:    s_cbranch_scc0 BB12_5
944; GFX10-WAVE64-NEXT:  ; %bb.2: ; %bb6
945; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
946; GFX10-WAVE64-NEXT:  BB12_3: ; %bb3
947; GFX10-WAVE64-NEXT:    v_cmp_nle_f32_e64 s[0:1], 0x3e7ae148, s0
948; GFX10-WAVE64-NEXT:    s_and_b64 vcc, exec, s[0:1]
949; GFX10-WAVE64-NEXT:  ; %bb.4: ; %bb5
950; GFX10-WAVE64-NEXT:  BB12_5:
951; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
952; GFX10-WAVE64-NEXT:    exp null off, off, off, off done vm
953; GFX10-WAVE64-NEXT:    s_endpgm
954;
955; GFX10-WAVE32-LABEL: no_skip_no_successors:
956; GFX10-WAVE32:       ; %bb.0: ; %bb
957; GFX10-WAVE32-NEXT:    v_cmp_nge_f32_e64 s1, s1, 0
958; GFX10-WAVE32-NEXT:    s_and_b32 vcc_lo, exec_lo, s1
959; GFX10-WAVE32-NEXT:    s_cbranch_vccz BB12_3
960; GFX10-WAVE32-NEXT:  ; %bb.1: ; %bb6
961; GFX10-WAVE32-NEXT:    s_mov_b32 s2, exec_lo
962; GFX10-WAVE32-NEXT:    s_andn2_b32 s2, s2, exec_lo
963; GFX10-WAVE32-NEXT:    s_cbranch_scc0 BB12_5
964; GFX10-WAVE32-NEXT:  ; %bb.2: ; %bb6
965; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
966; GFX10-WAVE32-NEXT:  BB12_3: ; %bb3
967; GFX10-WAVE32-NEXT:    v_cmp_nle_f32_e64 s0, 0x3e7ae148, s0
968; GFX10-WAVE32-NEXT:    s_and_b32 vcc_lo, exec_lo, s0
969; GFX10-WAVE32-NEXT:  ; %bb.4: ; %bb5
970; GFX10-WAVE32-NEXT:  BB12_5:
971; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
972; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
973; GFX10-WAVE32-NEXT:    s_endpgm
974bb:
975  %tmp = fcmp ult float %arg1, 0.000000e+00
976  %tmp2 = fcmp ult float %arg, 0x3FCF5C2900000000
977  br i1 %tmp, label %bb6, label %bb3
978
979bb3:                                              ; preds = %bb
980  br i1 %tmp2, label %bb5, label %bb4
981
982bb4:                                              ; preds = %bb3
983  br i1 true, label %bb5, label %bb7
984
985bb5:                                              ; preds = %bb4, %bb3
986  unreachable
987
988bb6:                                              ; preds = %bb
989  call void @llvm.amdgcn.kill(i1 false)
990  unreachable
991
992bb7:                                              ; preds = %bb4
993  ret void
994}
995
996define amdgpu_ps void @if_after_kill_block(float %arg, float %arg1, float %arg2, float %arg3) #0 {
997; SI-LABEL: if_after_kill_block:
998; SI:       ; %bb.0: ; %bb
999; SI-NEXT:    s_mov_b64 s[2:3], exec
1000; SI-NEXT:    s_wqm_b64 exec, exec
1001; SI-NEXT:    s_mov_b32 s0, 0
1002; SI-NEXT:    v_cmp_nle_f32_e32 vcc, 0, v1
1003; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1004; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
1005; SI-NEXT:    s_cbranch_execz BB13_3
1006; SI-NEXT:  ; %bb.1: ; %bb3
1007; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v0
1008; SI-NEXT:    s_andn2_b64 s[2:3], s[2:3], vcc
1009; SI-NEXT:    s_cbranch_scc0 BB13_6
1010; SI-NEXT:  ; %bb.2: ; %bb3
1011; SI-NEXT:    s_andn2_b64 exec, exec, vcc
1012; SI-NEXT:  BB13_3: ; %bb4
1013; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
1014; SI-NEXT:    s_mov_b32 s1, s0
1015; SI-NEXT:    s_mov_b32 s2, s0
1016; SI-NEXT:    s_mov_b32 s3, s0
1017; SI-NEXT:    s_mov_b32 s4, s0
1018; SI-NEXT:    s_mov_b32 s5, s0
1019; SI-NEXT:    s_mov_b32 s6, s0
1020; SI-NEXT:    s_mov_b32 s7, s0
1021; SI-NEXT:    image_sample_c v0, v[2:3], s[0:7], s[0:3] dmask:0x10
1022; SI-NEXT:    s_waitcnt vmcnt(0)
1023; SI-NEXT:    v_cmp_neq_f32_e32 vcc, 0, v0
1024; SI-NEXT:    s_and_saveexec_b64 s[0:1], vcc
1025; SI-NEXT:    s_cbranch_execz BB13_5
1026; SI-NEXT:  ; %bb.4: ; %bb8
1027; SI-NEXT:    s_mov_b32 s3, 0xf000
1028; SI-NEXT:    s_mov_b32 s2, -1
1029; SI-NEXT:    v_mov_b32_e32 v0, 9
1030; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
1031; SI-NEXT:    s_waitcnt vmcnt(0)
1032; SI-NEXT:  BB13_5: ; %UnifiedReturnBlock
1033; SI-NEXT:    s_endpgm
1034; SI-NEXT:  BB13_6:
1035; SI-NEXT:    s_mov_b64 exec, 0
1036; SI-NEXT:    exp null off, off, off, off done vm
1037; SI-NEXT:    s_endpgm
1038;
1039; GFX10-WAVE64-LABEL: if_after_kill_block:
1040; GFX10-WAVE64:       ; %bb.0: ; %bb
1041; GFX10-WAVE64-NEXT:    s_mov_b64 s[2:3], exec
1042; GFX10-WAVE64-NEXT:    s_wqm_b64 exec, exec
1043; GFX10-WAVE64-NEXT:    v_cmp_nle_f32_e32 vcc, 0, v1
1044; GFX10-WAVE64-NEXT:    s_mov_b32 s0, 0
1045; GFX10-WAVE64-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1046; GFX10-WAVE64-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
1047; GFX10-WAVE64-NEXT:    s_cbranch_execz BB13_3
1048; GFX10-WAVE64-NEXT:  ; %bb.1: ; %bb3
1049; GFX10-WAVE64-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v0
1050; GFX10-WAVE64-NEXT:    s_andn2_b64 s[2:3], s[2:3], vcc
1051; GFX10-WAVE64-NEXT:    s_cbranch_scc0 BB13_6
1052; GFX10-WAVE64-NEXT:  ; %bb.2: ; %bb3
1053; GFX10-WAVE64-NEXT:    s_andn2_b64 exec, exec, vcc
1054; GFX10-WAVE64-NEXT:  BB13_3: ; %bb4
1055; GFX10-WAVE64-NEXT:    s_or_b64 exec, exec, s[4:5]
1056; GFX10-WAVE64-NEXT:    s_mov_b32 s1, s0
1057; GFX10-WAVE64-NEXT:    s_mov_b32 s2, s0
1058; GFX10-WAVE64-NEXT:    s_mov_b32 s3, s0
1059; GFX10-WAVE64-NEXT:    s_mov_b32 s4, s0
1060; GFX10-WAVE64-NEXT:    s_mov_b32 s5, s0
1061; GFX10-WAVE64-NEXT:    s_mov_b32 s6, s0
1062; GFX10-WAVE64-NEXT:    s_mov_b32 s7, s0
1063; GFX10-WAVE64-NEXT:    image_sample_c v0, v[2:3], s[0:7], s[0:3] dmask:0x10 dim:SQ_RSRC_IMG_1D
1064; GFX10-WAVE64-NEXT:    s_waitcnt vmcnt(0)
1065; GFX10-WAVE64-NEXT:    v_cmp_neq_f32_e32 vcc, 0, v0
1066; GFX10-WAVE64-NEXT:    s_and_saveexec_b64 s[0:1], vcc
1067; GFX10-WAVE64-NEXT:    s_cbranch_execz BB13_5
1068; GFX10-WAVE64-NEXT:  ; %bb.4: ; %bb8
1069; GFX10-WAVE64-NEXT:    v_mov_b32_e32 v0, 9
1070; GFX10-WAVE64-NEXT:    global_store_dword v[0:1], v0, off
1071; GFX10-WAVE64-NEXT:    s_waitcnt_vscnt null, 0x0
1072; GFX10-WAVE64-NEXT:  BB13_5: ; %UnifiedReturnBlock
1073; GFX10-WAVE64-NEXT:    s_endpgm
1074; GFX10-WAVE64-NEXT:  BB13_6:
1075; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
1076; GFX10-WAVE64-NEXT:    exp null off, off, off, off done vm
1077; GFX10-WAVE64-NEXT:    s_endpgm
1078;
1079; GFX10-WAVE32-LABEL: if_after_kill_block:
1080; GFX10-WAVE32:       ; %bb.0: ; %bb
1081; GFX10-WAVE32-NEXT:    s_mov_b32 s1, exec_lo
1082; GFX10-WAVE32-NEXT:    s_wqm_b32 exec_lo, exec_lo
1083; GFX10-WAVE32-NEXT:    v_cmp_nle_f32_e32 vcc_lo, 0, v1
1084; GFX10-WAVE32-NEXT:    s_mov_b32 s0, 0
1085; GFX10-WAVE32-NEXT:    s_and_saveexec_b32 s2, vcc_lo
1086; GFX10-WAVE32-NEXT:    s_xor_b32 s2, exec_lo, s2
1087; GFX10-WAVE32-NEXT:    s_cbranch_execz BB13_3
1088; GFX10-WAVE32-NEXT:  ; %bb.1: ; %bb3
1089; GFX10-WAVE32-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, 0, v0
1090; GFX10-WAVE32-NEXT:    s_andn2_b32 s1, s1, vcc_lo
1091; GFX10-WAVE32-NEXT:    s_cbranch_scc0 BB13_6
1092; GFX10-WAVE32-NEXT:  ; %bb.2: ; %bb3
1093; GFX10-WAVE32-NEXT:    s_andn2_b32 exec_lo, exec_lo, vcc_lo
1094; GFX10-WAVE32-NEXT:  BB13_3: ; %bb4
1095; GFX10-WAVE32-NEXT:    s_or_b32 exec_lo, exec_lo, s2
1096; GFX10-WAVE32-NEXT:    s_mov_b32 s1, s0
1097; GFX10-WAVE32-NEXT:    s_mov_b32 s2, s0
1098; GFX10-WAVE32-NEXT:    s_mov_b32 s3, s0
1099; GFX10-WAVE32-NEXT:    s_mov_b32 s4, s0
1100; GFX10-WAVE32-NEXT:    s_mov_b32 s5, s0
1101; GFX10-WAVE32-NEXT:    s_mov_b32 s6, s0
1102; GFX10-WAVE32-NEXT:    s_mov_b32 s7, s0
1103; GFX10-WAVE32-NEXT:    image_sample_c v0, v[2:3], s[0:7], s[0:3] dmask:0x10 dim:SQ_RSRC_IMG_1D
1104; GFX10-WAVE32-NEXT:    s_waitcnt vmcnt(0)
1105; GFX10-WAVE32-NEXT:    v_cmp_neq_f32_e32 vcc_lo, 0, v0
1106; GFX10-WAVE32-NEXT:    s_and_saveexec_b32 s0, vcc_lo
1107; GFX10-WAVE32-NEXT:    s_cbranch_execz BB13_5
1108; GFX10-WAVE32-NEXT:  ; %bb.4: ; %bb8
1109; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v0, 9
1110; GFX10-WAVE32-NEXT:    global_store_dword v[0:1], v0, off
1111; GFX10-WAVE32-NEXT:    s_waitcnt_vscnt null, 0x0
1112; GFX10-WAVE32-NEXT:  BB13_5: ; %UnifiedReturnBlock
1113; GFX10-WAVE32-NEXT:    s_endpgm
1114; GFX10-WAVE32-NEXT:  BB13_6:
1115; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
1116; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
1117; GFX10-WAVE32-NEXT:    s_endpgm
1118bb:
1119  %tmp = fcmp ult float %arg1, 0.000000e+00
1120  br i1 %tmp, label %bb3, label %bb4
1121
1122bb3:                                              ; preds = %bb
1123  %cmp.arg = fcmp olt float %arg, 0.0
1124  call void @llvm.amdgcn.kill(i1 %cmp.arg)
1125  br label %bb4
1126
1127bb4:                                              ; preds = %bb3, %bb
1128  %tmp5 = call <4 x float> @llvm.amdgcn.image.sample.c.1d.v4f32.f32(i32 16, float %arg2, float %arg3, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
1129  %tmp6 = extractelement <4 x float> %tmp5, i32 0
1130  %tmp7 = fcmp une float %tmp6, 0.000000e+00
1131  br i1 %tmp7, label %bb8, label %bb9
1132
1133bb8:                                              ; preds = %bb9, %bb4
1134  store volatile i32 9, i32 addrspace(1)* undef
1135  ret void
1136
1137bb9:                                              ; preds = %bb4
1138  ret void
1139}
1140
1141define amdgpu_ps void @cbranch_kill(i32 inreg %0, float %val0, float %val1) {
1142; SI-LABEL: cbranch_kill:
1143; SI:       ; %bb.0: ; %.entry
1144; SI-NEXT:    s_mov_b32 s4, 0
1145; SI-NEXT:    s_mov_b64 s[0:1], exec
1146; SI-NEXT:    v_mov_b32_e32 v2, v1
1147; SI-NEXT:    v_mov_b32_e32 v3, v1
1148; SI-NEXT:    s_mov_b32 s5, s4
1149; SI-NEXT:    s_mov_b32 s6, s4
1150; SI-NEXT:    s_mov_b32 s7, s4
1151; SI-NEXT:    s_mov_b32 s8, s4
1152; SI-NEXT:    s_mov_b32 s9, s4
1153; SI-NEXT:    s_mov_b32 s10, s4
1154; SI-NEXT:    s_mov_b32 s11, s4
1155; SI-NEXT:    image_sample_lz v1, v[1:3], s[4:11], s[0:3] dmask:0x1 da
1156; SI-NEXT:    s_waitcnt vmcnt(0)
1157; SI-NEXT:    v_cmp_ge_f32_e32 vcc, 0, v1
1158; SI-NEXT:    s_and_saveexec_b64 s[2:3], vcc
1159; SI-NEXT:    s_xor_b64 s[2:3], exec, s[2:3]
1160; SI-NEXT:    s_cbranch_execz BB14_3
1161; SI-NEXT:  ; %bb.1: ; %kill
1162; SI-NEXT:    s_andn2_b64 s[0:1], s[0:1], exec
1163; SI-NEXT:    s_cbranch_scc0 BB14_6
1164; SI-NEXT:  ; %bb.2: ; %kill
1165; SI-NEXT:    s_mov_b64 exec, 0
1166; SI-NEXT:  BB14_3: ; %Flow
1167; SI-NEXT:    s_or_saveexec_b64 s[0:1], s[2:3]
1168; SI-NEXT:    ; implicit-def: $vgpr2
1169; SI-NEXT:    s_xor_b64 exec, exec, s[0:1]
1170; SI-NEXT:  ; %bb.4: ; %live
1171; SI-NEXT:    v_mul_f32_e32 v2, v0, v1
1172; SI-NEXT:  ; %bb.5: ; %export
1173; SI-NEXT:    s_or_b64 exec, exec, s[0:1]
1174; SI-NEXT:    exp mrt0 v2, v2, v2, v2 done vm
1175; SI-NEXT:    s_endpgm
1176; SI-NEXT:  BB14_6:
1177; SI-NEXT:    s_mov_b64 exec, 0
1178; SI-NEXT:    exp null off, off, off, off done vm
1179; SI-NEXT:    s_endpgm
1180;
1181; GFX10-WAVE64-LABEL: cbranch_kill:
1182; GFX10-WAVE64:       ; %bb.0: ; %.entry
1183; GFX10-WAVE64-NEXT:    s_mov_b32 s4, 0
1184; GFX10-WAVE64-NEXT:    s_mov_b64 s[0:1], exec
1185; GFX10-WAVE64-NEXT:    s_mov_b32 s5, s4
1186; GFX10-WAVE64-NEXT:    s_mov_b32 s6, s4
1187; GFX10-WAVE64-NEXT:    s_mov_b32 s7, s4
1188; GFX10-WAVE64-NEXT:    s_mov_b32 s8, s4
1189; GFX10-WAVE64-NEXT:    s_mov_b32 s9, s4
1190; GFX10-WAVE64-NEXT:    s_mov_b32 s10, s4
1191; GFX10-WAVE64-NEXT:    s_mov_b32 s11, s4
1192; GFX10-WAVE64-NEXT:    image_sample_lz v1, [v1, v1, v1], s[4:11], s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
1193; GFX10-WAVE64-NEXT:    s_waitcnt vmcnt(0)
1194; GFX10-WAVE64-NEXT:    v_cmp_ge_f32_e32 vcc, 0, v1
1195; GFX10-WAVE64-NEXT:    s_and_saveexec_b64 s[2:3], vcc
1196; GFX10-WAVE64-NEXT:    s_xor_b64 s[2:3], exec, s[2:3]
1197; GFX10-WAVE64-NEXT:    s_cbranch_execz BB14_3
1198; GFX10-WAVE64-NEXT:  ; %bb.1: ; %kill
1199; GFX10-WAVE64-NEXT:    s_andn2_b64 s[0:1], s[0:1], exec
1200; GFX10-WAVE64-NEXT:    s_cbranch_scc0 BB14_6
1201; GFX10-WAVE64-NEXT:  ; %bb.2: ; %kill
1202; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
1203; GFX10-WAVE64-NEXT:  BB14_3: ; %Flow
1204; GFX10-WAVE64-NEXT:    s_or_saveexec_b64 s[0:1], s[2:3]
1205; GFX10-WAVE64-NEXT:    ; implicit-def: $vgpr2
1206; GFX10-WAVE64-NEXT:    s_xor_b64 exec, exec, s[0:1]
1207; GFX10-WAVE64-NEXT:  ; %bb.4: ; %live
1208; GFX10-WAVE64-NEXT:    v_mul_f32_e32 v2, v0, v1
1209; GFX10-WAVE64-NEXT:  ; %bb.5: ; %export
1210; GFX10-WAVE64-NEXT:    s_or_b64 exec, exec, s[0:1]
1211; GFX10-WAVE64-NEXT:    exp mrt0 v2, v2, v2, v2 done vm
1212; GFX10-WAVE64-NEXT:    s_endpgm
1213; GFX10-WAVE64-NEXT:  BB14_6:
1214; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
1215; GFX10-WAVE64-NEXT:    exp null off, off, off, off done vm
1216; GFX10-WAVE64-NEXT:    s_endpgm
1217;
1218; GFX10-WAVE32-LABEL: cbranch_kill:
1219; GFX10-WAVE32:       ; %bb.0: ; %.entry
1220; GFX10-WAVE32-NEXT:    s_mov_b32 s4, 0
1221; GFX10-WAVE32-NEXT:    s_mov_b32 s0, exec_lo
1222; GFX10-WAVE32-NEXT:    s_mov_b32 s5, s4
1223; GFX10-WAVE32-NEXT:    s_mov_b32 s6, s4
1224; GFX10-WAVE32-NEXT:    s_mov_b32 s7, s4
1225; GFX10-WAVE32-NEXT:    s_mov_b32 s8, s4
1226; GFX10-WAVE32-NEXT:    s_mov_b32 s9, s4
1227; GFX10-WAVE32-NEXT:    s_mov_b32 s10, s4
1228; GFX10-WAVE32-NEXT:    s_mov_b32 s11, s4
1229; GFX10-WAVE32-NEXT:    image_sample_lz v1, [v1, v1, v1], s[4:11], s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
1230; GFX10-WAVE32-NEXT:    s_waitcnt vmcnt(0)
1231; GFX10-WAVE32-NEXT:    v_cmp_ge_f32_e32 vcc_lo, 0, v1
1232; GFX10-WAVE32-NEXT:    s_and_saveexec_b32 s1, vcc_lo
1233; GFX10-WAVE32-NEXT:    s_xor_b32 s1, exec_lo, s1
1234; GFX10-WAVE32-NEXT:    s_cbranch_execz BB14_3
1235; GFX10-WAVE32-NEXT:  ; %bb.1: ; %kill
1236; GFX10-WAVE32-NEXT:    s_andn2_b32 s0, s0, exec_lo
1237; GFX10-WAVE32-NEXT:    s_cbranch_scc0 BB14_6
1238; GFX10-WAVE32-NEXT:  ; %bb.2: ; %kill
1239; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
1240; GFX10-WAVE32-NEXT:  BB14_3: ; %Flow
1241; GFX10-WAVE32-NEXT:    s_or_saveexec_b32 s0, s1
1242; GFX10-WAVE32-NEXT:    ; implicit-def: $vgpr2
1243; GFX10-WAVE32-NEXT:    s_xor_b32 exec_lo, exec_lo, s0
1244; GFX10-WAVE32-NEXT:  ; %bb.4: ; %live
1245; GFX10-WAVE32-NEXT:    v_mul_f32_e32 v2, v0, v1
1246; GFX10-WAVE32-NEXT:  ; %bb.5: ; %export
1247; GFX10-WAVE32-NEXT:    s_or_b32 exec_lo, exec_lo, s0
1248; GFX10-WAVE32-NEXT:    exp mrt0 v2, v2, v2, v2 done vm
1249; GFX10-WAVE32-NEXT:    s_endpgm
1250; GFX10-WAVE32-NEXT:  BB14_6:
1251; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
1252; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
1253; GFX10-WAVE32-NEXT:    s_endpgm
1254.entry:
1255  %sample = call float @llvm.amdgcn.image.sample.l.2darray.f32.f32(i32 1, float %val1, float %val1, float %val1, float 0.000000e+00, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
1256  %cond0 = fcmp ugt float %sample, 0.000000e+00
1257  br i1 %cond0, label %live, label %kill
1258
1259kill:
1260  call void @llvm.amdgcn.kill(i1 false)
1261  br label %export
1262
1263live:
1264  %scale = fmul reassoc nnan nsz arcp contract float %val0, %sample
1265  br label %export
1266
1267export:
1268  %proxy = phi float [ undef, %kill ], [ %scale, %live ]
1269  call void @llvm.amdgcn.exp.f32(i32 immarg 0, i32 immarg 15, float %proxy, float %proxy, float %proxy, float %proxy, i1 immarg true, i1 immarg true) #3
1270  ret void
1271}
1272
1273
1274define amdgpu_ps void @complex_loop(i32 inreg %cmpa, i32 %cmpb, i32 %cmpc) {
1275; SI-LABEL: complex_loop:
1276; SI:       ; %bb.0: ; %.entry
1277; SI-NEXT:    s_cmp_lt_i32 s0, 1
1278; SI-NEXT:    v_mov_b32_e32 v2, -1
1279; SI-NEXT:    s_cbranch_scc1 BB15_7
1280; SI-NEXT:  ; %bb.1: ; %.lr.ph
1281; SI-NEXT:    s_mov_b64 s[2:3], exec
1282; SI-NEXT:    s_mov_b32 s4, 0
1283; SI-NEXT:    s_mov_b64 s[0:1], 0
1284; SI-NEXT:    s_branch BB15_3
1285; SI-NEXT:  BB15_2: ; %latch
1286; SI-NEXT:    ; in Loop: Header=BB15_3 Depth=1
1287; SI-NEXT:    s_or_b64 exec, exec, s[6:7]
1288; SI-NEXT:    s_add_i32 s4, s4, 1
1289; SI-NEXT:    v_cmp_ge_i32_e32 vcc, s4, v1
1290; SI-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
1291; SI-NEXT:    v_mov_b32_e32 v2, s4
1292; SI-NEXT:    s_andn2_b64 exec, exec, s[0:1]
1293; SI-NEXT:    s_cbranch_execz BB15_6
1294; SI-NEXT:  BB15_3: ; %hdr
1295; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
1296; SI-NEXT:    v_cmp_gt_u32_e32 vcc, s4, v0
1297; SI-NEXT:    s_and_saveexec_b64 s[6:7], vcc
1298; SI-NEXT:    s_xor_b64 s[6:7], exec, s[6:7]
1299; SI-NEXT:    s_cbranch_execz BB15_2
1300; SI-NEXT:  ; %bb.4: ; %kill
1301; SI-NEXT:    ; in Loop: Header=BB15_3 Depth=1
1302; SI-NEXT:    s_andn2_b64 s[2:3], s[2:3], exec
1303; SI-NEXT:    s_cbranch_scc0 BB15_8
1304; SI-NEXT:  ; %bb.5: ; %kill
1305; SI-NEXT:    ; in Loop: Header=BB15_3 Depth=1
1306; SI-NEXT:    s_mov_b64 exec, 0
1307; SI-NEXT:    s_branch BB15_2
1308; SI-NEXT:  BB15_6: ; %Flow
1309; SI-NEXT:    s_or_b64 exec, exec, s[0:1]
1310; SI-NEXT:  BB15_7: ; %._crit_edge
1311; SI-NEXT:    exp mrt0 v2, v2, v0, v0 done vm
1312; SI-NEXT:    s_endpgm
1313; SI-NEXT:  BB15_8:
1314; SI-NEXT:    s_mov_b64 exec, 0
1315; SI-NEXT:    exp null off, off, off, off done vm
1316; SI-NEXT:    s_endpgm
1317;
1318; GFX10-WAVE64-LABEL: complex_loop:
1319; GFX10-WAVE64:       ; %bb.0: ; %.entry
1320; GFX10-WAVE64-NEXT:    v_mov_b32_e32 v2, -1
1321; GFX10-WAVE64-NEXT:    s_cmp_lt_i32 s0, 1
1322; GFX10-WAVE64-NEXT:    s_cbranch_scc1 BB15_7
1323; GFX10-WAVE64-NEXT:  ; %bb.1: ; %.lr.ph
1324; GFX10-WAVE64-NEXT:    s_mov_b64 s[2:3], exec
1325; GFX10-WAVE64-NEXT:    s_mov_b32 s4, 0
1326; GFX10-WAVE64-NEXT:    s_mov_b64 s[0:1], 0
1327; GFX10-WAVE64-NEXT:    s_branch BB15_3
1328; GFX10-WAVE64-NEXT:  BB15_2: ; %latch
1329; GFX10-WAVE64-NEXT:    ; in Loop: Header=BB15_3 Depth=1
1330; GFX10-WAVE64-NEXT:    s_or_b64 exec, exec, s[6:7]
1331; GFX10-WAVE64-NEXT:    s_add_i32 s4, s4, 1
1332; GFX10-WAVE64-NEXT:    v_cmp_ge_i32_e32 vcc, s4, v1
1333; GFX10-WAVE64-NEXT:    v_mov_b32_e32 v2, s4
1334; GFX10-WAVE64-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
1335; GFX10-WAVE64-NEXT:    s_andn2_b64 exec, exec, s[0:1]
1336; GFX10-WAVE64-NEXT:    s_cbranch_execz BB15_6
1337; GFX10-WAVE64-NEXT:  BB15_3: ; %hdr
1338; GFX10-WAVE64-NEXT:    ; =>This Inner Loop Header: Depth=1
1339; GFX10-WAVE64-NEXT:    v_cmp_gt_u32_e32 vcc, s4, v0
1340; GFX10-WAVE64-NEXT:    s_and_saveexec_b64 s[6:7], vcc
1341; GFX10-WAVE64-NEXT:    s_xor_b64 s[6:7], exec, s[6:7]
1342; GFX10-WAVE64-NEXT:    s_cbranch_execz BB15_2
1343; GFX10-WAVE64-NEXT:  ; %bb.4: ; %kill
1344; GFX10-WAVE64-NEXT:    ; in Loop: Header=BB15_3 Depth=1
1345; GFX10-WAVE64-NEXT:    s_andn2_b64 s[2:3], s[2:3], exec
1346; GFX10-WAVE64-NEXT:    s_cbranch_scc0 BB15_8
1347; GFX10-WAVE64-NEXT:  ; %bb.5: ; %kill
1348; GFX10-WAVE64-NEXT:    ; in Loop: Header=BB15_3 Depth=1
1349; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
1350; GFX10-WAVE64-NEXT:    s_branch BB15_2
1351; GFX10-WAVE64-NEXT:  BB15_6: ; %Flow
1352; GFX10-WAVE64-NEXT:    s_or_b64 exec, exec, s[0:1]
1353; GFX10-WAVE64-NEXT:  BB15_7: ; %._crit_edge
1354; GFX10-WAVE64-NEXT:    exp mrt0 v2, v2, v0, v0 done vm
1355; GFX10-WAVE64-NEXT:    s_endpgm
1356; GFX10-WAVE64-NEXT:  BB15_8:
1357; GFX10-WAVE64-NEXT:    s_mov_b64 exec, 0
1358; GFX10-WAVE64-NEXT:    exp null off, off, off, off done vm
1359; GFX10-WAVE64-NEXT:    s_endpgm
1360;
1361; GFX10-WAVE32-LABEL: complex_loop:
1362; GFX10-WAVE32:       ; %bb.0: ; %.entry
1363; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v2, -1
1364; GFX10-WAVE32-NEXT:    s_cmp_lt_i32 s0, 1
1365; GFX10-WAVE32-NEXT:    s_cbranch_scc1 BB15_7
1366; GFX10-WAVE32-NEXT:  ; %bb.1: ; %.lr.ph
1367; GFX10-WAVE32-NEXT:    s_mov_b32 s1, exec_lo
1368; GFX10-WAVE32-NEXT:    s_mov_b32 s0, 0
1369; GFX10-WAVE32-NEXT:    s_mov_b32 s2, 0
1370; GFX10-WAVE32-NEXT:    s_branch BB15_3
1371; GFX10-WAVE32-NEXT:  BB15_2: ; %latch
1372; GFX10-WAVE32-NEXT:    ; in Loop: Header=BB15_3 Depth=1
1373; GFX10-WAVE32-NEXT:    s_or_b32 exec_lo, exec_lo, s3
1374; GFX10-WAVE32-NEXT:    s_add_i32 s2, s2, 1
1375; GFX10-WAVE32-NEXT:    v_cmp_ge_i32_e32 vcc_lo, s2, v1
1376; GFX10-WAVE32-NEXT:    v_mov_b32_e32 v2, s2
1377; GFX10-WAVE32-NEXT:    s_or_b32 s0, vcc_lo, s0
1378; GFX10-WAVE32-NEXT:    s_andn2_b32 exec_lo, exec_lo, s0
1379; GFX10-WAVE32-NEXT:    s_cbranch_execz BB15_6
1380; GFX10-WAVE32-NEXT:  BB15_3: ; %hdr
1381; GFX10-WAVE32-NEXT:    ; =>This Inner Loop Header: Depth=1
1382; GFX10-WAVE32-NEXT:    v_cmp_gt_u32_e32 vcc_lo, s2, v0
1383; GFX10-WAVE32-NEXT:    s_and_saveexec_b32 s3, vcc_lo
1384; GFX10-WAVE32-NEXT:    s_xor_b32 s3, exec_lo, s3
1385; GFX10-WAVE32-NEXT:    s_cbranch_execz BB15_2
1386; GFX10-WAVE32-NEXT:  ; %bb.4: ; %kill
1387; GFX10-WAVE32-NEXT:    ; in Loop: Header=BB15_3 Depth=1
1388; GFX10-WAVE32-NEXT:    s_andn2_b32 s1, s1, exec_lo
1389; GFX10-WAVE32-NEXT:    s_cbranch_scc0 BB15_8
1390; GFX10-WAVE32-NEXT:  ; %bb.5: ; %kill
1391; GFX10-WAVE32-NEXT:    ; in Loop: Header=BB15_3 Depth=1
1392; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
1393; GFX10-WAVE32-NEXT:    s_branch BB15_2
1394; GFX10-WAVE32-NEXT:  BB15_6: ; %Flow
1395; GFX10-WAVE32-NEXT:    s_or_b32 exec_lo, exec_lo, s0
1396; GFX10-WAVE32-NEXT:  BB15_7: ; %._crit_edge
1397; GFX10-WAVE32-NEXT:    exp mrt0 v2, v2, v0, v0 done vm
1398; GFX10-WAVE32-NEXT:    s_endpgm
1399; GFX10-WAVE32-NEXT:  BB15_8:
1400; GFX10-WAVE32-NEXT:    s_mov_b32 exec_lo, 0
1401; GFX10-WAVE32-NEXT:    exp null off, off, off, off done vm
1402; GFX10-WAVE32-NEXT:    s_endpgm
1403.entry:
1404  %flaga = icmp sgt i32 %cmpa, 0
1405  br i1 %flaga, label %.lr.ph, label %._crit_edge
1406
1407.lr.ph:
1408  br label %hdr
1409
1410hdr:
1411  %ctr = phi i32 [ 0, %.lr.ph ], [ %ctr.next, %latch ]
1412  %flagb = icmp ugt i32 %ctr, %cmpb
1413  br i1 %flagb, label %kill, label %latch
1414
1415kill:
1416  call void @llvm.amdgcn.kill(i1 false)
1417  br label %latch
1418
1419latch:
1420  %ctr.next = add nuw nsw i32 %ctr, 1
1421  %flagc = icmp slt i32 %ctr.next, %cmpc
1422  br i1 %flagc, label %hdr, label %._crit_edge
1423
1424._crit_edge:
1425  %tmp = phi i32 [ -1, %.entry ], [ %ctr.next, %latch ]
1426  %out = bitcast i32 %tmp to float
1427  call void @llvm.amdgcn.exp.f32(i32 immarg 0, i32 immarg 15, float %out, float %out, float undef, float undef, i1 immarg true, i1 immarg true)
1428  ret void
1429}
1430
1431define void @skip_mode_switch(i32 %arg) {
1432; SI-LABEL: skip_mode_switch:
1433; SI:       ; %bb.0: ; %entry
1434; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1435; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
1436; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1437; SI-NEXT:    s_cbranch_execz BB16_2
1438; SI-NEXT:  ; %bb.1: ; %bb.0
1439; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3
1440; SI-NEXT:  BB16_2: ; %bb.1
1441; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
1442; SI-NEXT:    s_setpc_b64 s[30:31]
1443;
1444; GFX10-WAVE64-LABEL: skip_mode_switch:
1445; GFX10-WAVE64:       ; %bb.0: ; %entry
1446; GFX10-WAVE64-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1447; GFX10-WAVE64-NEXT:    s_waitcnt_vscnt null, 0x0
1448; GFX10-WAVE64-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
1449; GFX10-WAVE64-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1450; GFX10-WAVE64-NEXT:    s_cbranch_execz BB16_2
1451; GFX10-WAVE64-NEXT:  ; %bb.1: ; %bb.0
1452; GFX10-WAVE64-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3
1453; GFX10-WAVE64-NEXT:  BB16_2: ; %bb.1
1454; GFX10-WAVE64-NEXT:    s_or_b64 exec, exec, s[4:5]
1455; GFX10-WAVE64-NEXT:    s_setpc_b64 s[30:31]
1456;
1457; GFX10-WAVE32-LABEL: skip_mode_switch:
1458; GFX10-WAVE32:       ; %bb.0: ; %entry
1459; GFX10-WAVE32-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1460; GFX10-WAVE32-NEXT:    s_waitcnt_vscnt null, 0x0
1461; GFX10-WAVE32-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
1462; GFX10-WAVE32-NEXT:    s_and_saveexec_b32 s4, vcc_lo
1463; GFX10-WAVE32-NEXT:    s_cbranch_execz BB16_2
1464; GFX10-WAVE32-NEXT:  ; %bb.1: ; %bb.0
1465; GFX10-WAVE32-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3
1466; GFX10-WAVE32-NEXT:  BB16_2: ; %bb.1
1467; GFX10-WAVE32-NEXT:    s_or_b32 exec_lo, exec_lo, s4
1468; GFX10-WAVE32-NEXT:    s_setpc_b64 s[30:31]
1469entry:
1470  %cmp = icmp eq i32 %arg, 0
1471  br i1 %cmp, label %bb.0, label %bb.1
1472
1473bb.0:
1474  call void @llvm.amdgcn.s.setreg(i32 2049, i32 3)
1475  br label %bb.1
1476
1477bb.1:
1478  ret void
1479}
1480
1481declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg) #3
1482declare float @llvm.amdgcn.image.sample.l.2darray.f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1
1483declare <4 x float> @llvm.amdgcn.image.sample.c.1d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
1484declare void @llvm.amdgcn.kill(i1) #0
1485
1486declare void @llvm.amdgcn.s.setreg(i32 immarg, i32)
1487
1488attributes #0 = { nounwind }
1489attributes #1 = { nounwind readonly }
1490attributes #2 = { nounwind readnone speculatable }
1491attributes #3 = { inaccessiblememonly nounwind writeonly }
1492