1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,SI %s
3; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,GFX10 %s
4
5define amdgpu_ps void @test_kill_depth_0_imm_pos() #0 {
6; GCN-LABEL: test_kill_depth_0_imm_pos:
7; GCN:       ; %bb.0:
8; GCN-NEXT:  ; %bb.1:
9; GCN-NEXT:    s_endpgm
10  call void @llvm.amdgcn.kill(i1 true)
11  ret void
12}
13
14define amdgpu_ps void @test_kill_depth_0_imm_neg() #0 {
15; GCN-LABEL: test_kill_depth_0_imm_neg:
16; GCN:       ; %bb.0:
17; GCN-NEXT:    s_mov_b64 exec, 0
18; GCN-NEXT:    s_cbranch_execz BB1_2
19; GCN-NEXT:  ; %bb.1:
20; GCN-NEXT:    s_endpgm
21; GCN-NEXT:  BB1_2:
22; GCN-NEXT:    exp null off, off, off, off done vm
23; GCN-NEXT:    s_endpgm
24  call void @llvm.amdgcn.kill(i1 false)
25  ret void
26}
27
28; FIXME: Ideally only one early-exit would be emitted
29define amdgpu_ps void @test_kill_depth_0_imm_neg_x2() #0 {
30; GCN-LABEL: test_kill_depth_0_imm_neg_x2:
31; GCN:       ; %bb.0:
32; GCN-NEXT:    s_mov_b64 exec, 0
33; GCN-NEXT:    s_cbranch_execz BB2_3
34; GCN-NEXT:  ; %bb.1:
35; GCN-NEXT:    s_mov_b64 exec, 0
36; GCN-NEXT:    s_cbranch_execz BB2_3
37; GCN-NEXT:  ; %bb.2:
38; GCN-NEXT:    s_endpgm
39; GCN-NEXT:  BB2_3:
40; GCN-NEXT:    exp null off, off, off, off done vm
41; GCN-NEXT:    s_endpgm
42  call void @llvm.amdgcn.kill(i1 false)
43  call void @llvm.amdgcn.kill(i1 false)
44  ret void
45}
46
47define amdgpu_ps void @test_kill_depth_var(float %x) #0 {
48; SI-LABEL: test_kill_depth_var:
49; SI:       ; %bb.0:
50; SI-NEXT:    v_cmpx_gt_f32_e32 vcc, 0, v0
51; SI-NEXT:    s_cbranch_execz BB3_2
52; SI-NEXT:  ; %bb.1:
53; SI-NEXT:    s_endpgm
54; SI-NEXT:  BB3_2:
55; SI-NEXT:    exp null off, off, off, off done vm
56; SI-NEXT:    s_endpgm
57;
58; GFX10-LABEL: test_kill_depth_var:
59; GFX10:       ; %bb.0:
60; GFX10-NEXT:    v_cmpx_gt_f32_e32 0, v0
61; GFX10-NEXT:    s_cbranch_execz BB3_2
62; GFX10-NEXT:  ; %bb.1:
63; GFX10-NEXT:    s_endpgm
64; GFX10-NEXT:  BB3_2:
65; GFX10-NEXT:    exp null off, off, off, off done vm
66; GFX10-NEXT:    s_endpgm
67  %cmp = fcmp olt float %x, 0.0
68  call void @llvm.amdgcn.kill(i1 %cmp)
69  ret void
70}
71
72; FIXME: Ideally only one early-exit would be emitted
73define amdgpu_ps void @test_kill_depth_var_x2_same(float %x) #0 {
74; SI-LABEL: test_kill_depth_var_x2_same:
75; SI:       ; %bb.0:
76; SI-NEXT:    v_cmpx_gt_f32_e32 vcc, 0, v0
77; SI-NEXT:    s_cbranch_execz BB4_3
78; SI-NEXT:  ; %bb.1:
79; SI-NEXT:    v_cmpx_gt_f32_e32 vcc, 0, v0
80; SI-NEXT:    s_cbranch_execz BB4_3
81; SI-NEXT:  ; %bb.2:
82; SI-NEXT:    s_endpgm
83; SI-NEXT:  BB4_3:
84; SI-NEXT:    exp null off, off, off, off done vm
85; SI-NEXT:    s_endpgm
86;
87; GFX10-LABEL: test_kill_depth_var_x2_same:
88; GFX10:       ; %bb.0:
89; GFX10-NEXT:    v_cmpx_gt_f32_e32 0, v0
90; GFX10-NEXT:    s_cbranch_execz BB4_3
91; GFX10-NEXT:  ; %bb.1:
92; GFX10-NEXT:    s_waitcnt_depctr 0xfffe
93; GFX10-NEXT:    v_cmpx_gt_f32_e32 0, v0
94; GFX10-NEXT:    s_cbranch_execz BB4_3
95; GFX10-NEXT:  ; %bb.2:
96; GFX10-NEXT:    s_endpgm
97; GFX10-NEXT:  BB4_3:
98; GFX10-NEXT:    exp null off, off, off, off done vm
99; GFX10-NEXT:    s_endpgm
100  %cmp = fcmp olt float %x, 0.0
101  call void @llvm.amdgcn.kill(i1 %cmp)
102  call void @llvm.amdgcn.kill(i1 %cmp)
103  ret void
104}
105
106; FIXME: Ideally only one early-exit would be emitted
107define amdgpu_ps void @test_kill_depth_var_x2(float %x, float %y) #0 {
108; SI-LABEL: test_kill_depth_var_x2:
109; SI:       ; %bb.0:
110; SI-NEXT:    v_cmpx_gt_f32_e32 vcc, 0, v0
111; SI-NEXT:    s_cbranch_execz BB5_3
112; SI-NEXT:  ; %bb.1:
113; SI-NEXT:    v_cmpx_gt_f32_e32 vcc, 0, v1
114; SI-NEXT:    s_cbranch_execz BB5_3
115; SI-NEXT:  ; %bb.2:
116; SI-NEXT:    s_endpgm
117; SI-NEXT:  BB5_3:
118; SI-NEXT:    exp null off, off, off, off done vm
119; SI-NEXT:    s_endpgm
120;
121; GFX10-LABEL: test_kill_depth_var_x2:
122; GFX10:       ; %bb.0:
123; GFX10-NEXT:    v_cmpx_gt_f32_e32 0, v0
124; GFX10-NEXT:    s_cbranch_execz BB5_3
125; GFX10-NEXT:  ; %bb.1:
126; GFX10-NEXT:    s_waitcnt_depctr 0xfffe
127; GFX10-NEXT:    v_cmpx_gt_f32_e32 0, v1
128; GFX10-NEXT:    s_cbranch_execz BB5_3
129; GFX10-NEXT:  ; %bb.2:
130; GFX10-NEXT:    s_endpgm
131; GFX10-NEXT:  BB5_3:
132; GFX10-NEXT:    exp null off, off, off, off done vm
133; GFX10-NEXT:    s_endpgm
134  %cmp.x = fcmp olt float %x, 0.0
135  call void @llvm.amdgcn.kill(i1 %cmp.x)
136  %cmp.y = fcmp olt float %y, 0.0
137  call void @llvm.amdgcn.kill(i1 %cmp.y)
138  ret void
139}
140
141define amdgpu_ps void @test_kill_depth_var_x2_instructions(float %x) #0 {
142; SI-LABEL: test_kill_depth_var_x2_instructions:
143; SI:       ; %bb.0:
144; SI-NEXT:    v_cmpx_gt_f32_e32 vcc, 0, v0
145; SI-NEXT:    s_cbranch_execz BB6_3
146; SI-NEXT:  ; %bb.1:
147; SI-NEXT:    ;;#ASMSTART
148; SI-NEXT:    v_mov_b32_e64 v7, -1
149; SI-NEXT:    ;;#ASMEND
150; SI-NEXT:    v_cmpx_gt_f32_e32 vcc, 0, v7
151; SI-NEXT:    s_cbranch_execz BB6_3
152; SI-NEXT:  ; %bb.2:
153; SI-NEXT:    s_endpgm
154; SI-NEXT:  BB6_3:
155; SI-NEXT:    exp null off, off, off, off done vm
156; SI-NEXT:    s_endpgm
157;
158; GFX10-LABEL: test_kill_depth_var_x2_instructions:
159; GFX10:       ; %bb.0:
160; GFX10-NEXT:    v_cmpx_gt_f32_e32 0, v0
161; GFX10-NEXT:    s_cbranch_execz BB6_3
162; GFX10-NEXT:  ; %bb.1:
163; GFX10-NEXT:    ;;#ASMSTART
164; GFX10-NEXT:    v_mov_b32_e64 v7, -1
165; GFX10-NEXT:    ;;#ASMEND
166; GFX10-NEXT:    s_waitcnt_depctr 0xfffe
167; GFX10-NEXT:    v_cmpx_gt_f32_e32 0, v7
168; GFX10-NEXT:    s_cbranch_execz BB6_3
169; GFX10-NEXT:  ; %bb.2:
170; GFX10-NEXT:    s_endpgm
171; GFX10-NEXT:  BB6_3:
172; GFX10-NEXT:    exp null off, off, off, off done vm
173; GFX10-NEXT:    s_endpgm
174  %cmp.x = fcmp olt float %x, 0.0
175  call void @llvm.amdgcn.kill(i1 %cmp.x)
176  %y = call float asm sideeffect "v_mov_b32_e64 v7, -1", "={v7}"()
177  %cmp.y = fcmp olt float %y, 0.0
178  call void @llvm.amdgcn.kill(i1 %cmp.y)
179  ret void
180}
181
182; FIXME: why does the skip depend on the asm length in the same block?
183define amdgpu_ps float @test_kill_control_flow(i32 inreg %arg) #0 {
184; SI-LABEL: test_kill_control_flow:
185; SI:       ; %bb.0: ; %entry
186; SI-NEXT:    s_cmp_lg_u32 s0, 0
187; SI-NEXT:    s_cbranch_scc1 BB7_2
188; SI-NEXT:  ; %bb.1: ; %bb
189; SI-NEXT:    ;;#ASMSTART
190; SI-NEXT:    v_mov_b32_e64 v7, -1
191; SI-NEXT:    v_nop_e64
192; SI-NEXT:    v_nop_e64
193; SI-NEXT:    v_nop_e64
194; SI-NEXT:    v_nop_e64
195; SI-NEXT:    v_nop_e64
196; SI-NEXT:    v_nop_e64
197; SI-NEXT:    v_nop_e64
198; SI-NEXT:    v_nop_e64
199; SI-NEXT:    v_nop_e64
200; SI-NEXT:    v_nop_e64
201; SI-NEXT:    ;;#ASMEND
202; SI-NEXT:    v_cmpx_gt_f32_e32 vcc, 0, v7
203; SI-NEXT:  BB7_2: ; %exit
204; SI-NEXT:    v_mov_b32_e32 v0, 1.0
205; SI-NEXT:    ; return to shader part epilog
206;
207; GFX10-LABEL: test_kill_control_flow:
208; GFX10:       ; %bb.0: ; %entry
209; GFX10-NEXT:    s_cmp_lg_u32 s0, 0
210; GFX10-NEXT:    s_cbranch_scc1 BB7_2
211; GFX10-NEXT:  ; %bb.1: ; %bb
212; GFX10-NEXT:    ;;#ASMSTART
213; GFX10-NEXT:    v_mov_b32_e64 v7, -1
214; GFX10-NEXT:    v_nop_e64
215; GFX10-NEXT:    v_nop_e64
216; GFX10-NEXT:    v_nop_e64
217; GFX10-NEXT:    v_nop_e64
218; GFX10-NEXT:    v_nop_e64
219; GFX10-NEXT:    v_nop_e64
220; GFX10-NEXT:    v_nop_e64
221; GFX10-NEXT:    v_nop_e64
222; GFX10-NEXT:    v_nop_e64
223; GFX10-NEXT:    v_nop_e64
224; GFX10-NEXT:    ;;#ASMEND
225; GFX10-NEXT:    v_cmpx_gt_f32_e32 0, v7
226; GFX10-NEXT:  BB7_2: ; %exit
227; GFX10-NEXT:    v_mov_b32_e32 v0, 1.0
228; GFX10-NEXT:    ; return to shader part epilog
229entry:
230  %cmp = icmp eq i32 %arg, 0
231  br i1 %cmp, label %bb, label %exit
232
233bb:
234  %var = call float asm sideeffect "v_mov_b32_e64 v7, -1
235    v_nop_e64
236    v_nop_e64
237    v_nop_e64
238    v_nop_e64
239    v_nop_e64
240    v_nop_e64
241    v_nop_e64
242    v_nop_e64
243    v_nop_e64
244    v_nop_e64", "={v7}"()
245  %cmp.var = fcmp olt float %var, 0.0
246  ; TODO: We could do an early-exit here (the branch above is uniform!)
247  call void @llvm.amdgcn.kill(i1 %cmp.var)
248  br label %exit
249
250exit:
251  ret float 1.0
252}
253
254define amdgpu_ps void @test_kill_control_flow_remainder(i32 inreg %arg) #0 {
255; SI-LABEL: test_kill_control_flow_remainder:
256; SI:       ; %bb.0: ; %entry
257; SI-NEXT:    s_cmp_lg_u32 s0, 0
258; SI-NEXT:    v_mov_b32_e32 v9, 0
259; SI-NEXT:    s_cbranch_scc1 BB8_3
260; SI-NEXT:  ; %bb.1: ; %bb
261; SI-NEXT:    ;;#ASMSTART
262; SI-NEXT:    v_mov_b32_e64 v7, -1
263; SI-NEXT:    v_nop_e64
264; SI-NEXT:    v_nop_e64
265; SI-NEXT:    v_nop_e64
266; SI-NEXT:    v_nop_e64
267; SI-NEXT:    v_nop_e64
268; SI-NEXT:    v_nop_e64
269; SI-NEXT:    v_nop_e64
270; SI-NEXT:    v_nop_e64
271; SI-NEXT:    v_nop_e64
272; SI-NEXT:    v_nop_e64
273; SI-NEXT:    v_nop_e64
274; SI-NEXT:    ;;#ASMEND
275; SI-NEXT:    ;;#ASMSTART
276; SI-NEXT:    v_mov_b32_e64 v8, -1
277; SI-NEXT:    ;;#ASMEND
278; SI-NEXT:    v_cmpx_gt_f32_e32 vcc, 0, v7
279; SI-NEXT:  ; %bb.2: ; %bb
280; SI-NEXT:    s_mov_b32 s3, 0xf000
281; SI-NEXT:    s_mov_b32 s2, -1
282; SI-NEXT:    buffer_store_dword v8, off, s[0:3], 0
283; SI-NEXT:    s_waitcnt vmcnt(0)
284; SI-NEXT:    ;;#ASMSTART
285; SI-NEXT:    v_mov_b32_e64 v9, -2
286; SI-NEXT:    ;;#ASMEND
287; SI-NEXT:  BB8_3: ; %exit
288; SI-NEXT:    s_mov_b32 s3, 0xf000
289; SI-NEXT:    s_mov_b32 s2, -1
290; SI-NEXT:    buffer_store_dword v9, off, s[0:3], 0
291; SI-NEXT:    s_endpgm
292;
293; GFX10-LABEL: test_kill_control_flow_remainder:
294; GFX10:       ; %bb.0: ; %entry
295; GFX10-NEXT:    v_mov_b32_e32 v9, 0
296; GFX10-NEXT:    s_cmp_lg_u32 s0, 0
297; GFX10-NEXT:    s_cbranch_scc0 BB8_2
298; GFX10-NEXT:  ; %bb.1: ; %exit
299; GFX10-NEXT:    global_store_dword v[0:1], v9, off
300; GFX10-NEXT:    s_endpgm
301; GFX10-NEXT:  BB8_2: ; %bb
302; GFX10-NEXT:    ;;#ASMSTART
303; GFX10-NEXT:    v_mov_b32_e64 v7, -1
304; GFX10-NEXT:    v_nop_e64
305; GFX10-NEXT:    v_nop_e64
306; GFX10-NEXT:    v_nop_e64
307; GFX10-NEXT:    v_nop_e64
308; GFX10-NEXT:    v_nop_e64
309; GFX10-NEXT:    v_nop_e64
310; GFX10-NEXT:    v_nop_e64
311; GFX10-NEXT:    v_nop_e64
312; GFX10-NEXT:    v_nop_e64
313; GFX10-NEXT:    v_nop_e64
314; GFX10-NEXT:    v_nop_e64
315; GFX10-NEXT:    ;;#ASMEND
316; GFX10-NEXT:    ;;#ASMSTART
317; GFX10-NEXT:    v_mov_b32_e64 v8, -1
318; GFX10-NEXT:    ;;#ASMEND
319; GFX10-NEXT:    v_cmpx_gt_f32_e32 0, v7
320; GFX10-NEXT:    s_cbranch_execz BB8_4
321; GFX10-NEXT:  ; %bb.3: ; %bb
322; GFX10-NEXT:    s_nop 3
323; GFX10-NEXT:    global_store_dword v[0:1], v8, off
324; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
325; GFX10-NEXT:    ;;#ASMSTART
326; GFX10-NEXT:    v_mov_b32_e64 v9, -2
327; GFX10-NEXT:    ;;#ASMEND
328; GFX10-NEXT:    global_store_dword v[0:1], v9, off
329; GFX10-NEXT:    s_endpgm
330; GFX10-NEXT:  BB8_4:
331; GFX10-NEXT:    exp null off, off, off, off done vm
332; GFX10-NEXT:    s_endpgm
333entry:
334  %cmp = icmp eq i32 %arg, 0
335  br i1 %cmp, label %bb, label %exit
336
337bb:
338  %var = call float asm sideeffect "v_mov_b32_e64 v7, -1
339    v_nop_e64
340    v_nop_e64
341    v_nop_e64
342    v_nop_e64
343    v_nop_e64
344    v_nop_e64
345    v_nop_e64
346    v_nop_e64
347    v_nop_e64
348    v_nop_e64
349    v_nop_e64", "={v7}"()
350  %live.across = call float asm sideeffect "v_mov_b32_e64 v8, -1", "={v8}"()
351  %cmp.var = fcmp olt float %var, 0.0
352  ; TODO: We could do an early-exit here (the branch above is uniform!)
353  call void @llvm.amdgcn.kill(i1 %cmp.var)
354  store volatile float %live.across, float addrspace(1)* undef
355  %live.out = call float asm sideeffect "v_mov_b32_e64 v9, -2", "={v9}"()
356  br label %exit
357
358exit:
359  %phi = phi float [ 0.0, %entry ], [ %live.out, %bb ]
360  store float %phi, float addrspace(1)* undef
361  ret void
362}
363
364define amdgpu_ps float @test_kill_control_flow_return(i32 inreg %arg) #0 {
365; SI-LABEL: test_kill_control_flow_return:
366; SI:       ; %bb.0: ; %entry
367; SI-NEXT:    v_cmp_eq_u32_e64 s[2:3], s0, 1
368; SI-NEXT:    s_and_b64 exec, exec, s[2:3]
369; SI-NEXT:    s_cbranch_execz BB9_4
370; SI-NEXT:  ; %bb.1: ; %entry
371; SI-NEXT:    s_cmp_lg_u32 s0, 0
372; SI-NEXT:    v_mov_b32_e32 v0, 0
373; SI-NEXT:    s_cbranch_scc0 BB9_3
374; SI-NEXT:  ; %bb.2: ; %exit
375; SI-NEXT:    s_branch BB9_5
376; SI-NEXT:  BB9_3: ; %bb
377; SI-NEXT:    ;;#ASMSTART
378; SI-NEXT:    v_mov_b32_e64 v7, -1
379; SI-NEXT:    v_nop_e64
380; SI-NEXT:    v_nop_e64
381; SI-NEXT:    v_nop_e64
382; SI-NEXT:    v_nop_e64
383; SI-NEXT:    v_nop_e64
384; SI-NEXT:    v_nop_e64
385; SI-NEXT:    v_nop_e64
386; SI-NEXT:    v_nop_e64
387; SI-NEXT:    v_nop_e64
388; SI-NEXT:    v_nop_e64
389; SI-NEXT:    ;;#ASMEND
390; SI-NEXT:    v_mov_b32_e32 v0, v7
391; SI-NEXT:    s_branch BB9_5
392; SI-NEXT:  BB9_4:
393; SI-NEXT:    exp null off, off, off, off done vm
394; SI-NEXT:    s_endpgm
395; SI-NEXT:  BB9_5:
396;
397; GFX10-LABEL: test_kill_control_flow_return:
398; GFX10:       ; %bb.0: ; %entry
399; GFX10-NEXT:    v_cmp_eq_u32_e64 s[2:3], s0, 1
400; GFX10-NEXT:    s_and_b64 exec, exec, s[2:3]
401; GFX10-NEXT:    s_cbranch_execz BB9_4
402; GFX10-NEXT:  ; %bb.1: ; %entry
403; GFX10-NEXT:    v_mov_b32_e32 v0, 0
404; GFX10-NEXT:    s_cmp_lg_u32 s0, 0
405; GFX10-NEXT:    s_cbranch_scc0 BB9_3
406; GFX10-NEXT:  ; %bb.2: ; %exit
407; GFX10-NEXT:    s_branch BB9_5
408; GFX10-NEXT:  BB9_3: ; %bb
409; GFX10-NEXT:    ;;#ASMSTART
410; GFX10-NEXT:    v_mov_b32_e64 v7, -1
411; GFX10-NEXT:    v_nop_e64
412; GFX10-NEXT:    v_nop_e64
413; GFX10-NEXT:    v_nop_e64
414; GFX10-NEXT:    v_nop_e64
415; GFX10-NEXT:    v_nop_e64
416; GFX10-NEXT:    v_nop_e64
417; GFX10-NEXT:    v_nop_e64
418; GFX10-NEXT:    v_nop_e64
419; GFX10-NEXT:    v_nop_e64
420; GFX10-NEXT:    v_nop_e64
421; GFX10-NEXT:    ;;#ASMEND
422; GFX10-NEXT:    v_mov_b32_e32 v0, v7
423; GFX10-NEXT:    s_branch BB9_5
424; GFX10-NEXT:  BB9_4:
425; GFX10-NEXT:    exp null off, off, off, off done vm
426; GFX10-NEXT:    s_endpgm
427; GFX10-NEXT:  BB9_5:
428entry:
429  %kill = icmp eq i32 %arg, 1
430  %cmp = icmp eq i32 %arg, 0
431  call void @llvm.amdgcn.kill(i1 %kill)
432  br i1 %cmp, label %bb, label %exit
433
434bb:
435  %var = call float asm sideeffect "v_mov_b32_e64 v7, -1
436    v_nop_e64
437    v_nop_e64
438    v_nop_e64
439    v_nop_e64
440    v_nop_e64
441    v_nop_e64
442    v_nop_e64
443    v_nop_e64
444    v_nop_e64
445    v_nop_e64", "={v7}"()
446  br label %exit
447
448exit:
449  %ret = phi float [ %var, %bb ], [ 0.0, %entry ]
450  ret float %ret
451}
452
453define amdgpu_ps void @test_kill_divergent_loop(i32 %arg) #0 {
454; SI-LABEL: test_kill_divergent_loop:
455; SI:       ; %bb.0: ; %entry
456; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
457; SI-NEXT:    s_and_saveexec_b64 s[0:1], vcc
458; SI-NEXT:    s_xor_b64 s[0:1], exec, s[0:1]
459; SI-NEXT:    s_cbranch_execz BB10_4
460; SI-NEXT:  ; %bb.1: ; %bb.preheader
461; SI-NEXT:    s_mov_b32 s3, 0xf000
462; SI-NEXT:    s_mov_b32 s2, -1
463; SI-NEXT:  BB10_2: ; %bb
464; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
465; SI-NEXT:    ;;#ASMSTART
466; SI-NEXT:    v_mov_b32_e64 v7, -1
467; SI-NEXT:    v_nop_e64
468; SI-NEXT:    v_nop_e64
469; SI-NEXT:    v_nop_e64
470; SI-NEXT:    v_nop_e64
471; SI-NEXT:    v_nop_e64
472; SI-NEXT:    v_nop_e64
473; SI-NEXT:    v_nop_e64
474; SI-NEXT:    v_nop_e64
475; SI-NEXT:    v_nop_e64
476; SI-NEXT:    v_nop_e64
477; SI-NEXT:    ;;#ASMEND
478; SI-NEXT:    v_cmpx_gt_f32_e32 vcc, 0, v7
479; SI-NEXT:  ; %bb.3: ; %bb
480; SI-NEXT:    ; in Loop: Header=BB10_2 Depth=1
481; SI-NEXT:    buffer_load_dword v0, off, s[0:3], 0 glc
482; SI-NEXT:    s_waitcnt vmcnt(0)
483; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
484; SI-NEXT:    s_and_b64 vcc, exec, vcc
485; SI-NEXT:    s_cbranch_vccnz BB10_2
486; SI-NEXT:  BB10_4: ; %Flow1
487; SI-NEXT:    s_or_b64 exec, exec, s[0:1]
488; SI-NEXT:    s_cbranch_execz BB10_6
489; SI-NEXT:  ; %bb.5: ; %Flow1
490; SI-NEXT:    s_mov_b32 s3, 0xf000
491; SI-NEXT:    s_mov_b32 s2, -1
492; SI-NEXT:    v_mov_b32_e32 v0, 8
493; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
494; SI-NEXT:    s_waitcnt vmcnt(0)
495; SI-NEXT:    s_endpgm
496; SI-NEXT:  BB10_6:
497; SI-NEXT:    exp null off, off, off, off done vm
498; SI-NEXT:    s_endpgm
499;
500; GFX10-LABEL: test_kill_divergent_loop:
501; GFX10:       ; %bb.0: ; %entry
502; GFX10-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
503; GFX10-NEXT:    s_and_saveexec_b64 s[0:1], vcc
504; GFX10-NEXT:    s_xor_b64 s[0:1], exec, s[0:1]
505; GFX10-NEXT:    s_cbranch_execz BB10_3
506; GFX10-NEXT:  BB10_1: ; %bb
507; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
508; GFX10-NEXT:    ;;#ASMSTART
509; GFX10-NEXT:    v_mov_b32_e64 v7, -1
510; GFX10-NEXT:    v_nop_e64
511; GFX10-NEXT:    v_nop_e64
512; GFX10-NEXT:    v_nop_e64
513; GFX10-NEXT:    v_nop_e64
514; GFX10-NEXT:    v_nop_e64
515; GFX10-NEXT:    v_nop_e64
516; GFX10-NEXT:    v_nop_e64
517; GFX10-NEXT:    v_nop_e64
518; GFX10-NEXT:    v_nop_e64
519; GFX10-NEXT:    v_nop_e64
520; GFX10-NEXT:    ;;#ASMEND
521; GFX10-NEXT:    s_waitcnt_depctr 0xfffe
522; GFX10-NEXT:    v_cmpx_gt_f32_e32 0, v7
523; GFX10-NEXT:  ; %bb.2: ; %bb
524; GFX10-NEXT:    ; in Loop: Header=BB10_1 Depth=1
525; GFX10-NEXT:    s_nop 4
526; GFX10-NEXT:    global_load_dword v0, v[0:1], off glc dlc
527; GFX10-NEXT:    s_waitcnt vmcnt(0)
528; GFX10-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
529; GFX10-NEXT:    s_and_b64 vcc, exec, vcc
530; GFX10-NEXT:    s_cbranch_vccnz BB10_1
531; GFX10-NEXT:  BB10_3: ; %Flow1
532; GFX10-NEXT:    s_or_b64 exec, exec, s[0:1]
533; GFX10-NEXT:    s_cbranch_execz BB10_5
534; GFX10-NEXT:  ; %bb.4: ; %Flow1
535; GFX10-NEXT:    v_mov_b32_e32 v0, 8
536; GFX10-NEXT:    global_store_dword v[0:1], v0, off
537; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
538; GFX10-NEXT:    s_endpgm
539; GFX10-NEXT:  BB10_5:
540; GFX10-NEXT:    exp null off, off, off, off done vm
541; GFX10-NEXT:    s_endpgm
542entry:
543  %cmp = icmp eq i32 %arg, 0
544  br i1 %cmp, label %bb, label %exit
545
546bb:
547  %var = call float asm sideeffect "v_mov_b32_e64 v7, -1
548    v_nop_e64
549    v_nop_e64
550    v_nop_e64
551    v_nop_e64
552    v_nop_e64
553    v_nop_e64
554    v_nop_e64
555    v_nop_e64
556    v_nop_e64
557    v_nop_e64", "={v7}"()
558  %cmp.var = fcmp olt float %var, 0.0
559  call void @llvm.amdgcn.kill(i1 %cmp.var)
560  %vgpr = load volatile i32, i32 addrspace(1)* undef
561  %loop.cond = icmp eq i32 %vgpr, 0
562  br i1 %loop.cond, label %bb, label %exit
563
564exit:
565  store volatile i32 8, i32 addrspace(1)* undef
566  ret void
567}
568
569; bug 28550
570define amdgpu_ps void @phi_use_def_before_kill(float inreg %x) #0 {
571; SI-LABEL: phi_use_def_before_kill:
572; SI:       ; %bb.0: ; %bb
573; SI-NEXT:    v_add_f32_e64 v1, s0, 1.0
574; SI-NEXT:    v_cmp_lt_f32_e32 vcc, 0, v1
575; SI-NEXT:    v_cndmask_b32_e64 v0, 0, -1.0, vcc
576; SI-NEXT:    v_cmpx_lt_f32_e32 vcc, 0, v1
577; SI-NEXT:    s_cbranch_execz BB11_6
578; SI-NEXT:  ; %bb.1: ; %bb
579; SI-NEXT:    s_cbranch_scc0 BB11_3
580; SI-NEXT:  ; %bb.2: ; %bb8
581; SI-NEXT:    s_mov_b32 s3, 0xf000
582; SI-NEXT:    s_mov_b32 s2, -1
583; SI-NEXT:    v_mov_b32_e32 v0, 8
584; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
585; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
586; SI-NEXT:    v_mov_b32_e32 v0, 4.0
587; SI-NEXT:  BB11_3: ; %phibb
588; SI-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v0
589; SI-NEXT:    s_and_b64 vcc, exec, vcc
590; SI-NEXT:    s_cbranch_vccz BB11_5
591; SI-NEXT:  ; %bb.4: ; %bb10
592; SI-NEXT:    s_mov_b32 s3, 0xf000
593; SI-NEXT:    s_mov_b32 s2, -1
594; SI-NEXT:    v_mov_b32_e32 v0, 9
595; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
596; SI-NEXT:    s_waitcnt vmcnt(0)
597; SI-NEXT:  BB11_5: ; %end
598; SI-NEXT:    s_endpgm
599; SI-NEXT:  BB11_6:
600; SI-NEXT:    exp null off, off, off, off done vm
601; SI-NEXT:    s_endpgm
602;
603; GFX10-LABEL: phi_use_def_before_kill:
604; GFX10:       ; %bb.0: ; %bb
605; GFX10-NEXT:    v_add_f32_e64 v1, s0, 1.0
606; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc, 0, v1
607; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, -1.0, vcc
608; GFX10-NEXT:    v_cmpx_lt_f32_e32 0, v1
609; GFX10-NEXT:    s_cbranch_execz BB11_6
610; GFX10-NEXT:  ; %bb.1: ; %bb
611; GFX10-NEXT:    s_cbranch_scc0 BB11_3
612; GFX10-NEXT:  ; %bb.2: ; %bb8
613; GFX10-NEXT:    v_mov_b32_e32 v1, 8
614; GFX10-NEXT:    v_mov_b32_e32 v0, 4.0
615; GFX10-NEXT:    s_nop 0
616; GFX10-NEXT:    global_store_dword v[0:1], v1, off
617; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
618; GFX10-NEXT:  BB11_3: ; %phibb
619; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v0
620; GFX10-NEXT:    s_and_b64 vcc, exec, vcc
621; GFX10-NEXT:    s_cbranch_vccz BB11_5
622; GFX10-NEXT:  ; %bb.4: ; %bb10
623; GFX10-NEXT:    v_mov_b32_e32 v0, 9
624; GFX10-NEXT:    global_store_dword v[0:1], v0, off
625; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
626; GFX10-NEXT:  BB11_5: ; %end
627; GFX10-NEXT:    s_endpgm
628; GFX10-NEXT:  BB11_6:
629; GFX10-NEXT:    exp null off, off, off, off done vm
630; GFX10-NEXT:    s_endpgm
631bb:
632  %tmp = fadd float %x, 1.000000e+00
633  %tmp1 = fcmp olt float 0.000000e+00, %tmp
634  %tmp2 = select i1 %tmp1, float -1.000000e+00, float 0.000000e+00
635  %cmp.tmp2 = fcmp olt float %tmp2, 0.0
636  call void @llvm.amdgcn.kill(i1 %cmp.tmp2)
637  br i1 undef, label %phibb, label %bb8
638
639phibb:
640  %tmp5 = phi float [ %tmp2, %bb ], [ 4.0, %bb8 ]
641  %tmp6 = fcmp oeq float %tmp5, 0.000000e+00
642  br i1 %tmp6, label %bb10, label %end
643
644bb8:
645  store volatile i32 8, i32 addrspace(1)* undef
646  br label %phibb
647
648bb10:
649  store volatile i32 9, i32 addrspace(1)* undef
650  br label %end
651
652end:
653  ret void
654}
655
656define amdgpu_ps void @no_skip_no_successors(float inreg %arg, float inreg %arg1) #0 {
657; SI-LABEL: no_skip_no_successors:
658; SI:       ; %bb.0: ; %bb
659; SI-NEXT:    v_cmp_nge_f32_e64 s[2:3], s1, 0
660; SI-NEXT:    s_and_b64 vcc, exec, s[2:3]
661; SI-NEXT:    s_cbranch_vccz BB12_2
662; SI-NEXT:  ; %bb.1: ; %bb6
663; SI-NEXT:    s_mov_b64 exec, 0
664; SI-NEXT:    exp null off, off, off, off done vm
665; SI-NEXT:    s_endpgm
666; SI-NEXT:  BB12_2: ; %bb3
667; SI-NEXT:    v_mov_b32_e32 v0, 0x3e7ae148
668; SI-NEXT:    v_cmp_nge_f32_e32 vcc, s0, v0
669; SI-NEXT:    s_and_b64 vcc, exec, vcc
670; SI-NEXT:  ; %bb.3: ; %bb5
671;
672; GFX10-LABEL: no_skip_no_successors:
673; GFX10:       ; %bb.0: ; %bb
674; GFX10-NEXT:    v_cmp_nge_f32_e64 s[2:3], s1, 0
675; GFX10-NEXT:    s_and_b64 vcc, exec, s[2:3]
676; GFX10-NEXT:    s_cbranch_vccz BB12_2
677; GFX10-NEXT:  ; %bb.1: ; %bb6
678; GFX10-NEXT:    s_mov_b64 exec, 0
679; GFX10-NEXT:    exp null off, off, off, off done vm
680; GFX10-NEXT:    s_endpgm
681; GFX10-NEXT:  BB12_2: ; %bb3
682; GFX10-NEXT:    v_cmp_nle_f32_e64 s[0:1], 0x3e7ae148, s0
683; GFX10-NEXT:    s_and_b64 vcc, exec, s[0:1]
684; GFX10-NEXT:  ; %bb.3: ; %bb5
685bb:
686  %tmp = fcmp ult float %arg1, 0.000000e+00
687  %tmp2 = fcmp ult float %arg, 0x3FCF5C2900000000
688  br i1 %tmp, label %bb6, label %bb3
689
690bb3:                                              ; preds = %bb
691  br i1 %tmp2, label %bb5, label %bb4
692
693bb4:                                              ; preds = %bb3
694  br i1 true, label %bb5, label %bb7
695
696bb5:                                              ; preds = %bb4, %bb3
697  unreachable
698
699bb6:                                              ; preds = %bb
700  call void @llvm.amdgcn.kill(i1 false)
701  unreachable
702
703bb7:                                              ; preds = %bb4
704  ret void
705}
706
707define amdgpu_ps void @if_after_kill_block(float %arg, float %arg1, float %arg2, float %arg3) #0 {
708; SI-LABEL: if_after_kill_block:
709; SI:       ; %bb.0: ; %bb
710; SI-NEXT:    s_wqm_b64 exec, exec
711; SI-NEXT:    s_mov_b32 s0, 0
712; SI-NEXT:    v_cmp_nle_f32_e32 vcc, 0, v1
713; SI-NEXT:    s_and_saveexec_b64 s[2:3], vcc
714; SI-NEXT:    s_xor_b64 s[2:3], exec, s[2:3]
715; SI-NEXT:    s_cbranch_execz BB13_2
716; SI-NEXT:  ; %bb.1: ; %bb3
717; SI-NEXT:    v_cmpx_gt_f32_e32 vcc, 0, v0
718; SI-NEXT:  BB13_2: ; %bb4
719; SI-NEXT:    s_or_b64 exec, exec, s[2:3]
720; SI-NEXT:    s_cbranch_execz BB13_6
721; SI-NEXT:  ; %bb.3: ; %bb4
722; SI-NEXT:    s_mov_b32 s1, s0
723; SI-NEXT:    s_mov_b32 s2, s0
724; SI-NEXT:    s_mov_b32 s3, s0
725; SI-NEXT:    s_mov_b32 s4, s0
726; SI-NEXT:    s_mov_b32 s5, s0
727; SI-NEXT:    s_mov_b32 s6, s0
728; SI-NEXT:    s_mov_b32 s7, s0
729; SI-NEXT:    image_sample_c v0, v[2:3], s[0:7], s[0:3] dmask:0x10
730; SI-NEXT:    s_waitcnt vmcnt(0)
731; SI-NEXT:    v_cmp_neq_f32_e32 vcc, 0, v0
732; SI-NEXT:    s_and_saveexec_b64 s[0:1], vcc
733; SI-NEXT:    s_cbranch_execz BB13_5
734; SI-NEXT:  ; %bb.4: ; %bb8
735; SI-NEXT:    s_mov_b32 s3, 0xf000
736; SI-NEXT:    s_mov_b32 s2, -1
737; SI-NEXT:    v_mov_b32_e32 v0, 9
738; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
739; SI-NEXT:    s_waitcnt vmcnt(0)
740; SI-NEXT:  BB13_5: ; %UnifiedReturnBlock
741; SI-NEXT:    s_endpgm
742; SI-NEXT:  BB13_6:
743; SI-NEXT:    exp null off, off, off, off done vm
744; SI-NEXT:    s_endpgm
745;
746; GFX10-LABEL: if_after_kill_block:
747; GFX10:       ; %bb.0: ; %bb
748; GFX10-NEXT:    s_wqm_b64 exec, exec
749; GFX10-NEXT:    v_cmp_nle_f32_e32 vcc, 0, v1
750; GFX10-NEXT:    s_mov_b32 s0, 0
751; GFX10-NEXT:    s_and_saveexec_b64 s[2:3], vcc
752; GFX10-NEXT:    s_xor_b64 s[2:3], exec, s[2:3]
753; GFX10-NEXT:    s_cbranch_execz BB13_2
754; GFX10-NEXT:  ; %bb.1: ; %bb3
755; GFX10-NEXT:    s_waitcnt_depctr 0xfffe
756; GFX10-NEXT:    v_cmpx_gt_f32_e32 0, v0
757; GFX10-NEXT:  BB13_2: ; %bb4
758; GFX10-NEXT:    s_or_b64 exec, exec, s[2:3]
759; GFX10-NEXT:    s_cbranch_execz BB13_6
760; GFX10-NEXT:  ; %bb.3: ; %bb4
761; GFX10-NEXT:    s_mov_b32 s1, s0
762; GFX10-NEXT:    s_mov_b32 s2, s0
763; GFX10-NEXT:    s_mov_b32 s3, s0
764; GFX10-NEXT:    s_mov_b32 s4, s0
765; GFX10-NEXT:    s_mov_b32 s5, s0
766; GFX10-NEXT:    s_mov_b32 s6, s0
767; GFX10-NEXT:    s_mov_b32 s7, s0
768; GFX10-NEXT:    image_sample_c v0, v[2:3], s[0:7], s[0:3] dmask:0x10 dim:SQ_RSRC_IMG_1D
769; GFX10-NEXT:    s_waitcnt vmcnt(0)
770; GFX10-NEXT:    v_cmp_neq_f32_e32 vcc, 0, v0
771; GFX10-NEXT:    s_and_saveexec_b64 s[0:1], vcc
772; GFX10-NEXT:    s_cbranch_execz BB13_5
773; GFX10-NEXT:  ; %bb.4: ; %bb8
774; GFX10-NEXT:    v_mov_b32_e32 v0, 9
775; GFX10-NEXT:    global_store_dword v[0:1], v0, off
776; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
777; GFX10-NEXT:  BB13_5: ; %UnifiedReturnBlock
778; GFX10-NEXT:    s_endpgm
779; GFX10-NEXT:  BB13_6:
780; GFX10-NEXT:    exp null off, off, off, off done vm
781; GFX10-NEXT:    s_endpgm
782bb:
783  %tmp = fcmp ult float %arg1, 0.000000e+00
784  br i1 %tmp, label %bb3, label %bb4
785
786bb3:                                              ; preds = %bb
787  %cmp.arg = fcmp olt float %arg, 0.0
788  call void @llvm.amdgcn.kill(i1 %cmp.arg)
789  br label %bb4
790
791bb4:                                              ; preds = %bb3, %bb
792  %tmp5 = call <4 x float> @llvm.amdgcn.image.sample.c.1d.v4f32.f32(i32 16, float %arg2, float %arg3, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
793  %tmp6 = extractelement <4 x float> %tmp5, i32 0
794  %tmp7 = fcmp une float %tmp6, 0.000000e+00
795  br i1 %tmp7, label %bb8, label %bb9
796
797bb8:                                              ; preds = %bb9, %bb4
798  store volatile i32 9, i32 addrspace(1)* undef
799  ret void
800
801bb9:                                              ; preds = %bb4
802  ret void
803}
804
805define amdgpu_ps void @cbranch_kill(i32 inreg %0, <2 x float> %1) {
806; SI-LABEL: cbranch_kill:
807; SI:       ; %bb.0: ; %.entry
808; SI-NEXT:    s_mov_b32 m0, s0
809; SI-NEXT:    s_mov_b32 s4, 0
810; SI-NEXT:    v_interp_p1_f32 v2, v0, attr1.x
811; SI-NEXT:    v_mov_b32_e32 v3, v2
812; SI-NEXT:    v_mov_b32_e32 v4, v2
813; SI-NEXT:    s_mov_b32 s5, s4
814; SI-NEXT:    s_mov_b32 s6, s4
815; SI-NEXT:    s_mov_b32 s7, s4
816; SI-NEXT:    s_mov_b32 s8, s4
817; SI-NEXT:    s_mov_b32 s9, s4
818; SI-NEXT:    s_mov_b32 s10, s4
819; SI-NEXT:    s_mov_b32 s11, s4
820; SI-NEXT:    image_sample_lz v2, v[2:4], s[4:11], s[0:3] dmask:0x1 da
821; SI-NEXT:    s_waitcnt vmcnt(0)
822; SI-NEXT:    v_cmp_ge_f32_e32 vcc, 0, v2
823; SI-NEXT:    s_and_saveexec_b64 s[2:3], vcc
824; SI-NEXT:    s_xor_b64 s[2:3], exec, s[2:3]
825; SI-NEXT:    s_cbranch_execz BB14_2
826; SI-NEXT:  ; %bb.1: ; %kill
827; SI-NEXT:    s_mov_b64 exec, 0
828; SI-NEXT:  BB14_2: ; %Flow
829; SI-NEXT:    s_or_saveexec_b64 s[2:3], s[2:3]
830; SI-NEXT:    ; implicit-def: $vgpr3
831; SI-NEXT:    ; implicit-def: $vgpr4
832; SI-NEXT:    ; implicit-def: $vgpr5
833; SI-NEXT:    ; implicit-def: $vgpr6
834; SI-NEXT:    s_xor_b64 exec, exec, s[2:3]
835; SI-NEXT:  ; %bb.3: ; %live
836; SI-NEXT:    s_mov_b32 m0, s0
837; SI-NEXT:    v_interp_p1_f32 v4, v0, attr0.x
838; SI-NEXT:    v_interp_p1_f32 v0, v0, attr0.y
839; SI-NEXT:    v_mul_f32_e32 v3, v4, v2
840; SI-NEXT:    v_interp_p2_f32 v4, v1, attr0.x
841; SI-NEXT:    v_mul_f32_e32 v5, v0, v2
842; SI-NEXT:    v_interp_p2_f32 v0, v1, attr0.y
843; SI-NEXT:    v_mul_f32_e32 v4, v4, v2
844; SI-NEXT:    v_mul_f32_e32 v6, v0, v2
845; SI-NEXT:  ; %bb.4: ; %export
846; SI-NEXT:    s_or_b64 exec, exec, s[2:3]
847; SI-NEXT:    s_cbranch_execz BB14_6
848; SI-NEXT:  ; %bb.5: ; %export
849; SI-NEXT:    v_cvt_pkrtz_f16_f32_e32 v0, v3, v4
850; SI-NEXT:    v_cvt_pkrtz_f16_f32_e32 v1, v5, v6
851; SI-NEXT:    exp mrt0 v0, v0, v1, v1 done compr vm
852; SI-NEXT:    s_endpgm
853; SI-NEXT:  BB14_6:
854; SI-NEXT:    exp null off, off, off, off done vm
855; SI-NEXT:    s_endpgm
856;
857; GFX10-LABEL: cbranch_kill:
858; GFX10:       ; %bb.0: ; %.entry
859; GFX10-NEXT:    s_mov_b32 m0, s0
860; GFX10-NEXT:    s_mov_b32 s4, 0
861; GFX10-NEXT:    v_interp_p1_f32_e32 v2, v0, attr1.x
862; GFX10-NEXT:    s_mov_b32 s5, s4
863; GFX10-NEXT:    s_mov_b32 s6, s4
864; GFX10-NEXT:    s_mov_b32 s7, s4
865; GFX10-NEXT:    s_mov_b32 s8, s4
866; GFX10-NEXT:    s_mov_b32 s9, s4
867; GFX10-NEXT:    s_mov_b32 s10, s4
868; GFX10-NEXT:    s_mov_b32 s11, s4
869; GFX10-NEXT:    image_sample_lz v2, [v2, v2, v2], s[4:11], s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
870; GFX10-NEXT:    s_waitcnt vmcnt(0)
871; GFX10-NEXT:    v_cmp_ge_f32_e32 vcc, 0, v2
872; GFX10-NEXT:    s_and_saveexec_b64 s[2:3], vcc
873; GFX10-NEXT:    s_xor_b64 s[2:3], exec, s[2:3]
874; GFX10-NEXT:    s_cbranch_execz BB14_2
875; GFX10-NEXT:  ; %bb.1: ; %kill
876; GFX10-NEXT:    s_mov_b64 exec, 0
877; GFX10-NEXT:  BB14_2: ; %Flow
878; GFX10-NEXT:    s_or_saveexec_b64 s[2:3], s[2:3]
879; GFX10-NEXT:    ; implicit-def: $vgpr3
880; GFX10-NEXT:    ; implicit-def: $vgpr5
881; GFX10-NEXT:    ; implicit-def: $vgpr4
882; GFX10-NEXT:    ; implicit-def: $vgpr6
883; GFX10-NEXT:    s_xor_b64 exec, exec, s[2:3]
884; GFX10-NEXT:  ; %bb.3: ; %live
885; GFX10-NEXT:    s_mov_b32 m0, s0
886; GFX10-NEXT:    v_interp_p1_f32_e32 v3, v0, attr0.x
887; GFX10-NEXT:    v_interp_p1_f32_e32 v0, v0, attr0.y
888; GFX10-NEXT:    v_mov_b32_e32 v7, v3
889; GFX10-NEXT:    v_mov_b32_e32 v11, v0
890; GFX10-NEXT:    v_mul_f32_e32 v3, v3, v2
891; GFX10-NEXT:    v_mul_f32_e32 v4, v0, v2
892; GFX10-NEXT:    v_interp_p2_f32_e32 v7, v1, attr0.x
893; GFX10-NEXT:    v_interp_p2_f32_e32 v11, v1, attr0.y
894; GFX10-NEXT:    v_mul_f32_e32 v5, v7, v2
895; GFX10-NEXT:    v_mul_f32_e32 v6, v11, v2
896; GFX10-NEXT:  ; %bb.4: ; %export
897; GFX10-NEXT:    s_or_b64 exec, exec, s[2:3]
898; GFX10-NEXT:    s_cbranch_execz BB14_6
899; GFX10-NEXT:  ; %bb.5: ; %export
900; GFX10-NEXT:    v_cvt_pkrtz_f16_f32_e32 v0, v3, v5
901; GFX10-NEXT:    v_cvt_pkrtz_f16_f32_e32 v1, v4, v6
902; GFX10-NEXT:    exp mrt0 v0, v0, v1, v1 done compr vm
903; GFX10-NEXT:    s_endpgm
904; GFX10-NEXT:  BB14_6:
905; GFX10-NEXT:    exp null off, off, off, off done vm
906; GFX10-NEXT:    s_endpgm
907.entry:
908  %val0 = extractelement <2 x float> %1, i32 0
909  %val1 = extractelement <2 x float> %1, i32 1
910  %p0 = call float @llvm.amdgcn.interp.p1(float %val0, i32 immarg 0, i32 immarg 1, i32 %0) #2
911  %sample = call float @llvm.amdgcn.image.sample.l.2darray.f32.f32(i32 1, float %p0, float %p0, float %p0, float 0.000000e+00, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
912  %cond0 = fcmp ugt float %sample, 0.000000e+00
913  br i1 %cond0, label %live, label %kill
914
915kill:
916  call void @llvm.amdgcn.kill(i1 false)
917  br label %export
918
919live:
920  %i0 = call float @llvm.amdgcn.interp.p1(float %val0, i32 immarg 0, i32 immarg 0, i32 %0) #2
921  %i1 = call float @llvm.amdgcn.interp.p2(float %i0, float %val1, i32 immarg 0, i32 immarg 0, i32 %0) #2
922  %i2 = call float @llvm.amdgcn.interp.p1(float %val0, i32 immarg 1, i32 immarg 0, i32 %0) #2
923  %i3 = call float @llvm.amdgcn.interp.p2(float %i2, float %val1, i32 immarg 1, i32 immarg 0, i32 %0) #2
924  %scale.i0 = fmul reassoc nnan nsz arcp contract float %i0, %sample
925  %scale.i1 = fmul reassoc nnan nsz arcp contract float %i1, %sample
926  %scale.i2 = fmul reassoc nnan nsz arcp contract float %i2, %sample
927  %scale.i3 = fmul reassoc nnan nsz arcp contract float %i3, %sample
928  br label %export
929
930export:
931  %proxy.0.0 = phi float [ undef, %kill ], [ %scale.i0, %live ]
932  %proxy.0.1 = phi float [ undef, %kill ], [ %scale.i1, %live ]
933  %proxy.0.2 = phi float [ undef, %kill ], [ %scale.i2, %live ]
934  %proxy.0.3 = phi float [ undef, %kill ], [ %scale.i3, %live ]
935  %out.0 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %proxy.0.0, float %proxy.0.1) #2
936  %out.1 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %proxy.0.2, float %proxy.0.3) #2
937  call void @llvm.amdgcn.exp.compr.v2f16(i32 immarg 0, i32 immarg 15, <2 x half> %out.0, <2 x half> %out.1, i1 immarg true, i1 immarg true) #3
938  ret void
939}
940
941define amdgpu_ps void @complex_loop(i32 inreg %cmpa, i32 %cmpb, i32 %cmpc) {
942; SI-LABEL: complex_loop:
943; SI:       ; %bb.0: ; %.entry
944; SI-NEXT:    s_cmp_lt_i32 s0, 1
945; SI-NEXT:    v_mov_b32_e32 v2, -1
946; SI-NEXT:    s_cbranch_scc1 BB15_6
947; SI-NEXT:  ; %bb.1: ; %.lr.ph
948; SI-NEXT:    s_mov_b32 s2, 0
949; SI-NEXT:    s_mov_b64 s[0:1], 0
950; SI-NEXT:    s_branch BB15_4
951; SI-NEXT:  BB15_2: ; %kill
952; SI-NEXT:    ; in Loop: Header=BB15_4 Depth=1
953; SI-NEXT:    s_mov_b64 exec, 0
954; SI-NEXT:  BB15_3: ; %latch
955; SI-NEXT:    ; in Loop: Header=BB15_4 Depth=1
956; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
957; SI-NEXT:    s_add_i32 s2, s2, 1
958; SI-NEXT:    v_cmp_ge_i32_e32 vcc, s2, v1
959; SI-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
960; SI-NEXT:    v_mov_b32_e32 v2, s2
961; SI-NEXT:    s_andn2_b64 exec, exec, s[0:1]
962; SI-NEXT:    s_cbranch_execz BB15_5
963; SI-NEXT:  BB15_4: ; %hdr
964; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
965; SI-NEXT:    v_cmp_gt_u32_e32 vcc, s2, v0
966; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
967; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
968; SI-NEXT:    s_cbranch_execnz BB15_2
969; SI-NEXT:    s_branch BB15_3
970; SI-NEXT:  BB15_5: ; %Flow
971; SI-NEXT:    s_or_b64 exec, exec, s[0:1]
972; SI-NEXT:  BB15_6: ; %._crit_edge
973; SI-NEXT:    exp mrt0 v2, v2, v0, v0 done compr vm
974; SI-NEXT:    s_endpgm
975;
976; GFX10-LABEL: complex_loop:
977; GFX10:       ; %bb.0: ; %.entry
978; GFX10-NEXT:    v_mov_b32_e32 v2, -1
979; GFX10-NEXT:    s_cmp_lt_i32 s0, 1
980; GFX10-NEXT:    s_cbranch_scc1 BB15_6
981; GFX10-NEXT:  ; %bb.1: ; %.lr.ph
982; GFX10-NEXT:    s_mov_b32 s2, 0
983; GFX10-NEXT:    s_mov_b64 s[0:1], 0
984; GFX10-NEXT:    s_branch BB15_4
985; GFX10-NEXT:  BB15_2: ; %kill
986; GFX10-NEXT:    ; in Loop: Header=BB15_4 Depth=1
987; GFX10-NEXT:    s_mov_b64 exec, 0
988; GFX10-NEXT:  BB15_3: ; %latch
989; GFX10-NEXT:    ; in Loop: Header=BB15_4 Depth=1
990; GFX10-NEXT:    s_or_b64 exec, exec, s[4:5]
991; GFX10-NEXT:    s_add_i32 s2, s2, 1
992; GFX10-NEXT:    v_cmp_ge_i32_e32 vcc, s2, v1
993; GFX10-NEXT:    v_mov_b32_e32 v2, s2
994; GFX10-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
995; GFX10-NEXT:    s_andn2_b64 exec, exec, s[0:1]
996; GFX10-NEXT:    s_cbranch_execz BB15_5
997; GFX10-NEXT:  BB15_4: ; %hdr
998; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
999; GFX10-NEXT:    v_cmp_gt_u32_e32 vcc, s2, v0
1000; GFX10-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1001; GFX10-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]
1002; GFX10-NEXT:    s_cbranch_execnz BB15_2
1003; GFX10-NEXT:    s_branch BB15_3
1004; GFX10-NEXT:  BB15_5: ; %Flow
1005; GFX10-NEXT:    s_or_b64 exec, exec, s[0:1]
1006; GFX10-NEXT:  BB15_6: ; %._crit_edge
1007; GFX10-NEXT:    exp mrt0 v2, v2, v0, v0 done compr vm
1008; GFX10-NEXT:    s_endpgm
1009.entry:
1010  %flaga = icmp sgt i32 %cmpa, 0
1011  br i1 %flaga, label %.lr.ph, label %._crit_edge
1012
1013.lr.ph:
1014  br label %hdr
1015
1016hdr:
1017  %ctr = phi i32 [ 0, %.lr.ph ], [ %ctr.next, %latch ]
1018  %flagb = icmp ugt i32 %ctr, %cmpb
1019  br i1 %flagb, label %kill, label %latch
1020
1021kill:
1022  call void @llvm.amdgcn.kill(i1 false)
1023  br label %latch
1024
1025latch:
1026  %ctr.next = add nuw nsw i32 %ctr, 1
1027  %flagc = icmp slt i32 %ctr.next, %cmpc
1028  br i1 %flagc, label %hdr, label %._crit_edge
1029
1030._crit_edge:
1031  %tmp = phi i32 [ -1, %.entry ], [ %ctr.next, %latch ]
1032  %out = bitcast i32 %tmp to <2 x half>
1033  call void @llvm.amdgcn.exp.compr.v2f16(i32 immarg 0, i32 immarg 15, <2 x half> %out, <2 x half> undef, i1 immarg true, i1 immarg true)
1034  ret void
1035}
1036
1037define void @skip_mode_switch(i32 %arg) {
1038; SI-LABEL: skip_mode_switch:
1039; SI:       ; %bb.0: ; %entry
1040; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1041; SI-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
1042; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1043; SI-NEXT:    s_cbranch_execz BB16_2
1044; SI-NEXT:  ; %bb.1: ; %bb.0
1045; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3
1046; SI-NEXT:  BB16_2: ; %bb.1
1047; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
1048; SI-NEXT:    s_setpc_b64 s[30:31]
1049;
1050; GFX10-LABEL: skip_mode_switch:
1051; GFX10:       ; %bb.0: ; %entry
1052; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1053; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
1054; GFX10-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
1055; GFX10-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1056; GFX10-NEXT:    s_cbranch_execz BB16_2
1057; GFX10-NEXT:  ; %bb.1: ; %bb.0
1058; GFX10-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 2), 3
1059; GFX10-NEXT:  BB16_2: ; %bb.1
1060; GFX10-NEXT:    s_or_b64 exec, exec, s[4:5]
1061; GFX10-NEXT:    s_setpc_b64 s[30:31]
1062entry:
1063  %cmp = icmp eq i32 %arg, 0
1064  br i1 %cmp, label %bb.0, label %bb.1
1065
1066bb.0:
1067  call void @llvm.amdgcn.s.setreg(i32 2049, i32 3)
1068  br label %bb.1
1069
1070bb.1:
1071  ret void
1072}
1073
1074declare float @llvm.amdgcn.interp.p1(float, i32 immarg, i32 immarg, i32) #2
1075declare float @llvm.amdgcn.interp.p2(float, float, i32 immarg, i32 immarg, i32) #2
1076declare void @llvm.amdgcn.exp.compr.v2f16(i32 immarg, i32 immarg, <2 x half>, <2 x half>, i1 immarg, i1 immarg) #3
1077declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #2
1078declare float @llvm.amdgcn.image.sample.l.2darray.f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1
1079declare <4 x float> @llvm.amdgcn.image.sample.c.1d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
1080declare void @llvm.amdgcn.kill(i1) #0
1081
1082declare void @llvm.amdgcn.s.setreg(i32 immarg, i32)
1083
1084attributes #0 = { nounwind }
1085attributes #1 = { nounwind readonly }
1086attributes #2 = { nounwind readnone speculatable }
1087attributes #3 = { inaccessiblememonly nounwind writeonly }
1088