1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s 2 3; CHECK-LABEL: {{^}}test_kill_depth_0_imm_pos: 4; CHECK-NEXT: ; %bb.0: 5; CHECK-NEXT: ; %bb.1: 6; CHECK-NEXT: s_endpgm 7define amdgpu_ps void @test_kill_depth_0_imm_pos() #0 { 8 call void @llvm.amdgcn.kill(i1 true) 9 ret void 10} 11 12; CHECK-LABEL: {{^}}test_kill_depth_0_imm_neg: 13; CHECK-NEXT: ; %bb.0: 14; CHECK-NEXT: s_mov_b64 exec, 0 15; CHECK-NEXT: s_cbranch_execnz BB1_2 16; CHECK-NEXT: ; %bb.1: 17; CHECK-NEXT: exp null off, off, off, off done vm 18; CHECK-NEXT: s_endpgm 19; CHECK-NEXT: BB1_2: 20; CHECK-NEXT: s_endpgm 21define amdgpu_ps void @test_kill_depth_0_imm_neg() #0 { 22 call void @llvm.amdgcn.kill(i1 false) 23 ret void 24} 25 26; FIXME: Ideally only one would be emitted 27; CHECK-LABEL: {{^}}test_kill_depth_0_imm_neg_x2: 28; CHECK-NEXT: ; %bb.0: 29; CHECK-NEXT: s_mov_b64 exec, 0 30; CHECK-NEXT: s_cbranch_execnz BB2_2 31; CHECK: exp null 32; CHECK-NEXT: s_endpgm 33; CHECK: BB2_2: 34; CHECK-NEXT: s_mov_b64 exec, 0 35; CHECK-NEXT: s_cbranch_execnz BB2_4 36; CHECK: exp null 37; CHECK-NEXT: s_endpgm 38; CHECK-NEXT: BB2_4: 39; CHECK-NEXT: s_endpgm 40define amdgpu_ps void @test_kill_depth_0_imm_neg_x2() #0 { 41 call void @llvm.amdgcn.kill(i1 false) 42 call void @llvm.amdgcn.kill(i1 false) 43 ret void 44} 45 46; CHECK-LABEL: {{^}}test_kill_depth_var: 47; CHECK-NEXT: ; %bb.0: 48; CHECK-NEXT: v_cmpx_gt_f32_e32 vcc, 0, v0 49; CHECK-NEXT: s_cbranch_execnz BB3_2 50; CHECK: exp null 51; CHECK-NEXT: s_endpgm 52; CHECK-NEXT: BB3_2: 53; CHECK-NEXT: s_endpgm 54define amdgpu_ps void @test_kill_depth_var(float %x) #0 { 55 %cmp = fcmp olt float %x, 0.0 56 call void @llvm.amdgcn.kill(i1 %cmp) 57 ret void 58} 59 60; FIXME: Ideally only one would be emitted 61; CHECK-LABEL: {{^}}test_kill_depth_var_x2_same: 62; CHECK-NEXT: ; %bb.0: 63; CHECK-NEXT: v_cmpx_gt_f32_e32 vcc, 0, v0 64; CHECK-NEXT: s_cbranch_execnz BB4_2 65; CHECK: exp null 66; CHECK-NEXT: s_endpgm 67; CHECK-NEXT: BB4_2: 68; CHECK-NEXT: v_cmpx_gt_f32_e32 vcc, 0, v0 69; CHECK-NEXT: s_cbranch_execnz BB4_4 70; CHECK: exp null 71; CHECK-NEXT: s_endpgm 72; CHECK-NEXT: BB4_4: 73; CHECK-NEXT: s_endpgm 74define amdgpu_ps void @test_kill_depth_var_x2_same(float %x) #0 { 75 %cmp = fcmp olt float %x, 0.0 76 call void @llvm.amdgcn.kill(i1 %cmp) 77 call void @llvm.amdgcn.kill(i1 %cmp) 78 ret void 79} 80 81; FIXME: Ideally only one early-exit would be emitted 82; CHECK-LABEL: {{^}}test_kill_depth_var_x2: 83; CHECK-NEXT: ; %bb.0: 84; CHECK-NEXT: v_cmpx_gt_f32_e32 vcc, 0, v0 85; CHECK-NEXT: s_cbranch_execnz BB5_2 86; CHECK: exp null 87; CHECK-NEXT: s_endpgm 88; CHECK-NEXT: BB5_2: 89; CHECK-NEXT: v_cmpx_gt_f32_e32 vcc, 0, v1 90; CHECK-NEXT: s_cbranch_execnz BB5_4 91; CHECK: exp null 92; CHECK-NEXT: s_endpgm 93; CHECK-NEXT: BB5_4: 94; CHECK-NEXT: s_endpgm 95define amdgpu_ps void @test_kill_depth_var_x2(float %x, float %y) #0 { 96 %cmp.x = fcmp olt float %x, 0.0 97 call void @llvm.amdgcn.kill(i1 %cmp.x) 98 %cmp.y = fcmp olt float %y, 0.0 99 call void @llvm.amdgcn.kill(i1 %cmp.y) 100 ret void 101} 102 103; CHECK-LABEL: {{^}}test_kill_depth_var_x2_instructions: 104; CHECK-NEXT: ; %bb.0: 105; CHECK-NEXT: v_cmpx_gt_f32_e32 vcc, 0, v0 106; CHECK-NEXT: s_cbranch_execnz BB6_2 107; CHECK-NEXT: ; %bb.1: 108; CHECK-NEXT: exp 109; CHECK-NEXT: s_endpgm 110; CHECK-NEXT: BB6_2: 111; CHECK: v_mov_b32_e64 v7, -1 112; CHECK: v_cmpx_gt_f32_e32 vcc, 0, v7 113; CHECK-NEXT: s_cbranch_execnz BB6_4 114; CHECK-NEXT: ; %bb.3: 115; CHECK-NEXT: exp 116; CHECK-NEXT: s_endpgm 117; CHECK-NEXT: BB6_4: 118; CHECK-NEXT: s_endpgm 119define amdgpu_ps void @test_kill_depth_var_x2_instructions(float %x) #0 { 120 %cmp.x = fcmp olt float %x, 0.0 121 call void @llvm.amdgcn.kill(i1 %cmp.x) 122 %y = call float asm sideeffect "v_mov_b32_e64 v7, -1", "={v7}"() 123 %cmp.y = fcmp olt float %y, 0.0 124 call void @llvm.amdgcn.kill(i1 %cmp.y) 125 ret void 126} 127 128; FIXME: why does the skip depend on the asm length in the same block? 129 130; CHECK-LABEL: {{^}}test_kill_control_flow: 131; CHECK: s_cmp_lg_u32 s{{[0-9]+}}, 0 132; CHECK: s_cbranch_scc1 [[RETURN_BB:BB[0-9]+_[0-9]+]] 133 134; CHECK-NEXT: ; %bb.1: 135; CHECK: v_mov_b32_e64 v7, -1 136; CHECK: v_nop_e64 137; CHECK: v_nop_e64 138; CHECK: v_nop_e64 139; CHECK: v_nop_e64 140; CHECK: v_nop_e64 141; CHECK: v_nop_e64 142; CHECK: v_nop_e64 143; CHECK: v_nop_e64 144; CHECK: v_nop_e64 145; CHECK: v_nop_e64 146 147; CHECK: v_cmpx_gt_f32_e32 vcc, 0, v7 148 149; TODO: We could do an early-exit here (the branch above is uniform!) 150; CHECK-NOT: exp null 151 152; CHECK: v_mov_b32_e32 v0, 1.0 153define amdgpu_ps float @test_kill_control_flow(i32 inreg %arg) #0 { 154entry: 155 %cmp = icmp eq i32 %arg, 0 156 br i1 %cmp, label %bb, label %exit 157 158bb: 159 %var = call float asm sideeffect " 160 v_mov_b32_e64 v7, -1 161 v_nop_e64 162 v_nop_e64 163 v_nop_e64 164 v_nop_e64 165 v_nop_e64 166 v_nop_e64 167 v_nop_e64 168 v_nop_e64 169 v_nop_e64 170 v_nop_e64", "={v7}"() 171 %cmp.var = fcmp olt float %var, 0.0 172 call void @llvm.amdgcn.kill(i1 %cmp.var) 173 br label %exit 174 175exit: 176 ret float 1.0 177} 178 179; CHECK-LABEL: {{^}}test_kill_control_flow_remainder: 180; CHECK: s_cmp_lg_u32 s{{[0-9]+}}, 0 181; CHECK-NEXT: v_mov_b32_e32 v{{[0-9]+}}, 0 182; CHECK-NEXT: s_cbranch_scc1 [[RETURN_BB:BB[0-9]+_[0-9]+]] 183 184; CHECK-NEXT: ; %bb.1: ; %bb 185; CHECK: v_mov_b32_e64 v7, -1 186; CHECK: v_nop_e64 187; CHECK: v_nop_e64 188; CHECK: v_nop_e64 189; CHECK: v_nop_e64 190; CHECK: v_nop_e64 191; CHECK: v_nop_e64 192; CHECK: v_nop_e64 193; CHECK: v_nop_e64 194; CHECK: ;;#ASMEND 195; CHECK: v_mov_b32_e64 v8, -1 196; CHECK: ;;#ASMEND 197; CHECK: v_cmpx_gt_f32_e32 vcc, 0, v7 198 199; TODO: We could do an early-exit here (the branch above is uniform!) 200; CHECK-NOT: exp null 201 202; CHECK: buffer_store_dword v8 203; CHECK: v_mov_b32_e64 v9, -2 204 205; CHECK: {{^}}BB{{[0-9]+_[0-9]+}}: 206; CHECK: buffer_store_dword v9 207; CHECK-NEXT: s_endpgm 208define amdgpu_ps void @test_kill_control_flow_remainder(i32 inreg %arg) #0 { 209entry: 210 %cmp = icmp eq i32 %arg, 0 211 br i1 %cmp, label %bb, label %exit 212 213bb: 214 %var = call float asm sideeffect " 215 v_mov_b32_e64 v7, -1 216 v_nop_e64 217 v_nop_e64 218 v_nop_e64 219 v_nop_e64 220 v_nop_e64 221 v_nop_e64 222 v_nop_e64 223 v_nop_e64 224 v_nop_e64 225 v_nop_e64 226 v_nop_e64", "={v7}"() 227 %live.across = call float asm sideeffect "v_mov_b32_e64 v8, -1", "={v8}"() 228 %cmp.var = fcmp olt float %var, 0.0 229 call void @llvm.amdgcn.kill(i1 %cmp.var) 230 store volatile float %live.across, float addrspace(1)* undef 231 %live.out = call float asm sideeffect "v_mov_b32_e64 v9, -2", "={v9}"() 232 br label %exit 233 234exit: 235 %phi = phi float [ 0.0, %entry ], [ %live.out, %bb ] 236 store float %phi, float addrspace(1)* undef 237 ret void 238} 239 240; CHECK-LABEL: {{^}}test_kill_divergent_loop: 241; CHECK: v_cmp_eq_u32_e32 vcc, 0, v0 242; CHECK-NEXT: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], vcc 243; CHECK-NEXT: s_xor_b64 [[SAVEEXEC]], exec, [[SAVEEXEC]] 244; CHECK-NEXT: s_cbranch_execz [[EXIT:BB[0-9]+_[0-9]+]] 245 246; CHECK: ; %bb.{{[0-9]+}}: ; %bb.preheader 247; CHECK: s_mov_b32 248 249; CHECK: [[LOOP_BB:BB[0-9]+_[0-9]+]]: 250 251; CHECK: v_mov_b32_e64 v7, -1 252; CHECK: v_nop_e64 253; CHECK: v_cmpx_gt_f32_e32 vcc, 0, v7 254 255; CHECK-NEXT: ; %bb.3: 256; CHECK: buffer_load_dword [[LOAD:v[0-9]+]] 257; CHECK: v_cmp_eq_u32_e32 vcc, 0, [[LOAD]] 258; CHECK-NEXT: s_and_b64 vcc, exec, vcc 259; CHECK-NEXT: s_cbranch_vccnz [[LOOP_BB]] 260 261; CHECK-NEXT: {{^}}[[EXIT]]: 262; CHECK: s_or_b64 exec, exec, [[SAVEEXEC]] 263; CHECK: buffer_store_dword 264; CHECK: s_endpgm 265define amdgpu_ps void @test_kill_divergent_loop(i32 %arg) #0 { 266entry: 267 %cmp = icmp eq i32 %arg, 0 268 br i1 %cmp, label %bb, label %exit 269 270bb: 271 %var = call float asm sideeffect " 272 v_mov_b32_e64 v7, -1 273 v_nop_e64 274 v_nop_e64 275 v_nop_e64 276 v_nop_e64 277 v_nop_e64 278 v_nop_e64 279 v_nop_e64 280 v_nop_e64 281 v_nop_e64 282 v_nop_e64", "={v7}"() 283 %cmp.var = fcmp olt float %var, 0.0 284 call void @llvm.amdgcn.kill(i1 %cmp.var) 285 %vgpr = load volatile i32, i32 addrspace(1)* undef 286 %loop.cond = icmp eq i32 %vgpr, 0 287 br i1 %loop.cond, label %bb, label %exit 288 289exit: 290 store volatile i32 8, i32 addrspace(1)* undef 291 ret void 292} 293 294; bug 28550 295; CHECK-LABEL: {{^}}phi_use_def_before_kill: 296; CHECK: v_cndmask_b32_e64 [[PHIREG:v[0-9]+]], 0, -1.0, 297; CHECK: v_cmpx_lt_f32_e32 vcc, 0, 298; CHECK-NEXT: s_cbranch_execnz [[BB4:BB[0-9]+_[0-9]+]] 299 300; CHECK: exp 301; CHECK-NEXT: s_endpgm 302 303; CHECK: [[KILLBB:BB[0-9]+_[0-9]+]]: 304; CHECK-NEXT: s_cbranch_scc0 [[PHIBB:BB[0-9]+_[0-9]+]] 305 306; CHECK: [[PHIBB]]: 307; CHECK: v_cmp_eq_f32_e32 vcc, 0, [[PHIREG]] 308; CHECK: s_cbranch_vccz [[ENDBB:BB[0-9]+_[0-9]+]] 309 310; CHECK: ; %bb10 311; CHECK: v_mov_b32_e32 v{{[0-9]+}}, 9 312; CHECK: buffer_store_dword 313 314; CHECK: [[ENDBB]]: 315; CHECK-NEXT: s_endpgm 316define amdgpu_ps void @phi_use_def_before_kill(float inreg %x) #0 { 317bb: 318 %tmp = fadd float %x, 1.000000e+00 319 %tmp1 = fcmp olt float 0.000000e+00, %tmp 320 %tmp2 = select i1 %tmp1, float -1.000000e+00, float 0.000000e+00 321 %cmp.tmp2 = fcmp olt float %tmp2, 0.0 322 call void @llvm.amdgcn.kill(i1 %cmp.tmp2) 323 br i1 undef, label %phibb, label %bb8 324 325phibb: 326 %tmp5 = phi float [ %tmp2, %bb ], [ 4.0, %bb8 ] 327 %tmp6 = fcmp oeq float %tmp5, 0.000000e+00 328 br i1 %tmp6, label %bb10, label %end 329 330bb8: 331 store volatile i32 8, i32 addrspace(1)* undef 332 br label %phibb 333 334bb10: 335 store volatile i32 9, i32 addrspace(1)* undef 336 br label %end 337 338end: 339 ret void 340} 341 342; CHECK-LABEL: {{^}}no_skip_no_successors: 343; CHECK: v_cmp_nge_f32 344; CHECK: s_cbranch_vccz [[SKIPKILL:BB[0-9]+_[0-9]+]] 345 346; CHECK: ; %bb6 347; CHECK: s_mov_b64 exec, 0 348 349; CHECK: [[SKIPKILL]]: 350; CHECK: v_cmp_nge_f32_e32 vcc 351; CHECK: %bb.3: ; %bb5 352; CHECK-NEXT: .Lfunc_end{{[0-9]+}} 353define amdgpu_ps void @no_skip_no_successors(float inreg %arg, float inreg %arg1) #0 { 354bb: 355 %tmp = fcmp ult float %arg1, 0.000000e+00 356 %tmp2 = fcmp ult float %arg, 0x3FCF5C2900000000 357 br i1 %tmp, label %bb6, label %bb3 358 359bb3: ; preds = %bb 360 br i1 %tmp2, label %bb5, label %bb4 361 362bb4: ; preds = %bb3 363 br i1 true, label %bb5, label %bb7 364 365bb5: ; preds = %bb4, %bb3 366 unreachable 367 368bb6: ; preds = %bb 369 call void @llvm.amdgcn.kill(i1 false) 370 unreachable 371 372bb7: ; preds = %bb4 373 ret void 374} 375 376; CHECK-LABEL: {{^}}if_after_kill_block: 377; CHECK: ; %bb.0: 378; CHECK: s_and_saveexec_b64 379; CHECK: s_xor_b64 380 381; CHECK: v_cmpx_gt_f32_e32 vcc, 0, 382; CHECK: BB{{[0-9]+_[0-9]+}}: 383; CHECK: s_or_b64 exec, exec 384; CHECK: image_sample_c 385 386; CHECK: v_cmp_neq_f32_e32 vcc, 0, 387; CHECK: s_and_saveexec_b64 s{{\[[0-9]+:[0-9]+\]}}, vcc 388; CHECK-NEXT: s_cbranch_execz [[END:BB[0-9]+_[0-9]+]] 389; CHECK-NOT: branch 390 391; CHECK: ; %bb.{{[0-9]+}}: ; %bb8 392; CHECK: buffer_store_dword 393 394; CHECK: [[END]]: 395; CHECK: s_endpgm 396define amdgpu_ps void @if_after_kill_block(float %arg, float %arg1, float %arg2, float %arg3) #0 { 397bb: 398 %tmp = fcmp ult float %arg1, 0.000000e+00 399 br i1 %tmp, label %bb3, label %bb4 400 401bb3: ; preds = %bb 402 %cmp.arg = fcmp olt float %arg, 0.0 403 call void @llvm.amdgcn.kill(i1 %cmp.arg) 404 br label %bb4 405 406bb4: ; preds = %bb3, %bb 407 %tmp5 = call <4 x float> @llvm.amdgcn.image.sample.c.1d.v4f32.f32(i32 16, float %arg2, float %arg3, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0) 408 %tmp6 = extractelement <4 x float> %tmp5, i32 0 409 %tmp7 = fcmp une float %tmp6, 0.000000e+00 410 br i1 %tmp7, label %bb8, label %bb9 411 412bb8: ; preds = %bb9, %bb4 413 store volatile i32 9, i32 addrspace(1)* undef 414 ret void 415 416bb9: ; preds = %bb4 417 ret void 418} 419 420; CHECK-LABEL: {{^}}cbranch_kill: 421; CHECK-NOT: exp null off, off, off, off done vm 422define amdgpu_ps void @cbranch_kill(i32 inreg %0, <2 x float> %1) { 423.entry: 424 %val0 = extractelement <2 x float> %1, i32 0 425 %val1 = extractelement <2 x float> %1, i32 1 426 %p0 = call float @llvm.amdgcn.interp.p1(float %val0, i32 immarg 0, i32 immarg 1, i32 %0) #2 427 %sample = call float @llvm.amdgcn.image.sample.l.2darray.f32.f32(i32 1, float %p0, float %p0, float %p0, float 0.000000e+00, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0) 428 %cond0 = fcmp ugt float %sample, 0.000000e+00 429 br i1 %cond0, label %live, label %kill 430 431kill: 432 call void @llvm.amdgcn.kill(i1 false) 433 br label %export 434 435live: 436 %i0 = call float @llvm.amdgcn.interp.p1(float %val0, i32 immarg 0, i32 immarg 0, i32 %0) #2 437 %i1 = call float @llvm.amdgcn.interp.p2(float %i0, float %val1, i32 immarg 0, i32 immarg 0, i32 %0) #2 438 %i2 = call float @llvm.amdgcn.interp.p1(float %val0, i32 immarg 1, i32 immarg 0, i32 %0) #2 439 %i3 = call float @llvm.amdgcn.interp.p2(float %i2, float %val1, i32 immarg 1, i32 immarg 0, i32 %0) #2 440 %scale.i0 = fmul reassoc nnan nsz arcp contract float %i0, %sample 441 %scale.i1 = fmul reassoc nnan nsz arcp contract float %i1, %sample 442 %scale.i2 = fmul reassoc nnan nsz arcp contract float %i2, %sample 443 %scale.i3 = fmul reassoc nnan nsz arcp contract float %i3, %sample 444 br label %export 445 446export: 447 %proxy.0.0 = phi float [ undef, %kill ], [ %scale.i0, %live ] 448 %proxy.0.1 = phi float [ undef, %kill ], [ %scale.i1, %live ] 449 %proxy.0.2 = phi float [ undef, %kill ], [ %scale.i2, %live ] 450 %proxy.0.3 = phi float [ undef, %kill ], [ %scale.i3, %live ] 451 %out.0 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %proxy.0.0, float %proxy.0.1) #2 452 %out.1 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %proxy.0.2, float %proxy.0.3) #2 453 call void @llvm.amdgcn.exp.compr.v2f16(i32 immarg 0, i32 immarg 15, <2 x half> %out.0, <2 x half> %out.1, i1 immarg true, i1 immarg true) #3 454 ret void 455} 456 457; CHECK-LABEL: {{^}}complex_loop: 458; CHECK: s_mov_b64 exec, 0 459; CHECK-NOT: exp null 460define amdgpu_ps void @complex_loop(i32 inreg %cmpa, i32 %cmpb, i32 %cmpc) { 461.entry: 462 %flaga = icmp sgt i32 %cmpa, 0 463 br i1 %flaga, label %.lr.ph, label %._crit_edge 464 465.lr.ph: 466 br label %hdr 467 468hdr: 469 %ctr = phi i32 [ 0, %.lr.ph ], [ %ctr.next, %latch ] 470 %flagb = icmp ugt i32 %ctr, %cmpb 471 br i1 %flagb, label %kill, label %latch 472 473kill: 474 call void @llvm.amdgcn.kill(i1 false) 475 br label %latch 476 477latch: 478 %ctr.next = add nuw nsw i32 %ctr, 1 479 %flagc = icmp slt i32 %ctr.next, %cmpc 480 br i1 %flagc, label %hdr, label %._crit_edge 481 482._crit_edge: 483 %tmp = phi i32 [ -1, %.entry ], [ %ctr.next, %latch ] 484 %out = bitcast i32 %tmp to <2 x half> 485 call void @llvm.amdgcn.exp.compr.v2f16(i32 immarg 0, i32 immarg 15, <2 x half> %out, <2 x half> undef, i1 immarg true, i1 immarg true) 486 ret void 487} 488 489; CHECK-LABEL: {{^}}skip_mode_switch: 490; CHECK: s_and_saveexec_b64 491; CHECK-NEXT: s_cbranch_execz 492; CHECK: s_setreg_imm32 493; CHECK: s_or_b64 exec, exec 494define void @skip_mode_switch(i32 %arg) { 495entry: 496 %cmp = icmp eq i32 %arg, 0 497 br i1 %cmp, label %bb.0, label %bb.1 498 499bb.0: 500 call void @llvm.amdgcn.s.setreg(i32 2049, i32 3) 501 br label %bb.1 502 503bb.1: 504 ret void 505} 506 507declare float @llvm.amdgcn.interp.p1(float, i32 immarg, i32 immarg, i32) #2 508declare float @llvm.amdgcn.interp.p2(float, float, i32 immarg, i32 immarg, i32) #2 509declare void @llvm.amdgcn.exp.compr.v2f16(i32 immarg, i32 immarg, <2 x half>, <2 x half>, i1 immarg, i1 immarg) #3 510declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #2 511declare float @llvm.amdgcn.image.sample.l.2darray.f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1 512declare <4 x float> @llvm.amdgcn.image.sample.c.1d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 513declare void @llvm.amdgcn.kill(i1) #0 514 515declare void @llvm.amdgcn.s.setreg(i32 immarg, i32) 516 517attributes #0 = { nounwind } 518attributes #1 = { nounwind readonly } 519attributes #2 = { nounwind readnone speculatable } 520attributes #3 = { inaccessiblememonly nounwind writeonly } 521