1; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
3
4declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
5
6; GCN-LABEL: {{^}}sint_to_fp_i32_to_f64
7; GCN: v_cvt_f64_i32_e32
8define amdgpu_kernel void @sint_to_fp_i32_to_f64(double addrspace(1)* %out, i32 %in) {
9  %result = sitofp i32 %in to double
10  store double %result, double addrspace(1)* %out
11  ret void
12}
13
14; We can't fold the SGPRs into v_cndmask_b32_e64, because it already
15; uses an SGPR (implicit vcc).
16
17; GCN-LABEL: {{^}}sint_to_fp_i1_f64:
18; VI-DAG: s_cmp_eq_u32
19; VI-DAG: s_cselect_b32 s[[SSEL:[0-9]+]], 0xbff00000, 0
20; VI-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
21; VI-DAG: v_mov_b32_e32 v[[SEL:[0-9]+]], s[[SSEL]]
22; VI: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[ZERO]]:[[SEL]]{{\]}}
23; VI: s_endpgm
24
25; SI-DAG: s_cmp_eq_u32
26; SI-DAG: s_cselect_b64 vcc, -1, 0
27; SI-DAG: v_cndmask_b32_e32 v[[SEL:[0-9]+]], 0, v{{[0-9]+}}, vcc
28; SI-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
29; SI: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[ZERO]]:[[SEL]]{{\]}}
30; SI: s_endpgm
31define amdgpu_kernel void @sint_to_fp_i1_f64(double addrspace(1)* %out, i32 %in) {
32  %cmp = icmp eq i32 %in, 0
33  %fp = sitofp i1 %cmp to double
34  store double %fp, double addrspace(1)* %out, align 4
35  ret void
36}
37
38; GCN-LABEL: {{^}}sint_to_fp_i1_f64_load:
39; GCN: v_cndmask_b32_e64 [[IRESULT:v[0-9]]], 0, -1
40; GCN: v_cvt_f64_i32_e32 [[RESULT:v\[[0-9]+:[0-9]\]]], [[IRESULT]]
41; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
42; GCN: s_endpgm
43define amdgpu_kernel void @sint_to_fp_i1_f64_load(double addrspace(1)* %out, i1 %in) {
44  %fp = sitofp i1 %in to double
45  store double %fp, double addrspace(1)* %out, align 8
46  ret void
47}
48
49; GCN-LABEL: @s_sint_to_fp_i64_to_f64
50define amdgpu_kernel void @s_sint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 %in) {
51  %result = sitofp i64 %in to double
52  store double %result, double addrspace(1)* %out
53  ret void
54}
55
56; GCN-LABEL: @v_sint_to_fp_i64_to_f64
57; GCN: flat_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
58; GCN-DAG: v_cvt_f64_i32_e32 [[HI_CONV:v\[[0-9]+:[0-9]+\]]], v[[HI]]
59; GCN-DAG: v_cvt_f64_u32_e32 [[LO_CONV:v\[[0-9]+:[0-9]+\]]], v[[LO]]
60; GCN-DAG: v_ldexp_f64 [[LDEXP:v\[[0-9]+:[0-9]+\]]], [[HI_CONV]], 32
61; GCN: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[LDEXP]], [[LO_CONV]]
62; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
63define amdgpu_kernel void @v_sint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 addrspace(1)* %in) {
64  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
65  %gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
66  %val = load i64, i64 addrspace(1)* %gep, align 8
67  %result = sitofp i64 %val to double
68  store double %result, double addrspace(1)* %out
69  ret void
70}
71
72; FIXME: bfe and sext on VI+
73; GCN-LABEL: {{^}}s_sint_to_fp_i8_to_f64:
74; GCN: s_load_dword [[VAL:s[0-9]+]]
75; SI-NOT: bfe
76; SI: s_sext_i32_i8 [[SEXT:s[0-9]+]], [[VAL]]
77
78; VI: s_bfe_i32 [[BFE:s[0-9]+]], [[VAL]], 0x80000
79; VI: s_sext_i32_i16 [[SEXT:s[0-9]+]], [[BFE]]
80
81; GCN: v_cvt_f64_i32_e32 v{{\[[0-9]+:[0-9]+\]}}, [[SEXT]]
82define amdgpu_kernel void @s_sint_to_fp_i8_to_f64(double addrspace(1)* %out, i8 %in) {
83  %fp = sitofp i8 %in to double
84  store double %fp, double addrspace(1)* %out
85  ret void
86}
87
88; GCN-LABEL: {{^}}v_sint_to_fp_i8_to_f64:
89; GCN: v_bfe_i32 [[SEXT:v[0-9]+]]
90; GCN: v_cvt_f64_i32_e32 v{{\[[0-9]+:[0-9]+\]}}, [[SEXT]]
91define double @v_sint_to_fp_i8_to_f64(i8 %in) {
92  %fp = sitofp i8 %in to double
93  ret double %fp
94}
95