1; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
3
4declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
5
6; GCN-LABEL: {{^}}sint_to_fp_i32_to_f64
7; GCN: v_cvt_f64_i32_e32
8define amdgpu_kernel void @sint_to_fp_i32_to_f64(double addrspace(1)* %out, i32 %in) {
9  %result = sitofp i32 %in to double
10  store double %result, double addrspace(1)* %out
11  ret void
12}
13
14; We can't fold the SGPRs into v_cndmask_b32_e64, because it already
15; uses an SGPR (implicit vcc).
16
17; GCN-LABEL: {{^}}sint_to_fp_i1_f64:
18; GCN-DAG: v_cmp_eq_u32_e64 vcc,
19; GCN-DAG: v_cndmask_b32_e32 v[[SEL:[0-9]+]], 0, v{{[0-9]+}}
20; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
21; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[ZERO]]:[[SEL]]{{\]}}
22; GCN: s_endpgm
23define amdgpu_kernel void @sint_to_fp_i1_f64(double addrspace(1)* %out, i32 %in) {
24  %cmp = icmp eq i32 %in, 0
25  %fp = sitofp i1 %cmp to double
26  store double %fp, double addrspace(1)* %out, align 4
27  ret void
28}
29
30; GCN-LABEL: {{^}}sint_to_fp_i1_f64_load:
31; GCN: v_cndmask_b32_e64 [[IRESULT:v[0-9]]], 0, -1
32; GCN: v_cvt_f64_i32_e32 [[RESULT:v\[[0-9]+:[0-9]\]]], [[IRESULT]]
33; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
34; GCN: s_endpgm
35define amdgpu_kernel void @sint_to_fp_i1_f64_load(double addrspace(1)* %out, i1 %in) {
36  %fp = sitofp i1 %in to double
37  store double %fp, double addrspace(1)* %out, align 8
38  ret void
39}
40
41; GCN-LABEL: @s_sint_to_fp_i64_to_f64
42define amdgpu_kernel void @s_sint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 %in) {
43  %result = sitofp i64 %in to double
44  store double %result, double addrspace(1)* %out
45  ret void
46}
47
48; GCN-LABEL: @v_sint_to_fp_i64_to_f64
49; GCN: flat_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
50; GCN-DAG: v_cvt_f64_i32_e32 [[HI_CONV:v\[[0-9]+:[0-9]+\]]], v[[HI]]
51; GCN-DAG: v_cvt_f64_u32_e32 [[LO_CONV:v\[[0-9]+:[0-9]+\]]], v[[LO]]
52; GCN-DAG: v_ldexp_f64 [[LDEXP:v\[[0-9]+:[0-9]+\]]], [[HI_CONV]], 32
53; GCN: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[LDEXP]], [[LO_CONV]]
54; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
55define amdgpu_kernel void @v_sint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 addrspace(1)* %in) {
56  %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
57  %gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
58  %val = load i64, i64 addrspace(1)* %gep, align 8
59  %result = sitofp i64 %val to double
60  store double %result, double addrspace(1)* %out
61  ret void
62}
63
64; FIXME: bfe and sext on VI+
65; GCN-LABEL: {{^}}s_sint_to_fp_i8_to_f64:
66; GCN: s_load_dword [[VAL:s[0-9]+]]
67; SI-NOT: bfe
68; SI: s_sext_i32_i8 [[SEXT:s[0-9]+]], [[VAL]]
69
70; VI: s_bfe_i32 [[BFE:s[0-9]+]], [[VAL]], 0x80000
71; VI: s_sext_i32_i16 [[SEXT:s[0-9]+]], [[BFE]]
72
73; GCN: v_cvt_f64_i32_e32 v{{\[[0-9]+:[0-9]+\]}}, [[SEXT]]
74define amdgpu_kernel void @s_sint_to_fp_i8_to_f64(double addrspace(1)* %out, i8 %in) {
75  %fp = sitofp i8 %in to double
76  store double %fp, double addrspace(1)* %out
77  ret void
78}
79
80; GCN-LABEL: {{^}}v_sint_to_fp_i8_to_f64:
81; GCN: v_bfe_i32 [[SEXT:v[0-9]+]]
82; GCN: v_cvt_f64_i32_e32 v{{\[[0-9]+:[0-9]+\]}}, [[SEXT]]
83define double @v_sint_to_fp_i8_to_f64(i8 %in) {
84  %fp = sitofp i8 %in to double
85  ret double %fp
86}
87