1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=SI 3; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=VI 4; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck %s --check-prefix=GFX9 5; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck %s --check-prefix=GFX10 6; RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck %s --check-prefix=GFX11 7 8; Test that add/sub with a constant is swapped to sub/add with negated 9; constant to minimize code size. 10 11define amdgpu_kernel void @v_test_i32_x_sub_64(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { 12; SI-LABEL: v_test_i32_x_sub_64: 13; SI: ; %bb.0: 14; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 15; SI-NEXT: s_mov_b32 s7, 0xf000 16; SI-NEXT: s_mov_b32 s6, 0 17; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 18; SI-NEXT: v_mov_b32_e32 v1, 0 19; SI-NEXT: s_waitcnt lgkmcnt(0) 20; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 21; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 22; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 23; SI-NEXT: s_waitcnt vmcnt(0) 24; SI-NEXT: v_subrev_i32_e32 v2, vcc, 64, v2 25; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 26; SI-NEXT: s_endpgm 27; 28; VI-LABEL: v_test_i32_x_sub_64: 29; VI: ; %bb.0: 30; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 31; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 32; VI-NEXT: s_waitcnt lgkmcnt(0) 33; VI-NEXT: v_mov_b32_e32 v1, s3 34; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 35; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 36; VI-NEXT: flat_load_dword v3, v[0:1] 37; VI-NEXT: v_mov_b32_e32 v1, s1 38; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 39; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 40; VI-NEXT: s_waitcnt vmcnt(0) 41; VI-NEXT: v_subrev_u32_e32 v2, vcc, 64, v3 42; VI-NEXT: flat_store_dword v[0:1], v2 43; VI-NEXT: s_endpgm 44; 45; GFX9-LABEL: v_test_i32_x_sub_64: 46; GFX9: ; %bb.0: 47; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 48; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 49; GFX9-NEXT: s_waitcnt lgkmcnt(0) 50; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 51; GFX9-NEXT: s_waitcnt vmcnt(0) 52; GFX9-NEXT: v_subrev_u32_e32 v1, 64, v1 53; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 54; GFX9-NEXT: s_endpgm 55; 56; GFX10-LABEL: v_test_i32_x_sub_64: 57; GFX10: ; %bb.0: 58; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 59; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 60; GFX10-NEXT: s_waitcnt lgkmcnt(0) 61; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 62; GFX10-NEXT: s_waitcnt vmcnt(0) 63; GFX10-NEXT: v_subrev_nc_u32_e32 v1, 64, v1 64; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 65; GFX10-NEXT: s_endpgm 66; 67; GFX11-LABEL: v_test_i32_x_sub_64: 68; GFX11: ; %bb.0: 69; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 70; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 71; GFX11-NEXT: s_waitcnt lgkmcnt(0) 72; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 73; GFX11-NEXT: s_waitcnt vmcnt(0) 74; GFX11-NEXT: v_subrev_nc_u32_e32 v1, 64, v1 75; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 76; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 77; GFX11-NEXT: s_endpgm 78 %tid = call i32 @llvm.amdgcn.workitem.id.x() 79 %tid.ext = sext i32 %tid to i64 80 %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %tid.ext 81 %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext 82 %x = load i32, i32 addrspace(1)* %gep 83 %result = sub i32 %x, 64 84 store i32 %result, i32 addrspace(1)* %gep.out 85 ret void 86} 87 88define amdgpu_kernel void @v_test_i32_x_sub_64_multi_use(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { 89; SI-LABEL: v_test_i32_x_sub_64_multi_use: 90; SI: ; %bb.0: 91; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 92; SI-NEXT: s_mov_b32 s7, 0xf000 93; SI-NEXT: s_mov_b32 s6, 0 94; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 95; SI-NEXT: v_mov_b32_e32 v1, 0 96; SI-NEXT: s_waitcnt lgkmcnt(0) 97; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 98; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc 99; SI-NEXT: s_waitcnt vmcnt(0) 100; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 glc 101; SI-NEXT: s_waitcnt vmcnt(0) 102; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 103; SI-NEXT: v_subrev_i32_e32 v2, vcc, 64, v2 104; SI-NEXT: v_subrev_i32_e32 v3, vcc, 64, v3 105; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 106; SI-NEXT: s_waitcnt vmcnt(0) 107; SI-NEXT: buffer_store_dword v3, v[0:1], s[0:3], 0 addr64 108; SI-NEXT: s_waitcnt vmcnt(0) 109; SI-NEXT: s_endpgm 110; 111; VI-LABEL: v_test_i32_x_sub_64_multi_use: 112; VI: ; %bb.0: 113; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 114; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 115; VI-NEXT: s_waitcnt lgkmcnt(0) 116; VI-NEXT: v_mov_b32_e32 v1, s3 117; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 118; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 119; VI-NEXT: flat_load_dword v3, v[0:1] glc 120; VI-NEXT: s_waitcnt vmcnt(0) 121; VI-NEXT: flat_load_dword v4, v[0:1] glc 122; VI-NEXT: s_waitcnt vmcnt(0) 123; VI-NEXT: v_mov_b32_e32 v1, s1 124; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 125; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 126; VI-NEXT: v_subrev_u32_e32 v2, vcc, 64, v3 127; VI-NEXT: v_subrev_u32_e32 v3, vcc, 64, v4 128; VI-NEXT: flat_store_dword v[0:1], v2 129; VI-NEXT: s_waitcnt vmcnt(0) 130; VI-NEXT: flat_store_dword v[0:1], v3 131; VI-NEXT: s_waitcnt vmcnt(0) 132; VI-NEXT: s_endpgm 133; 134; GFX9-LABEL: v_test_i32_x_sub_64_multi_use: 135; GFX9: ; %bb.0: 136; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 137; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 138; GFX9-NEXT: s_waitcnt lgkmcnt(0) 139; GFX9-NEXT: global_load_dword v1, v0, s[2:3] glc 140; GFX9-NEXT: s_waitcnt vmcnt(0) 141; GFX9-NEXT: global_load_dword v2, v0, s[2:3] glc 142; GFX9-NEXT: s_waitcnt vmcnt(0) 143; GFX9-NEXT: v_subrev_u32_e32 v1, 64, v1 144; GFX9-NEXT: v_subrev_u32_e32 v2, 64, v2 145; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 146; GFX9-NEXT: s_waitcnt vmcnt(0) 147; GFX9-NEXT: global_store_dword v0, v2, s[0:1] 148; GFX9-NEXT: s_waitcnt vmcnt(0) 149; GFX9-NEXT: s_endpgm 150; 151; GFX10-LABEL: v_test_i32_x_sub_64_multi_use: 152; GFX10: ; %bb.0: 153; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 154; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 155; GFX10-NEXT: s_waitcnt lgkmcnt(0) 156; GFX10-NEXT: global_load_dword v1, v0, s[2:3] glc dlc 157; GFX10-NEXT: s_waitcnt vmcnt(0) 158; GFX10-NEXT: global_load_dword v2, v0, s[2:3] glc dlc 159; GFX10-NEXT: s_waitcnt vmcnt(0) 160; GFX10-NEXT: v_subrev_nc_u32_e32 v1, 64, v1 161; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 64, v2 162; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 163; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 164; GFX10-NEXT: global_store_dword v0, v2, s[0:1] 165; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 166; GFX10-NEXT: s_endpgm 167; 168; GFX11-LABEL: v_test_i32_x_sub_64_multi_use: 169; GFX11: ; %bb.0: 170; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 171; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 172; GFX11-NEXT: s_waitcnt lgkmcnt(0) 173; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] glc dlc 174; GFX11-NEXT: s_waitcnt vmcnt(0) 175; GFX11-NEXT: global_load_b32 v2, v0, s[2:3] glc dlc 176; GFX11-NEXT: s_waitcnt vmcnt(0) 177; GFX11-NEXT: v_subrev_nc_u32_e32 v1, 64, v1 178; GFX11-NEXT: v_subrev_nc_u32_e32 v2, 64, v2 179; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] dlc 180; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 181; GFX11-NEXT: global_store_b32 v0, v2, s[0:1] dlc 182; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 183; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 184; GFX11-NEXT: s_endpgm 185 %tid = call i32 @llvm.amdgcn.workitem.id.x() 186 %tid.ext = sext i32 %tid to i64 187 %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %tid.ext 188 %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext 189 %x = load volatile i32, i32 addrspace(1)* %gep 190 %y = load volatile i32, i32 addrspace(1)* %gep 191 %result0 = sub i32 %x, 64 192 %result1 = sub i32 %y, 64 193 store volatile i32 %result0, i32 addrspace(1)* %gep.out 194 store volatile i32 %result1, i32 addrspace(1)* %gep.out 195 ret void 196} 197 198define amdgpu_kernel void @v_test_i32_64_sub_x(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { 199; SI-LABEL: v_test_i32_64_sub_x: 200; SI: ; %bb.0: 201; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 202; SI-NEXT: s_mov_b32 s7, 0xf000 203; SI-NEXT: s_mov_b32 s6, 0 204; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 205; SI-NEXT: v_mov_b32_e32 v1, 0 206; SI-NEXT: s_waitcnt lgkmcnt(0) 207; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 208; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 209; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 210; SI-NEXT: s_waitcnt vmcnt(0) 211; SI-NEXT: v_sub_i32_e32 v2, vcc, 64, v2 212; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 213; SI-NEXT: s_endpgm 214; 215; VI-LABEL: v_test_i32_64_sub_x: 216; VI: ; %bb.0: 217; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 218; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 219; VI-NEXT: s_waitcnt lgkmcnt(0) 220; VI-NEXT: v_mov_b32_e32 v1, s3 221; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 222; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 223; VI-NEXT: flat_load_dword v3, v[0:1] 224; VI-NEXT: v_mov_b32_e32 v1, s1 225; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 226; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 227; VI-NEXT: s_waitcnt vmcnt(0) 228; VI-NEXT: v_sub_u32_e32 v2, vcc, 64, v3 229; VI-NEXT: flat_store_dword v[0:1], v2 230; VI-NEXT: s_endpgm 231; 232; GFX9-LABEL: v_test_i32_64_sub_x: 233; GFX9: ; %bb.0: 234; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 235; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 236; GFX9-NEXT: s_waitcnt lgkmcnt(0) 237; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 238; GFX9-NEXT: s_waitcnt vmcnt(0) 239; GFX9-NEXT: v_sub_u32_e32 v1, 64, v1 240; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 241; GFX9-NEXT: s_endpgm 242; 243; GFX10-LABEL: v_test_i32_64_sub_x: 244; GFX10: ; %bb.0: 245; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 246; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 247; GFX10-NEXT: s_waitcnt lgkmcnt(0) 248; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 249; GFX10-NEXT: s_waitcnt vmcnt(0) 250; GFX10-NEXT: v_sub_nc_u32_e32 v1, 64, v1 251; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 252; GFX10-NEXT: s_endpgm 253; 254; GFX11-LABEL: v_test_i32_64_sub_x: 255; GFX11: ; %bb.0: 256; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 257; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 258; GFX11-NEXT: s_waitcnt lgkmcnt(0) 259; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 260; GFX11-NEXT: s_waitcnt vmcnt(0) 261; GFX11-NEXT: v_sub_nc_u32_e32 v1, 64, v1 262; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 263; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 264; GFX11-NEXT: s_endpgm 265 %tid = call i32 @llvm.amdgcn.workitem.id.x() 266 %tid.ext = sext i32 %tid to i64 267 %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %tid.ext 268 %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext 269 %x = load i32, i32 addrspace(1)* %gep 270 %result = sub i32 64, %x 271 store i32 %result, i32 addrspace(1)* %gep.out 272 ret void 273} 274 275define amdgpu_kernel void @v_test_i32_x_sub_65(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { 276; SI-LABEL: v_test_i32_x_sub_65: 277; SI: ; %bb.0: 278; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 279; SI-NEXT: s_mov_b32 s7, 0xf000 280; SI-NEXT: s_mov_b32 s6, 0 281; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 282; SI-NEXT: v_mov_b32_e32 v1, 0 283; SI-NEXT: s_waitcnt lgkmcnt(0) 284; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 285; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 286; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 287; SI-NEXT: s_waitcnt vmcnt(0) 288; SI-NEXT: v_add_i32_e32 v2, vcc, 0xffffffbf, v2 289; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 290; SI-NEXT: s_endpgm 291; 292; VI-LABEL: v_test_i32_x_sub_65: 293; VI: ; %bb.0: 294; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 295; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 296; VI-NEXT: s_waitcnt lgkmcnt(0) 297; VI-NEXT: v_mov_b32_e32 v1, s3 298; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 299; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 300; VI-NEXT: flat_load_dword v3, v[0:1] 301; VI-NEXT: v_mov_b32_e32 v1, s1 302; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 303; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 304; VI-NEXT: s_waitcnt vmcnt(0) 305; VI-NEXT: v_add_u32_e32 v2, vcc, 0xffffffbf, v3 306; VI-NEXT: flat_store_dword v[0:1], v2 307; VI-NEXT: s_endpgm 308; 309; GFX9-LABEL: v_test_i32_x_sub_65: 310; GFX9: ; %bb.0: 311; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 312; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 313; GFX9-NEXT: s_waitcnt lgkmcnt(0) 314; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 315; GFX9-NEXT: s_waitcnt vmcnt(0) 316; GFX9-NEXT: v_add_u32_e32 v1, 0xffffffbf, v1 317; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 318; GFX9-NEXT: s_endpgm 319; 320; GFX10-LABEL: v_test_i32_x_sub_65: 321; GFX10: ; %bb.0: 322; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 323; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 324; GFX10-NEXT: s_waitcnt lgkmcnt(0) 325; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 326; GFX10-NEXT: s_waitcnt vmcnt(0) 327; GFX10-NEXT: v_add_nc_u32_e32 v1, 0xffffffbf, v1 328; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 329; GFX10-NEXT: s_endpgm 330; 331; GFX11-LABEL: v_test_i32_x_sub_65: 332; GFX11: ; %bb.0: 333; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 334; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 335; GFX11-NEXT: s_waitcnt lgkmcnt(0) 336; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 337; GFX11-NEXT: s_waitcnt vmcnt(0) 338; GFX11-NEXT: v_add_nc_u32_e32 v1, 0xffffffbf, v1 339; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 340; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 341; GFX11-NEXT: s_endpgm 342 %tid = call i32 @llvm.amdgcn.workitem.id.x() 343 %tid.ext = sext i32 %tid to i64 344 %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %tid.ext 345 %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext 346 %x = load i32, i32 addrspace(1)* %gep 347 %result = sub i32 %x, 65 348 store i32 %result, i32 addrspace(1)* %gep.out 349 ret void 350} 351 352define amdgpu_kernel void @v_test_i32_65_sub_x(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { 353; SI-LABEL: v_test_i32_65_sub_x: 354; SI: ; %bb.0: 355; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 356; SI-NEXT: s_mov_b32 s7, 0xf000 357; SI-NEXT: s_mov_b32 s6, 0 358; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 359; SI-NEXT: v_mov_b32_e32 v1, 0 360; SI-NEXT: s_waitcnt lgkmcnt(0) 361; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 362; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 363; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 364; SI-NEXT: s_waitcnt vmcnt(0) 365; SI-NEXT: v_sub_i32_e32 v2, vcc, 0x41, v2 366; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 367; SI-NEXT: s_endpgm 368; 369; VI-LABEL: v_test_i32_65_sub_x: 370; VI: ; %bb.0: 371; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 372; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 373; VI-NEXT: s_waitcnt lgkmcnt(0) 374; VI-NEXT: v_mov_b32_e32 v1, s3 375; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 376; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 377; VI-NEXT: flat_load_dword v3, v[0:1] 378; VI-NEXT: v_mov_b32_e32 v1, s1 379; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 380; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 381; VI-NEXT: s_waitcnt vmcnt(0) 382; VI-NEXT: v_sub_u32_e32 v2, vcc, 0x41, v3 383; VI-NEXT: flat_store_dword v[0:1], v2 384; VI-NEXT: s_endpgm 385; 386; GFX9-LABEL: v_test_i32_65_sub_x: 387; GFX9: ; %bb.0: 388; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 389; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 390; GFX9-NEXT: s_waitcnt lgkmcnt(0) 391; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 392; GFX9-NEXT: s_waitcnt vmcnt(0) 393; GFX9-NEXT: v_sub_u32_e32 v1, 0x41, v1 394; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 395; GFX9-NEXT: s_endpgm 396; 397; GFX10-LABEL: v_test_i32_65_sub_x: 398; GFX10: ; %bb.0: 399; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 400; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 401; GFX10-NEXT: s_waitcnt lgkmcnt(0) 402; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 403; GFX10-NEXT: s_waitcnt vmcnt(0) 404; GFX10-NEXT: v_sub_nc_u32_e32 v1, 0x41, v1 405; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 406; GFX10-NEXT: s_endpgm 407; 408; GFX11-LABEL: v_test_i32_65_sub_x: 409; GFX11: ; %bb.0: 410; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 411; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 412; GFX11-NEXT: s_waitcnt lgkmcnt(0) 413; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 414; GFX11-NEXT: s_waitcnt vmcnt(0) 415; GFX11-NEXT: v_sub_nc_u32_e32 v1, 0x41, v1 416; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 417; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 418; GFX11-NEXT: s_endpgm 419 %tid = call i32 @llvm.amdgcn.workitem.id.x() 420 %tid.ext = sext i32 %tid to i64 421 %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %tid.ext 422 %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext 423 %x = load i32, i32 addrspace(1)* %gep 424 %result = sub i32 65, %x 425 store i32 %result, i32 addrspace(1)* %gep.out 426 ret void 427} 428 429define amdgpu_kernel void @v_test_i32_x_sub_neg16(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { 430; SI-LABEL: v_test_i32_x_sub_neg16: 431; SI: ; %bb.0: 432; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 433; SI-NEXT: s_mov_b32 s7, 0xf000 434; SI-NEXT: s_mov_b32 s6, 0 435; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 436; SI-NEXT: v_mov_b32_e32 v1, 0 437; SI-NEXT: s_waitcnt lgkmcnt(0) 438; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 439; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 440; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 441; SI-NEXT: s_waitcnt vmcnt(0) 442; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v2 443; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 444; SI-NEXT: s_endpgm 445; 446; VI-LABEL: v_test_i32_x_sub_neg16: 447; VI: ; %bb.0: 448; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 449; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 450; VI-NEXT: s_waitcnt lgkmcnt(0) 451; VI-NEXT: v_mov_b32_e32 v1, s3 452; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 453; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 454; VI-NEXT: flat_load_dword v3, v[0:1] 455; VI-NEXT: v_mov_b32_e32 v1, s1 456; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 457; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 458; VI-NEXT: s_waitcnt vmcnt(0) 459; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v3 460; VI-NEXT: flat_store_dword v[0:1], v2 461; VI-NEXT: s_endpgm 462; 463; GFX9-LABEL: v_test_i32_x_sub_neg16: 464; GFX9: ; %bb.0: 465; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 466; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 467; GFX9-NEXT: s_waitcnt lgkmcnt(0) 468; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 469; GFX9-NEXT: s_waitcnt vmcnt(0) 470; GFX9-NEXT: v_add_u32_e32 v1, 16, v1 471; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 472; GFX9-NEXT: s_endpgm 473; 474; GFX10-LABEL: v_test_i32_x_sub_neg16: 475; GFX10: ; %bb.0: 476; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 477; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 478; GFX10-NEXT: s_waitcnt lgkmcnt(0) 479; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 480; GFX10-NEXT: s_waitcnt vmcnt(0) 481; GFX10-NEXT: v_add_nc_u32_e32 v1, 16, v1 482; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 483; GFX10-NEXT: s_endpgm 484; 485; GFX11-LABEL: v_test_i32_x_sub_neg16: 486; GFX11: ; %bb.0: 487; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 488; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 489; GFX11-NEXT: s_waitcnt lgkmcnt(0) 490; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 491; GFX11-NEXT: s_waitcnt vmcnt(0) 492; GFX11-NEXT: v_add_nc_u32_e32 v1, 16, v1 493; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 494; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 495; GFX11-NEXT: s_endpgm 496 %tid = call i32 @llvm.amdgcn.workitem.id.x() 497 %tid.ext = sext i32 %tid to i64 498 %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %tid.ext 499 %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext 500 %x = load i32, i32 addrspace(1)* %gep 501 %result = sub i32 %x, -16 502 store i32 %result, i32 addrspace(1)* %gep.out 503 ret void 504} 505 506define amdgpu_kernel void @v_test_i32_neg16_sub_x(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { 507; SI-LABEL: v_test_i32_neg16_sub_x: 508; SI: ; %bb.0: 509; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 510; SI-NEXT: s_mov_b32 s7, 0xf000 511; SI-NEXT: s_mov_b32 s6, 0 512; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 513; SI-NEXT: v_mov_b32_e32 v1, 0 514; SI-NEXT: s_waitcnt lgkmcnt(0) 515; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 516; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 517; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 518; SI-NEXT: s_waitcnt vmcnt(0) 519; SI-NEXT: v_sub_i32_e32 v2, vcc, -16, v2 520; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 521; SI-NEXT: s_endpgm 522; 523; VI-LABEL: v_test_i32_neg16_sub_x: 524; VI: ; %bb.0: 525; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 526; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 527; VI-NEXT: s_waitcnt lgkmcnt(0) 528; VI-NEXT: v_mov_b32_e32 v1, s3 529; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 530; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 531; VI-NEXT: flat_load_dword v3, v[0:1] 532; VI-NEXT: v_mov_b32_e32 v1, s1 533; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 534; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 535; VI-NEXT: s_waitcnt vmcnt(0) 536; VI-NEXT: v_sub_u32_e32 v2, vcc, -16, v3 537; VI-NEXT: flat_store_dword v[0:1], v2 538; VI-NEXT: s_endpgm 539; 540; GFX9-LABEL: v_test_i32_neg16_sub_x: 541; GFX9: ; %bb.0: 542; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 543; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 544; GFX9-NEXT: s_waitcnt lgkmcnt(0) 545; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 546; GFX9-NEXT: s_waitcnt vmcnt(0) 547; GFX9-NEXT: v_sub_u32_e32 v1, -16, v1 548; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 549; GFX9-NEXT: s_endpgm 550; 551; GFX10-LABEL: v_test_i32_neg16_sub_x: 552; GFX10: ; %bb.0: 553; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 554; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 555; GFX10-NEXT: s_waitcnt lgkmcnt(0) 556; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 557; GFX10-NEXT: s_waitcnt vmcnt(0) 558; GFX10-NEXT: v_sub_nc_u32_e32 v1, -16, v1 559; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 560; GFX10-NEXT: s_endpgm 561; 562; GFX11-LABEL: v_test_i32_neg16_sub_x: 563; GFX11: ; %bb.0: 564; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 565; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 566; GFX11-NEXT: s_waitcnt lgkmcnt(0) 567; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 568; GFX11-NEXT: s_waitcnt vmcnt(0) 569; GFX11-NEXT: v_sub_nc_u32_e32 v1, -16, v1 570; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 571; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 572; GFX11-NEXT: s_endpgm 573 %tid = call i32 @llvm.amdgcn.workitem.id.x() 574 %tid.ext = sext i32 %tid to i64 575 %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %tid.ext 576 %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext 577 %x = load i32, i32 addrspace(1)* %gep 578 %result = sub i32 -16, %x 579 store i32 %result, i32 addrspace(1)* %gep.out 580 ret void 581} 582 583define amdgpu_kernel void @v_test_i32_x_sub_neg17(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { 584; SI-LABEL: v_test_i32_x_sub_neg17: 585; SI: ; %bb.0: 586; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 587; SI-NEXT: s_mov_b32 s7, 0xf000 588; SI-NEXT: s_mov_b32 s6, 0 589; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 590; SI-NEXT: v_mov_b32_e32 v1, 0 591; SI-NEXT: s_waitcnt lgkmcnt(0) 592; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 593; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 594; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 595; SI-NEXT: s_waitcnt vmcnt(0) 596; SI-NEXT: v_add_i32_e32 v2, vcc, 17, v2 597; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 598; SI-NEXT: s_endpgm 599; 600; VI-LABEL: v_test_i32_x_sub_neg17: 601; VI: ; %bb.0: 602; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 603; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 604; VI-NEXT: s_waitcnt lgkmcnt(0) 605; VI-NEXT: v_mov_b32_e32 v1, s3 606; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 607; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 608; VI-NEXT: flat_load_dword v3, v[0:1] 609; VI-NEXT: v_mov_b32_e32 v1, s1 610; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 611; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 612; VI-NEXT: s_waitcnt vmcnt(0) 613; VI-NEXT: v_add_u32_e32 v2, vcc, 17, v3 614; VI-NEXT: flat_store_dword v[0:1], v2 615; VI-NEXT: s_endpgm 616; 617; GFX9-LABEL: v_test_i32_x_sub_neg17: 618; GFX9: ; %bb.0: 619; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 620; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 621; GFX9-NEXT: s_waitcnt lgkmcnt(0) 622; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 623; GFX9-NEXT: s_waitcnt vmcnt(0) 624; GFX9-NEXT: v_add_u32_e32 v1, 17, v1 625; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 626; GFX9-NEXT: s_endpgm 627; 628; GFX10-LABEL: v_test_i32_x_sub_neg17: 629; GFX10: ; %bb.0: 630; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 631; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 632; GFX10-NEXT: s_waitcnt lgkmcnt(0) 633; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 634; GFX10-NEXT: s_waitcnt vmcnt(0) 635; GFX10-NEXT: v_add_nc_u32_e32 v1, 17, v1 636; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 637; GFX10-NEXT: s_endpgm 638; 639; GFX11-LABEL: v_test_i32_x_sub_neg17: 640; GFX11: ; %bb.0: 641; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 642; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 643; GFX11-NEXT: s_waitcnt lgkmcnt(0) 644; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 645; GFX11-NEXT: s_waitcnt vmcnt(0) 646; GFX11-NEXT: v_add_nc_u32_e32 v1, 17, v1 647; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 648; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 649; GFX11-NEXT: s_endpgm 650 %tid = call i32 @llvm.amdgcn.workitem.id.x() 651 %tid.ext = sext i32 %tid to i64 652 %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %tid.ext 653 %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext 654 %x = load i32, i32 addrspace(1)* %gep 655 %result = sub i32 %x, -17 656 store i32 %result, i32 addrspace(1)* %gep.out 657 ret void 658} 659 660define amdgpu_kernel void @v_test_i32_neg17_sub_x(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { 661; SI-LABEL: v_test_i32_neg17_sub_x: 662; SI: ; %bb.0: 663; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 664; SI-NEXT: s_mov_b32 s7, 0xf000 665; SI-NEXT: s_mov_b32 s6, 0 666; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 667; SI-NEXT: v_mov_b32_e32 v1, 0 668; SI-NEXT: s_waitcnt lgkmcnt(0) 669; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 670; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 671; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 672; SI-NEXT: s_waitcnt vmcnt(0) 673; SI-NEXT: v_sub_i32_e32 v2, vcc, 0xffffffef, v2 674; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 675; SI-NEXT: s_endpgm 676; 677; VI-LABEL: v_test_i32_neg17_sub_x: 678; VI: ; %bb.0: 679; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 680; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 681; VI-NEXT: s_waitcnt lgkmcnt(0) 682; VI-NEXT: v_mov_b32_e32 v1, s3 683; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 684; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 685; VI-NEXT: flat_load_dword v3, v[0:1] 686; VI-NEXT: v_mov_b32_e32 v1, s1 687; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 688; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 689; VI-NEXT: s_waitcnt vmcnt(0) 690; VI-NEXT: v_sub_u32_e32 v2, vcc, 0xffffffef, v3 691; VI-NEXT: flat_store_dword v[0:1], v2 692; VI-NEXT: s_endpgm 693; 694; GFX9-LABEL: v_test_i32_neg17_sub_x: 695; GFX9: ; %bb.0: 696; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 697; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 698; GFX9-NEXT: s_waitcnt lgkmcnt(0) 699; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 700; GFX9-NEXT: s_waitcnt vmcnt(0) 701; GFX9-NEXT: v_sub_u32_e32 v1, 0xffffffef, v1 702; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 703; GFX9-NEXT: s_endpgm 704; 705; GFX10-LABEL: v_test_i32_neg17_sub_x: 706; GFX10: ; %bb.0: 707; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 708; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 709; GFX10-NEXT: s_waitcnt lgkmcnt(0) 710; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 711; GFX10-NEXT: s_waitcnt vmcnt(0) 712; GFX10-NEXT: v_sub_nc_u32_e32 v1, 0xffffffef, v1 713; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 714; GFX10-NEXT: s_endpgm 715; 716; GFX11-LABEL: v_test_i32_neg17_sub_x: 717; GFX11: ; %bb.0: 718; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 719; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 720; GFX11-NEXT: s_waitcnt lgkmcnt(0) 721; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 722; GFX11-NEXT: s_waitcnt vmcnt(0) 723; GFX11-NEXT: v_sub_nc_u32_e32 v1, 0xffffffef, v1 724; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 725; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 726; GFX11-NEXT: s_endpgm 727 %tid = call i32 @llvm.amdgcn.workitem.id.x() 728 %tid.ext = sext i32 %tid to i64 729 %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %tid.ext 730 %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext 731 %x = load i32, i32 addrspace(1)* %gep 732 %result = sub i32 -17, %x 733 store i32 %result, i32 addrspace(1)* %gep.out 734 ret void 735} 736 737define amdgpu_kernel void @s_test_i32_x_sub_64(i32 %x) #0 { 738; SI-LABEL: s_test_i32_x_sub_64: 739; SI: ; %bb.0: 740; SI-NEXT: s_load_dword s0, s[0:1], 0x9 741; SI-NEXT: s_waitcnt lgkmcnt(0) 742; SI-NEXT: s_sub_i32 s0, s0, 64 743; SI-NEXT: ;;#ASMSTART 744; SI-NEXT: ; use s0 745; SI-NEXT: ;;#ASMEND 746; SI-NEXT: s_endpgm 747; 748; VI-LABEL: s_test_i32_x_sub_64: 749; VI: ; %bb.0: 750; VI-NEXT: s_load_dword s0, s[0:1], 0x24 751; VI-NEXT: s_waitcnt lgkmcnt(0) 752; VI-NEXT: s_sub_i32 s0, s0, 64 753; VI-NEXT: ;;#ASMSTART 754; VI-NEXT: ; use s0 755; VI-NEXT: ;;#ASMEND 756; VI-NEXT: s_endpgm 757; 758; GFX9-LABEL: s_test_i32_x_sub_64: 759; GFX9: ; %bb.0: 760; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24 761; GFX9-NEXT: s_waitcnt lgkmcnt(0) 762; GFX9-NEXT: s_sub_i32 s0, s0, 64 763; GFX9-NEXT: ;;#ASMSTART 764; GFX9-NEXT: ; use s0 765; GFX9-NEXT: ;;#ASMEND 766; GFX9-NEXT: s_endpgm 767; 768; GFX10-LABEL: s_test_i32_x_sub_64: 769; GFX10: ; %bb.0: 770; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24 771; GFX10-NEXT: s_waitcnt lgkmcnt(0) 772; GFX10-NEXT: s_sub_i32 s0, s0, 64 773; GFX10-NEXT: ;;#ASMSTART 774; GFX10-NEXT: ; use s0 775; GFX10-NEXT: ;;#ASMEND 776; GFX10-NEXT: s_endpgm 777; 778; GFX11-LABEL: s_test_i32_x_sub_64: 779; GFX11: ; %bb.0: 780; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x24 781; GFX11-NEXT: s_waitcnt lgkmcnt(0) 782; GFX11-NEXT: s_sub_i32 s0, s0, 64 783; GFX11-NEXT: ;;#ASMSTART 784; GFX11-NEXT: ; use s0 785; GFX11-NEXT: ;;#ASMEND 786; GFX11-NEXT: s_endpgm 787 %result = sub i32 %x, 64 788 call void asm sideeffect "; use $0", "s"(i32 %result) 789 ret void 790} 791 792define amdgpu_kernel void @v_test_i16_x_sub_64(i16 addrspace(1)* %out, i16 addrspace(1)* %in) #0 { 793; SI-LABEL: v_test_i16_x_sub_64: 794; SI: ; %bb.0: 795; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 796; SI-NEXT: s_mov_b32 s7, 0xf000 797; SI-NEXT: s_mov_b32 s6, 0 798; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0 799; SI-NEXT: v_mov_b32_e32 v1, 0 800; SI-NEXT: s_waitcnt lgkmcnt(0) 801; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 802; SI-NEXT: buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 803; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 804; SI-NEXT: s_waitcnt vmcnt(0) 805; SI-NEXT: v_subrev_i32_e32 v2, vcc, 64, v2 806; SI-NEXT: buffer_store_short v2, v[0:1], s[0:3], 0 addr64 807; SI-NEXT: s_endpgm 808; 809; VI-LABEL: v_test_i16_x_sub_64: 810; VI: ; %bb.0: 811; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 812; VI-NEXT: v_lshlrev_b32_e32 v2, 1, v0 813; VI-NEXT: s_waitcnt lgkmcnt(0) 814; VI-NEXT: v_mov_b32_e32 v1, s3 815; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 816; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 817; VI-NEXT: flat_load_ushort v3, v[0:1] 818; VI-NEXT: v_mov_b32_e32 v1, s1 819; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 820; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 821; VI-NEXT: s_waitcnt vmcnt(0) 822; VI-NEXT: v_subrev_u16_e32 v2, 64, v3 823; VI-NEXT: flat_store_short v[0:1], v2 824; VI-NEXT: s_endpgm 825; 826; GFX9-LABEL: v_test_i16_x_sub_64: 827; GFX9: ; %bb.0: 828; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 829; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0 830; GFX9-NEXT: s_waitcnt lgkmcnt(0) 831; GFX9-NEXT: global_load_ushort v1, v0, s[2:3] 832; GFX9-NEXT: s_waitcnt vmcnt(0) 833; GFX9-NEXT: v_subrev_u16_e32 v1, 64, v1 834; GFX9-NEXT: global_store_short v0, v1, s[0:1] 835; GFX9-NEXT: s_endpgm 836; 837; GFX10-LABEL: v_test_i16_x_sub_64: 838; GFX10: ; %bb.0: 839; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 840; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0 841; GFX10-NEXT: s_waitcnt lgkmcnt(0) 842; GFX10-NEXT: global_load_ushort v1, v0, s[2:3] 843; GFX10-NEXT: s_waitcnt vmcnt(0) 844; GFX10-NEXT: v_sub_nc_u16 v1, v1, 64 845; GFX10-NEXT: global_store_short v0, v1, s[0:1] 846; GFX10-NEXT: s_endpgm 847; 848; GFX11-LABEL: v_test_i16_x_sub_64: 849; GFX11: ; %bb.0: 850; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 851; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0 852; GFX11-NEXT: s_waitcnt lgkmcnt(0) 853; GFX11-NEXT: global_load_u16 v1, v0, s[2:3] 854; GFX11-NEXT: s_waitcnt vmcnt(0) 855; GFX11-NEXT: v_sub_nc_u16 v1, v1, 64 856; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] 857; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 858; GFX11-NEXT: s_endpgm 859 %tid = call i32 @llvm.amdgcn.workitem.id.x() 860 %tid.ext = sext i32 %tid to i64 861 %gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i64 %tid.ext 862 %gep.out = getelementptr inbounds i16, i16 addrspace(1)* %out, i64 %tid.ext 863 %x = load i16, i16 addrspace(1)* %gep 864 %result = sub i16 %x, 64 865 store i16 %result, i16 addrspace(1)* %gep.out 866 ret void 867} 868 869define amdgpu_kernel void @v_test_i16_x_sub_64_zext_to_i32(i32 addrspace(1)* %out, i16 addrspace(1)* %in) #0 { 870; SI-LABEL: v_test_i16_x_sub_64_zext_to_i32: 871; SI: ; %bb.0: 872; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 873; SI-NEXT: s_mov_b32 s7, 0xf000 874; SI-NEXT: s_mov_b32 s6, 0 875; SI-NEXT: v_lshlrev_b32_e32 v1, 1, v0 876; SI-NEXT: v_mov_b32_e32 v2, 0 877; SI-NEXT: s_waitcnt lgkmcnt(0) 878; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 879; SI-NEXT: buffer_load_ushort v3, v[1:2], s[4:7], 0 addr64 880; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 881; SI-NEXT: v_lshlrev_b32_e32 v1, 2, v0 882; SI-NEXT: s_waitcnt vmcnt(0) 883; SI-NEXT: v_subrev_i32_e32 v0, vcc, 64, v3 884; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0 885; SI-NEXT: buffer_store_dword v0, v[1:2], s[0:3], 0 addr64 886; SI-NEXT: s_endpgm 887; 888; VI-LABEL: v_test_i16_x_sub_64_zext_to_i32: 889; VI: ; %bb.0: 890; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 891; VI-NEXT: v_lshlrev_b32_e32 v1, 1, v0 892; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 893; VI-NEXT: s_waitcnt lgkmcnt(0) 894; VI-NEXT: v_mov_b32_e32 v2, s3 895; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v1 896; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc 897; VI-NEXT: flat_load_ushort v2, v[1:2] 898; VI-NEXT: v_mov_b32_e32 v1, s1 899; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 900; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 901; VI-NEXT: s_waitcnt vmcnt(0) 902; VI-NEXT: v_subrev_u16_e32 v2, 64, v2 903; VI-NEXT: flat_store_dword v[0:1], v2 904; VI-NEXT: s_endpgm 905; 906; GFX9-LABEL: v_test_i16_x_sub_64_zext_to_i32: 907; GFX9: ; %bb.0: 908; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 909; GFX9-NEXT: v_lshlrev_b32_e32 v1, 1, v0 910; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 911; GFX9-NEXT: s_waitcnt lgkmcnt(0) 912; GFX9-NEXT: global_load_ushort v1, v1, s[2:3] 913; GFX9-NEXT: s_waitcnt vmcnt(0) 914; GFX9-NEXT: v_subrev_u16_e32 v1, 64, v1 915; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 916; GFX9-NEXT: s_endpgm 917; 918; GFX10-LABEL: v_test_i16_x_sub_64_zext_to_i32: 919; GFX10: ; %bb.0: 920; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 921; GFX10-NEXT: v_lshlrev_b32_e32 v1, 1, v0 922; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 923; GFX10-NEXT: s_waitcnt lgkmcnt(0) 924; GFX10-NEXT: global_load_ushort v1, v1, s[2:3] 925; GFX10-NEXT: s_waitcnt vmcnt(0) 926; GFX10-NEXT: v_sub_nc_u16 v1, v1, 64 927; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1 928; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 929; GFX10-NEXT: s_endpgm 930; 931; GFX11-LABEL: v_test_i16_x_sub_64_zext_to_i32: 932; GFX11: ; %bb.0: 933; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 934; GFX11-NEXT: v_lshlrev_b32_e32 v1, 1, v0 935; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 936; GFX11-NEXT: s_waitcnt lgkmcnt(0) 937; GFX11-NEXT: global_load_u16 v1, v1, s[2:3] 938; GFX11-NEXT: s_waitcnt vmcnt(0) 939; GFX11-NEXT: v_sub_nc_u16 v1, v1, 64 940; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) 941; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1 942; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 943; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 944; GFX11-NEXT: s_endpgm 945 %tid = call i32 @llvm.amdgcn.workitem.id.x() 946 %tid.ext = sext i32 %tid to i64 947 %gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i64 %tid.ext 948 %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext 949 %x = load i16, i16 addrspace(1)* %gep 950 %result = sub i16 %x, 64 951 %zext = zext i16 %result to i32 952 store i32 %zext, i32 addrspace(1)* %gep.out 953 ret void 954} 955 956define amdgpu_kernel void @v_test_i16_x_sub_64_multi_use(i16 addrspace(1)* %out, i16 addrspace(1)* %in) #0 { 957; SI-LABEL: v_test_i16_x_sub_64_multi_use: 958; SI: ; %bb.0: 959; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 960; SI-NEXT: s_mov_b32 s7, 0xf000 961; SI-NEXT: s_mov_b32 s6, 0 962; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0 963; SI-NEXT: v_mov_b32_e32 v1, 0 964; SI-NEXT: s_waitcnt lgkmcnt(0) 965; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 966; SI-NEXT: buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 glc 967; SI-NEXT: s_waitcnt vmcnt(0) 968; SI-NEXT: buffer_load_ushort v3, v[0:1], s[4:7], 0 addr64 glc 969; SI-NEXT: s_waitcnt vmcnt(0) 970; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 971; SI-NEXT: v_subrev_i32_e32 v2, vcc, 64, v2 972; SI-NEXT: v_subrev_i32_e32 v3, vcc, 64, v3 973; SI-NEXT: buffer_store_short v2, v[0:1], s[0:3], 0 addr64 974; SI-NEXT: s_waitcnt vmcnt(0) 975; SI-NEXT: buffer_store_short v3, v[0:1], s[0:3], 0 addr64 976; SI-NEXT: s_waitcnt vmcnt(0) 977; SI-NEXT: s_endpgm 978; 979; VI-LABEL: v_test_i16_x_sub_64_multi_use: 980; VI: ; %bb.0: 981; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 982; VI-NEXT: v_lshlrev_b32_e32 v2, 1, v0 983; VI-NEXT: s_waitcnt lgkmcnt(0) 984; VI-NEXT: v_mov_b32_e32 v1, s3 985; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 986; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 987; VI-NEXT: flat_load_ushort v3, v[0:1] glc 988; VI-NEXT: s_waitcnt vmcnt(0) 989; VI-NEXT: flat_load_ushort v4, v[0:1] glc 990; VI-NEXT: s_waitcnt vmcnt(0) 991; VI-NEXT: v_mov_b32_e32 v1, s1 992; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 993; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 994; VI-NEXT: v_subrev_u16_e32 v2, 64, v3 995; VI-NEXT: v_subrev_u16_e32 v3, 64, v4 996; VI-NEXT: flat_store_short v[0:1], v2 997; VI-NEXT: s_waitcnt vmcnt(0) 998; VI-NEXT: flat_store_short v[0:1], v3 999; VI-NEXT: s_waitcnt vmcnt(0) 1000; VI-NEXT: s_endpgm 1001; 1002; GFX9-LABEL: v_test_i16_x_sub_64_multi_use: 1003; GFX9: ; %bb.0: 1004; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1005; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0 1006; GFX9-NEXT: s_waitcnt lgkmcnt(0) 1007; GFX9-NEXT: global_load_ushort v1, v0, s[2:3] glc 1008; GFX9-NEXT: s_waitcnt vmcnt(0) 1009; GFX9-NEXT: global_load_ushort v2, v0, s[2:3] glc 1010; GFX9-NEXT: s_waitcnt vmcnt(0) 1011; GFX9-NEXT: v_subrev_u16_e32 v1, 64, v1 1012; GFX9-NEXT: v_subrev_u16_e32 v2, 64, v2 1013; GFX9-NEXT: global_store_short v0, v1, s[0:1] 1014; GFX9-NEXT: s_waitcnt vmcnt(0) 1015; GFX9-NEXT: global_store_short v0, v2, s[0:1] 1016; GFX9-NEXT: s_waitcnt vmcnt(0) 1017; GFX9-NEXT: s_endpgm 1018; 1019; GFX10-LABEL: v_test_i16_x_sub_64_multi_use: 1020; GFX10: ; %bb.0: 1021; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1022; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0 1023; GFX10-NEXT: s_waitcnt lgkmcnt(0) 1024; GFX10-NEXT: global_load_ushort v1, v0, s[2:3] glc dlc 1025; GFX10-NEXT: s_waitcnt vmcnt(0) 1026; GFX10-NEXT: global_load_ushort v2, v0, s[2:3] glc dlc 1027; GFX10-NEXT: s_waitcnt vmcnt(0) 1028; GFX10-NEXT: v_sub_nc_u16 v1, v1, 64 1029; GFX10-NEXT: v_sub_nc_u16 v2, v2, 64 1030; GFX10-NEXT: global_store_short v0, v1, s[0:1] 1031; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1032; GFX10-NEXT: global_store_short v0, v2, s[0:1] 1033; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 1034; GFX10-NEXT: s_endpgm 1035; 1036; GFX11-LABEL: v_test_i16_x_sub_64_multi_use: 1037; GFX11: ; %bb.0: 1038; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 1039; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0 1040; GFX11-NEXT: s_waitcnt lgkmcnt(0) 1041; GFX11-NEXT: global_load_u16 v1, v0, s[2:3] glc dlc 1042; GFX11-NEXT: s_waitcnt vmcnt(0) 1043; GFX11-NEXT: global_load_u16 v2, v0, s[2:3] glc dlc 1044; GFX11-NEXT: s_waitcnt vmcnt(0) 1045; GFX11-NEXT: v_sub_nc_u16 v1, v1, 64 1046; GFX11-NEXT: v_sub_nc_u16 v2, v2, 64 1047; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] dlc 1048; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 1049; GFX11-NEXT: global_store_b16 v0, v2, s[0:1] dlc 1050; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 1051; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 1052; GFX11-NEXT: s_endpgm 1053 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1054 %tid.ext = sext i32 %tid to i64 1055 %gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i64 %tid.ext 1056 %gep.out = getelementptr inbounds i16, i16 addrspace(1)* %out, i64 %tid.ext 1057 %x = load volatile i16, i16 addrspace(1)* %gep 1058 %y = load volatile i16, i16 addrspace(1)* %gep 1059 %result0 = sub i16 %x, 64 1060 %result1 = sub i16 %y, 64 1061 store volatile i16 %result0, i16 addrspace(1)* %gep.out 1062 store volatile i16 %result1, i16 addrspace(1)* %gep.out 1063 ret void 1064} 1065 1066define amdgpu_kernel void @v_test_v2i16_x_sub_64_64(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1067; SI-LABEL: v_test_v2i16_x_sub_64_64: 1068; SI: ; %bb.0: 1069; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1070; SI-NEXT: s_mov_b32 s7, 0xf000 1071; SI-NEXT: s_mov_b32 s6, 0 1072; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1073; SI-NEXT: v_mov_b32_e32 v1, 0 1074; SI-NEXT: s_waitcnt lgkmcnt(0) 1075; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1076; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1077; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1078; SI-NEXT: s_waitcnt vmcnt(0) 1079; SI-NEXT: v_subrev_i32_e32 v3, vcc, 64, v2 1080; SI-NEXT: s_mov_b32 s4, 0xffff0000 1081; SI-NEXT: v_bfi_b32 v2, s4, v2, v3 1082; SI-NEXT: v_add_i32_e32 v2, vcc, 0xffc00000, v2 1083; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 1084; SI-NEXT: s_endpgm 1085; 1086; VI-LABEL: v_test_v2i16_x_sub_64_64: 1087; VI: ; %bb.0: 1088; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1089; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1090; VI-NEXT: v_mov_b32_e32 v4, 64 1091; VI-NEXT: s_waitcnt lgkmcnt(0) 1092; VI-NEXT: v_mov_b32_e32 v1, s3 1093; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 1094; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1095; VI-NEXT: flat_load_dword v3, v[0:1] 1096; VI-NEXT: v_mov_b32_e32 v1, s1 1097; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 1098; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1099; VI-NEXT: s_waitcnt vmcnt(0) 1100; VI-NEXT: v_sub_u16_sdwa v2, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1101; VI-NEXT: v_subrev_u16_e32 v3, 64, v3 1102; VI-NEXT: v_or_b32_e32 v2, v3, v2 1103; VI-NEXT: flat_store_dword v[0:1], v2 1104; VI-NEXT: s_endpgm 1105; 1106; GFX9-LABEL: v_test_v2i16_x_sub_64_64: 1107; GFX9: ; %bb.0: 1108; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1109; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1110; GFX9-NEXT: s_waitcnt lgkmcnt(0) 1111; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 1112; GFX9-NEXT: s_waitcnt vmcnt(0) 1113; GFX9-NEXT: v_pk_sub_i16 v1, v1, 64 op_sel_hi:[1,0] 1114; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 1115; GFX9-NEXT: s_endpgm 1116; 1117; GFX10-LABEL: v_test_v2i16_x_sub_64_64: 1118; GFX10: ; %bb.0: 1119; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1120; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1121; GFX10-NEXT: s_waitcnt lgkmcnt(0) 1122; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 1123; GFX10-NEXT: s_waitcnt vmcnt(0) 1124; GFX10-NEXT: v_pk_sub_i16 v1, v1, 64 op_sel_hi:[1,0] 1125; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 1126; GFX10-NEXT: s_endpgm 1127; 1128; GFX11-LABEL: v_test_v2i16_x_sub_64_64: 1129; GFX11: ; %bb.0: 1130; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 1131; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1132; GFX11-NEXT: s_waitcnt lgkmcnt(0) 1133; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 1134; GFX11-NEXT: s_waitcnt vmcnt(0) 1135; GFX11-NEXT: v_pk_sub_i16 v1, v1, 64 op_sel_hi:[1,0] 1136; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 1137; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 1138; GFX11-NEXT: s_endpgm 1139 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1140 %tid.ext = sext i32 %tid to i64 1141 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 1142 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 1143 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 1144 %result = sub <2 x i16> %x, <i16 64, i16 64> 1145 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 1146 ret void 1147} 1148 1149define amdgpu_kernel void @v_test_v2i16_x_sub_7_64(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1150; SI-LABEL: v_test_v2i16_x_sub_7_64: 1151; SI: ; %bb.0: 1152; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1153; SI-NEXT: s_mov_b32 s7, 0xf000 1154; SI-NEXT: s_mov_b32 s6, 0 1155; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1156; SI-NEXT: v_mov_b32_e32 v1, 0 1157; SI-NEXT: s_waitcnt lgkmcnt(0) 1158; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1159; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1160; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1161; SI-NEXT: s_waitcnt vmcnt(0) 1162; SI-NEXT: v_add_i32_e32 v3, vcc, -7, v2 1163; SI-NEXT: s_mov_b32 s4, 0xffff0000 1164; SI-NEXT: v_bfi_b32 v2, s4, v2, v3 1165; SI-NEXT: v_add_i32_e32 v2, vcc, 0xffc00000, v2 1166; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 1167; SI-NEXT: s_endpgm 1168; 1169; VI-LABEL: v_test_v2i16_x_sub_7_64: 1170; VI: ; %bb.0: 1171; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1172; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1173; VI-NEXT: v_mov_b32_e32 v4, 64 1174; VI-NEXT: s_waitcnt lgkmcnt(0) 1175; VI-NEXT: v_mov_b32_e32 v1, s3 1176; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 1177; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1178; VI-NEXT: flat_load_dword v3, v[0:1] 1179; VI-NEXT: v_mov_b32_e32 v1, s1 1180; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 1181; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1182; VI-NEXT: s_waitcnt vmcnt(0) 1183; VI-NEXT: v_add_u16_e32 v2, -7, v3 1184; VI-NEXT: v_sub_u16_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1185; VI-NEXT: v_or_b32_e32 v2, v2, v3 1186; VI-NEXT: flat_store_dword v[0:1], v2 1187; VI-NEXT: s_endpgm 1188; 1189; GFX9-LABEL: v_test_v2i16_x_sub_7_64: 1190; GFX9: ; %bb.0: 1191; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1192; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1193; GFX9-NEXT: s_waitcnt lgkmcnt(0) 1194; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 1195; GFX9-NEXT: s_mov_b32 s2, 0x400007 1196; GFX9-NEXT: s_waitcnt vmcnt(0) 1197; GFX9-NEXT: v_pk_sub_i16 v1, v1, s2 1198; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 1199; GFX9-NEXT: s_endpgm 1200; 1201; GFX10-LABEL: v_test_v2i16_x_sub_7_64: 1202; GFX10: ; %bb.0: 1203; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1204; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1205; GFX10-NEXT: s_waitcnt lgkmcnt(0) 1206; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 1207; GFX10-NEXT: s_waitcnt vmcnt(0) 1208; GFX10-NEXT: v_pk_sub_i16 v1, v1, 0x400007 1209; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 1210; GFX10-NEXT: s_endpgm 1211; 1212; GFX11-LABEL: v_test_v2i16_x_sub_7_64: 1213; GFX11: ; %bb.0: 1214; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 1215; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1216; GFX11-NEXT: s_waitcnt lgkmcnt(0) 1217; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 1218; GFX11-NEXT: s_waitcnt vmcnt(0) 1219; GFX11-NEXT: v_pk_sub_i16 v1, v1, 0x400007 1220; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 1221; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 1222; GFX11-NEXT: s_endpgm 1223 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1224 %tid.ext = sext i32 %tid to i64 1225 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 1226 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 1227 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 1228 %result = sub <2 x i16> %x, <i16 7, i16 64> 1229 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 1230 ret void 1231} 1232 1233define amdgpu_kernel void @v_test_v2i16_x_sub_64_123(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1234; SI-LABEL: v_test_v2i16_x_sub_64_123: 1235; SI: ; %bb.0: 1236; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1237; SI-NEXT: s_mov_b32 s7, 0xf000 1238; SI-NEXT: s_mov_b32 s6, 0 1239; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1240; SI-NEXT: v_mov_b32_e32 v1, 0 1241; SI-NEXT: s_waitcnt lgkmcnt(0) 1242; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1243; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1244; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1245; SI-NEXT: s_waitcnt vmcnt(0) 1246; SI-NEXT: v_subrev_i32_e32 v3, vcc, 64, v2 1247; SI-NEXT: s_mov_b32 s4, 0xffff0000 1248; SI-NEXT: v_bfi_b32 v2, s4, v2, v3 1249; SI-NEXT: v_add_i32_e32 v2, vcc, 0xff850000, v2 1250; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 1251; SI-NEXT: s_endpgm 1252; 1253; VI-LABEL: v_test_v2i16_x_sub_64_123: 1254; VI: ; %bb.0: 1255; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1256; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1257; VI-NEXT: v_mov_b32_e32 v4, 0xffffff85 1258; VI-NEXT: s_waitcnt lgkmcnt(0) 1259; VI-NEXT: v_mov_b32_e32 v1, s3 1260; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 1261; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1262; VI-NEXT: flat_load_dword v3, v[0:1] 1263; VI-NEXT: v_mov_b32_e32 v1, s1 1264; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 1265; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1266; VI-NEXT: s_waitcnt vmcnt(0) 1267; VI-NEXT: v_add_u16_sdwa v2, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1268; VI-NEXT: v_subrev_u16_e32 v3, 64, v3 1269; VI-NEXT: v_or_b32_e32 v2, v3, v2 1270; VI-NEXT: flat_store_dword v[0:1], v2 1271; VI-NEXT: s_endpgm 1272; 1273; GFX9-LABEL: v_test_v2i16_x_sub_64_123: 1274; GFX9: ; %bb.0: 1275; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1276; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1277; GFX9-NEXT: s_waitcnt lgkmcnt(0) 1278; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 1279; GFX9-NEXT: s_mov_b32 s2, 0x7b0040 1280; GFX9-NEXT: s_waitcnt vmcnt(0) 1281; GFX9-NEXT: v_pk_sub_i16 v1, v1, s2 1282; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 1283; GFX9-NEXT: s_endpgm 1284; 1285; GFX10-LABEL: v_test_v2i16_x_sub_64_123: 1286; GFX10: ; %bb.0: 1287; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1288; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1289; GFX10-NEXT: s_waitcnt lgkmcnt(0) 1290; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 1291; GFX10-NEXT: s_waitcnt vmcnt(0) 1292; GFX10-NEXT: v_pk_sub_i16 v1, v1, 0x7b0040 1293; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 1294; GFX10-NEXT: s_endpgm 1295; 1296; GFX11-LABEL: v_test_v2i16_x_sub_64_123: 1297; GFX11: ; %bb.0: 1298; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 1299; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1300; GFX11-NEXT: s_waitcnt lgkmcnt(0) 1301; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 1302; GFX11-NEXT: s_waitcnt vmcnt(0) 1303; GFX11-NEXT: v_pk_sub_i16 v1, v1, 0x7b0040 1304; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 1305; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 1306; GFX11-NEXT: s_endpgm 1307 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1308 %tid.ext = sext i32 %tid to i64 1309 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 1310 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 1311 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 1312 %result = sub <2 x i16> %x, <i16 64, i16 123> 1313 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 1314 ret void 1315} 1316 1317; Can fold 0 and inline immediate in other half. 1318define amdgpu_kernel void @v_test_v2i16_x_sub_7_0(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1319; SI-LABEL: v_test_v2i16_x_sub_7_0: 1320; SI: ; %bb.0: 1321; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1322; SI-NEXT: s_mov_b32 s7, 0xf000 1323; SI-NEXT: s_mov_b32 s6, 0 1324; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1325; SI-NEXT: v_mov_b32_e32 v1, 0 1326; SI-NEXT: s_waitcnt lgkmcnt(0) 1327; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1328; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1329; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1330; SI-NEXT: s_waitcnt vmcnt(0) 1331; SI-NEXT: v_add_i32_e32 v3, vcc, -7, v2 1332; SI-NEXT: s_mov_b32 s4, 0xffff 1333; SI-NEXT: v_bfi_b32 v2, s4, v3, v2 1334; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 1335; SI-NEXT: s_endpgm 1336; 1337; VI-LABEL: v_test_v2i16_x_sub_7_0: 1338; VI: ; %bb.0: 1339; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1340; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1341; VI-NEXT: s_waitcnt lgkmcnt(0) 1342; VI-NEXT: v_mov_b32_e32 v1, s3 1343; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 1344; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1345; VI-NEXT: flat_load_dword v3, v[0:1] 1346; VI-NEXT: v_mov_b32_e32 v1, s1 1347; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 1348; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1349; VI-NEXT: s_waitcnt vmcnt(0) 1350; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 1351; VI-NEXT: v_add_u16_e32 v3, -7, v3 1352; VI-NEXT: v_or_b32_e32 v2, v3, v2 1353; VI-NEXT: flat_store_dword v[0:1], v2 1354; VI-NEXT: s_endpgm 1355; 1356; GFX9-LABEL: v_test_v2i16_x_sub_7_0: 1357; GFX9: ; %bb.0: 1358; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1359; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1360; GFX9-NEXT: s_waitcnt lgkmcnt(0) 1361; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 1362; GFX9-NEXT: s_waitcnt vmcnt(0) 1363; GFX9-NEXT: v_pk_sub_i16 v1, v1, 7 1364; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 1365; GFX9-NEXT: s_endpgm 1366; 1367; GFX10-LABEL: v_test_v2i16_x_sub_7_0: 1368; GFX10: ; %bb.0: 1369; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1370; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1371; GFX10-NEXT: s_waitcnt lgkmcnt(0) 1372; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 1373; GFX10-NEXT: s_waitcnt vmcnt(0) 1374; GFX10-NEXT: v_pk_sub_i16 v1, v1, 7 1375; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 1376; GFX10-NEXT: s_endpgm 1377; 1378; GFX11-LABEL: v_test_v2i16_x_sub_7_0: 1379; GFX11: ; %bb.0: 1380; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 1381; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1382; GFX11-NEXT: s_waitcnt lgkmcnt(0) 1383; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 1384; GFX11-NEXT: s_waitcnt vmcnt(0) 1385; GFX11-NEXT: v_pk_sub_i16 v1, v1, 7 1386; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 1387; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 1388; GFX11-NEXT: s_endpgm 1389 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1390 %tid.ext = sext i32 %tid to i64 1391 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 1392 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 1393 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 1394 %result = sub <2 x i16> %x, <i16 7, i16 0> 1395 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 1396 ret void 1397} 1398 1399; Can fold 0 and inline immediate in other half. 1400define amdgpu_kernel void @v_test_v2i16_x_sub_0_16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1401; SI-LABEL: v_test_v2i16_x_sub_0_16: 1402; SI: ; %bb.0: 1403; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1404; SI-NEXT: s_mov_b32 s7, 0xf000 1405; SI-NEXT: s_mov_b32 s6, 0 1406; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1407; SI-NEXT: v_mov_b32_e32 v1, 0 1408; SI-NEXT: s_waitcnt lgkmcnt(0) 1409; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1410; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1411; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1412; SI-NEXT: s_waitcnt vmcnt(0) 1413; SI-NEXT: v_add_i32_e32 v2, vcc, 0xfff00000, v2 1414; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 1415; SI-NEXT: s_endpgm 1416; 1417; VI-LABEL: v_test_v2i16_x_sub_0_16: 1418; VI: ; %bb.0: 1419; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1420; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1421; VI-NEXT: s_waitcnt lgkmcnt(0) 1422; VI-NEXT: v_mov_b32_e32 v1, s3 1423; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 1424; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1425; VI-NEXT: flat_load_dword v3, v[0:1] 1426; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 1427; VI-NEXT: v_mov_b32_e32 v2, -16 1428; VI-NEXT: v_mov_b32_e32 v1, s1 1429; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1430; VI-NEXT: s_waitcnt vmcnt(0) 1431; VI-NEXT: v_add_u16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1432; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1433; VI-NEXT: flat_store_dword v[0:1], v2 1434; VI-NEXT: s_endpgm 1435; 1436; GFX9-LABEL: v_test_v2i16_x_sub_0_16: 1437; GFX9: ; %bb.0: 1438; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1439; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1440; GFX9-NEXT: s_waitcnt lgkmcnt(0) 1441; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 1442; GFX9-NEXT: s_waitcnt vmcnt(0) 1443; GFX9-NEXT: v_pk_sub_i16 v1, v1, 16 op_sel:[0,1] op_sel_hi:[1,0] 1444; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 1445; GFX9-NEXT: s_endpgm 1446; 1447; GFX10-LABEL: v_test_v2i16_x_sub_0_16: 1448; GFX10: ; %bb.0: 1449; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1450; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1451; GFX10-NEXT: s_waitcnt lgkmcnt(0) 1452; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 1453; GFX10-NEXT: s_waitcnt vmcnt(0) 1454; GFX10-NEXT: v_pk_sub_i16 v1, v1, 16 op_sel:[0,1] op_sel_hi:[1,0] 1455; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 1456; GFX10-NEXT: s_endpgm 1457; 1458; GFX11-LABEL: v_test_v2i16_x_sub_0_16: 1459; GFX11: ; %bb.0: 1460; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 1461; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1462; GFX11-NEXT: s_waitcnt lgkmcnt(0) 1463; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 1464; GFX11-NEXT: s_waitcnt vmcnt(0) 1465; GFX11-NEXT: v_pk_sub_i16 v1, v1, 16 op_sel:[0,1] op_sel_hi:[1,0] 1466; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 1467; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 1468; GFX11-NEXT: s_endpgm 1469 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1470 %tid.ext = sext i32 %tid to i64 1471 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 1472 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 1473 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 1474 %result = sub <2 x i16> %x, <i16 0, i16 16> 1475 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 1476 ret void 1477} 1478 1479define amdgpu_kernel void @v_test_v2i16_x_sub_0_1_0(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1480; SI-LABEL: v_test_v2i16_x_sub_0_1_0: 1481; SI: ; %bb.0: 1482; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1483; SI-NEXT: s_mov_b32 s7, 0xf000 1484; SI-NEXT: s_mov_b32 s6, 0 1485; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1486; SI-NEXT: v_mov_b32_e32 v1, 0 1487; SI-NEXT: s_waitcnt lgkmcnt(0) 1488; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1489; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1490; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1491; SI-NEXT: s_waitcnt vmcnt(0) 1492; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3c000000, v2 1493; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 1494; SI-NEXT: s_endpgm 1495; 1496; VI-LABEL: v_test_v2i16_x_sub_0_1_0: 1497; VI: ; %bb.0: 1498; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1499; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1500; VI-NEXT: s_waitcnt lgkmcnt(0) 1501; VI-NEXT: v_mov_b32_e32 v1, s3 1502; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 1503; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1504; VI-NEXT: flat_load_dword v3, v[0:1] 1505; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 1506; VI-NEXT: v_mov_b32_e32 v2, 0x3c00 1507; VI-NEXT: v_mov_b32_e32 v1, s1 1508; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1509; VI-NEXT: s_waitcnt vmcnt(0) 1510; VI-NEXT: v_add_u16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1511; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1512; VI-NEXT: flat_store_dword v[0:1], v2 1513; VI-NEXT: s_endpgm 1514; 1515; GFX9-LABEL: v_test_v2i16_x_sub_0_1_0: 1516; GFX9: ; %bb.0: 1517; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1518; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1519; GFX9-NEXT: s_waitcnt lgkmcnt(0) 1520; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 1521; GFX9-NEXT: s_brev_b32 s2, 35 1522; GFX9-NEXT: s_waitcnt vmcnt(0) 1523; GFX9-NEXT: v_pk_sub_i16 v1, v1, s2 1524; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 1525; GFX9-NEXT: s_endpgm 1526; 1527; GFX10-LABEL: v_test_v2i16_x_sub_0_1_0: 1528; GFX10: ; %bb.0: 1529; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1530; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1531; GFX10-NEXT: s_waitcnt lgkmcnt(0) 1532; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 1533; GFX10-NEXT: s_waitcnt vmcnt(0) 1534; GFX10-NEXT: v_pk_sub_i16 v1, v1, 0xc400 op_sel:[0,1] op_sel_hi:[1,0] 1535; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 1536; GFX10-NEXT: s_endpgm 1537; 1538; GFX11-LABEL: v_test_v2i16_x_sub_0_1_0: 1539; GFX11: ; %bb.0: 1540; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 1541; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1542; GFX11-NEXT: s_waitcnt lgkmcnt(0) 1543; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 1544; GFX11-NEXT: s_waitcnt vmcnt(0) 1545; GFX11-NEXT: v_pk_sub_i16 v1, v1, 0xc400 op_sel:[0,1] op_sel_hi:[1,0] 1546; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 1547; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 1548; GFX11-NEXT: s_endpgm 1549 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1550 %tid.ext = sext i32 %tid to i64 1551 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 1552 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 1553 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 1554 %result = sub <2 x i16> %x, <i16 0, i16 -15360> 1555 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 1556 ret void 1557} 1558 1559define amdgpu_kernel void @v_test_v2i16_x_sub_0_neg1_0(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1560; SI-LABEL: v_test_v2i16_x_sub_0_neg1_0: 1561; SI: ; %bb.0: 1562; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1563; SI-NEXT: s_mov_b32 s7, 0xf000 1564; SI-NEXT: s_mov_b32 s6, 0 1565; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1566; SI-NEXT: v_mov_b32_e32 v1, 0 1567; SI-NEXT: s_waitcnt lgkmcnt(0) 1568; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1569; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1570; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1571; SI-NEXT: s_waitcnt vmcnt(0) 1572; SI-NEXT: v_add_i32_e32 v2, vcc, 0xbc000000, v2 1573; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 1574; SI-NEXT: s_endpgm 1575; 1576; VI-LABEL: v_test_v2i16_x_sub_0_neg1_0: 1577; VI: ; %bb.0: 1578; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1579; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1580; VI-NEXT: s_waitcnt lgkmcnt(0) 1581; VI-NEXT: v_mov_b32_e32 v1, s3 1582; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 1583; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1584; VI-NEXT: flat_load_dword v3, v[0:1] 1585; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 1586; VI-NEXT: v_mov_b32_e32 v2, 0xffffbc00 1587; VI-NEXT: v_mov_b32_e32 v1, s1 1588; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1589; VI-NEXT: s_waitcnt vmcnt(0) 1590; VI-NEXT: v_add_u16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1591; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1592; VI-NEXT: flat_store_dword v[0:1], v2 1593; VI-NEXT: s_endpgm 1594; 1595; GFX9-LABEL: v_test_v2i16_x_sub_0_neg1_0: 1596; GFX9: ; %bb.0: 1597; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1598; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1599; GFX9-NEXT: s_waitcnt lgkmcnt(0) 1600; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 1601; GFX9-NEXT: s_brev_b32 s2, 34 1602; GFX9-NEXT: s_waitcnt vmcnt(0) 1603; GFX9-NEXT: v_pk_sub_i16 v1, v1, s2 1604; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 1605; GFX9-NEXT: s_endpgm 1606; 1607; GFX10-LABEL: v_test_v2i16_x_sub_0_neg1_0: 1608; GFX10: ; %bb.0: 1609; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1610; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1611; GFX10-NEXT: s_waitcnt lgkmcnt(0) 1612; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 1613; GFX10-NEXT: s_waitcnt vmcnt(0) 1614; GFX10-NEXT: v_pk_sub_i16 v1, v1, 0x4400 op_sel:[0,1] op_sel_hi:[1,0] 1615; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 1616; GFX10-NEXT: s_endpgm 1617; 1618; GFX11-LABEL: v_test_v2i16_x_sub_0_neg1_0: 1619; GFX11: ; %bb.0: 1620; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 1621; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1622; GFX11-NEXT: s_waitcnt lgkmcnt(0) 1623; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 1624; GFX11-NEXT: s_waitcnt vmcnt(0) 1625; GFX11-NEXT: v_pk_sub_i16 v1, v1, 0x4400 op_sel:[0,1] op_sel_hi:[1,0] 1626; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 1627; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 1628; GFX11-NEXT: s_endpgm 1629 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1630 %tid.ext = sext i32 %tid to i64 1631 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 1632 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 1633 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 1634 %result = sub <2 x i16> %x, <i16 0, i16 17408> 1635 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 1636 ret void 1637} 1638 1639; -32 isn't an inline immediate, but 32 is 1640define amdgpu_kernel void @v_test_v2i16_x_add_neg32_neg32(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1641; SI-LABEL: v_test_v2i16_x_add_neg32_neg32: 1642; SI: ; %bb.0: 1643; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1644; SI-NEXT: s_mov_b32 s7, 0xf000 1645; SI-NEXT: s_mov_b32 s6, 0 1646; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1647; SI-NEXT: v_mov_b32_e32 v1, 0 1648; SI-NEXT: s_waitcnt lgkmcnt(0) 1649; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1650; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1651; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1652; SI-NEXT: s_waitcnt vmcnt(0) 1653; SI-NEXT: v_subrev_i32_e32 v3, vcc, 32, v2 1654; SI-NEXT: s_mov_b32 s4, 0xffff0000 1655; SI-NEXT: v_bfi_b32 v2, s4, v2, v3 1656; SI-NEXT: v_add_i32_e32 v2, vcc, 0xffe00000, v2 1657; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 1658; SI-NEXT: s_endpgm 1659; 1660; VI-LABEL: v_test_v2i16_x_add_neg32_neg32: 1661; VI: ; %bb.0: 1662; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1663; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1664; VI-NEXT: v_mov_b32_e32 v4, 32 1665; VI-NEXT: s_waitcnt lgkmcnt(0) 1666; VI-NEXT: v_mov_b32_e32 v1, s3 1667; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 1668; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1669; VI-NEXT: flat_load_dword v3, v[0:1] 1670; VI-NEXT: v_mov_b32_e32 v1, s1 1671; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 1672; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1673; VI-NEXT: s_waitcnt vmcnt(0) 1674; VI-NEXT: v_sub_u16_sdwa v2, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1675; VI-NEXT: v_subrev_u16_e32 v3, 32, v3 1676; VI-NEXT: v_or_b32_e32 v2, v3, v2 1677; VI-NEXT: flat_store_dword v[0:1], v2 1678; VI-NEXT: s_endpgm 1679; 1680; GFX9-LABEL: v_test_v2i16_x_add_neg32_neg32: 1681; GFX9: ; %bb.0: 1682; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1683; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1684; GFX9-NEXT: s_waitcnt lgkmcnt(0) 1685; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 1686; GFX9-NEXT: s_waitcnt vmcnt(0) 1687; GFX9-NEXT: v_pk_sub_u16 v1, v1, 32 op_sel_hi:[1,0] 1688; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 1689; GFX9-NEXT: s_endpgm 1690; 1691; GFX10-LABEL: v_test_v2i16_x_add_neg32_neg32: 1692; GFX10: ; %bb.0: 1693; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1694; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1695; GFX10-NEXT: s_waitcnt lgkmcnt(0) 1696; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 1697; GFX10-NEXT: s_waitcnt vmcnt(0) 1698; GFX10-NEXT: v_pk_sub_u16 v1, v1, 32 op_sel_hi:[1,0] 1699; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 1700; GFX10-NEXT: s_endpgm 1701; 1702; GFX11-LABEL: v_test_v2i16_x_add_neg32_neg32: 1703; GFX11: ; %bb.0: 1704; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 1705; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1706; GFX11-NEXT: s_waitcnt lgkmcnt(0) 1707; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 1708; GFX11-NEXT: s_waitcnt vmcnt(0) 1709; GFX11-NEXT: v_pk_sub_u16 v1, v1, 32 op_sel_hi:[1,0] 1710; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 1711; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 1712; GFX11-NEXT: s_endpgm 1713 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1714 %tid.ext = sext i32 %tid to i64 1715 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 1716 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 1717 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 1718 %result = add <2 x i16> %x, <i16 -32, i16 -32> 1719 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 1720 ret void 1721} 1722 1723define amdgpu_kernel void @v_test_v2i16_x_add_0_neg32(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1724; SI-LABEL: v_test_v2i16_x_add_0_neg32: 1725; SI: ; %bb.0: 1726; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1727; SI-NEXT: s_mov_b32 s7, 0xf000 1728; SI-NEXT: s_mov_b32 s6, 0 1729; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1730; SI-NEXT: v_mov_b32_e32 v1, 0 1731; SI-NEXT: s_waitcnt lgkmcnt(0) 1732; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1733; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1734; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1735; SI-NEXT: s_waitcnt vmcnt(0) 1736; SI-NEXT: v_add_i32_e32 v2, vcc, 0xffe00000, v2 1737; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 1738; SI-NEXT: s_endpgm 1739; 1740; VI-LABEL: v_test_v2i16_x_add_0_neg32: 1741; VI: ; %bb.0: 1742; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1743; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1744; VI-NEXT: s_waitcnt lgkmcnt(0) 1745; VI-NEXT: v_mov_b32_e32 v1, s3 1746; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 1747; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1748; VI-NEXT: flat_load_dword v3, v[0:1] 1749; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 1750; VI-NEXT: v_mov_b32_e32 v2, 32 1751; VI-NEXT: v_mov_b32_e32 v1, s1 1752; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1753; VI-NEXT: s_waitcnt vmcnt(0) 1754; VI-NEXT: v_sub_u16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1755; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1756; VI-NEXT: flat_store_dword v[0:1], v2 1757; VI-NEXT: s_endpgm 1758; 1759; GFX9-LABEL: v_test_v2i16_x_add_0_neg32: 1760; GFX9: ; %bb.0: 1761; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1762; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1763; GFX9-NEXT: s_waitcnt lgkmcnt(0) 1764; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 1765; GFX9-NEXT: s_waitcnt vmcnt(0) 1766; GFX9-NEXT: v_pk_sub_u16 v1, v1, 32 op_sel:[0,1] op_sel_hi:[1,0] 1767; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 1768; GFX9-NEXT: s_endpgm 1769; 1770; GFX10-LABEL: v_test_v2i16_x_add_0_neg32: 1771; GFX10: ; %bb.0: 1772; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1773; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1774; GFX10-NEXT: s_waitcnt lgkmcnt(0) 1775; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 1776; GFX10-NEXT: s_waitcnt vmcnt(0) 1777; GFX10-NEXT: v_pk_sub_u16 v1, v1, 32 op_sel:[0,1] op_sel_hi:[1,0] 1778; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 1779; GFX10-NEXT: s_endpgm 1780; 1781; GFX11-LABEL: v_test_v2i16_x_add_0_neg32: 1782; GFX11: ; %bb.0: 1783; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 1784; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1785; GFX11-NEXT: s_waitcnt lgkmcnt(0) 1786; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 1787; GFX11-NEXT: s_waitcnt vmcnt(0) 1788; GFX11-NEXT: v_pk_sub_u16 v1, v1, 32 op_sel:[0,1] op_sel_hi:[1,0] 1789; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 1790; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 1791; GFX11-NEXT: s_endpgm 1792 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1793 %tid.ext = sext i32 %tid to i64 1794 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 1795 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 1796 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 1797 %result = add <2 x i16> %x, <i16 0, i16 -32> 1798 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 1799 ret void 1800} 1801 1802define amdgpu_kernel void @v_test_v2i16_x_add_neg32_0(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1803; SI-LABEL: v_test_v2i16_x_add_neg32_0: 1804; SI: ; %bb.0: 1805; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1806; SI-NEXT: s_mov_b32 s7, 0xf000 1807; SI-NEXT: s_mov_b32 s6, 0 1808; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1809; SI-NEXT: v_mov_b32_e32 v1, 0 1810; SI-NEXT: s_waitcnt lgkmcnt(0) 1811; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1812; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1813; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1814; SI-NEXT: s_waitcnt vmcnt(0) 1815; SI-NEXT: v_subrev_i32_e32 v3, vcc, 32, v2 1816; SI-NEXT: s_mov_b32 s4, 0xffff 1817; SI-NEXT: v_bfi_b32 v2, s4, v3, v2 1818; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 1819; SI-NEXT: s_endpgm 1820; 1821; VI-LABEL: v_test_v2i16_x_add_neg32_0: 1822; VI: ; %bb.0: 1823; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1824; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1825; VI-NEXT: s_waitcnt lgkmcnt(0) 1826; VI-NEXT: v_mov_b32_e32 v1, s3 1827; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 1828; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1829; VI-NEXT: flat_load_dword v3, v[0:1] 1830; VI-NEXT: v_mov_b32_e32 v1, s1 1831; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 1832; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1833; VI-NEXT: s_waitcnt vmcnt(0) 1834; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 1835; VI-NEXT: v_subrev_u16_e32 v3, 32, v3 1836; VI-NEXT: v_or_b32_e32 v2, v3, v2 1837; VI-NEXT: flat_store_dword v[0:1], v2 1838; VI-NEXT: s_endpgm 1839; 1840; GFX9-LABEL: v_test_v2i16_x_add_neg32_0: 1841; GFX9: ; %bb.0: 1842; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1843; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1844; GFX9-NEXT: s_waitcnt lgkmcnt(0) 1845; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 1846; GFX9-NEXT: s_waitcnt vmcnt(0) 1847; GFX9-NEXT: v_pk_sub_u16 v1, v1, 32 1848; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 1849; GFX9-NEXT: s_endpgm 1850; 1851; GFX10-LABEL: v_test_v2i16_x_add_neg32_0: 1852; GFX10: ; %bb.0: 1853; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1854; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1855; GFX10-NEXT: s_waitcnt lgkmcnt(0) 1856; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 1857; GFX10-NEXT: s_waitcnt vmcnt(0) 1858; GFX10-NEXT: v_pk_sub_u16 v1, v1, 32 1859; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 1860; GFX10-NEXT: s_endpgm 1861; 1862; GFX11-LABEL: v_test_v2i16_x_add_neg32_0: 1863; GFX11: ; %bb.0: 1864; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 1865; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1866; GFX11-NEXT: s_waitcnt lgkmcnt(0) 1867; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 1868; GFX11-NEXT: s_waitcnt vmcnt(0) 1869; GFX11-NEXT: v_pk_sub_u16 v1, v1, 32 1870; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 1871; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 1872; GFX11-NEXT: s_endpgm 1873 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1874 %tid.ext = sext i32 %tid to i64 1875 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 1876 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 1877 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 1878 %result = add <2 x i16> %x, <i16 -32, i16 0> 1879 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 1880 ret void 1881} 1882 1883; 16 and -16 are both inline immediates 1884define amdgpu_kernel void @v_test_v2i16_x_add_neg16_neg16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1885; SI-LABEL: v_test_v2i16_x_add_neg16_neg16: 1886; SI: ; %bb.0: 1887; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1888; SI-NEXT: s_mov_b32 s7, 0xf000 1889; SI-NEXT: s_mov_b32 s6, 0 1890; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1891; SI-NEXT: v_mov_b32_e32 v1, 0 1892; SI-NEXT: s_waitcnt lgkmcnt(0) 1893; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1894; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1895; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1896; SI-NEXT: s_waitcnt vmcnt(0) 1897; SI-NEXT: v_add_i32_e32 v3, vcc, -16, v2 1898; SI-NEXT: s_mov_b32 s4, 0xffff0000 1899; SI-NEXT: v_bfi_b32 v2, s4, v2, v3 1900; SI-NEXT: v_add_i32_e32 v2, vcc, 0xfff00000, v2 1901; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 1902; SI-NEXT: s_endpgm 1903; 1904; VI-LABEL: v_test_v2i16_x_add_neg16_neg16: 1905; VI: ; %bb.0: 1906; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1907; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1908; VI-NEXT: v_mov_b32_e32 v4, -16 1909; VI-NEXT: s_waitcnt lgkmcnt(0) 1910; VI-NEXT: v_mov_b32_e32 v1, s3 1911; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 1912; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1913; VI-NEXT: flat_load_dword v3, v[0:1] 1914; VI-NEXT: v_mov_b32_e32 v1, s1 1915; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 1916; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1917; VI-NEXT: s_waitcnt vmcnt(0) 1918; VI-NEXT: v_add_u16_e32 v2, -16, v3 1919; VI-NEXT: v_add_u16_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1920; VI-NEXT: v_or_b32_e32 v2, v2, v3 1921; VI-NEXT: flat_store_dword v[0:1], v2 1922; VI-NEXT: s_endpgm 1923; 1924; GFX9-LABEL: v_test_v2i16_x_add_neg16_neg16: 1925; GFX9: ; %bb.0: 1926; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1927; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1928; GFX9-NEXT: s_waitcnt lgkmcnt(0) 1929; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 1930; GFX9-NEXT: s_waitcnt vmcnt(0) 1931; GFX9-NEXT: v_pk_sub_u16 v1, v1, 16 op_sel_hi:[1,0] 1932; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 1933; GFX9-NEXT: s_endpgm 1934; 1935; GFX10-LABEL: v_test_v2i16_x_add_neg16_neg16: 1936; GFX10: ; %bb.0: 1937; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1938; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1939; GFX10-NEXT: s_waitcnt lgkmcnt(0) 1940; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 1941; GFX10-NEXT: s_waitcnt vmcnt(0) 1942; GFX10-NEXT: v_pk_sub_u16 v1, v1, 16 op_sel_hi:[1,0] 1943; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 1944; GFX10-NEXT: s_endpgm 1945; 1946; GFX11-LABEL: v_test_v2i16_x_add_neg16_neg16: 1947; GFX11: ; %bb.0: 1948; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 1949; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1950; GFX11-NEXT: s_waitcnt lgkmcnt(0) 1951; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 1952; GFX11-NEXT: s_waitcnt vmcnt(0) 1953; GFX11-NEXT: v_pk_sub_u16 v1, v1, 16 op_sel_hi:[1,0] 1954; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 1955; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 1956; GFX11-NEXT: s_endpgm 1957 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1958 %tid.ext = sext i32 %tid to i64 1959 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 1960 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 1961 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 1962 %result = add <2 x i16> %x, <i16 -16, i16 -16> 1963 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 1964 ret void 1965} 1966 1967define amdgpu_kernel void @v_test_v2i16_x_add_0_neg16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1968; SI-LABEL: v_test_v2i16_x_add_0_neg16: 1969; SI: ; %bb.0: 1970; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1971; SI-NEXT: s_mov_b32 s7, 0xf000 1972; SI-NEXT: s_mov_b32 s6, 0 1973; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1974; SI-NEXT: v_mov_b32_e32 v1, 0 1975; SI-NEXT: s_waitcnt lgkmcnt(0) 1976; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1977; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1978; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1979; SI-NEXT: s_waitcnt vmcnt(0) 1980; SI-NEXT: v_add_i32_e32 v2, vcc, 0xfff00000, v2 1981; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 1982; SI-NEXT: s_endpgm 1983; 1984; VI-LABEL: v_test_v2i16_x_add_0_neg16: 1985; VI: ; %bb.0: 1986; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1987; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1988; VI-NEXT: s_waitcnt lgkmcnt(0) 1989; VI-NEXT: v_mov_b32_e32 v1, s3 1990; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 1991; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1992; VI-NEXT: flat_load_dword v3, v[0:1] 1993; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 1994; VI-NEXT: v_mov_b32_e32 v2, -16 1995; VI-NEXT: v_mov_b32_e32 v1, s1 1996; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1997; VI-NEXT: s_waitcnt vmcnt(0) 1998; VI-NEXT: v_add_u16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1999; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 2000; VI-NEXT: flat_store_dword v[0:1], v2 2001; VI-NEXT: s_endpgm 2002; 2003; GFX9-LABEL: v_test_v2i16_x_add_0_neg16: 2004; GFX9: ; %bb.0: 2005; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2006; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2007; GFX9-NEXT: s_waitcnt lgkmcnt(0) 2008; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 2009; GFX9-NEXT: s_waitcnt vmcnt(0) 2010; GFX9-NEXT: v_pk_sub_u16 v1, v1, 16 op_sel:[0,1] op_sel_hi:[1,0] 2011; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 2012; GFX9-NEXT: s_endpgm 2013; 2014; GFX10-LABEL: v_test_v2i16_x_add_0_neg16: 2015; GFX10: ; %bb.0: 2016; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2017; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2018; GFX10-NEXT: s_waitcnt lgkmcnt(0) 2019; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 2020; GFX10-NEXT: s_waitcnt vmcnt(0) 2021; GFX10-NEXT: v_pk_sub_u16 v1, v1, 16 op_sel:[0,1] op_sel_hi:[1,0] 2022; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 2023; GFX10-NEXT: s_endpgm 2024; 2025; GFX11-LABEL: v_test_v2i16_x_add_0_neg16: 2026; GFX11: ; %bb.0: 2027; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 2028; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2029; GFX11-NEXT: s_waitcnt lgkmcnt(0) 2030; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 2031; GFX11-NEXT: s_waitcnt vmcnt(0) 2032; GFX11-NEXT: v_pk_sub_u16 v1, v1, 16 op_sel:[0,1] op_sel_hi:[1,0] 2033; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 2034; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 2035; GFX11-NEXT: s_endpgm 2036 %tid = call i32 @llvm.amdgcn.workitem.id.x() 2037 %tid.ext = sext i32 %tid to i64 2038 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 2039 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 2040 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 2041 %result = add <2 x i16> %x, <i16 0, i16 -16> 2042 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 2043 ret void 2044} 2045 2046define amdgpu_kernel void @v_test_v2i16_x_add_neg16_0(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 2047; SI-LABEL: v_test_v2i16_x_add_neg16_0: 2048; SI: ; %bb.0: 2049; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 2050; SI-NEXT: s_mov_b32 s7, 0xf000 2051; SI-NEXT: s_mov_b32 s6, 0 2052; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2053; SI-NEXT: v_mov_b32_e32 v1, 0 2054; SI-NEXT: s_waitcnt lgkmcnt(0) 2055; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 2056; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 2057; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 2058; SI-NEXT: s_waitcnt vmcnt(0) 2059; SI-NEXT: v_add_i32_e32 v3, vcc, -16, v2 2060; SI-NEXT: s_mov_b32 s4, 0xffff 2061; SI-NEXT: v_bfi_b32 v2, s4, v3, v2 2062; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 2063; SI-NEXT: s_endpgm 2064; 2065; VI-LABEL: v_test_v2i16_x_add_neg16_0: 2066; VI: ; %bb.0: 2067; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2068; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2069; VI-NEXT: s_waitcnt lgkmcnt(0) 2070; VI-NEXT: v_mov_b32_e32 v1, s3 2071; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 2072; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2073; VI-NEXT: flat_load_dword v3, v[0:1] 2074; VI-NEXT: v_mov_b32_e32 v1, s1 2075; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 2076; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2077; VI-NEXT: s_waitcnt vmcnt(0) 2078; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 2079; VI-NEXT: v_add_u16_e32 v3, -16, v3 2080; VI-NEXT: v_or_b32_e32 v2, v3, v2 2081; VI-NEXT: flat_store_dword v[0:1], v2 2082; VI-NEXT: s_endpgm 2083; 2084; GFX9-LABEL: v_test_v2i16_x_add_neg16_0: 2085; GFX9: ; %bb.0: 2086; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2087; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2088; GFX9-NEXT: s_waitcnt lgkmcnt(0) 2089; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 2090; GFX9-NEXT: s_waitcnt vmcnt(0) 2091; GFX9-NEXT: v_pk_sub_u16 v1, v1, 16 2092; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 2093; GFX9-NEXT: s_endpgm 2094; 2095; GFX10-LABEL: v_test_v2i16_x_add_neg16_0: 2096; GFX10: ; %bb.0: 2097; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2098; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2099; GFX10-NEXT: s_waitcnt lgkmcnt(0) 2100; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 2101; GFX10-NEXT: s_waitcnt vmcnt(0) 2102; GFX10-NEXT: v_pk_sub_u16 v1, v1, 16 2103; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 2104; GFX10-NEXT: s_endpgm 2105; 2106; GFX11-LABEL: v_test_v2i16_x_add_neg16_0: 2107; GFX11: ; %bb.0: 2108; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 2109; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2110; GFX11-NEXT: s_waitcnt lgkmcnt(0) 2111; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 2112; GFX11-NEXT: s_waitcnt vmcnt(0) 2113; GFX11-NEXT: v_pk_sub_u16 v1, v1, 16 2114; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 2115; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 2116; GFX11-NEXT: s_endpgm 2117 %tid = call i32 @llvm.amdgcn.workitem.id.x() 2118 %tid.ext = sext i32 %tid to i64 2119 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 2120 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 2121 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 2122 %result = add <2 x i16> %x, <i16 -16, i16 0> 2123 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 2124 ret void 2125} 2126 2127define amdgpu_kernel void @v_test_v2i16_x_add_neg_fpone(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 2128; SI-LABEL: v_test_v2i16_x_add_neg_fpone: 2129; SI: ; %bb.0: 2130; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 2131; SI-NEXT: s_mov_b32 s7, 0xf000 2132; SI-NEXT: s_mov_b32 s6, 0 2133; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2134; SI-NEXT: v_mov_b32_e32 v1, 0 2135; SI-NEXT: s_waitcnt lgkmcnt(0) 2136; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 2137; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 2138; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 2139; SI-NEXT: s_waitcnt vmcnt(0) 2140; SI-NEXT: v_add_i32_e32 v3, vcc, 0xffffc400, v2 2141; SI-NEXT: s_mov_b32 s4, 0xffff0000 2142; SI-NEXT: v_bfi_b32 v2, s4, v2, v3 2143; SI-NEXT: v_add_i32_e32 v2, vcc, 0xc4000000, v2 2144; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 2145; SI-NEXT: s_endpgm 2146; 2147; VI-LABEL: v_test_v2i16_x_add_neg_fpone: 2148; VI: ; %bb.0: 2149; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2150; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2151; VI-NEXT: v_mov_b32_e32 v4, 0xffffc400 2152; VI-NEXT: s_waitcnt lgkmcnt(0) 2153; VI-NEXT: v_mov_b32_e32 v1, s3 2154; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 2155; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2156; VI-NEXT: flat_load_dword v3, v[0:1] 2157; VI-NEXT: v_mov_b32_e32 v1, s1 2158; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 2159; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2160; VI-NEXT: s_waitcnt vmcnt(0) 2161; VI-NEXT: v_add_u16_e32 v2, 0xc400, v3 2162; VI-NEXT: v_add_u16_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 2163; VI-NEXT: v_or_b32_e32 v2, v2, v3 2164; VI-NEXT: flat_store_dword v[0:1], v2 2165; VI-NEXT: s_endpgm 2166; 2167; GFX9-LABEL: v_test_v2i16_x_add_neg_fpone: 2168; GFX9: ; %bb.0: 2169; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2170; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2171; GFX9-NEXT: s_waitcnt lgkmcnt(0) 2172; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 2173; GFX9-NEXT: s_mov_b32 s2, 0x3c003c00 2174; GFX9-NEXT: s_waitcnt vmcnt(0) 2175; GFX9-NEXT: v_pk_sub_u16 v1, v1, s2 2176; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 2177; GFX9-NEXT: s_endpgm 2178; 2179; GFX10-LABEL: v_test_v2i16_x_add_neg_fpone: 2180; GFX10: ; %bb.0: 2181; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2182; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2183; GFX10-NEXT: s_waitcnt lgkmcnt(0) 2184; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 2185; GFX10-NEXT: s_waitcnt vmcnt(0) 2186; GFX10-NEXT: v_pk_sub_u16 v1, v1, 0x3c00 op_sel_hi:[1,0] 2187; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 2188; GFX10-NEXT: s_endpgm 2189; 2190; GFX11-LABEL: v_test_v2i16_x_add_neg_fpone: 2191; GFX11: ; %bb.0: 2192; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 2193; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2194; GFX11-NEXT: s_waitcnt lgkmcnt(0) 2195; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 2196; GFX11-NEXT: s_waitcnt vmcnt(0) 2197; GFX11-NEXT: v_pk_sub_u16 v1, v1, 0x3c00 op_sel_hi:[1,0] 2198; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 2199; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 2200; GFX11-NEXT: s_endpgm 2201 %tid = call i32 @llvm.amdgcn.workitem.id.x() 2202 %tid.ext = sext i32 %tid to i64 2203 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 2204 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 2205 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 2206 %result = add <2 x i16> %x, <i16 -15360, i16 -15360> 2207 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 2208 ret void 2209} 2210 2211define amdgpu_kernel void @v_test_v2i16_x_add_neg_negfpone(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 2212; SI-LABEL: v_test_v2i16_x_add_neg_negfpone: 2213; SI: ; %bb.0: 2214; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 2215; SI-NEXT: s_mov_b32 s7, 0xf000 2216; SI-NEXT: s_mov_b32 s6, 0 2217; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2218; SI-NEXT: v_mov_b32_e32 v1, 0 2219; SI-NEXT: s_waitcnt lgkmcnt(0) 2220; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 2221; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 2222; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 2223; SI-NEXT: s_waitcnt vmcnt(0) 2224; SI-NEXT: v_add_i32_e32 v3, vcc, 0x4400, v2 2225; SI-NEXT: s_mov_b32 s4, 0xffff0000 2226; SI-NEXT: v_bfi_b32 v2, s4, v2, v3 2227; SI-NEXT: v_add_i32_e32 v2, vcc, 0x44000000, v2 2228; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 2229; SI-NEXT: s_endpgm 2230; 2231; VI-LABEL: v_test_v2i16_x_add_neg_negfpone: 2232; VI: ; %bb.0: 2233; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2234; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2235; VI-NEXT: v_mov_b32_e32 v4, 0x4400 2236; VI-NEXT: s_waitcnt lgkmcnt(0) 2237; VI-NEXT: v_mov_b32_e32 v1, s3 2238; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 2239; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2240; VI-NEXT: flat_load_dword v3, v[0:1] 2241; VI-NEXT: v_mov_b32_e32 v1, s1 2242; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 2243; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2244; VI-NEXT: s_waitcnt vmcnt(0) 2245; VI-NEXT: v_add_u16_e32 v2, 0x4400, v3 2246; VI-NEXT: v_add_u16_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 2247; VI-NEXT: v_or_b32_e32 v2, v2, v3 2248; VI-NEXT: flat_store_dword v[0:1], v2 2249; VI-NEXT: s_endpgm 2250; 2251; GFX9-LABEL: v_test_v2i16_x_add_neg_negfpone: 2252; GFX9: ; %bb.0: 2253; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2254; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2255; GFX9-NEXT: s_waitcnt lgkmcnt(0) 2256; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 2257; GFX9-NEXT: s_mov_b32 s2, 0xbc00bc00 2258; GFX9-NEXT: s_waitcnt vmcnt(0) 2259; GFX9-NEXT: v_pk_sub_u16 v1, v1, s2 2260; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 2261; GFX9-NEXT: s_endpgm 2262; 2263; GFX10-LABEL: v_test_v2i16_x_add_neg_negfpone: 2264; GFX10: ; %bb.0: 2265; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2266; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2267; GFX10-NEXT: s_waitcnt lgkmcnt(0) 2268; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 2269; GFX10-NEXT: s_waitcnt vmcnt(0) 2270; GFX10-NEXT: v_pk_sub_u16 v1, v1, 0xbc00 op_sel_hi:[1,0] 2271; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 2272; GFX10-NEXT: s_endpgm 2273; 2274; GFX11-LABEL: v_test_v2i16_x_add_neg_negfpone: 2275; GFX11: ; %bb.0: 2276; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 2277; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2278; GFX11-NEXT: s_waitcnt lgkmcnt(0) 2279; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 2280; GFX11-NEXT: s_waitcnt vmcnt(0) 2281; GFX11-NEXT: v_pk_sub_u16 v1, v1, 0xbc00 op_sel_hi:[1,0] 2282; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 2283; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 2284; GFX11-NEXT: s_endpgm 2285 %tid = call i32 @llvm.amdgcn.workitem.id.x() 2286 %tid.ext = sext i32 %tid to i64 2287 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 2288 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 2289 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 2290 %result = add <2 x i16> %x, <i16 17408, i16 17408> 2291 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 2292 ret void 2293} 2294 2295define amdgpu_kernel void @v_test_v2i16_x_add_neg_fptwo(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 2296; SI-LABEL: v_test_v2i16_x_add_neg_fptwo: 2297; SI: ; %bb.0: 2298; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 2299; SI-NEXT: s_mov_b32 s7, 0xf000 2300; SI-NEXT: s_mov_b32 s6, 0 2301; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2302; SI-NEXT: v_mov_b32_e32 v1, 0 2303; SI-NEXT: s_waitcnt lgkmcnt(0) 2304; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 2305; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 2306; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 2307; SI-NEXT: s_waitcnt vmcnt(0) 2308; SI-NEXT: v_add_i32_e32 v3, vcc, 0x4000, v2 2309; SI-NEXT: s_mov_b32 s4, 0xffff0000 2310; SI-NEXT: v_bfi_b32 v2, s4, v2, v3 2311; SI-NEXT: v_add_i32_e32 v2, vcc, 2.0, v2 2312; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 2313; SI-NEXT: s_endpgm 2314; 2315; VI-LABEL: v_test_v2i16_x_add_neg_fptwo: 2316; VI: ; %bb.0: 2317; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2318; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2319; VI-NEXT: v_mov_b32_e32 v4, 0x4000 2320; VI-NEXT: s_waitcnt lgkmcnt(0) 2321; VI-NEXT: v_mov_b32_e32 v1, s3 2322; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 2323; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2324; VI-NEXT: flat_load_dword v3, v[0:1] 2325; VI-NEXT: v_mov_b32_e32 v1, s1 2326; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 2327; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2328; VI-NEXT: s_waitcnt vmcnt(0) 2329; VI-NEXT: v_add_u16_e32 v2, 0x4000, v3 2330; VI-NEXT: v_add_u16_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 2331; VI-NEXT: v_or_b32_e32 v2, v2, v3 2332; VI-NEXT: flat_store_dword v[0:1], v2 2333; VI-NEXT: s_endpgm 2334; 2335; GFX9-LABEL: v_test_v2i16_x_add_neg_fptwo: 2336; GFX9: ; %bb.0: 2337; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2338; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2339; GFX9-NEXT: s_waitcnt lgkmcnt(0) 2340; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 2341; GFX9-NEXT: s_mov_b32 s2, 0xc000c000 2342; GFX9-NEXT: s_waitcnt vmcnt(0) 2343; GFX9-NEXT: v_pk_sub_u16 v1, v1, s2 2344; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 2345; GFX9-NEXT: s_endpgm 2346; 2347; GFX10-LABEL: v_test_v2i16_x_add_neg_fptwo: 2348; GFX10: ; %bb.0: 2349; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2350; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2351; GFX10-NEXT: s_waitcnt lgkmcnt(0) 2352; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 2353; GFX10-NEXT: s_waitcnt vmcnt(0) 2354; GFX10-NEXT: v_pk_sub_u16 v1, v1, 0xc000 op_sel_hi:[1,0] 2355; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 2356; GFX10-NEXT: s_endpgm 2357; 2358; GFX11-LABEL: v_test_v2i16_x_add_neg_fptwo: 2359; GFX11: ; %bb.0: 2360; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 2361; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2362; GFX11-NEXT: s_waitcnt lgkmcnt(0) 2363; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 2364; GFX11-NEXT: s_waitcnt vmcnt(0) 2365; GFX11-NEXT: v_pk_sub_u16 v1, v1, 0xc000 op_sel_hi:[1,0] 2366; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 2367; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 2368; GFX11-NEXT: s_endpgm 2369 %tid = call i32 @llvm.amdgcn.workitem.id.x() 2370 %tid.ext = sext i32 %tid to i64 2371 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 2372 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 2373 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 2374 %result = add <2 x i16> %x, <i16 16384, i16 16384> 2375 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 2376 ret void 2377} 2378 2379define amdgpu_kernel void @v_test_v2i16_x_add_neg_negfptwo(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 2380; SI-LABEL: v_test_v2i16_x_add_neg_negfptwo: 2381; SI: ; %bb.0: 2382; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 2383; SI-NEXT: s_mov_b32 s7, 0xf000 2384; SI-NEXT: s_mov_b32 s6, 0 2385; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2386; SI-NEXT: v_mov_b32_e32 v1, 0 2387; SI-NEXT: s_waitcnt lgkmcnt(0) 2388; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 2389; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 2390; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 2391; SI-NEXT: s_waitcnt vmcnt(0) 2392; SI-NEXT: v_add_i32_e32 v3, vcc, 0xffffc000, v2 2393; SI-NEXT: s_mov_b32 s4, 0xffff0000 2394; SI-NEXT: v_bfi_b32 v2, s4, v2, v3 2395; SI-NEXT: v_add_i32_e32 v2, vcc, -2.0, v2 2396; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 2397; SI-NEXT: s_endpgm 2398; 2399; VI-LABEL: v_test_v2i16_x_add_neg_negfptwo: 2400; VI: ; %bb.0: 2401; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2402; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2403; VI-NEXT: v_mov_b32_e32 v4, 0xffffc000 2404; VI-NEXT: s_waitcnt lgkmcnt(0) 2405; VI-NEXT: v_mov_b32_e32 v1, s3 2406; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 2407; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2408; VI-NEXT: flat_load_dword v3, v[0:1] 2409; VI-NEXT: v_mov_b32_e32 v1, s1 2410; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 2411; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2412; VI-NEXT: s_waitcnt vmcnt(0) 2413; VI-NEXT: v_add_u16_e32 v2, 0xc000, v3 2414; VI-NEXT: v_add_u16_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 2415; VI-NEXT: v_or_b32_e32 v2, v2, v3 2416; VI-NEXT: flat_store_dword v[0:1], v2 2417; VI-NEXT: s_endpgm 2418; 2419; GFX9-LABEL: v_test_v2i16_x_add_neg_negfptwo: 2420; GFX9: ; %bb.0: 2421; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2422; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2423; GFX9-NEXT: s_waitcnt lgkmcnt(0) 2424; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 2425; GFX9-NEXT: s_mov_b32 s2, 0x40004000 2426; GFX9-NEXT: s_waitcnt vmcnt(0) 2427; GFX9-NEXT: v_pk_sub_u16 v1, v1, s2 2428; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 2429; GFX9-NEXT: s_endpgm 2430; 2431; GFX10-LABEL: v_test_v2i16_x_add_neg_negfptwo: 2432; GFX10: ; %bb.0: 2433; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2434; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2435; GFX10-NEXT: s_waitcnt lgkmcnt(0) 2436; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 2437; GFX10-NEXT: s_waitcnt vmcnt(0) 2438; GFX10-NEXT: v_pk_sub_u16 v1, v1, 0x4000 op_sel_hi:[1,0] 2439; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 2440; GFX10-NEXT: s_endpgm 2441; 2442; GFX11-LABEL: v_test_v2i16_x_add_neg_negfptwo: 2443; GFX11: ; %bb.0: 2444; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 2445; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2446; GFX11-NEXT: s_waitcnt lgkmcnt(0) 2447; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 2448; GFX11-NEXT: s_waitcnt vmcnt(0) 2449; GFX11-NEXT: v_pk_sub_u16 v1, v1, 0x4000 op_sel_hi:[1,0] 2450; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 2451; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 2452; GFX11-NEXT: s_endpgm 2453 %tid = call i32 @llvm.amdgcn.workitem.id.x() 2454 %tid.ext = sext i32 %tid to i64 2455 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 2456 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 2457 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 2458 %result = add <2 x i16> %x, <i16 -16384, i16 -16384> 2459 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 2460 ret void 2461} 2462 2463define amdgpu_kernel void @v_test_v2i16_x_add_undef_neg32(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 2464; SI-LABEL: v_test_v2i16_x_add_undef_neg32: 2465; SI: ; %bb.0: 2466; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 2467; SI-NEXT: s_mov_b32 s7, 0xf000 2468; SI-NEXT: s_mov_b32 s6, 0 2469; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2470; SI-NEXT: v_mov_b32_e32 v1, 0 2471; SI-NEXT: s_waitcnt lgkmcnt(0) 2472; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 2473; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 2474; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 2475; SI-NEXT: s_waitcnt vmcnt(0) 2476; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 2477; SI-NEXT: v_add_i32_e32 v2, vcc, 0xffe00000, v2 2478; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 2479; SI-NEXT: s_endpgm 2480; 2481; VI-LABEL: v_test_v2i16_x_add_undef_neg32: 2482; VI: ; %bb.0: 2483; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2484; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2485; VI-NEXT: s_waitcnt lgkmcnt(0) 2486; VI-NEXT: v_mov_b32_e32 v1, s3 2487; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 2488; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2489; VI-NEXT: flat_load_dword v3, v[0:1] 2490; VI-NEXT: v_mov_b32_e32 v1, s1 2491; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 2492; VI-NEXT: v_mov_b32_e32 v2, 32 2493; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2494; VI-NEXT: s_waitcnt vmcnt(0) 2495; VI-NEXT: v_sub_u16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 2496; VI-NEXT: flat_store_dword v[0:1], v2 2497; VI-NEXT: s_endpgm 2498; 2499; GFX9-LABEL: v_test_v2i16_x_add_undef_neg32: 2500; GFX9: ; %bb.0: 2501; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2502; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2503; GFX9-NEXT: s_waitcnt lgkmcnt(0) 2504; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 2505; GFX9-NEXT: s_waitcnt vmcnt(0) 2506; GFX9-NEXT: v_pk_sub_u16 v1, v1, 32 op_sel:[0,1] op_sel_hi:[1,0] 2507; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 2508; GFX9-NEXT: s_endpgm 2509; 2510; GFX10-LABEL: v_test_v2i16_x_add_undef_neg32: 2511; GFX10: ; %bb.0: 2512; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2513; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2514; GFX10-NEXT: s_waitcnt lgkmcnt(0) 2515; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 2516; GFX10-NEXT: s_waitcnt vmcnt(0) 2517; GFX10-NEXT: v_pk_sub_u16 v1, v1, 32 op_sel:[0,1] op_sel_hi:[1,0] 2518; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 2519; GFX10-NEXT: s_endpgm 2520; 2521; GFX11-LABEL: v_test_v2i16_x_add_undef_neg32: 2522; GFX11: ; %bb.0: 2523; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 2524; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2525; GFX11-NEXT: s_waitcnt lgkmcnt(0) 2526; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 2527; GFX11-NEXT: s_waitcnt vmcnt(0) 2528; GFX11-NEXT: v_pk_sub_u16 v1, v1, 32 op_sel:[0,1] op_sel_hi:[1,0] 2529; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 2530; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 2531; GFX11-NEXT: s_endpgm 2532 %tid = call i32 @llvm.amdgcn.workitem.id.x() 2533 %tid.ext = sext i32 %tid to i64 2534 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 2535 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 2536 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 2537 %result = add <2 x i16> %x, <i16 undef, i16 -32> 2538 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 2539 ret void 2540} 2541 2542define amdgpu_kernel void @v_test_v2i16_x_add_neg32_undef(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 2543; SI-LABEL: v_test_v2i16_x_add_neg32_undef: 2544; SI: ; %bb.0: 2545; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 2546; SI-NEXT: s_mov_b32 s7, 0xf000 2547; SI-NEXT: s_mov_b32 s6, 0 2548; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2549; SI-NEXT: v_mov_b32_e32 v1, 0 2550; SI-NEXT: s_waitcnt lgkmcnt(0) 2551; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 2552; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 2553; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 2554; SI-NEXT: s_waitcnt vmcnt(0) 2555; SI-NEXT: v_subrev_i32_e32 v2, vcc, 32, v2 2556; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 2557; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 2558; SI-NEXT: s_endpgm 2559; 2560; VI-LABEL: v_test_v2i16_x_add_neg32_undef: 2561; VI: ; %bb.0: 2562; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2563; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2564; VI-NEXT: s_waitcnt lgkmcnt(0) 2565; VI-NEXT: v_mov_b32_e32 v1, s3 2566; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 2567; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2568; VI-NEXT: flat_load_dword v3, v[0:1] 2569; VI-NEXT: v_mov_b32_e32 v1, s1 2570; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 2571; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2572; VI-NEXT: s_waitcnt vmcnt(0) 2573; VI-NEXT: v_subrev_u16_e32 v2, 32, v3 2574; VI-NEXT: flat_store_dword v[0:1], v2 2575; VI-NEXT: s_endpgm 2576; 2577; GFX9-LABEL: v_test_v2i16_x_add_neg32_undef: 2578; GFX9: ; %bb.0: 2579; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2580; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2581; GFX9-NEXT: s_waitcnt lgkmcnt(0) 2582; GFX9-NEXT: global_load_dword v1, v0, s[2:3] 2583; GFX9-NEXT: s_waitcnt vmcnt(0) 2584; GFX9-NEXT: v_pk_sub_u16 v1, v1, 32 2585; GFX9-NEXT: global_store_dword v0, v1, s[0:1] 2586; GFX9-NEXT: s_endpgm 2587; 2588; GFX10-LABEL: v_test_v2i16_x_add_neg32_undef: 2589; GFX10: ; %bb.0: 2590; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2591; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2592; GFX10-NEXT: s_waitcnt lgkmcnt(0) 2593; GFX10-NEXT: global_load_dword v1, v0, s[2:3] 2594; GFX10-NEXT: s_waitcnt vmcnt(0) 2595; GFX10-NEXT: v_pk_sub_u16 v1, v1, 32 2596; GFX10-NEXT: global_store_dword v0, v1, s[0:1] 2597; GFX10-NEXT: s_endpgm 2598; 2599; GFX11-LABEL: v_test_v2i16_x_add_neg32_undef: 2600; GFX11: ; %bb.0: 2601; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 2602; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2603; GFX11-NEXT: s_waitcnt lgkmcnt(0) 2604; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] 2605; GFX11-NEXT: s_waitcnt vmcnt(0) 2606; GFX11-NEXT: v_pk_sub_u16 v1, v1, 32 2607; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] 2608; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) 2609; GFX11-NEXT: s_endpgm 2610 %tid = call i32 @llvm.amdgcn.workitem.id.x() 2611 %tid.ext = sext i32 %tid to i64 2612 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 2613 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 2614 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 2615 %result = add <2 x i16> %x, <i16 -32, i16 undef> 2616 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 2617 ret void 2618} 2619 2620declare i32 @llvm.amdgcn.workitem.id.x() #1 2621 2622attributes #0 = { nounwind } 2623attributes #1 = { nounwind readnone } 2624