1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,SI 3; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,VI 4; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,GFX9 5; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,GFX10 6 7; Test that add/sub with a constant is swapped to sub/add with negated 8; constant to minimize code size. 9 10define amdgpu_kernel void @v_test_i32_x_sub_64(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { 11; SI-LABEL: v_test_i32_x_sub_64: 12; SI: ; %bb.0: 13; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 14; SI-NEXT: s_mov_b32 s7, 0xf000 15; SI-NEXT: s_mov_b32 s6, 0 16; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 17; SI-NEXT: v_mov_b32_e32 v1, 0 18; SI-NEXT: s_waitcnt lgkmcnt(0) 19; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 20; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 21; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 22; SI-NEXT: s_waitcnt vmcnt(0) 23; SI-NEXT: v_subrev_i32_e32 v2, vcc, 64, v2 24; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 25; SI-NEXT: s_endpgm 26; 27; VI-LABEL: v_test_i32_x_sub_64: 28; VI: ; %bb.0: 29; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 30; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 31; VI-NEXT: s_waitcnt lgkmcnt(0) 32; VI-NEXT: v_mov_b32_e32 v1, s3 33; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 34; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 35; VI-NEXT: flat_load_dword v3, v[0:1] 36; VI-NEXT: v_mov_b32_e32 v1, s1 37; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 38; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 39; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 40; VI-NEXT: v_subrev_u32_e32 v2, vcc, 64, v3 41; VI-NEXT: flat_store_dword v[0:1], v2 42; VI-NEXT: s_endpgm 43; 44; GFX9-LABEL: v_test_i32_x_sub_64: 45; GFX9: ; %bb.0: 46; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 47; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 48; GFX9-NEXT: s_waitcnt lgkmcnt(0) 49; GFX9-NEXT: v_mov_b32_e32 v1, s3 50; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 51; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 52; GFX9-NEXT: global_load_dword v3, v[0:1], off 53; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 54; GFX9-NEXT: v_mov_b32_e32 v1, s1 55; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 56; GFX9-NEXT: s_waitcnt vmcnt(0) 57; GFX9-NEXT: v_subrev_u32_e32 v2, 64, v3 58; GFX9-NEXT: global_store_dword v[0:1], v2, off 59; GFX9-NEXT: s_endpgm 60; 61; GFX10-LABEL: v_test_i32_x_sub_64: 62; GFX10: ; %bb.0: 63; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 64; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 65; GFX10-NEXT: ; implicit-def: $vcc_hi 66; GFX10-NEXT: s_waitcnt lgkmcnt(0) 67; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 68; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 69; GFX10-NEXT: global_load_dword v3, v[0:1], off 70; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 71; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 72; GFX10-NEXT: s_waitcnt vmcnt(0) 73; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 64, v3 74; GFX10-NEXT: global_store_dword v[0:1], v2, off 75; GFX10-NEXT: s_endpgm 76 %tid = call i32 @llvm.amdgcn.workitem.id.x() 77 %tid.ext = sext i32 %tid to i64 78 %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %tid.ext 79 %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext 80 %x = load i32, i32 addrspace(1)* %gep 81 %result = sub i32 %x, 64 82 store i32 %result, i32 addrspace(1)* %gep.out 83 ret void 84} 85 86define amdgpu_kernel void @v_test_i32_x_sub_64_multi_use(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { 87; SI-LABEL: v_test_i32_x_sub_64_multi_use: 88; SI: ; %bb.0: 89; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 90; SI-NEXT: s_mov_b32 s7, 0xf000 91; SI-NEXT: s_mov_b32 s6, 0 92; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 93; SI-NEXT: v_mov_b32_e32 v1, 0 94; SI-NEXT: s_waitcnt lgkmcnt(0) 95; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 96; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 97; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 98; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 99; SI-NEXT: s_waitcnt vmcnt(1) 100; SI-NEXT: v_subrev_i32_e32 v2, vcc, 64, v2 101; SI-NEXT: s_waitcnt vmcnt(0) 102; SI-NEXT: v_subrev_i32_e32 v3, vcc, 64, v3 103; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 104; SI-NEXT: buffer_store_dword v3, v[0:1], s[0:3], 0 addr64 105; SI-NEXT: s_endpgm 106; 107; VI-LABEL: v_test_i32_x_sub_64_multi_use: 108; VI: ; %bb.0: 109; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 110; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 111; VI-NEXT: s_waitcnt lgkmcnt(0) 112; VI-NEXT: v_mov_b32_e32 v1, s3 113; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 114; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 115; VI-NEXT: flat_load_dword v4, v[0:1] 116; VI-NEXT: flat_load_dword v0, v[0:1] 117; VI-NEXT: v_mov_b32_e32 v3, s1 118; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 119; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc 120; VI-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1) 121; VI-NEXT: v_subrev_u32_e32 v1, vcc, 64, v4 122; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 123; VI-NEXT: v_subrev_u32_e32 v0, vcc, 64, v0 124; VI-NEXT: flat_store_dword v[2:3], v1 125; VI-NEXT: flat_store_dword v[2:3], v0 126; VI-NEXT: s_endpgm 127; 128; GFX9-LABEL: v_test_i32_x_sub_64_multi_use: 129; GFX9: ; %bb.0: 130; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 131; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 132; GFX9-NEXT: s_waitcnt lgkmcnt(0) 133; GFX9-NEXT: v_mov_b32_e32 v1, s3 134; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 135; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 136; GFX9-NEXT: global_load_dword v4, v[0:1], off 137; GFX9-NEXT: global_load_dword v0, v[0:1], off 138; GFX9-NEXT: v_mov_b32_e32 v3, s1 139; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2 140; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc 141; GFX9-NEXT: s_waitcnt vmcnt(1) 142; GFX9-NEXT: v_subrev_u32_e32 v1, 64, v4 143; GFX9-NEXT: s_waitcnt vmcnt(0) 144; GFX9-NEXT: v_subrev_u32_e32 v0, 64, v0 145; GFX9-NEXT: global_store_dword v[2:3], v1, off 146; GFX9-NEXT: global_store_dword v[2:3], v0, off 147; GFX9-NEXT: s_endpgm 148; 149; GFX10-LABEL: v_test_i32_x_sub_64_multi_use: 150; GFX10: ; %bb.0: 151; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 152; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 153; GFX10-NEXT: ; implicit-def: $vcc_hi 154; GFX10-NEXT: s_waitcnt lgkmcnt(0) 155; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 156; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 157; GFX10-NEXT: global_load_dword v3, v[0:1], off 158; GFX10-NEXT: global_load_dword v4, v[0:1], off 159; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 160; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 161; GFX10-NEXT: s_waitcnt vmcnt(1) 162; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 64, v3 163; GFX10-NEXT: s_waitcnt vmcnt(0) 164; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 64, v4 165; GFX10-NEXT: global_store_dword v[0:1], v2, off 166; GFX10-NEXT: global_store_dword v[0:1], v3, off 167; GFX10-NEXT: s_endpgm 168 %tid = call i32 @llvm.amdgcn.workitem.id.x() 169 %tid.ext = sext i32 %tid to i64 170 %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %tid.ext 171 %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext 172 %x = load volatile i32, i32 addrspace(1)* %gep 173 %y = load volatile i32, i32 addrspace(1)* %gep 174 %result0 = sub i32 %x, 64 175 %result1 = sub i32 %y, 64 176 store volatile i32 %result0, i32 addrspace(1)* %gep.out 177 store volatile i32 %result1, i32 addrspace(1)* %gep.out 178 ret void 179} 180 181define amdgpu_kernel void @v_test_i32_64_sub_x(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { 182; SI-LABEL: v_test_i32_64_sub_x: 183; SI: ; %bb.0: 184; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 185; SI-NEXT: s_mov_b32 s7, 0xf000 186; SI-NEXT: s_mov_b32 s6, 0 187; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 188; SI-NEXT: v_mov_b32_e32 v1, 0 189; SI-NEXT: s_waitcnt lgkmcnt(0) 190; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 191; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 192; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 193; SI-NEXT: s_waitcnt vmcnt(0) 194; SI-NEXT: v_sub_i32_e32 v2, vcc, 64, v2 195; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 196; SI-NEXT: s_endpgm 197; 198; VI-LABEL: v_test_i32_64_sub_x: 199; VI: ; %bb.0: 200; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 201; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 202; VI-NEXT: s_waitcnt lgkmcnt(0) 203; VI-NEXT: v_mov_b32_e32 v1, s3 204; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 205; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 206; VI-NEXT: flat_load_dword v3, v[0:1] 207; VI-NEXT: v_mov_b32_e32 v1, s1 208; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 209; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 210; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 211; VI-NEXT: v_sub_u32_e32 v2, vcc, 64, v3 212; VI-NEXT: flat_store_dword v[0:1], v2 213; VI-NEXT: s_endpgm 214; 215; GFX9-LABEL: v_test_i32_64_sub_x: 216; GFX9: ; %bb.0: 217; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 218; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 219; GFX9-NEXT: s_waitcnt lgkmcnt(0) 220; GFX9-NEXT: v_mov_b32_e32 v1, s3 221; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 222; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 223; GFX9-NEXT: global_load_dword v3, v[0:1], off 224; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 225; GFX9-NEXT: v_mov_b32_e32 v1, s1 226; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 227; GFX9-NEXT: s_waitcnt vmcnt(0) 228; GFX9-NEXT: v_sub_u32_e32 v2, 64, v3 229; GFX9-NEXT: global_store_dword v[0:1], v2, off 230; GFX9-NEXT: s_endpgm 231; 232; GFX10-LABEL: v_test_i32_64_sub_x: 233; GFX10: ; %bb.0: 234; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 235; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 236; GFX10-NEXT: ; implicit-def: $vcc_hi 237; GFX10-NEXT: s_waitcnt lgkmcnt(0) 238; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 239; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 240; GFX10-NEXT: global_load_dword v3, v[0:1], off 241; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 242; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 243; GFX10-NEXT: s_waitcnt vmcnt(0) 244; GFX10-NEXT: v_sub_nc_u32_e32 v2, 64, v3 245; GFX10-NEXT: global_store_dword v[0:1], v2, off 246; GFX10-NEXT: s_endpgm 247 %tid = call i32 @llvm.amdgcn.workitem.id.x() 248 %tid.ext = sext i32 %tid to i64 249 %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %tid.ext 250 %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext 251 %x = load i32, i32 addrspace(1)* %gep 252 %result = sub i32 64, %x 253 store i32 %result, i32 addrspace(1)* %gep.out 254 ret void 255} 256 257define amdgpu_kernel void @v_test_i32_x_sub_65(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { 258; SI-LABEL: v_test_i32_x_sub_65: 259; SI: ; %bb.0: 260; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 261; SI-NEXT: s_mov_b32 s7, 0xf000 262; SI-NEXT: s_mov_b32 s6, 0 263; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 264; SI-NEXT: v_mov_b32_e32 v1, 0 265; SI-NEXT: s_waitcnt lgkmcnt(0) 266; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 267; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 268; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 269; SI-NEXT: s_waitcnt vmcnt(0) 270; SI-NEXT: v_add_i32_e32 v2, vcc, 0xffffffbf, v2 271; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 272; SI-NEXT: s_endpgm 273; 274; VI-LABEL: v_test_i32_x_sub_65: 275; VI: ; %bb.0: 276; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 277; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 278; VI-NEXT: s_waitcnt lgkmcnt(0) 279; VI-NEXT: v_mov_b32_e32 v1, s3 280; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 281; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 282; VI-NEXT: flat_load_dword v3, v[0:1] 283; VI-NEXT: v_mov_b32_e32 v1, s1 284; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 285; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 286; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 287; VI-NEXT: v_add_u32_e32 v2, vcc, 0xffffffbf, v3 288; VI-NEXT: flat_store_dword v[0:1], v2 289; VI-NEXT: s_endpgm 290; 291; GFX9-LABEL: v_test_i32_x_sub_65: 292; GFX9: ; %bb.0: 293; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 294; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 295; GFX9-NEXT: s_waitcnt lgkmcnt(0) 296; GFX9-NEXT: v_mov_b32_e32 v1, s3 297; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 298; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 299; GFX9-NEXT: global_load_dword v3, v[0:1], off 300; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 301; GFX9-NEXT: v_mov_b32_e32 v1, s1 302; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 303; GFX9-NEXT: s_waitcnt vmcnt(0) 304; GFX9-NEXT: v_add_u32_e32 v2, 0xffffffbf, v3 305; GFX9-NEXT: global_store_dword v[0:1], v2, off 306; GFX9-NEXT: s_endpgm 307; 308; GFX10-LABEL: v_test_i32_x_sub_65: 309; GFX10: ; %bb.0: 310; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 311; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 312; GFX10-NEXT: ; implicit-def: $vcc_hi 313; GFX10-NEXT: s_waitcnt lgkmcnt(0) 314; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 315; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 316; GFX10-NEXT: global_load_dword v3, v[0:1], off 317; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 318; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 319; GFX10-NEXT: s_waitcnt vmcnt(0) 320; GFX10-NEXT: v_add_nc_u32_e32 v2, 0xffffffbf, v3 321; GFX10-NEXT: global_store_dword v[0:1], v2, off 322; GFX10-NEXT: s_endpgm 323 %tid = call i32 @llvm.amdgcn.workitem.id.x() 324 %tid.ext = sext i32 %tid to i64 325 %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %tid.ext 326 %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext 327 %x = load i32, i32 addrspace(1)* %gep 328 %result = sub i32 %x, 65 329 store i32 %result, i32 addrspace(1)* %gep.out 330 ret void 331} 332 333define amdgpu_kernel void @v_test_i32_65_sub_x(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { 334; SI-LABEL: v_test_i32_65_sub_x: 335; SI: ; %bb.0: 336; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 337; SI-NEXT: s_mov_b32 s7, 0xf000 338; SI-NEXT: s_mov_b32 s6, 0 339; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 340; SI-NEXT: v_mov_b32_e32 v1, 0 341; SI-NEXT: s_waitcnt lgkmcnt(0) 342; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 343; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 344; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 345; SI-NEXT: s_waitcnt vmcnt(0) 346; SI-NEXT: v_sub_i32_e32 v2, vcc, 0x41, v2 347; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 348; SI-NEXT: s_endpgm 349; 350; VI-LABEL: v_test_i32_65_sub_x: 351; VI: ; %bb.0: 352; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 353; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 354; VI-NEXT: s_waitcnt lgkmcnt(0) 355; VI-NEXT: v_mov_b32_e32 v1, s3 356; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 357; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 358; VI-NEXT: flat_load_dword v3, v[0:1] 359; VI-NEXT: v_mov_b32_e32 v1, s1 360; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 361; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 362; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 363; VI-NEXT: v_sub_u32_e32 v2, vcc, 0x41, v3 364; VI-NEXT: flat_store_dword v[0:1], v2 365; VI-NEXT: s_endpgm 366; 367; GFX9-LABEL: v_test_i32_65_sub_x: 368; GFX9: ; %bb.0: 369; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 370; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 371; GFX9-NEXT: s_waitcnt lgkmcnt(0) 372; GFX9-NEXT: v_mov_b32_e32 v1, s3 373; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 374; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 375; GFX9-NEXT: global_load_dword v3, v[0:1], off 376; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 377; GFX9-NEXT: v_mov_b32_e32 v1, s1 378; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 379; GFX9-NEXT: s_waitcnt vmcnt(0) 380; GFX9-NEXT: v_sub_u32_e32 v2, 0x41, v3 381; GFX9-NEXT: global_store_dword v[0:1], v2, off 382; GFX9-NEXT: s_endpgm 383; 384; GFX10-LABEL: v_test_i32_65_sub_x: 385; GFX10: ; %bb.0: 386; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 387; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 388; GFX10-NEXT: ; implicit-def: $vcc_hi 389; GFX10-NEXT: s_waitcnt lgkmcnt(0) 390; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 391; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 392; GFX10-NEXT: global_load_dword v3, v[0:1], off 393; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 394; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 395; GFX10-NEXT: s_waitcnt vmcnt(0) 396; GFX10-NEXT: v_sub_nc_u32_e32 v2, 0x41, v3 397; GFX10-NEXT: global_store_dword v[0:1], v2, off 398; GFX10-NEXT: s_endpgm 399 %tid = call i32 @llvm.amdgcn.workitem.id.x() 400 %tid.ext = sext i32 %tid to i64 401 %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %tid.ext 402 %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext 403 %x = load i32, i32 addrspace(1)* %gep 404 %result = sub i32 65, %x 405 store i32 %result, i32 addrspace(1)* %gep.out 406 ret void 407} 408 409define amdgpu_kernel void @v_test_i32_x_sub_neg16(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { 410; SI-LABEL: v_test_i32_x_sub_neg16: 411; SI: ; %bb.0: 412; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 413; SI-NEXT: s_mov_b32 s7, 0xf000 414; SI-NEXT: s_mov_b32 s6, 0 415; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 416; SI-NEXT: v_mov_b32_e32 v1, 0 417; SI-NEXT: s_waitcnt lgkmcnt(0) 418; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 419; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 420; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 421; SI-NEXT: s_waitcnt vmcnt(0) 422; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v2 423; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 424; SI-NEXT: s_endpgm 425; 426; VI-LABEL: v_test_i32_x_sub_neg16: 427; VI: ; %bb.0: 428; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 429; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 430; VI-NEXT: s_waitcnt lgkmcnt(0) 431; VI-NEXT: v_mov_b32_e32 v1, s3 432; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 433; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 434; VI-NEXT: flat_load_dword v3, v[0:1] 435; VI-NEXT: v_mov_b32_e32 v1, s1 436; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 437; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 438; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 439; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v3 440; VI-NEXT: flat_store_dword v[0:1], v2 441; VI-NEXT: s_endpgm 442; 443; GFX9-LABEL: v_test_i32_x_sub_neg16: 444; GFX9: ; %bb.0: 445; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 446; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 447; GFX9-NEXT: s_waitcnt lgkmcnt(0) 448; GFX9-NEXT: v_mov_b32_e32 v1, s3 449; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 450; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 451; GFX9-NEXT: global_load_dword v3, v[0:1], off 452; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 453; GFX9-NEXT: v_mov_b32_e32 v1, s1 454; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 455; GFX9-NEXT: s_waitcnt vmcnt(0) 456; GFX9-NEXT: v_add_u32_e32 v2, 16, v3 457; GFX9-NEXT: global_store_dword v[0:1], v2, off 458; GFX9-NEXT: s_endpgm 459; 460; GFX10-LABEL: v_test_i32_x_sub_neg16: 461; GFX10: ; %bb.0: 462; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 463; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 464; GFX10-NEXT: ; implicit-def: $vcc_hi 465; GFX10-NEXT: s_waitcnt lgkmcnt(0) 466; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 467; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 468; GFX10-NEXT: global_load_dword v3, v[0:1], off 469; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 470; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 471; GFX10-NEXT: s_waitcnt vmcnt(0) 472; GFX10-NEXT: v_add_nc_u32_e32 v2, 16, v3 473; GFX10-NEXT: global_store_dword v[0:1], v2, off 474; GFX10-NEXT: s_endpgm 475 %tid = call i32 @llvm.amdgcn.workitem.id.x() 476 %tid.ext = sext i32 %tid to i64 477 %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %tid.ext 478 %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext 479 %x = load i32, i32 addrspace(1)* %gep 480 %result = sub i32 %x, -16 481 store i32 %result, i32 addrspace(1)* %gep.out 482 ret void 483} 484 485define amdgpu_kernel void @v_test_i32_neg16_sub_x(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { 486; SI-LABEL: v_test_i32_neg16_sub_x: 487; SI: ; %bb.0: 488; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 489; SI-NEXT: s_mov_b32 s7, 0xf000 490; SI-NEXT: s_mov_b32 s6, 0 491; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 492; SI-NEXT: v_mov_b32_e32 v1, 0 493; SI-NEXT: s_waitcnt lgkmcnt(0) 494; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 495; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 496; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 497; SI-NEXT: s_waitcnt vmcnt(0) 498; SI-NEXT: v_sub_i32_e32 v2, vcc, -16, v2 499; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 500; SI-NEXT: s_endpgm 501; 502; VI-LABEL: v_test_i32_neg16_sub_x: 503; VI: ; %bb.0: 504; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 505; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 506; VI-NEXT: s_waitcnt lgkmcnt(0) 507; VI-NEXT: v_mov_b32_e32 v1, s3 508; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 509; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 510; VI-NEXT: flat_load_dword v3, v[0:1] 511; VI-NEXT: v_mov_b32_e32 v1, s1 512; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 513; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 514; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 515; VI-NEXT: v_sub_u32_e32 v2, vcc, -16, v3 516; VI-NEXT: flat_store_dword v[0:1], v2 517; VI-NEXT: s_endpgm 518; 519; GFX9-LABEL: v_test_i32_neg16_sub_x: 520; GFX9: ; %bb.0: 521; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 522; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 523; GFX9-NEXT: s_waitcnt lgkmcnt(0) 524; GFX9-NEXT: v_mov_b32_e32 v1, s3 525; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 526; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 527; GFX9-NEXT: global_load_dword v3, v[0:1], off 528; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 529; GFX9-NEXT: v_mov_b32_e32 v1, s1 530; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 531; GFX9-NEXT: s_waitcnt vmcnt(0) 532; GFX9-NEXT: v_sub_u32_e32 v2, -16, v3 533; GFX9-NEXT: global_store_dword v[0:1], v2, off 534; GFX9-NEXT: s_endpgm 535; 536; GFX10-LABEL: v_test_i32_neg16_sub_x: 537; GFX10: ; %bb.0: 538; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 539; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 540; GFX10-NEXT: ; implicit-def: $vcc_hi 541; GFX10-NEXT: s_waitcnt lgkmcnt(0) 542; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 543; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 544; GFX10-NEXT: global_load_dword v3, v[0:1], off 545; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 546; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 547; GFX10-NEXT: s_waitcnt vmcnt(0) 548; GFX10-NEXT: v_sub_nc_u32_e32 v2, -16, v3 549; GFX10-NEXT: global_store_dword v[0:1], v2, off 550; GFX10-NEXT: s_endpgm 551 %tid = call i32 @llvm.amdgcn.workitem.id.x() 552 %tid.ext = sext i32 %tid to i64 553 %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %tid.ext 554 %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext 555 %x = load i32, i32 addrspace(1)* %gep 556 %result = sub i32 -16, %x 557 store i32 %result, i32 addrspace(1)* %gep.out 558 ret void 559} 560 561define amdgpu_kernel void @v_test_i32_x_sub_neg17(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { 562; SI-LABEL: v_test_i32_x_sub_neg17: 563; SI: ; %bb.0: 564; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 565; SI-NEXT: s_mov_b32 s7, 0xf000 566; SI-NEXT: s_mov_b32 s6, 0 567; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 568; SI-NEXT: v_mov_b32_e32 v1, 0 569; SI-NEXT: s_waitcnt lgkmcnt(0) 570; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 571; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 572; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 573; SI-NEXT: s_waitcnt vmcnt(0) 574; SI-NEXT: v_add_i32_e32 v2, vcc, 17, v2 575; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 576; SI-NEXT: s_endpgm 577; 578; VI-LABEL: v_test_i32_x_sub_neg17: 579; VI: ; %bb.0: 580; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 581; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 582; VI-NEXT: s_waitcnt lgkmcnt(0) 583; VI-NEXT: v_mov_b32_e32 v1, s3 584; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 585; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 586; VI-NEXT: flat_load_dword v3, v[0:1] 587; VI-NEXT: v_mov_b32_e32 v1, s1 588; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 589; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 590; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 591; VI-NEXT: v_add_u32_e32 v2, vcc, 17, v3 592; VI-NEXT: flat_store_dword v[0:1], v2 593; VI-NEXT: s_endpgm 594; 595; GFX9-LABEL: v_test_i32_x_sub_neg17: 596; GFX9: ; %bb.0: 597; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 598; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 599; GFX9-NEXT: s_waitcnt lgkmcnt(0) 600; GFX9-NEXT: v_mov_b32_e32 v1, s3 601; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 602; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 603; GFX9-NEXT: global_load_dword v3, v[0:1], off 604; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 605; GFX9-NEXT: v_mov_b32_e32 v1, s1 606; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 607; GFX9-NEXT: s_waitcnt vmcnt(0) 608; GFX9-NEXT: v_add_u32_e32 v2, 17, v3 609; GFX9-NEXT: global_store_dword v[0:1], v2, off 610; GFX9-NEXT: s_endpgm 611; 612; GFX10-LABEL: v_test_i32_x_sub_neg17: 613; GFX10: ; %bb.0: 614; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 615; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 616; GFX10-NEXT: ; implicit-def: $vcc_hi 617; GFX10-NEXT: s_waitcnt lgkmcnt(0) 618; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 619; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 620; GFX10-NEXT: global_load_dword v3, v[0:1], off 621; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 622; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 623; GFX10-NEXT: s_waitcnt vmcnt(0) 624; GFX10-NEXT: v_add_nc_u32_e32 v2, 17, v3 625; GFX10-NEXT: global_store_dword v[0:1], v2, off 626; GFX10-NEXT: s_endpgm 627 %tid = call i32 @llvm.amdgcn.workitem.id.x() 628 %tid.ext = sext i32 %tid to i64 629 %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %tid.ext 630 %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext 631 %x = load i32, i32 addrspace(1)* %gep 632 %result = sub i32 %x, -17 633 store i32 %result, i32 addrspace(1)* %gep.out 634 ret void 635} 636 637define amdgpu_kernel void @v_test_i32_neg17_sub_x(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { 638; SI-LABEL: v_test_i32_neg17_sub_x: 639; SI: ; %bb.0: 640; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 641; SI-NEXT: s_mov_b32 s7, 0xf000 642; SI-NEXT: s_mov_b32 s6, 0 643; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 644; SI-NEXT: v_mov_b32_e32 v1, 0 645; SI-NEXT: s_waitcnt lgkmcnt(0) 646; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 647; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 648; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 649; SI-NEXT: s_waitcnt vmcnt(0) 650; SI-NEXT: v_sub_i32_e32 v2, vcc, 0xffffffef, v2 651; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 652; SI-NEXT: s_endpgm 653; 654; VI-LABEL: v_test_i32_neg17_sub_x: 655; VI: ; %bb.0: 656; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 657; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 658; VI-NEXT: s_waitcnt lgkmcnt(0) 659; VI-NEXT: v_mov_b32_e32 v1, s3 660; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 661; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 662; VI-NEXT: flat_load_dword v3, v[0:1] 663; VI-NEXT: v_mov_b32_e32 v1, s1 664; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 665; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 666; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 667; VI-NEXT: v_sub_u32_e32 v2, vcc, 0xffffffef, v3 668; VI-NEXT: flat_store_dword v[0:1], v2 669; VI-NEXT: s_endpgm 670; 671; GFX9-LABEL: v_test_i32_neg17_sub_x: 672; GFX9: ; %bb.0: 673; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 674; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 675; GFX9-NEXT: s_waitcnt lgkmcnt(0) 676; GFX9-NEXT: v_mov_b32_e32 v1, s3 677; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 678; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 679; GFX9-NEXT: global_load_dword v3, v[0:1], off 680; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 681; GFX9-NEXT: v_mov_b32_e32 v1, s1 682; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 683; GFX9-NEXT: s_waitcnt vmcnt(0) 684; GFX9-NEXT: v_sub_u32_e32 v2, 0xffffffef, v3 685; GFX9-NEXT: global_store_dword v[0:1], v2, off 686; GFX9-NEXT: s_endpgm 687; 688; GFX10-LABEL: v_test_i32_neg17_sub_x: 689; GFX10: ; %bb.0: 690; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 691; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 692; GFX10-NEXT: ; implicit-def: $vcc_hi 693; GFX10-NEXT: s_waitcnt lgkmcnt(0) 694; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 695; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 696; GFX10-NEXT: global_load_dword v3, v[0:1], off 697; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 698; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 699; GFX10-NEXT: s_waitcnt vmcnt(0) 700; GFX10-NEXT: v_sub_nc_u32_e32 v2, 0xffffffef, v3 701; GFX10-NEXT: global_store_dword v[0:1], v2, off 702; GFX10-NEXT: s_endpgm 703 %tid = call i32 @llvm.amdgcn.workitem.id.x() 704 %tid.ext = sext i32 %tid to i64 705 %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %tid.ext 706 %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext 707 %x = load i32, i32 addrspace(1)* %gep 708 %result = sub i32 -17, %x 709 store i32 %result, i32 addrspace(1)* %gep.out 710 ret void 711} 712 713define amdgpu_kernel void @s_test_i32_x_sub_64(i32 %x) #0 { 714; SI-LABEL: s_test_i32_x_sub_64: 715; SI: ; %bb.0: 716; SI-NEXT: s_load_dword s0, s[0:1], 0x9 717; SI-NEXT: s_waitcnt lgkmcnt(0) 718; SI-NEXT: s_sub_i32 s0, s0, 64 719; SI-NEXT: ;;#ASMSTART 720; SI-NEXT: ; use s0 721; SI-NEXT: ;;#ASMEND 722; SI-NEXT: s_endpgm 723; 724; VI-LABEL: s_test_i32_x_sub_64: 725; VI: ; %bb.0: 726; VI-NEXT: s_load_dword s0, s[0:1], 0x24 727; VI-NEXT: s_waitcnt lgkmcnt(0) 728; VI-NEXT: s_sub_i32 s0, s0, 64 729; VI-NEXT: ;;#ASMSTART 730; VI-NEXT: ; use s0 731; VI-NEXT: ;;#ASMEND 732; VI-NEXT: s_endpgm 733; 734; GFX9-LABEL: s_test_i32_x_sub_64: 735; GFX9: ; %bb.0: 736; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24 737; GFX9-NEXT: s_waitcnt lgkmcnt(0) 738; GFX9-NEXT: s_sub_i32 s0, s0, 64 739; GFX9-NEXT: ;;#ASMSTART 740; GFX9-NEXT: ; use s0 741; GFX9-NEXT: ;;#ASMEND 742; GFX9-NEXT: s_endpgm 743; 744; GFX10-LABEL: s_test_i32_x_sub_64: 745; GFX10: ; %bb.0: 746; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24 747; GFX10-NEXT: ; implicit-def: $vcc_hi 748; GFX10-NEXT: s_waitcnt lgkmcnt(0) 749; GFX10-NEXT: s_sub_i32 s0, s0, 64 750; GFX10-NEXT: ;;#ASMSTART 751; GFX10-NEXT: ; use s0 752; GFX10-NEXT: ;;#ASMEND 753; GFX10-NEXT: s_endpgm 754 %result = sub i32 %x, 64 755 call void asm sideeffect "; use $0", "s"(i32 %result) 756 ret void 757} 758 759define amdgpu_kernel void @v_test_i16_x_sub_64(i16 addrspace(1)* %out, i16 addrspace(1)* %in) #0 { 760; SI-LABEL: v_test_i16_x_sub_64: 761; SI: ; %bb.0: 762; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 763; SI-NEXT: s_mov_b32 s7, 0xf000 764; SI-NEXT: s_mov_b32 s6, 0 765; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0 766; SI-NEXT: v_mov_b32_e32 v1, 0 767; SI-NEXT: s_waitcnt lgkmcnt(0) 768; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 769; SI-NEXT: buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 770; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 771; SI-NEXT: s_waitcnt vmcnt(0) 772; SI-NEXT: v_subrev_i32_e32 v2, vcc, 64, v2 773; SI-NEXT: buffer_store_short v2, v[0:1], s[0:3], 0 addr64 774; SI-NEXT: s_endpgm 775; 776; VI-LABEL: v_test_i16_x_sub_64: 777; VI: ; %bb.0: 778; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 779; VI-NEXT: v_lshlrev_b32_e32 v2, 1, v0 780; VI-NEXT: s_waitcnt lgkmcnt(0) 781; VI-NEXT: v_mov_b32_e32 v1, s3 782; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 783; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 784; VI-NEXT: flat_load_ushort v3, v[0:1] 785; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 786; VI-NEXT: v_mov_b32_e32 v1, s1 787; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 788; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 789; VI-NEXT: v_subrev_u16_e32 v2, 64, v3 790; VI-NEXT: flat_store_short v[0:1], v2 791; VI-NEXT: s_endpgm 792; 793; GFX9-LABEL: v_test_i16_x_sub_64: 794; GFX9: ; %bb.0: 795; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 796; GFX9-NEXT: v_lshlrev_b32_e32 v2, 1, v0 797; GFX9-NEXT: s_waitcnt lgkmcnt(0) 798; GFX9-NEXT: v_mov_b32_e32 v1, s3 799; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 800; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 801; GFX9-NEXT: global_load_ushort v3, v[0:1], off 802; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 803; GFX9-NEXT: v_mov_b32_e32 v1, s1 804; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 805; GFX9-NEXT: s_waitcnt vmcnt(0) 806; GFX9-NEXT: v_subrev_u16_e32 v2, 64, v3 807; GFX9-NEXT: global_store_short v[0:1], v2, off 808; GFX9-NEXT: s_endpgm 809; 810; GFX10-LABEL: v_test_i16_x_sub_64: 811; GFX10: ; %bb.0: 812; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 813; GFX10-NEXT: v_lshlrev_b32_e32 v2, 1, v0 814; GFX10-NEXT: ; implicit-def: $vcc_hi 815; GFX10-NEXT: s_waitcnt lgkmcnt(0) 816; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 817; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 818; GFX10-NEXT: global_load_ushort v3, v[0:1], off 819; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 820; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 821; GFX10-NEXT: s_waitcnt vmcnt(0) 822; GFX10-NEXT: v_sub_nc_u16_e64 v2, v3, 64 823; GFX10-NEXT: global_store_short v[0:1], v2, off 824; GFX10-NEXT: s_endpgm 825 %tid = call i32 @llvm.amdgcn.workitem.id.x() 826 %tid.ext = sext i32 %tid to i64 827 %gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i64 %tid.ext 828 %gep.out = getelementptr inbounds i16, i16 addrspace(1)* %out, i64 %tid.ext 829 %x = load i16, i16 addrspace(1)* %gep 830 %result = sub i16 %x, 64 831 store i16 %result, i16 addrspace(1)* %gep.out 832 ret void 833} 834 835define amdgpu_kernel void @v_test_i16_x_sub_64_zext_to_i32(i32 addrspace(1)* %out, i16 addrspace(1)* %in) #0 { 836; SI-LABEL: v_test_i16_x_sub_64_zext_to_i32: 837; SI: ; %bb.0: 838; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 839; SI-NEXT: s_mov_b32 s7, 0xf000 840; SI-NEXT: s_mov_b32 s6, 0 841; SI-NEXT: v_lshlrev_b32_e32 v1, 1, v0 842; SI-NEXT: v_mov_b32_e32 v2, 0 843; SI-NEXT: s_waitcnt lgkmcnt(0) 844; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 845; SI-NEXT: buffer_load_ushort v3, v[1:2], s[4:7], 0 addr64 846; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 847; SI-NEXT: v_lshlrev_b32_e32 v1, 2, v0 848; SI-NEXT: s_waitcnt vmcnt(0) 849; SI-NEXT: v_subrev_i32_e32 v0, vcc, 64, v3 850; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0 851; SI-NEXT: buffer_store_dword v0, v[1:2], s[0:3], 0 addr64 852; SI-NEXT: s_endpgm 853; 854; VI-LABEL: v_test_i16_x_sub_64_zext_to_i32: 855; VI: ; %bb.0: 856; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 857; VI-NEXT: v_lshlrev_b32_e32 v1, 1, v0 858; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 859; VI-NEXT: s_waitcnt lgkmcnt(0) 860; VI-NEXT: v_mov_b32_e32 v3, s3 861; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v1 862; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc 863; VI-NEXT: flat_load_ushort v3, v[0:1] 864; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 865; VI-NEXT: v_mov_b32_e32 v1, s1 866; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 867; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 868; VI-NEXT: v_subrev_u16_e32 v2, 64, v3 869; VI-NEXT: flat_store_dword v[0:1], v2 870; VI-NEXT: s_endpgm 871; 872; GFX9-LABEL: v_test_i16_x_sub_64_zext_to_i32: 873; GFX9: ; %bb.0: 874; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 875; GFX9-NEXT: v_lshlrev_b32_e32 v1, 1, v0 876; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 877; GFX9-NEXT: s_waitcnt lgkmcnt(0) 878; GFX9-NEXT: v_mov_b32_e32 v3, s3 879; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v1 880; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc 881; GFX9-NEXT: global_load_ushort v3, v[0:1], off 882; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 883; GFX9-NEXT: v_mov_b32_e32 v1, s1 884; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 885; GFX9-NEXT: s_waitcnt vmcnt(0) 886; GFX9-NEXT: v_subrev_u16_e32 v2, 64, v3 887; GFX9-NEXT: global_store_dword v[0:1], v2, off 888; GFX9-NEXT: s_endpgm 889; 890; GFX10-LABEL: v_test_i16_x_sub_64_zext_to_i32: 891; GFX10: ; %bb.0: 892; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 893; GFX10-NEXT: v_lshlrev_b32_e32 v1, 1, v0 894; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 895; GFX10-NEXT: ; implicit-def: $vcc_hi 896; GFX10-NEXT: s_waitcnt lgkmcnt(0) 897; GFX10-NEXT: v_add_co_u32_e64 v1, s2, s2, v1 898; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v0 899; GFX10-NEXT: v_add_co_ci_u32_e64 v2, s2, s3, 0, s2 900; GFX10-NEXT: global_load_ushort v1, v[1:2], off 901; GFX10-NEXT: s_waitcnt vmcnt(0) 902; GFX10-NEXT: v_sub_nc_u16_e64 v2, v1, 64 903; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 904; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v2 905; GFX10-NEXT: global_store_dword v[0:1], v2, off 906; GFX10-NEXT: s_endpgm 907 %tid = call i32 @llvm.amdgcn.workitem.id.x() 908 %tid.ext = sext i32 %tid to i64 909 %gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i64 %tid.ext 910 %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext 911 %x = load i16, i16 addrspace(1)* %gep 912 %result = sub i16 %x, 64 913 %zext = zext i16 %result to i32 914 store i32 %zext, i32 addrspace(1)* %gep.out 915 ret void 916} 917 918define amdgpu_kernel void @v_test_i16_x_sub_64_multi_use(i16 addrspace(1)* %out, i16 addrspace(1)* %in) #0 { 919; SI-LABEL: v_test_i16_x_sub_64_multi_use: 920; SI: ; %bb.0: 921; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 922; SI-NEXT: s_mov_b32 s7, 0xf000 923; SI-NEXT: s_mov_b32 s6, 0 924; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0 925; SI-NEXT: v_mov_b32_e32 v1, 0 926; SI-NEXT: s_waitcnt lgkmcnt(0) 927; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 928; SI-NEXT: buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 929; SI-NEXT: buffer_load_ushort v3, v[0:1], s[4:7], 0 addr64 930; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 931; SI-NEXT: s_waitcnt vmcnt(1) 932; SI-NEXT: v_subrev_i32_e32 v2, vcc, 64, v2 933; SI-NEXT: s_waitcnt vmcnt(0) 934; SI-NEXT: v_subrev_i32_e32 v3, vcc, 64, v3 935; SI-NEXT: buffer_store_short v2, v[0:1], s[0:3], 0 addr64 936; SI-NEXT: buffer_store_short v3, v[0:1], s[0:3], 0 addr64 937; SI-NEXT: s_endpgm 938; 939; VI-LABEL: v_test_i16_x_sub_64_multi_use: 940; VI: ; %bb.0: 941; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 942; VI-NEXT: v_lshlrev_b32_e32 v2, 1, v0 943; VI-NEXT: s_waitcnt lgkmcnt(0) 944; VI-NEXT: v_mov_b32_e32 v1, s3 945; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 946; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 947; VI-NEXT: flat_load_ushort v4, v[0:1] 948; VI-NEXT: flat_load_ushort v0, v[0:1] 949; VI-NEXT: v_mov_b32_e32 v3, s1 950; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 951; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc 952; VI-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1) 953; VI-NEXT: v_subrev_u16_e32 v1, 64, v4 954; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 955; VI-NEXT: v_subrev_u16_e32 v0, 64, v0 956; VI-NEXT: flat_store_short v[2:3], v1 957; VI-NEXT: flat_store_short v[2:3], v0 958; VI-NEXT: s_endpgm 959; 960; GFX9-LABEL: v_test_i16_x_sub_64_multi_use: 961; GFX9: ; %bb.0: 962; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 963; GFX9-NEXT: v_lshlrev_b32_e32 v2, 1, v0 964; GFX9-NEXT: s_waitcnt lgkmcnt(0) 965; GFX9-NEXT: v_mov_b32_e32 v1, s3 966; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 967; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 968; GFX9-NEXT: global_load_ushort v4, v[0:1], off 969; GFX9-NEXT: global_load_ushort v0, v[0:1], off 970; GFX9-NEXT: v_mov_b32_e32 v3, s1 971; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2 972; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc 973; GFX9-NEXT: s_waitcnt vmcnt(1) 974; GFX9-NEXT: v_subrev_u16_e32 v1, 64, v4 975; GFX9-NEXT: s_waitcnt vmcnt(0) 976; GFX9-NEXT: v_subrev_u16_e32 v0, 64, v0 977; GFX9-NEXT: global_store_short v[2:3], v1, off 978; GFX9-NEXT: global_store_short v[2:3], v0, off 979; GFX9-NEXT: s_endpgm 980; 981; GFX10-LABEL: v_test_i16_x_sub_64_multi_use: 982; GFX10: ; %bb.0: 983; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 984; GFX10-NEXT: v_lshlrev_b32_e32 v2, 1, v0 985; GFX10-NEXT: ; implicit-def: $vcc_hi 986; GFX10-NEXT: s_waitcnt lgkmcnt(0) 987; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 988; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 989; GFX10-NEXT: global_load_ushort v3, v[0:1], off 990; GFX10-NEXT: global_load_ushort v4, v[0:1], off 991; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 992; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 993; GFX10-NEXT: s_waitcnt vmcnt(1) 994; GFX10-NEXT: v_sub_nc_u16_e64 v2, v3, 64 995; GFX10-NEXT: s_waitcnt vmcnt(0) 996; GFX10-NEXT: v_sub_nc_u16_e64 v3, v4, 64 997; GFX10-NEXT: global_store_short v[0:1], v2, off 998; GFX10-NEXT: global_store_short v[0:1], v3, off 999; GFX10-NEXT: s_endpgm 1000 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1001 %tid.ext = sext i32 %tid to i64 1002 %gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i64 %tid.ext 1003 %gep.out = getelementptr inbounds i16, i16 addrspace(1)* %out, i64 %tid.ext 1004 %x = load volatile i16, i16 addrspace(1)* %gep 1005 %y = load volatile i16, i16 addrspace(1)* %gep 1006 %result0 = sub i16 %x, 64 1007 %result1 = sub i16 %y, 64 1008 store volatile i16 %result0, i16 addrspace(1)* %gep.out 1009 store volatile i16 %result1, i16 addrspace(1)* %gep.out 1010 ret void 1011} 1012 1013define amdgpu_kernel void @v_test_v2i16_x_sub_64_64(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1014; SI-LABEL: v_test_v2i16_x_sub_64_64: 1015; SI: ; %bb.0: 1016; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1017; SI-NEXT: s_mov_b32 s7, 0xf000 1018; SI-NEXT: s_mov_b32 s6, 0 1019; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1020; SI-NEXT: v_mov_b32_e32 v1, 0 1021; SI-NEXT: s_waitcnt lgkmcnt(0) 1022; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1023; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1024; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1025; SI-NEXT: s_waitcnt vmcnt(0) 1026; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 1027; SI-NEXT: v_subrev_i32_e32 v2, vcc, 64, v2 1028; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 1029; SI-NEXT: v_or_b32_e32 v2, v3, v2 1030; SI-NEXT: v_add_i32_e32 v2, vcc, 0xffc00000, v2 1031; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 1032; SI-NEXT: s_endpgm 1033; 1034; VI-LABEL: v_test_v2i16_x_sub_64_64: 1035; VI: ; %bb.0: 1036; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1037; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1038; VI-NEXT: v_mov_b32_e32 v3, 64 1039; VI-NEXT: s_waitcnt lgkmcnt(0) 1040; VI-NEXT: v_mov_b32_e32 v1, s3 1041; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 1042; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1043; VI-NEXT: flat_load_dword v4, v[0:1] 1044; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 1045; VI-NEXT: v_mov_b32_e32 v1, s1 1046; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1047; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 1048; VI-NEXT: v_sub_u16_sdwa v2, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1049; VI-NEXT: v_subrev_u16_e32 v3, 64, v4 1050; VI-NEXT: v_or_b32_e32 v2, v3, v2 1051; VI-NEXT: flat_store_dword v[0:1], v2 1052; VI-NEXT: s_endpgm 1053; 1054; GFX9-LABEL: v_test_v2i16_x_sub_64_64: 1055; GFX9: ; %bb.0: 1056; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1057; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1058; GFX9-NEXT: s_waitcnt lgkmcnt(0) 1059; GFX9-NEXT: v_mov_b32_e32 v1, s3 1060; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 1061; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 1062; GFX9-NEXT: global_load_dword v3, v[0:1], off 1063; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 1064; GFX9-NEXT: v_mov_b32_e32 v1, s1 1065; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 1066; GFX9-NEXT: s_waitcnt vmcnt(0) 1067; GFX9-NEXT: v_pk_sub_i16 v2, v3, 64 op_sel_hi:[1,0] 1068; GFX9-NEXT: global_store_dword v[0:1], v2, off 1069; GFX9-NEXT: s_endpgm 1070; 1071; GFX10-LABEL: v_test_v2i16_x_sub_64_64: 1072; GFX10: ; %bb.0: 1073; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1074; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1075; GFX10-NEXT: ; implicit-def: $vcc_hi 1076; GFX10-NEXT: s_waitcnt lgkmcnt(0) 1077; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 1078; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 1079; GFX10-NEXT: global_load_dword v3, v[0:1], off 1080; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 1081; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 1082; GFX10-NEXT: s_waitcnt vmcnt(0) 1083; GFX10-NEXT: v_pk_sub_i16 v2, v3, 64 op_sel_hi:[1,0] 1084; GFX10-NEXT: global_store_dword v[0:1], v2, off 1085; GFX10-NEXT: s_endpgm 1086 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1087 %tid.ext = sext i32 %tid to i64 1088 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 1089 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 1090 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 1091 %result = sub <2 x i16> %x, <i16 64, i16 64> 1092 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 1093 ret void 1094} 1095 1096define amdgpu_kernel void @v_test_v2i16_x_sub_7_64(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1097; SI-LABEL: v_test_v2i16_x_sub_7_64: 1098; SI: ; %bb.0: 1099; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1100; SI-NEXT: s_mov_b32 s7, 0xf000 1101; SI-NEXT: s_mov_b32 s6, 0 1102; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1103; SI-NEXT: v_mov_b32_e32 v1, 0 1104; SI-NEXT: s_waitcnt lgkmcnt(0) 1105; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1106; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1107; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1108; SI-NEXT: s_waitcnt vmcnt(0) 1109; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 1110; SI-NEXT: v_add_i32_e32 v2, vcc, -7, v2 1111; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 1112; SI-NEXT: v_or_b32_e32 v2, v3, v2 1113; SI-NEXT: v_add_i32_e32 v2, vcc, 0xffc00000, v2 1114; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 1115; SI-NEXT: s_endpgm 1116; 1117; VI-LABEL: v_test_v2i16_x_sub_7_64: 1118; VI: ; %bb.0: 1119; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1120; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1121; VI-NEXT: v_mov_b32_e32 v3, 64 1122; VI-NEXT: s_waitcnt lgkmcnt(0) 1123; VI-NEXT: v_mov_b32_e32 v1, s3 1124; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 1125; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1126; VI-NEXT: flat_load_dword v4, v[0:1] 1127; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 1128; VI-NEXT: v_mov_b32_e32 v1, s1 1129; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1130; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 1131; VI-NEXT: v_add_u16_e32 v2, -7, v4 1132; VI-NEXT: v_sub_u16_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1133; VI-NEXT: v_or_b32_e32 v2, v2, v3 1134; VI-NEXT: flat_store_dword v[0:1], v2 1135; VI-NEXT: s_endpgm 1136; 1137; GFX9-LABEL: v_test_v2i16_x_sub_7_64: 1138; GFX9: ; %bb.0: 1139; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1140; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1141; GFX9-NEXT: s_mov_b32 s4, 0x400007 1142; GFX9-NEXT: s_waitcnt lgkmcnt(0) 1143; GFX9-NEXT: v_mov_b32_e32 v1, s3 1144; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 1145; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 1146; GFX9-NEXT: global_load_dword v3, v[0:1], off 1147; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 1148; GFX9-NEXT: v_mov_b32_e32 v1, s1 1149; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 1150; GFX9-NEXT: s_waitcnt vmcnt(0) 1151; GFX9-NEXT: v_pk_sub_i16 v2, v3, s4 1152; GFX9-NEXT: global_store_dword v[0:1], v2, off 1153; GFX9-NEXT: s_endpgm 1154; 1155; GFX10-LABEL: v_test_v2i16_x_sub_7_64: 1156; GFX10: ; %bb.0: 1157; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1158; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1159; GFX10-NEXT: ; implicit-def: $vcc_hi 1160; GFX10-NEXT: s_waitcnt lgkmcnt(0) 1161; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 1162; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 1163; GFX10-NEXT: global_load_dword v3, v[0:1], off 1164; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 1165; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 1166; GFX10-NEXT: s_waitcnt vmcnt(0) 1167; GFX10-NEXT: v_pk_sub_i16 v2, v3, 7 op_sel_hi:[1,0] 1168; GFX10-NEXT: global_store_dword v[0:1], v2, off 1169; GFX10-NEXT: s_endpgm 1170 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1171 %tid.ext = sext i32 %tid to i64 1172 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 1173 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 1174 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 1175 %result = sub <2 x i16> %x, <i16 7, i16 64> 1176 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 1177 ret void 1178} 1179 1180define amdgpu_kernel void @v_test_v2i16_x_sub_64_123(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1181; SI-LABEL: v_test_v2i16_x_sub_64_123: 1182; SI: ; %bb.0: 1183; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1184; SI-NEXT: s_mov_b32 s7, 0xf000 1185; SI-NEXT: s_mov_b32 s6, 0 1186; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1187; SI-NEXT: v_mov_b32_e32 v1, 0 1188; SI-NEXT: s_waitcnt lgkmcnt(0) 1189; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1190; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1191; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1192; SI-NEXT: s_waitcnt vmcnt(0) 1193; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 1194; SI-NEXT: v_subrev_i32_e32 v2, vcc, 64, v2 1195; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 1196; SI-NEXT: v_or_b32_e32 v2, v3, v2 1197; SI-NEXT: v_add_i32_e32 v2, vcc, 0xff850000, v2 1198; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 1199; SI-NEXT: s_endpgm 1200; 1201; VI-LABEL: v_test_v2i16_x_sub_64_123: 1202; VI: ; %bb.0: 1203; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1204; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1205; VI-NEXT: v_mov_b32_e32 v3, 0xffffff85 1206; VI-NEXT: s_waitcnt lgkmcnt(0) 1207; VI-NEXT: v_mov_b32_e32 v1, s3 1208; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 1209; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1210; VI-NEXT: flat_load_dword v4, v[0:1] 1211; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 1212; VI-NEXT: v_mov_b32_e32 v1, s1 1213; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1214; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 1215; VI-NEXT: v_add_u16_sdwa v2, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1216; VI-NEXT: v_subrev_u16_e32 v3, 64, v4 1217; VI-NEXT: v_or_b32_e32 v2, v3, v2 1218; VI-NEXT: flat_store_dword v[0:1], v2 1219; VI-NEXT: s_endpgm 1220; 1221; GFX9-LABEL: v_test_v2i16_x_sub_64_123: 1222; GFX9: ; %bb.0: 1223; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1224; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1225; GFX9-NEXT: s_mov_b32 s4, 0x7b0040 1226; GFX9-NEXT: s_waitcnt lgkmcnt(0) 1227; GFX9-NEXT: v_mov_b32_e32 v1, s3 1228; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 1229; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 1230; GFX9-NEXT: global_load_dword v3, v[0:1], off 1231; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 1232; GFX9-NEXT: v_mov_b32_e32 v1, s1 1233; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 1234; GFX9-NEXT: s_waitcnt vmcnt(0) 1235; GFX9-NEXT: v_pk_sub_i16 v2, v3, s4 1236; GFX9-NEXT: global_store_dword v[0:1], v2, off 1237; GFX9-NEXT: s_endpgm 1238; 1239; GFX10-LABEL: v_test_v2i16_x_sub_64_123: 1240; GFX10: ; %bb.0: 1241; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1242; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1243; GFX10-NEXT: ; implicit-def: $vcc_hi 1244; GFX10-NEXT: s_waitcnt lgkmcnt(0) 1245; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 1246; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 1247; GFX10-NEXT: global_load_dword v3, v[0:1], off 1248; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 1249; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 1250; GFX10-NEXT: s_waitcnt vmcnt(0) 1251; GFX10-NEXT: v_pk_sub_i16 v2, v3, 64 op_sel_hi:[1,0] 1252; GFX10-NEXT: global_store_dword v[0:1], v2, off 1253; GFX10-NEXT: s_endpgm 1254 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1255 %tid.ext = sext i32 %tid to i64 1256 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 1257 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 1258 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 1259 %result = sub <2 x i16> %x, <i16 64, i16 123> 1260 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 1261 ret void 1262} 1263 1264; Can fold 0 and inline immediate in other half. 1265define amdgpu_kernel void @v_test_v2i16_x_sub_7_0(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1266; SI-LABEL: v_test_v2i16_x_sub_7_0: 1267; SI: ; %bb.0: 1268; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1269; SI-NEXT: s_mov_b32 s7, 0xf000 1270; SI-NEXT: s_mov_b32 s6, 0 1271; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1272; SI-NEXT: v_mov_b32_e32 v1, 0 1273; SI-NEXT: s_waitcnt lgkmcnt(0) 1274; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1275; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1276; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1277; SI-NEXT: s_waitcnt vmcnt(0) 1278; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 1279; SI-NEXT: v_add_i32_e32 v2, vcc, -7, v2 1280; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 1281; SI-NEXT: v_or_b32_e32 v2, v2, v3 1282; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 1283; SI-NEXT: s_endpgm 1284; 1285; VI-LABEL: v_test_v2i16_x_sub_7_0: 1286; VI: ; %bb.0: 1287; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1288; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1289; VI-NEXT: s_waitcnt lgkmcnt(0) 1290; VI-NEXT: v_mov_b32_e32 v1, s3 1291; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 1292; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1293; VI-NEXT: flat_load_dword v3, v[0:1] 1294; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 1295; VI-NEXT: v_mov_b32_e32 v1, s1 1296; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1297; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 1298; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 1299; VI-NEXT: v_add_u16_e32 v3, -7, v3 1300; VI-NEXT: v_or_b32_e32 v2, v3, v2 1301; VI-NEXT: flat_store_dword v[0:1], v2 1302; VI-NEXT: s_endpgm 1303; 1304; GFX9-LABEL: v_test_v2i16_x_sub_7_0: 1305; GFX9: ; %bb.0: 1306; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1307; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1308; GFX9-NEXT: s_waitcnt lgkmcnt(0) 1309; GFX9-NEXT: v_mov_b32_e32 v1, s3 1310; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 1311; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 1312; GFX9-NEXT: global_load_dword v3, v[0:1], off 1313; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 1314; GFX9-NEXT: v_mov_b32_e32 v1, s1 1315; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 1316; GFX9-NEXT: s_waitcnt vmcnt(0) 1317; GFX9-NEXT: v_pk_sub_i16 v2, v3, 7 1318; GFX9-NEXT: global_store_dword v[0:1], v2, off 1319; GFX9-NEXT: s_endpgm 1320; 1321; GFX10-LABEL: v_test_v2i16_x_sub_7_0: 1322; GFX10: ; %bb.0: 1323; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1324; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1325; GFX10-NEXT: ; implicit-def: $vcc_hi 1326; GFX10-NEXT: s_waitcnt lgkmcnt(0) 1327; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 1328; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 1329; GFX10-NEXT: global_load_dword v3, v[0:1], off 1330; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 1331; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 1332; GFX10-NEXT: s_waitcnt vmcnt(0) 1333; GFX10-NEXT: v_pk_sub_i16 v2, v3, 7 1334; GFX10-NEXT: global_store_dword v[0:1], v2, off 1335; GFX10-NEXT: s_endpgm 1336 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1337 %tid.ext = sext i32 %tid to i64 1338 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 1339 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 1340 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 1341 %result = sub <2 x i16> %x, <i16 7, i16 0> 1342 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 1343 ret void 1344} 1345 1346; Can fold 0 and inline immediate in other half. 1347define amdgpu_kernel void @v_test_v2i16_x_sub_0_16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1348; SI-LABEL: v_test_v2i16_x_sub_0_16: 1349; SI: ; %bb.0: 1350; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1351; SI-NEXT: s_mov_b32 s7, 0xf000 1352; SI-NEXT: s_mov_b32 s6, 0 1353; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1354; SI-NEXT: v_mov_b32_e32 v1, 0 1355; SI-NEXT: s_waitcnt lgkmcnt(0) 1356; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1357; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1358; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1359; SI-NEXT: s_waitcnt vmcnt(0) 1360; SI-NEXT: v_add_i32_e32 v2, vcc, 0xfff00000, v2 1361; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 1362; SI-NEXT: s_endpgm 1363; 1364; VI-LABEL: v_test_v2i16_x_sub_0_16: 1365; VI: ; %bb.0: 1366; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1367; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1368; VI-NEXT: v_mov_b32_e32 v3, -16 1369; VI-NEXT: s_waitcnt lgkmcnt(0) 1370; VI-NEXT: v_mov_b32_e32 v1, s3 1371; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 1372; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1373; VI-NEXT: flat_load_dword v4, v[0:1] 1374; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 1375; VI-NEXT: v_mov_b32_e32 v1, s1 1376; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1377; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 1378; VI-NEXT: v_add_u16_sdwa v2, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1379; VI-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1380; VI-NEXT: flat_store_dword v[0:1], v2 1381; VI-NEXT: s_endpgm 1382; 1383; GFX9-LABEL: v_test_v2i16_x_sub_0_16: 1384; GFX9: ; %bb.0: 1385; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1386; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1387; GFX9-NEXT: s_waitcnt lgkmcnt(0) 1388; GFX9-NEXT: v_mov_b32_e32 v1, s3 1389; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 1390; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 1391; GFX9-NEXT: global_load_dword v3, v[0:1], off 1392; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 1393; GFX9-NEXT: v_mov_b32_e32 v1, s1 1394; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 1395; GFX9-NEXT: s_waitcnt vmcnt(0) 1396; GFX9-NEXT: v_pk_sub_i16 v2, v3, 16 op_sel:[0,1] op_sel_hi:[1,0] 1397; GFX9-NEXT: global_store_dword v[0:1], v2, off 1398; GFX9-NEXT: s_endpgm 1399; 1400; GFX10-LABEL: v_test_v2i16_x_sub_0_16: 1401; GFX10: ; %bb.0: 1402; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1403; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1404; GFX10-NEXT: ; implicit-def: $vcc_hi 1405; GFX10-NEXT: s_waitcnt lgkmcnt(0) 1406; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 1407; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 1408; GFX10-NEXT: global_load_dword v3, v[0:1], off 1409; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 1410; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 1411; GFX10-NEXT: s_waitcnt vmcnt(0) 1412; GFX10-NEXT: v_pk_sub_i16 v2, v3, 16 op_sel:[0,1] op_sel_hi:[1,0] 1413; GFX10-NEXT: global_store_dword v[0:1], v2, off 1414; GFX10-NEXT: s_endpgm 1415 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1416 %tid.ext = sext i32 %tid to i64 1417 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 1418 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 1419 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 1420 %result = sub <2 x i16> %x, <i16 0, i16 16> 1421 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 1422 ret void 1423} 1424 1425define amdgpu_kernel void @v_test_v2i16_x_sub_0_1_0(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1426; SI-LABEL: v_test_v2i16_x_sub_0_1_0: 1427; SI: ; %bb.0: 1428; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1429; SI-NEXT: s_mov_b32 s7, 0xf000 1430; SI-NEXT: s_mov_b32 s6, 0 1431; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1432; SI-NEXT: v_mov_b32_e32 v1, 0 1433; SI-NEXT: s_waitcnt lgkmcnt(0) 1434; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1435; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1436; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1437; SI-NEXT: s_waitcnt vmcnt(0) 1438; SI-NEXT: v_add_i32_e32 v2, vcc, 0x3c000000, v2 1439; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 1440; SI-NEXT: s_endpgm 1441; 1442; VI-LABEL: v_test_v2i16_x_sub_0_1_0: 1443; VI: ; %bb.0: 1444; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1445; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1446; VI-NEXT: v_mov_b32_e32 v3, 0x3c00 1447; VI-NEXT: s_waitcnt lgkmcnt(0) 1448; VI-NEXT: v_mov_b32_e32 v1, s3 1449; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 1450; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1451; VI-NEXT: flat_load_dword v4, v[0:1] 1452; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 1453; VI-NEXT: v_mov_b32_e32 v1, s1 1454; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1455; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 1456; VI-NEXT: v_add_u16_sdwa v2, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1457; VI-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1458; VI-NEXT: flat_store_dword v[0:1], v2 1459; VI-NEXT: s_endpgm 1460; 1461; GFX9-LABEL: v_test_v2i16_x_sub_0_1_0: 1462; GFX9: ; %bb.0: 1463; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1464; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1465; GFX9-NEXT: s_waitcnt lgkmcnt(0) 1466; GFX9-NEXT: v_mov_b32_e32 v1, s3 1467; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 1468; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 1469; GFX9-NEXT: global_load_dword v3, v[0:1], off 1470; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 1471; GFX9-NEXT: v_mov_b32_e32 v1, s1 1472; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 1473; GFX9-NEXT: s_waitcnt vmcnt(0) 1474; GFX9-NEXT: v_pk_sub_i16 v2, v3, -4.0 op_sel:[0,1] op_sel_hi:[1,0] 1475; GFX9-NEXT: global_store_dword v[0:1], v2, off 1476; GFX9-NEXT: s_endpgm 1477; 1478; GFX10-LABEL: v_test_v2i16_x_sub_0_1_0: 1479; GFX10: ; %bb.0: 1480; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1481; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1482; GFX10-NEXT: ; implicit-def: $vcc_hi 1483; GFX10-NEXT: s_waitcnt lgkmcnt(0) 1484; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 1485; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 1486; GFX10-NEXT: global_load_dword v3, v[0:1], off 1487; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 1488; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 1489; GFX10-NEXT: s_waitcnt vmcnt(0) 1490; GFX10-NEXT: v_pk_sub_i16 v2, v3, -4.0 op_sel:[0,1] op_sel_hi:[1,0] 1491; GFX10-NEXT: global_store_dword v[0:1], v2, off 1492; GFX10-NEXT: s_endpgm 1493 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1494 %tid.ext = sext i32 %tid to i64 1495 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 1496 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 1497 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 1498 %result = sub <2 x i16> %x, <i16 0, i16 -15360> 1499 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 1500 ret void 1501} 1502 1503define amdgpu_kernel void @v_test_v2i16_x_sub_0_neg1_0(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1504; SI-LABEL: v_test_v2i16_x_sub_0_neg1_0: 1505; SI: ; %bb.0: 1506; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1507; SI-NEXT: s_mov_b32 s7, 0xf000 1508; SI-NEXT: s_mov_b32 s6, 0 1509; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1510; SI-NEXT: v_mov_b32_e32 v1, 0 1511; SI-NEXT: s_waitcnt lgkmcnt(0) 1512; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1513; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1514; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1515; SI-NEXT: s_waitcnt vmcnt(0) 1516; SI-NEXT: v_add_i32_e32 v2, vcc, 0xbc000000, v2 1517; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 1518; SI-NEXT: s_endpgm 1519; 1520; VI-LABEL: v_test_v2i16_x_sub_0_neg1_0: 1521; VI: ; %bb.0: 1522; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1523; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1524; VI-NEXT: v_mov_b32_e32 v3, 0xffffbc00 1525; VI-NEXT: s_waitcnt lgkmcnt(0) 1526; VI-NEXT: v_mov_b32_e32 v1, s3 1527; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 1528; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1529; VI-NEXT: flat_load_dword v4, v[0:1] 1530; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 1531; VI-NEXT: v_mov_b32_e32 v1, s1 1532; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1533; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 1534; VI-NEXT: v_add_u16_sdwa v2, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1535; VI-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1536; VI-NEXT: flat_store_dword v[0:1], v2 1537; VI-NEXT: s_endpgm 1538; 1539; GFX9-LABEL: v_test_v2i16_x_sub_0_neg1_0: 1540; GFX9: ; %bb.0: 1541; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1542; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1543; GFX9-NEXT: s_waitcnt lgkmcnt(0) 1544; GFX9-NEXT: v_mov_b32_e32 v1, s3 1545; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 1546; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 1547; GFX9-NEXT: global_load_dword v3, v[0:1], off 1548; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 1549; GFX9-NEXT: v_mov_b32_e32 v1, s1 1550; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 1551; GFX9-NEXT: s_waitcnt vmcnt(0) 1552; GFX9-NEXT: v_pk_sub_i16 v2, v3, 4.0 op_sel:[0,1] op_sel_hi:[1,0] 1553; GFX9-NEXT: global_store_dword v[0:1], v2, off 1554; GFX9-NEXT: s_endpgm 1555; 1556; GFX10-LABEL: v_test_v2i16_x_sub_0_neg1_0: 1557; GFX10: ; %bb.0: 1558; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1559; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1560; GFX10-NEXT: ; implicit-def: $vcc_hi 1561; GFX10-NEXT: s_waitcnt lgkmcnt(0) 1562; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 1563; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 1564; GFX10-NEXT: global_load_dword v3, v[0:1], off 1565; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 1566; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 1567; GFX10-NEXT: s_waitcnt vmcnt(0) 1568; GFX10-NEXT: v_pk_sub_i16 v2, v3, 4.0 op_sel:[0,1] op_sel_hi:[1,0] 1569; GFX10-NEXT: global_store_dword v[0:1], v2, off 1570; GFX10-NEXT: s_endpgm 1571 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1572 %tid.ext = sext i32 %tid to i64 1573 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 1574 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 1575 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 1576 %result = sub <2 x i16> %x, <i16 0, i16 17408> 1577 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 1578 ret void 1579} 1580 1581; -32 isn't an inline immediate, but 32 is 1582define amdgpu_kernel void @v_test_v2i16_x_add_neg32_neg32(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1583; SI-LABEL: v_test_v2i16_x_add_neg32_neg32: 1584; SI: ; %bb.0: 1585; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1586; SI-NEXT: s_mov_b32 s7, 0xf000 1587; SI-NEXT: s_mov_b32 s6, 0 1588; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1589; SI-NEXT: v_mov_b32_e32 v1, 0 1590; SI-NEXT: s_waitcnt lgkmcnt(0) 1591; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1592; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1593; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1594; SI-NEXT: s_waitcnt vmcnt(0) 1595; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 1596; SI-NEXT: v_subrev_i32_e32 v2, vcc, 32, v2 1597; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 1598; SI-NEXT: v_or_b32_e32 v2, v3, v2 1599; SI-NEXT: v_add_i32_e32 v2, vcc, 0xffe00000, v2 1600; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 1601; SI-NEXT: s_endpgm 1602; 1603; VI-LABEL: v_test_v2i16_x_add_neg32_neg32: 1604; VI: ; %bb.0: 1605; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1606; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1607; VI-NEXT: v_mov_b32_e32 v3, 32 1608; VI-NEXT: s_waitcnt lgkmcnt(0) 1609; VI-NEXT: v_mov_b32_e32 v1, s3 1610; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 1611; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1612; VI-NEXT: flat_load_dword v4, v[0:1] 1613; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 1614; VI-NEXT: v_mov_b32_e32 v1, s1 1615; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1616; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 1617; VI-NEXT: v_sub_u16_sdwa v2, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1618; VI-NEXT: v_subrev_u16_e32 v3, 32, v4 1619; VI-NEXT: v_or_b32_e32 v2, v3, v2 1620; VI-NEXT: flat_store_dword v[0:1], v2 1621; VI-NEXT: s_endpgm 1622; 1623; GFX9-LABEL: v_test_v2i16_x_add_neg32_neg32: 1624; GFX9: ; %bb.0: 1625; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1626; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1627; GFX9-NEXT: s_waitcnt lgkmcnt(0) 1628; GFX9-NEXT: v_mov_b32_e32 v1, s3 1629; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 1630; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 1631; GFX9-NEXT: global_load_dword v3, v[0:1], off 1632; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 1633; GFX9-NEXT: v_mov_b32_e32 v1, s1 1634; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 1635; GFX9-NEXT: s_waitcnt vmcnt(0) 1636; GFX9-NEXT: v_pk_sub_u16 v2, v3, 32 op_sel_hi:[1,0] 1637; GFX9-NEXT: global_store_dword v[0:1], v2, off 1638; GFX9-NEXT: s_endpgm 1639; 1640; GFX10-LABEL: v_test_v2i16_x_add_neg32_neg32: 1641; GFX10: ; %bb.0: 1642; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1643; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1644; GFX10-NEXT: ; implicit-def: $vcc_hi 1645; GFX10-NEXT: s_waitcnt lgkmcnt(0) 1646; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 1647; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 1648; GFX10-NEXT: global_load_dword v3, v[0:1], off 1649; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 1650; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 1651; GFX10-NEXT: s_waitcnt vmcnt(0) 1652; GFX10-NEXT: v_pk_sub_u16 v2, v3, 32 op_sel_hi:[1,0] 1653; GFX10-NEXT: global_store_dword v[0:1], v2, off 1654; GFX10-NEXT: s_endpgm 1655 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1656 %tid.ext = sext i32 %tid to i64 1657 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 1658 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 1659 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 1660 %result = add <2 x i16> %x, <i16 -32, i16 -32> 1661 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 1662 ret void 1663} 1664 1665define amdgpu_kernel void @v_test_v2i16_x_add_0_neg32(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1666; SI-LABEL: v_test_v2i16_x_add_0_neg32: 1667; SI: ; %bb.0: 1668; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1669; SI-NEXT: s_mov_b32 s7, 0xf000 1670; SI-NEXT: s_mov_b32 s6, 0 1671; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1672; SI-NEXT: v_mov_b32_e32 v1, 0 1673; SI-NEXT: s_waitcnt lgkmcnt(0) 1674; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1675; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1676; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1677; SI-NEXT: s_waitcnt vmcnt(0) 1678; SI-NEXT: v_add_i32_e32 v2, vcc, 0xffe00000, v2 1679; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 1680; SI-NEXT: s_endpgm 1681; 1682; VI-LABEL: v_test_v2i16_x_add_0_neg32: 1683; VI: ; %bb.0: 1684; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1685; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1686; VI-NEXT: v_mov_b32_e32 v3, 32 1687; VI-NEXT: s_waitcnt lgkmcnt(0) 1688; VI-NEXT: v_mov_b32_e32 v1, s3 1689; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 1690; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1691; VI-NEXT: flat_load_dword v4, v[0:1] 1692; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 1693; VI-NEXT: v_mov_b32_e32 v1, s1 1694; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1695; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 1696; VI-NEXT: v_sub_u16_sdwa v2, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1697; VI-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1698; VI-NEXT: flat_store_dword v[0:1], v2 1699; VI-NEXT: s_endpgm 1700; 1701; GFX9-LABEL: v_test_v2i16_x_add_0_neg32: 1702; GFX9: ; %bb.0: 1703; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1704; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1705; GFX9-NEXT: s_waitcnt lgkmcnt(0) 1706; GFX9-NEXT: v_mov_b32_e32 v1, s3 1707; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 1708; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 1709; GFX9-NEXT: global_load_dword v3, v[0:1], off 1710; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 1711; GFX9-NEXT: v_mov_b32_e32 v1, s1 1712; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 1713; GFX9-NEXT: s_waitcnt vmcnt(0) 1714; GFX9-NEXT: v_pk_sub_u16 v2, v3, 32 op_sel:[0,1] op_sel_hi:[1,0] 1715; GFX9-NEXT: global_store_dword v[0:1], v2, off 1716; GFX9-NEXT: s_endpgm 1717; 1718; GFX10-LABEL: v_test_v2i16_x_add_0_neg32: 1719; GFX10: ; %bb.0: 1720; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1721; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1722; GFX10-NEXT: ; implicit-def: $vcc_hi 1723; GFX10-NEXT: s_waitcnt lgkmcnt(0) 1724; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 1725; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 1726; GFX10-NEXT: global_load_dword v3, v[0:1], off 1727; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 1728; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 1729; GFX10-NEXT: s_waitcnt vmcnt(0) 1730; GFX10-NEXT: v_pk_sub_u16 v2, v3, 32 op_sel:[0,1] op_sel_hi:[1,0] 1731; GFX10-NEXT: global_store_dword v[0:1], v2, off 1732; GFX10-NEXT: s_endpgm 1733 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1734 %tid.ext = sext i32 %tid to i64 1735 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 1736 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 1737 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 1738 %result = add <2 x i16> %x, <i16 0, i16 -32> 1739 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 1740 ret void 1741} 1742 1743define amdgpu_kernel void @v_test_v2i16_x_add_neg32_0(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1744; SI-LABEL: v_test_v2i16_x_add_neg32_0: 1745; SI: ; %bb.0: 1746; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1747; SI-NEXT: s_mov_b32 s7, 0xf000 1748; SI-NEXT: s_mov_b32 s6, 0 1749; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1750; SI-NEXT: v_mov_b32_e32 v1, 0 1751; SI-NEXT: s_waitcnt lgkmcnt(0) 1752; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1753; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1754; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1755; SI-NEXT: s_waitcnt vmcnt(0) 1756; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 1757; SI-NEXT: v_subrev_i32_e32 v2, vcc, 32, v2 1758; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 1759; SI-NEXT: v_or_b32_e32 v2, v2, v3 1760; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 1761; SI-NEXT: s_endpgm 1762; 1763; VI-LABEL: v_test_v2i16_x_add_neg32_0: 1764; VI: ; %bb.0: 1765; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1766; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1767; VI-NEXT: s_waitcnt lgkmcnt(0) 1768; VI-NEXT: v_mov_b32_e32 v1, s3 1769; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 1770; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1771; VI-NEXT: flat_load_dword v3, v[0:1] 1772; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 1773; VI-NEXT: v_mov_b32_e32 v1, s1 1774; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1775; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 1776; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 1777; VI-NEXT: v_subrev_u16_e32 v3, 32, v3 1778; VI-NEXT: v_or_b32_e32 v2, v3, v2 1779; VI-NEXT: flat_store_dword v[0:1], v2 1780; VI-NEXT: s_endpgm 1781; 1782; GFX9-LABEL: v_test_v2i16_x_add_neg32_0: 1783; GFX9: ; %bb.0: 1784; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1785; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1786; GFX9-NEXT: s_waitcnt lgkmcnt(0) 1787; GFX9-NEXT: v_mov_b32_e32 v1, s3 1788; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 1789; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 1790; GFX9-NEXT: global_load_dword v3, v[0:1], off 1791; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 1792; GFX9-NEXT: v_mov_b32_e32 v1, s1 1793; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 1794; GFX9-NEXT: s_waitcnt vmcnt(0) 1795; GFX9-NEXT: v_pk_sub_u16 v2, v3, 32 1796; GFX9-NEXT: global_store_dword v[0:1], v2, off 1797; GFX9-NEXT: s_endpgm 1798; 1799; GFX10-LABEL: v_test_v2i16_x_add_neg32_0: 1800; GFX10: ; %bb.0: 1801; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1802; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1803; GFX10-NEXT: ; implicit-def: $vcc_hi 1804; GFX10-NEXT: s_waitcnt lgkmcnt(0) 1805; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 1806; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 1807; GFX10-NEXT: global_load_dword v3, v[0:1], off 1808; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 1809; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 1810; GFX10-NEXT: s_waitcnt vmcnt(0) 1811; GFX10-NEXT: v_pk_sub_u16 v2, v3, 32 1812; GFX10-NEXT: global_store_dword v[0:1], v2, off 1813; GFX10-NEXT: s_endpgm 1814 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1815 %tid.ext = sext i32 %tid to i64 1816 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 1817 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 1818 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 1819 %result = add <2 x i16> %x, <i16 -32, i16 0> 1820 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 1821 ret void 1822} 1823 1824; 16 and -16 are both inline immediates 1825define amdgpu_kernel void @v_test_v2i16_x_add_neg16_neg16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1826; SI-LABEL: v_test_v2i16_x_add_neg16_neg16: 1827; SI: ; %bb.0: 1828; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1829; SI-NEXT: s_mov_b32 s7, 0xf000 1830; SI-NEXT: s_mov_b32 s6, 0 1831; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1832; SI-NEXT: v_mov_b32_e32 v1, 0 1833; SI-NEXT: s_waitcnt lgkmcnt(0) 1834; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1835; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1836; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1837; SI-NEXT: s_waitcnt vmcnt(0) 1838; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 1839; SI-NEXT: v_add_i32_e32 v2, vcc, -16, v2 1840; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 1841; SI-NEXT: v_or_b32_e32 v2, v3, v2 1842; SI-NEXT: v_add_i32_e32 v2, vcc, 0xfff00000, v2 1843; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 1844; SI-NEXT: s_endpgm 1845; 1846; VI-LABEL: v_test_v2i16_x_add_neg16_neg16: 1847; VI: ; %bb.0: 1848; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1849; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1850; VI-NEXT: v_mov_b32_e32 v3, -16 1851; VI-NEXT: s_waitcnt lgkmcnt(0) 1852; VI-NEXT: v_mov_b32_e32 v1, s3 1853; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 1854; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1855; VI-NEXT: flat_load_dword v4, v[0:1] 1856; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 1857; VI-NEXT: v_mov_b32_e32 v1, s1 1858; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1859; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 1860; VI-NEXT: v_add_u16_e32 v2, -16, v4 1861; VI-NEXT: v_add_u16_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1862; VI-NEXT: v_or_b32_e32 v2, v2, v3 1863; VI-NEXT: flat_store_dword v[0:1], v2 1864; VI-NEXT: s_endpgm 1865; 1866; GFX9-LABEL: v_test_v2i16_x_add_neg16_neg16: 1867; GFX9: ; %bb.0: 1868; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1869; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1870; GFX9-NEXT: s_waitcnt lgkmcnt(0) 1871; GFX9-NEXT: v_mov_b32_e32 v1, s3 1872; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 1873; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 1874; GFX9-NEXT: global_load_dword v3, v[0:1], off 1875; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 1876; GFX9-NEXT: v_mov_b32_e32 v1, s1 1877; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 1878; GFX9-NEXT: s_waitcnt vmcnt(0) 1879; GFX9-NEXT: v_pk_sub_u16 v2, v3, 16 op_sel_hi:[1,0] 1880; GFX9-NEXT: global_store_dword v[0:1], v2, off 1881; GFX9-NEXT: s_endpgm 1882; 1883; GFX10-LABEL: v_test_v2i16_x_add_neg16_neg16: 1884; GFX10: ; %bb.0: 1885; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1886; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1887; GFX10-NEXT: ; implicit-def: $vcc_hi 1888; GFX10-NEXT: s_waitcnt lgkmcnt(0) 1889; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 1890; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 1891; GFX10-NEXT: global_load_dword v3, v[0:1], off 1892; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 1893; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 1894; GFX10-NEXT: s_waitcnt vmcnt(0) 1895; GFX10-NEXT: v_pk_sub_u16 v2, v3, 16 op_sel_hi:[1,0] 1896; GFX10-NEXT: global_store_dword v[0:1], v2, off 1897; GFX10-NEXT: s_endpgm 1898 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1899 %tid.ext = sext i32 %tid to i64 1900 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 1901 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 1902 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 1903 %result = add <2 x i16> %x, <i16 -16, i16 -16> 1904 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 1905 ret void 1906} 1907 1908define amdgpu_kernel void @v_test_v2i16_x_add_0_neg16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1909; SI-LABEL: v_test_v2i16_x_add_0_neg16: 1910; SI: ; %bb.0: 1911; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1912; SI-NEXT: s_mov_b32 s7, 0xf000 1913; SI-NEXT: s_mov_b32 s6, 0 1914; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1915; SI-NEXT: v_mov_b32_e32 v1, 0 1916; SI-NEXT: s_waitcnt lgkmcnt(0) 1917; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1918; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1919; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1920; SI-NEXT: s_waitcnt vmcnt(0) 1921; SI-NEXT: v_add_i32_e32 v2, vcc, 0xfff00000, v2 1922; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 1923; SI-NEXT: s_endpgm 1924; 1925; VI-LABEL: v_test_v2i16_x_add_0_neg16: 1926; VI: ; %bb.0: 1927; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1928; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1929; VI-NEXT: v_mov_b32_e32 v3, -16 1930; VI-NEXT: s_waitcnt lgkmcnt(0) 1931; VI-NEXT: v_mov_b32_e32 v1, s3 1932; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 1933; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1934; VI-NEXT: flat_load_dword v4, v[0:1] 1935; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 1936; VI-NEXT: v_mov_b32_e32 v1, s1 1937; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1938; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 1939; VI-NEXT: v_add_u16_sdwa v2, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 1940; VI-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1941; VI-NEXT: flat_store_dword v[0:1], v2 1942; VI-NEXT: s_endpgm 1943; 1944; GFX9-LABEL: v_test_v2i16_x_add_0_neg16: 1945; GFX9: ; %bb.0: 1946; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1947; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1948; GFX9-NEXT: s_waitcnt lgkmcnt(0) 1949; GFX9-NEXT: v_mov_b32_e32 v1, s3 1950; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 1951; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 1952; GFX9-NEXT: global_load_dword v3, v[0:1], off 1953; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 1954; GFX9-NEXT: v_mov_b32_e32 v1, s1 1955; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 1956; GFX9-NEXT: s_waitcnt vmcnt(0) 1957; GFX9-NEXT: v_pk_sub_u16 v2, v3, 16 op_sel:[0,1] op_sel_hi:[1,0] 1958; GFX9-NEXT: global_store_dword v[0:1], v2, off 1959; GFX9-NEXT: s_endpgm 1960; 1961; GFX10-LABEL: v_test_v2i16_x_add_0_neg16: 1962; GFX10: ; %bb.0: 1963; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1964; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 1965; GFX10-NEXT: ; implicit-def: $vcc_hi 1966; GFX10-NEXT: s_waitcnt lgkmcnt(0) 1967; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 1968; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 1969; GFX10-NEXT: global_load_dword v3, v[0:1], off 1970; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 1971; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 1972; GFX10-NEXT: s_waitcnt vmcnt(0) 1973; GFX10-NEXT: v_pk_sub_u16 v2, v3, 16 op_sel:[0,1] op_sel_hi:[1,0] 1974; GFX10-NEXT: global_store_dword v[0:1], v2, off 1975; GFX10-NEXT: s_endpgm 1976 %tid = call i32 @llvm.amdgcn.workitem.id.x() 1977 %tid.ext = sext i32 %tid to i64 1978 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 1979 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 1980 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 1981 %result = add <2 x i16> %x, <i16 0, i16 -16> 1982 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 1983 ret void 1984} 1985 1986define amdgpu_kernel void @v_test_v2i16_x_add_neg16_0(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 1987; SI-LABEL: v_test_v2i16_x_add_neg16_0: 1988; SI: ; %bb.0: 1989; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1990; SI-NEXT: s_mov_b32 s7, 0xf000 1991; SI-NEXT: s_mov_b32 s6, 0 1992; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 1993; SI-NEXT: v_mov_b32_e32 v1, 0 1994; SI-NEXT: s_waitcnt lgkmcnt(0) 1995; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 1996; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 1997; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 1998; SI-NEXT: s_waitcnt vmcnt(0) 1999; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 2000; SI-NEXT: v_add_i32_e32 v2, vcc, -16, v2 2001; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 2002; SI-NEXT: v_or_b32_e32 v2, v2, v3 2003; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 2004; SI-NEXT: s_endpgm 2005; 2006; VI-LABEL: v_test_v2i16_x_add_neg16_0: 2007; VI: ; %bb.0: 2008; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2009; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2010; VI-NEXT: s_waitcnt lgkmcnt(0) 2011; VI-NEXT: v_mov_b32_e32 v1, s3 2012; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 2013; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2014; VI-NEXT: flat_load_dword v3, v[0:1] 2015; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 2016; VI-NEXT: v_mov_b32_e32 v1, s1 2017; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2018; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 2019; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 2020; VI-NEXT: v_add_u16_e32 v3, -16, v3 2021; VI-NEXT: v_or_b32_e32 v2, v3, v2 2022; VI-NEXT: flat_store_dword v[0:1], v2 2023; VI-NEXT: s_endpgm 2024; 2025; GFX9-LABEL: v_test_v2i16_x_add_neg16_0: 2026; GFX9: ; %bb.0: 2027; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2028; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2029; GFX9-NEXT: s_waitcnt lgkmcnt(0) 2030; GFX9-NEXT: v_mov_b32_e32 v1, s3 2031; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 2032; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 2033; GFX9-NEXT: global_load_dword v3, v[0:1], off 2034; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 2035; GFX9-NEXT: v_mov_b32_e32 v1, s1 2036; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 2037; GFX9-NEXT: s_waitcnt vmcnt(0) 2038; GFX9-NEXT: v_pk_sub_u16 v2, v3, 16 2039; GFX9-NEXT: global_store_dword v[0:1], v2, off 2040; GFX9-NEXT: s_endpgm 2041; 2042; GFX10-LABEL: v_test_v2i16_x_add_neg16_0: 2043; GFX10: ; %bb.0: 2044; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2045; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2046; GFX10-NEXT: ; implicit-def: $vcc_hi 2047; GFX10-NEXT: s_waitcnt lgkmcnt(0) 2048; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 2049; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 2050; GFX10-NEXT: global_load_dword v3, v[0:1], off 2051; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 2052; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 2053; GFX10-NEXT: s_waitcnt vmcnt(0) 2054; GFX10-NEXT: v_pk_sub_u16 v2, v3, 16 2055; GFX10-NEXT: global_store_dword v[0:1], v2, off 2056; GFX10-NEXT: s_endpgm 2057 %tid = call i32 @llvm.amdgcn.workitem.id.x() 2058 %tid.ext = sext i32 %tid to i64 2059 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 2060 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 2061 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 2062 %result = add <2 x i16> %x, <i16 -16, i16 0> 2063 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 2064 ret void 2065} 2066 2067define amdgpu_kernel void @v_test_v2i16_x_add_neg_fpone(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 2068; SI-LABEL: v_test_v2i16_x_add_neg_fpone: 2069; SI: ; %bb.0: 2070; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 2071; SI-NEXT: s_mov_b32 s7, 0xf000 2072; SI-NEXT: s_mov_b32 s6, 0 2073; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2074; SI-NEXT: v_mov_b32_e32 v1, 0 2075; SI-NEXT: s_waitcnt lgkmcnt(0) 2076; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 2077; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 2078; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 2079; SI-NEXT: s_waitcnt vmcnt(0) 2080; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 2081; SI-NEXT: v_add_i32_e32 v2, vcc, 0xffffc400, v2 2082; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 2083; SI-NEXT: v_or_b32_e32 v2, v3, v2 2084; SI-NEXT: v_add_i32_e32 v2, vcc, 0xc4000000, v2 2085; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 2086; SI-NEXT: s_endpgm 2087; 2088; VI-LABEL: v_test_v2i16_x_add_neg_fpone: 2089; VI: ; %bb.0: 2090; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2091; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2092; VI-NEXT: v_mov_b32_e32 v3, 0xffffc400 2093; VI-NEXT: s_waitcnt lgkmcnt(0) 2094; VI-NEXT: v_mov_b32_e32 v1, s3 2095; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 2096; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2097; VI-NEXT: flat_load_dword v4, v[0:1] 2098; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 2099; VI-NEXT: v_mov_b32_e32 v1, s1 2100; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2101; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 2102; VI-NEXT: v_add_u16_e32 v2, 0xffffc400, v4 2103; VI-NEXT: v_add_u16_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 2104; VI-NEXT: v_or_b32_e32 v2, v2, v3 2105; VI-NEXT: flat_store_dword v[0:1], v2 2106; VI-NEXT: s_endpgm 2107; 2108; GFX9-LABEL: v_test_v2i16_x_add_neg_fpone: 2109; GFX9: ; %bb.0: 2110; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2111; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2112; GFX9-NEXT: s_waitcnt lgkmcnt(0) 2113; GFX9-NEXT: v_mov_b32_e32 v1, s3 2114; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 2115; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 2116; GFX9-NEXT: global_load_dword v3, v[0:1], off 2117; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 2118; GFX9-NEXT: v_mov_b32_e32 v1, s1 2119; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 2120; GFX9-NEXT: s_waitcnt vmcnt(0) 2121; GFX9-NEXT: v_pk_sub_u16 v2, v3, 1.0 op_sel_hi:[1,0] 2122; GFX9-NEXT: global_store_dword v[0:1], v2, off 2123; GFX9-NEXT: s_endpgm 2124; 2125; GFX10-LABEL: v_test_v2i16_x_add_neg_fpone: 2126; GFX10: ; %bb.0: 2127; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2128; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2129; GFX10-NEXT: ; implicit-def: $vcc_hi 2130; GFX10-NEXT: s_waitcnt lgkmcnt(0) 2131; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 2132; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 2133; GFX10-NEXT: global_load_dword v3, v[0:1], off 2134; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 2135; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 2136; GFX10-NEXT: s_waitcnt vmcnt(0) 2137; GFX10-NEXT: v_pk_sub_u16 v2, v3, 1.0 op_sel_hi:[1,0] 2138; GFX10-NEXT: global_store_dword v[0:1], v2, off 2139; GFX10-NEXT: s_endpgm 2140 %tid = call i32 @llvm.amdgcn.workitem.id.x() 2141 %tid.ext = sext i32 %tid to i64 2142 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 2143 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 2144 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 2145 %result = add <2 x i16> %x, <i16 -15360, i16 -15360> 2146 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 2147 ret void 2148} 2149 2150define amdgpu_kernel void @v_test_v2i16_x_add_neg_negfpone(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 2151; SI-LABEL: v_test_v2i16_x_add_neg_negfpone: 2152; SI: ; %bb.0: 2153; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 2154; SI-NEXT: s_mov_b32 s7, 0xf000 2155; SI-NEXT: s_mov_b32 s6, 0 2156; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2157; SI-NEXT: v_mov_b32_e32 v1, 0 2158; SI-NEXT: s_waitcnt lgkmcnt(0) 2159; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 2160; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 2161; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 2162; SI-NEXT: s_waitcnt vmcnt(0) 2163; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 2164; SI-NEXT: v_add_i32_e32 v2, vcc, 0x4400, v2 2165; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 2166; SI-NEXT: v_or_b32_e32 v2, v3, v2 2167; SI-NEXT: v_add_i32_e32 v2, vcc, 0x44000000, v2 2168; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 2169; SI-NEXT: s_endpgm 2170; 2171; VI-LABEL: v_test_v2i16_x_add_neg_negfpone: 2172; VI: ; %bb.0: 2173; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2174; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2175; VI-NEXT: v_mov_b32_e32 v3, 0x4400 2176; VI-NEXT: s_waitcnt lgkmcnt(0) 2177; VI-NEXT: v_mov_b32_e32 v1, s3 2178; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 2179; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2180; VI-NEXT: flat_load_dword v4, v[0:1] 2181; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 2182; VI-NEXT: v_mov_b32_e32 v1, s1 2183; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2184; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 2185; VI-NEXT: v_add_u16_e32 v2, 4.0, v4 2186; VI-NEXT: v_add_u16_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 2187; VI-NEXT: v_or_b32_e32 v2, v2, v3 2188; VI-NEXT: flat_store_dword v[0:1], v2 2189; VI-NEXT: s_endpgm 2190; 2191; GFX9-LABEL: v_test_v2i16_x_add_neg_negfpone: 2192; GFX9: ; %bb.0: 2193; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2194; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2195; GFX9-NEXT: s_waitcnt lgkmcnt(0) 2196; GFX9-NEXT: v_mov_b32_e32 v1, s3 2197; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 2198; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 2199; GFX9-NEXT: global_load_dword v3, v[0:1], off 2200; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 2201; GFX9-NEXT: v_mov_b32_e32 v1, s1 2202; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 2203; GFX9-NEXT: s_waitcnt vmcnt(0) 2204; GFX9-NEXT: v_pk_sub_u16 v2, v3, -1.0 op_sel_hi:[1,0] 2205; GFX9-NEXT: global_store_dword v[0:1], v2, off 2206; GFX9-NEXT: s_endpgm 2207; 2208; GFX10-LABEL: v_test_v2i16_x_add_neg_negfpone: 2209; GFX10: ; %bb.0: 2210; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2211; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2212; GFX10-NEXT: ; implicit-def: $vcc_hi 2213; GFX10-NEXT: s_waitcnt lgkmcnt(0) 2214; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 2215; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 2216; GFX10-NEXT: global_load_dword v3, v[0:1], off 2217; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 2218; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 2219; GFX10-NEXT: s_waitcnt vmcnt(0) 2220; GFX10-NEXT: v_pk_sub_u16 v2, v3, -1.0 op_sel_hi:[1,0] 2221; GFX10-NEXT: global_store_dword v[0:1], v2, off 2222; GFX10-NEXT: s_endpgm 2223 %tid = call i32 @llvm.amdgcn.workitem.id.x() 2224 %tid.ext = sext i32 %tid to i64 2225 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 2226 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 2227 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 2228 %result = add <2 x i16> %x, <i16 17408, i16 17408> 2229 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 2230 ret void 2231} 2232 2233define amdgpu_kernel void @v_test_v2i16_x_add_neg_fptwo(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 2234; SI-LABEL: v_test_v2i16_x_add_neg_fptwo: 2235; SI: ; %bb.0: 2236; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 2237; SI-NEXT: s_mov_b32 s7, 0xf000 2238; SI-NEXT: s_mov_b32 s6, 0 2239; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2240; SI-NEXT: v_mov_b32_e32 v1, 0 2241; SI-NEXT: s_waitcnt lgkmcnt(0) 2242; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 2243; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 2244; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 2245; SI-NEXT: s_waitcnt vmcnt(0) 2246; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 2247; SI-NEXT: v_add_i32_e32 v2, vcc, 0x4000, v2 2248; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 2249; SI-NEXT: v_or_b32_e32 v2, v3, v2 2250; SI-NEXT: v_add_i32_e32 v2, vcc, 2.0, v2 2251; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 2252; SI-NEXT: s_endpgm 2253; 2254; VI-LABEL: v_test_v2i16_x_add_neg_fptwo: 2255; VI: ; %bb.0: 2256; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2257; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2258; VI-NEXT: v_mov_b32_e32 v3, 0x4000 2259; VI-NEXT: s_waitcnt lgkmcnt(0) 2260; VI-NEXT: v_mov_b32_e32 v1, s3 2261; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 2262; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2263; VI-NEXT: flat_load_dword v4, v[0:1] 2264; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 2265; VI-NEXT: v_mov_b32_e32 v1, s1 2266; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2267; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 2268; VI-NEXT: v_add_u16_e32 v2, 2.0, v4 2269; VI-NEXT: v_add_u16_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 2270; VI-NEXT: v_or_b32_e32 v2, v2, v3 2271; VI-NEXT: flat_store_dword v[0:1], v2 2272; VI-NEXT: s_endpgm 2273; 2274; GFX9-LABEL: v_test_v2i16_x_add_neg_fptwo: 2275; GFX9: ; %bb.0: 2276; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2277; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2278; GFX9-NEXT: s_waitcnt lgkmcnt(0) 2279; GFX9-NEXT: v_mov_b32_e32 v1, s3 2280; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 2281; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 2282; GFX9-NEXT: global_load_dword v3, v[0:1], off 2283; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 2284; GFX9-NEXT: v_mov_b32_e32 v1, s1 2285; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 2286; GFX9-NEXT: s_waitcnt vmcnt(0) 2287; GFX9-NEXT: v_pk_sub_u16 v2, v3, -2.0 op_sel_hi:[1,0] 2288; GFX9-NEXT: global_store_dword v[0:1], v2, off 2289; GFX9-NEXT: s_endpgm 2290; 2291; GFX10-LABEL: v_test_v2i16_x_add_neg_fptwo: 2292; GFX10: ; %bb.0: 2293; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2294; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2295; GFX10-NEXT: ; implicit-def: $vcc_hi 2296; GFX10-NEXT: s_waitcnt lgkmcnt(0) 2297; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 2298; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 2299; GFX10-NEXT: global_load_dword v3, v[0:1], off 2300; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 2301; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 2302; GFX10-NEXT: s_waitcnt vmcnt(0) 2303; GFX10-NEXT: v_pk_sub_u16 v2, v3, -2.0 op_sel_hi:[1,0] 2304; GFX10-NEXT: global_store_dword v[0:1], v2, off 2305; GFX10-NEXT: s_endpgm 2306 %tid = call i32 @llvm.amdgcn.workitem.id.x() 2307 %tid.ext = sext i32 %tid to i64 2308 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 2309 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 2310 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 2311 %result = add <2 x i16> %x, <i16 16384, i16 16384> 2312 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 2313 ret void 2314} 2315 2316define amdgpu_kernel void @v_test_v2i16_x_add_neg_negfptwo(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 2317; SI-LABEL: v_test_v2i16_x_add_neg_negfptwo: 2318; SI: ; %bb.0: 2319; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 2320; SI-NEXT: s_mov_b32 s7, 0xf000 2321; SI-NEXT: s_mov_b32 s6, 0 2322; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2323; SI-NEXT: v_mov_b32_e32 v1, 0 2324; SI-NEXT: s_waitcnt lgkmcnt(0) 2325; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 2326; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 2327; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 2328; SI-NEXT: s_waitcnt vmcnt(0) 2329; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 2330; SI-NEXT: v_add_i32_e32 v2, vcc, 0xffffc000, v2 2331; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 2332; SI-NEXT: v_or_b32_e32 v2, v3, v2 2333; SI-NEXT: v_add_i32_e32 v2, vcc, -2.0, v2 2334; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 2335; SI-NEXT: s_endpgm 2336; 2337; VI-LABEL: v_test_v2i16_x_add_neg_negfptwo: 2338; VI: ; %bb.0: 2339; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2340; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2341; VI-NEXT: v_mov_b32_e32 v3, 0xffffc000 2342; VI-NEXT: s_waitcnt lgkmcnt(0) 2343; VI-NEXT: v_mov_b32_e32 v1, s3 2344; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 2345; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2346; VI-NEXT: flat_load_dword v4, v[0:1] 2347; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 2348; VI-NEXT: v_mov_b32_e32 v1, s1 2349; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2350; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 2351; VI-NEXT: v_add_u16_e32 v2, 0xffffc000, v4 2352; VI-NEXT: v_add_u16_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 2353; VI-NEXT: v_or_b32_e32 v2, v2, v3 2354; VI-NEXT: flat_store_dword v[0:1], v2 2355; VI-NEXT: s_endpgm 2356; 2357; GFX9-LABEL: v_test_v2i16_x_add_neg_negfptwo: 2358; GFX9: ; %bb.0: 2359; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2360; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2361; GFX9-NEXT: s_waitcnt lgkmcnt(0) 2362; GFX9-NEXT: v_mov_b32_e32 v1, s3 2363; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 2364; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 2365; GFX9-NEXT: global_load_dword v3, v[0:1], off 2366; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 2367; GFX9-NEXT: v_mov_b32_e32 v1, s1 2368; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 2369; GFX9-NEXT: s_waitcnt vmcnt(0) 2370; GFX9-NEXT: v_pk_sub_u16 v2, v3, 2.0 op_sel_hi:[1,0] 2371; GFX9-NEXT: global_store_dword v[0:1], v2, off 2372; GFX9-NEXT: s_endpgm 2373; 2374; GFX10-LABEL: v_test_v2i16_x_add_neg_negfptwo: 2375; GFX10: ; %bb.0: 2376; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2377; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2378; GFX10-NEXT: ; implicit-def: $vcc_hi 2379; GFX10-NEXT: s_waitcnt lgkmcnt(0) 2380; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 2381; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 2382; GFX10-NEXT: global_load_dword v3, v[0:1], off 2383; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 2384; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 2385; GFX10-NEXT: s_waitcnt vmcnt(0) 2386; GFX10-NEXT: v_pk_sub_u16 v2, v3, 2.0 op_sel_hi:[1,0] 2387; GFX10-NEXT: global_store_dword v[0:1], v2, off 2388; GFX10-NEXT: s_endpgm 2389 %tid = call i32 @llvm.amdgcn.workitem.id.x() 2390 %tid.ext = sext i32 %tid to i64 2391 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 2392 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 2393 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 2394 %result = add <2 x i16> %x, <i16 -16384, i16 -16384> 2395 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 2396 ret void 2397} 2398 2399define amdgpu_kernel void @v_test_v2i16_x_add_undef_neg32(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 2400; SI-LABEL: v_test_v2i16_x_add_undef_neg32: 2401; SI: ; %bb.0: 2402; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 2403; SI-NEXT: s_mov_b32 s7, 0xf000 2404; SI-NEXT: s_mov_b32 s6, 0 2405; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2406; SI-NEXT: v_mov_b32_e32 v1, 0 2407; SI-NEXT: s_waitcnt lgkmcnt(0) 2408; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 2409; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 2410; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 2411; SI-NEXT: s_waitcnt vmcnt(0) 2412; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 2413; SI-NEXT: v_add_i32_e32 v2, vcc, 0xffe00000, v2 2414; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 2415; SI-NEXT: s_endpgm 2416; 2417; VI-LABEL: v_test_v2i16_x_add_undef_neg32: 2418; VI: ; %bb.0: 2419; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2420; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2421; VI-NEXT: v_mov_b32_e32 v3, 32 2422; VI-NEXT: s_waitcnt lgkmcnt(0) 2423; VI-NEXT: v_mov_b32_e32 v1, s3 2424; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 2425; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2426; VI-NEXT: flat_load_dword v4, v[0:1] 2427; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 2428; VI-NEXT: v_mov_b32_e32 v1, s1 2429; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2430; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 2431; VI-NEXT: v_sub_u16_sdwa v2, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 2432; VI-NEXT: flat_store_dword v[0:1], v2 2433; VI-NEXT: s_endpgm 2434; 2435; GFX9-LABEL: v_test_v2i16_x_add_undef_neg32: 2436; GFX9: ; %bb.0: 2437; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2438; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2439; GFX9-NEXT: s_waitcnt lgkmcnt(0) 2440; GFX9-NEXT: v_mov_b32_e32 v1, s3 2441; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 2442; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 2443; GFX9-NEXT: global_load_dword v3, v[0:1], off 2444; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 2445; GFX9-NEXT: v_mov_b32_e32 v1, s1 2446; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 2447; GFX9-NEXT: s_waitcnt vmcnt(0) 2448; GFX9-NEXT: v_pk_sub_u16 v2, v3, 32 op_sel:[0,1] op_sel_hi:[1,0] 2449; GFX9-NEXT: global_store_dword v[0:1], v2, off 2450; GFX9-NEXT: s_endpgm 2451; 2452; GFX10-LABEL: v_test_v2i16_x_add_undef_neg32: 2453; GFX10: ; %bb.0: 2454; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2455; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2456; GFX10-NEXT: ; implicit-def: $vcc_hi 2457; GFX10-NEXT: s_waitcnt lgkmcnt(0) 2458; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 2459; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 2460; GFX10-NEXT: global_load_dword v3, v[0:1], off 2461; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 2462; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 2463; GFX10-NEXT: s_waitcnt vmcnt(0) 2464; GFX10-NEXT: v_pk_sub_u16 v2, v3, 32 op_sel:[0,1] op_sel_hi:[1,0] 2465; GFX10-NEXT: global_store_dword v[0:1], v2, off 2466; GFX10-NEXT: s_endpgm 2467 %tid = call i32 @llvm.amdgcn.workitem.id.x() 2468 %tid.ext = sext i32 %tid to i64 2469 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 2470 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 2471 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 2472 %result = add <2 x i16> %x, <i16 undef, i16 -32> 2473 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 2474 ret void 2475} 2476 2477define amdgpu_kernel void @v_test_v2i16_x_add_neg32_undef(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { 2478; SI-LABEL: v_test_v2i16_x_add_neg32_undef: 2479; SI: ; %bb.0: 2480; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 2481; SI-NEXT: s_mov_b32 s7, 0xf000 2482; SI-NEXT: s_mov_b32 s6, 0 2483; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 2484; SI-NEXT: v_mov_b32_e32 v1, 0 2485; SI-NEXT: s_waitcnt lgkmcnt(0) 2486; SI-NEXT: s_mov_b64 s[4:5], s[2:3] 2487; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 2488; SI-NEXT: s_mov_b64 s[2:3], s[6:7] 2489; SI-NEXT: s_waitcnt vmcnt(0) 2490; SI-NEXT: v_subrev_i32_e32 v2, vcc, 32, v2 2491; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 2492; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 2493; SI-NEXT: s_endpgm 2494; 2495; VI-LABEL: v_test_v2i16_x_add_neg32_undef: 2496; VI: ; %bb.0: 2497; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2498; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2499; VI-NEXT: s_waitcnt lgkmcnt(0) 2500; VI-NEXT: v_mov_b32_e32 v1, s3 2501; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 2502; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2503; VI-NEXT: flat_load_dword v3, v[0:1] 2504; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 2505; VI-NEXT: v_mov_b32_e32 v1, s1 2506; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 2507; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 2508; VI-NEXT: v_subrev_u16_e32 v2, 32, v3 2509; VI-NEXT: flat_store_dword v[0:1], v2 2510; VI-NEXT: s_endpgm 2511; 2512; GFX9-LABEL: v_test_v2i16_x_add_neg32_undef: 2513; GFX9: ; %bb.0: 2514; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2515; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2516; GFX9-NEXT: s_waitcnt lgkmcnt(0) 2517; GFX9-NEXT: v_mov_b32_e32 v1, s3 2518; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s2, v2 2519; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 2520; GFX9-NEXT: global_load_dword v3, v[0:1], off 2521; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v2 2522; GFX9-NEXT: v_mov_b32_e32 v1, s1 2523; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc 2524; GFX9-NEXT: s_waitcnt vmcnt(0) 2525; GFX9-NEXT: v_pk_sub_u16 v2, v3, 32 2526; GFX9-NEXT: global_store_dword v[0:1], v2, off 2527; GFX9-NEXT: s_endpgm 2528; 2529; GFX10-LABEL: v_test_v2i16_x_add_neg32_undef: 2530; GFX10: ; %bb.0: 2531; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 2532; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0 2533; GFX10-NEXT: ; implicit-def: $vcc_hi 2534; GFX10-NEXT: s_waitcnt lgkmcnt(0) 2535; GFX10-NEXT: v_add_co_u32_e64 v0, s2, s2, v2 2536; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s2, s3, 0, s2 2537; GFX10-NEXT: global_load_dword v3, v[0:1], off 2538; GFX10-NEXT: v_add_co_u32_e64 v0, s0, s0, v2 2539; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0 2540; GFX10-NEXT: s_waitcnt vmcnt(0) 2541; GFX10-NEXT: v_pk_sub_u16 v2, v3, 32 2542; GFX10-NEXT: global_store_dword v[0:1], v2, off 2543; GFX10-NEXT: s_endpgm 2544 %tid = call i32 @llvm.amdgcn.workitem.id.x() 2545 %tid.ext = sext i32 %tid to i64 2546 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext 2547 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext 2548 %x = load <2 x i16>, <2 x i16> addrspace(1)* %gep 2549 %result = add <2 x i16> %x, <i16 -32, i16 undef> 2550 store <2 x i16> %result, <2 x i16> addrspace(1)* %gep.out 2551 ret void 2552} 2553 2554declare i32 @llvm.amdgcn.workitem.id.x() #1 2555 2556attributes #0 = { nounwind } 2557attributes #1 = { nounwind readnone } 2558