1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
3; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
4
5; ===================================================================================
6; V_LSHL_OR_B32
7; ===================================================================================
8
9define amdgpu_ps float @shl_or(i32 %a, i32 %b, i32 %c) {
10; VI-LABEL: shl_or:
11; VI:       ; %bb.0:
12; VI-NEXT:    v_lshlrev_b32_e32 v0, v1, v0
13; VI-NEXT:    v_or_b32_e32 v0, v0, v2
14; VI-NEXT:    ; return to shader part epilog
15;
16; GFX9-LABEL: shl_or:
17; GFX9:       ; %bb.0:
18; GFX9-NEXT:    v_lshl_or_b32 v0, v0, v1, v2
19; GFX9-NEXT:    ; return to shader part epilog
20  %x = shl i32 %a, %b
21  %result = or i32 %x, %c
22  %bc = bitcast i32 %result to float
23  ret float %bc
24}
25
26define amdgpu_ps float @shl_or_vgpr_c(i32 inreg %a, i32 inreg %b, i32 %c) {
27; VI-LABEL: shl_or_vgpr_c:
28; VI:       ; %bb.0:
29; VI-NEXT:    s_lshl_b32 s0, s2, s3
30; VI-NEXT:    v_or_b32_e32 v0, s0, v0
31; VI-NEXT:    ; return to shader part epilog
32;
33; GFX9-LABEL: shl_or_vgpr_c:
34; GFX9:       ; %bb.0:
35; GFX9-NEXT:    s_lshl_b32 s0, s2, s3
36; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
37; GFX9-NEXT:    ; return to shader part epilog
38  %x = shl i32 %a, %b
39  %result = or i32 %x, %c
40  %bc = bitcast i32 %result to float
41  ret float %bc
42}
43
44define amdgpu_ps float @shl_or_vgpr_all2(i32 %a, i32 %b, i32 %c) {
45; VI-LABEL: shl_or_vgpr_all2:
46; VI:       ; %bb.0:
47; VI-NEXT:    v_lshlrev_b32_e32 v0, v1, v0
48; VI-NEXT:    v_or_b32_e32 v0, v2, v0
49; VI-NEXT:    ; return to shader part epilog
50;
51; GFX9-LABEL: shl_or_vgpr_all2:
52; GFX9:       ; %bb.0:
53; GFX9-NEXT:    v_lshl_or_b32 v0, v0, v1, v2
54; GFX9-NEXT:    ; return to shader part epilog
55  %x = shl i32 %a, %b
56  %result = or i32 %c, %x
57  %bc = bitcast i32 %result to float
58  ret float %bc
59}
60
61define amdgpu_ps float @shl_or_vgpr_ac(i32 %a, i32 inreg %b, i32 %c) {
62; VI-LABEL: shl_or_vgpr_ac:
63; VI:       ; %bb.0:
64; VI-NEXT:    v_lshlrev_b32_e32 v0, s2, v0
65; VI-NEXT:    v_or_b32_e32 v0, v0, v1
66; VI-NEXT:    ; return to shader part epilog
67;
68; GFX9-LABEL: shl_or_vgpr_ac:
69; GFX9:       ; %bb.0:
70; GFX9-NEXT:    v_lshl_or_b32 v0, v0, s2, v1
71; GFX9-NEXT:    ; return to shader part epilog
72  %x = shl i32 %a, %b
73  %result = or i32 %x, %c
74  %bc = bitcast i32 %result to float
75  ret float %bc
76}
77
78define amdgpu_ps float @shl_or_vgpr_const(i32 %a, i32 %b) {
79; VI-LABEL: shl_or_vgpr_const:
80; VI:       ; %bb.0:
81; VI-NEXT:    v_lshlrev_b32_e32 v0, v1, v0
82; VI-NEXT:    v_or_b32_e32 v0, 6, v0
83; VI-NEXT:    ; return to shader part epilog
84;
85; GFX9-LABEL: shl_or_vgpr_const:
86; GFX9:       ; %bb.0:
87; GFX9-NEXT:    v_lshl_or_b32 v0, v0, v1, 6
88; GFX9-NEXT:    ; return to shader part epilog
89  %x = shl i32 %a, %b
90  %result = or i32 %x, 6
91  %bc = bitcast i32 %result to float
92  ret float %bc
93}
94
95define amdgpu_ps float @shl_or_vgpr_const2(i32 %a, i32 %b) {
96; VI-LABEL: shl_or_vgpr_const2:
97; VI:       ; %bb.0:
98; VI-NEXT:    v_lshlrev_b32_e32 v0, 6, v0
99; VI-NEXT:    v_or_b32_e32 v0, v0, v1
100; VI-NEXT:    ; return to shader part epilog
101;
102; GFX9-LABEL: shl_or_vgpr_const2:
103; GFX9:       ; %bb.0:
104; GFX9-NEXT:    v_lshl_or_b32 v0, v0, 6, v1
105; GFX9-NEXT:    ; return to shader part epilog
106  %x = shl i32 %a, 6
107  %result = or i32 %x, %b
108  %bc = bitcast i32 %result to float
109  ret float %bc
110}
111
112define amdgpu_ps float @shl_or_vgpr_const_scalar1(i32 inreg %a, i32 %b) {
113; VI-LABEL: shl_or_vgpr_const_scalar1:
114; VI:       ; %bb.0:
115; VI-NEXT:    s_lshl_b32 s0, s2, 6
116; VI-NEXT:    v_or_b32_e32 v0, s0, v0
117; VI-NEXT:    ; return to shader part epilog
118;
119; GFX9-LABEL: shl_or_vgpr_const_scalar1:
120; GFX9:       ; %bb.0:
121; GFX9-NEXT:    v_lshl_or_b32 v0, s2, 6, v0
122; GFX9-NEXT:    ; return to shader part epilog
123  %x = shl i32 %a, 6
124  %result = or i32 %x, %b
125  %bc = bitcast i32 %result to float
126  ret float %bc
127}
128
129define amdgpu_ps float @shl_or_vgpr_const_scalar2(i32 %a, i32 inreg %b) {
130; VI-LABEL: shl_or_vgpr_const_scalar2:
131; VI:       ; %bb.0:
132; VI-NEXT:    v_lshlrev_b32_e32 v0, 6, v0
133; VI-NEXT:    v_or_b32_e32 v0, s2, v0
134; VI-NEXT:    ; return to shader part epilog
135;
136; GFX9-LABEL: shl_or_vgpr_const_scalar2:
137; GFX9:       ; %bb.0:
138; GFX9-NEXT:    v_lshl_or_b32 v0, v0, 6, s2
139; GFX9-NEXT:    ; return to shader part epilog
140  %x = shl i32 %a, 6
141  %result = or i32 %x, %b
142  %bc = bitcast i32 %result to float
143  ret float %bc
144}
145