1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
3; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
4; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
5
6; ===================================================================================
7; V_LSHL_OR_B32
8; ===================================================================================
9
10define amdgpu_ps float @shl_or(i32 %a, i32 %b, i32 %c) {
11; VI-LABEL: shl_or:
12; VI:       ; %bb.0:
13; VI-NEXT:    v_lshlrev_b32_e32 v0, v1, v0
14; VI-NEXT:    v_or_b32_e32 v0, v0, v2
15; VI-NEXT:    ; return to shader part epilog
16;
17; GFX9-LABEL: shl_or:
18; GFX9:       ; %bb.0:
19; GFX9-NEXT:    v_lshl_or_b32 v0, v0, v1, v2
20; GFX9-NEXT:    ; return to shader part epilog
21;
22; GFX10-LABEL: shl_or:
23; GFX10:       ; %bb.0:
24; GFX10-NEXT:    v_lshl_or_b32 v0, v0, v1, v2
25; GFX10-NEXT:    ; return to shader part epilog
26  %x = shl i32 %a, %b
27  %result = or i32 %x, %c
28  %bc = bitcast i32 %result to float
29  ret float %bc
30}
31
32define amdgpu_ps float @shl_or_vgpr_c(i32 inreg %a, i32 inreg %b, i32 %c) {
33; VI-LABEL: shl_or_vgpr_c:
34; VI:       ; %bb.0:
35; VI-NEXT:    s_lshl_b32 s0, s2, s3
36; VI-NEXT:    v_or_b32_e32 v0, s0, v0
37; VI-NEXT:    ; return to shader part epilog
38;
39; GFX9-LABEL: shl_or_vgpr_c:
40; GFX9:       ; %bb.0:
41; GFX9-NEXT:    s_lshl_b32 s0, s2, s3
42; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
43; GFX9-NEXT:    ; return to shader part epilog
44;
45; GFX10-LABEL: shl_or_vgpr_c:
46; GFX10:       ; %bb.0:
47; GFX10-NEXT:    v_lshl_or_b32 v0, s2, s3, v0
48; GFX10-NEXT:    ; return to shader part epilog
49  %x = shl i32 %a, %b
50  %result = or i32 %x, %c
51  %bc = bitcast i32 %result to float
52  ret float %bc
53}
54
55define amdgpu_ps float @shl_or_vgpr_all2(i32 %a, i32 %b, i32 %c) {
56; VI-LABEL: shl_or_vgpr_all2:
57; VI:       ; %bb.0:
58; VI-NEXT:    v_lshlrev_b32_e32 v0, v1, v0
59; VI-NEXT:    v_or_b32_e32 v0, v2, v0
60; VI-NEXT:    ; return to shader part epilog
61;
62; GFX9-LABEL: shl_or_vgpr_all2:
63; GFX9:       ; %bb.0:
64; GFX9-NEXT:    v_lshl_or_b32 v0, v0, v1, v2
65; GFX9-NEXT:    ; return to shader part epilog
66;
67; GFX10-LABEL: shl_or_vgpr_all2:
68; GFX10:       ; %bb.0:
69; GFX10-NEXT:    v_lshl_or_b32 v0, v0, v1, v2
70; GFX10-NEXT:    ; return to shader part epilog
71  %x = shl i32 %a, %b
72  %result = or i32 %c, %x
73  %bc = bitcast i32 %result to float
74  ret float %bc
75}
76
77define amdgpu_ps float @shl_or_vgpr_ac(i32 %a, i32 inreg %b, i32 %c) {
78; VI-LABEL: shl_or_vgpr_ac:
79; VI:       ; %bb.0:
80; VI-NEXT:    v_lshlrev_b32_e32 v0, s2, v0
81; VI-NEXT:    v_or_b32_e32 v0, v0, v1
82; VI-NEXT:    ; return to shader part epilog
83;
84; GFX9-LABEL: shl_or_vgpr_ac:
85; GFX9:       ; %bb.0:
86; GFX9-NEXT:    v_lshl_or_b32 v0, v0, s2, v1
87; GFX9-NEXT:    ; return to shader part epilog
88;
89; GFX10-LABEL: shl_or_vgpr_ac:
90; GFX10:       ; %bb.0:
91; GFX10-NEXT:    v_lshl_or_b32 v0, v0, s2, v1
92; GFX10-NEXT:    ; return to shader part epilog
93  %x = shl i32 %a, %b
94  %result = or i32 %x, %c
95  %bc = bitcast i32 %result to float
96  ret float %bc
97}
98
99define amdgpu_ps float @shl_or_vgpr_const(i32 %a, i32 %b) {
100; VI-LABEL: shl_or_vgpr_const:
101; VI:       ; %bb.0:
102; VI-NEXT:    v_lshlrev_b32_e32 v0, v1, v0
103; VI-NEXT:    v_or_b32_e32 v0, 6, v0
104; VI-NEXT:    ; return to shader part epilog
105;
106; GFX9-LABEL: shl_or_vgpr_const:
107; GFX9:       ; %bb.0:
108; GFX9-NEXT:    v_lshl_or_b32 v0, v0, v1, 6
109; GFX9-NEXT:    ; return to shader part epilog
110;
111; GFX10-LABEL: shl_or_vgpr_const:
112; GFX10:       ; %bb.0:
113; GFX10-NEXT:    v_lshl_or_b32 v0, v0, v1, 6
114; GFX10-NEXT:    ; return to shader part epilog
115  %x = shl i32 %a, %b
116  %result = or i32 %x, 6
117  %bc = bitcast i32 %result to float
118  ret float %bc
119}
120
121define amdgpu_ps float @shl_or_vgpr_const2(i32 %a, i32 %b) {
122; VI-LABEL: shl_or_vgpr_const2:
123; VI:       ; %bb.0:
124; VI-NEXT:    v_lshlrev_b32_e32 v0, 6, v0
125; VI-NEXT:    v_or_b32_e32 v0, v0, v1
126; VI-NEXT:    ; return to shader part epilog
127;
128; GFX9-LABEL: shl_or_vgpr_const2:
129; GFX9:       ; %bb.0:
130; GFX9-NEXT:    v_lshl_or_b32 v0, v0, 6, v1
131; GFX9-NEXT:    ; return to shader part epilog
132;
133; GFX10-LABEL: shl_or_vgpr_const2:
134; GFX10:       ; %bb.0:
135; GFX10-NEXT:    v_lshl_or_b32 v0, v0, 6, v1
136; GFX10-NEXT:    ; return to shader part epilog
137  %x = shl i32 %a, 6
138  %result = or i32 %x, %b
139  %bc = bitcast i32 %result to float
140  ret float %bc
141}
142
143define amdgpu_ps float @shl_or_vgpr_const_scalar1(i32 inreg %a, i32 %b) {
144; VI-LABEL: shl_or_vgpr_const_scalar1:
145; VI:       ; %bb.0:
146; VI-NEXT:    s_lshl_b32 s0, s2, 6
147; VI-NEXT:    v_or_b32_e32 v0, s0, v0
148; VI-NEXT:    ; return to shader part epilog
149;
150; GFX9-LABEL: shl_or_vgpr_const_scalar1:
151; GFX9:       ; %bb.0:
152; GFX9-NEXT:    v_lshl_or_b32 v0, s2, 6, v0
153; GFX9-NEXT:    ; return to shader part epilog
154;
155; GFX10-LABEL: shl_or_vgpr_const_scalar1:
156; GFX10:       ; %bb.0:
157; GFX10-NEXT:    v_lshl_or_b32 v0, s2, 6, v0
158; GFX10-NEXT:    ; return to shader part epilog
159  %x = shl i32 %a, 6
160  %result = or i32 %x, %b
161  %bc = bitcast i32 %result to float
162  ret float %bc
163}
164
165define amdgpu_ps float @shl_or_vgpr_const_scalar2(i32 %a, i32 inreg %b) {
166; VI-LABEL: shl_or_vgpr_const_scalar2:
167; VI:       ; %bb.0:
168; VI-NEXT:    v_lshlrev_b32_e32 v0, 6, v0
169; VI-NEXT:    v_or_b32_e32 v0, s2, v0
170; VI-NEXT:    ; return to shader part epilog
171;
172; GFX9-LABEL: shl_or_vgpr_const_scalar2:
173; GFX9:       ; %bb.0:
174; GFX9-NEXT:    v_lshl_or_b32 v0, v0, 6, s2
175; GFX9-NEXT:    ; return to shader part epilog
176;
177; GFX10-LABEL: shl_or_vgpr_const_scalar2:
178; GFX10:       ; %bb.0:
179; GFX10-NEXT:    v_lshl_or_b32 v0, v0, 6, s2
180; GFX10-NEXT:    ; return to shader part epilog
181  %x = shl i32 %a, 6
182  %result = or i32 %x, %b
183  %bc = bitcast i32 %result to float
184  ret float %bc
185}
186