1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
3; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
4; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
5
6; ===================================================================================
7; V_LSHL_ADD_U32
8; ===================================================================================
9
10define amdgpu_ps float @shl_add(i32 %a, i32 %b, i32 %c) {
11; VI-LABEL: shl_add:
12; VI:       ; %bb.0:
13; VI-NEXT:    v_lshlrev_b32_e32 v0, v1, v0
14; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
15; VI-NEXT:    ; return to shader part epilog
16;
17; GFX9-LABEL: shl_add:
18; GFX9:       ; %bb.0:
19; GFX9-NEXT:    v_lshl_add_u32 v0, v0, v1, v2
20; GFX9-NEXT:    ; return to shader part epilog
21;
22; GFX10-LABEL: shl_add:
23; GFX10:       ; %bb.0:
24; GFX10-NEXT:    v_lshl_add_u32 v0, v0, v1, v2
25; GFX10-NEXT:    ; return to shader part epilog
26  %x = shl i32 %a, %b
27  %result = add i32 %x, %c
28  %bc = bitcast i32 %result to float
29  ret float %bc
30}
31
32; ThreeOp instruction variant not used due to Constant Bus Limitations
33define amdgpu_ps float @shl_add_vgpr_a(i32 %a, i32 inreg %b, i32 inreg %c) {
34; VI-LABEL: shl_add_vgpr_a:
35; VI:       ; %bb.0:
36; VI-NEXT:    v_lshlrev_b32_e32 v0, s2, v0
37; VI-NEXT:    v_add_u32_e32 v0, vcc, s3, v0
38; VI-NEXT:    ; return to shader part epilog
39;
40; GFX9-LABEL: shl_add_vgpr_a:
41; GFX9:       ; %bb.0:
42; GFX9-NEXT:    v_lshlrev_b32_e32 v0, s2, v0
43; GFX9-NEXT:    v_add_u32_e32 v0, s3, v0
44; GFX9-NEXT:    ; return to shader part epilog
45;
46; GFX10-LABEL: shl_add_vgpr_a:
47; GFX10:       ; %bb.0:
48; GFX10-NEXT:    v_lshl_add_u32 v0, v0, s2, s3
49; GFX10-NEXT:    ; return to shader part epilog
50  %x = shl i32 %a, %b
51  %result = add i32 %x, %c
52  %bc = bitcast i32 %result to float
53  ret float %bc
54}
55
56define amdgpu_ps float @shl_add_vgpr_all(i32 %a, i32 %b, i32 %c) {
57; VI-LABEL: shl_add_vgpr_all:
58; VI:       ; %bb.0:
59; VI-NEXT:    v_lshlrev_b32_e32 v0, v1, v0
60; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
61; VI-NEXT:    ; return to shader part epilog
62;
63; GFX9-LABEL: shl_add_vgpr_all:
64; GFX9:       ; %bb.0:
65; GFX9-NEXT:    v_lshl_add_u32 v0, v0, v1, v2
66; GFX9-NEXT:    ; return to shader part epilog
67;
68; GFX10-LABEL: shl_add_vgpr_all:
69; GFX10:       ; %bb.0:
70; GFX10-NEXT:    v_lshl_add_u32 v0, v0, v1, v2
71; GFX10-NEXT:    ; return to shader part epilog
72  %x = shl i32 %a, %b
73  %result = add i32 %x, %c
74  %bc = bitcast i32 %result to float
75  ret float %bc
76}
77
78define amdgpu_ps float @shl_add_vgpr_ab(i32 %a, i32 %b, i32 inreg %c) {
79; VI-LABEL: shl_add_vgpr_ab:
80; VI:       ; %bb.0:
81; VI-NEXT:    v_lshlrev_b32_e32 v0, v1, v0
82; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v0
83; VI-NEXT:    ; return to shader part epilog
84;
85; GFX9-LABEL: shl_add_vgpr_ab:
86; GFX9:       ; %bb.0:
87; GFX9-NEXT:    v_lshl_add_u32 v0, v0, v1, s2
88; GFX9-NEXT:    ; return to shader part epilog
89;
90; GFX10-LABEL: shl_add_vgpr_ab:
91; GFX10:       ; %bb.0:
92; GFX10-NEXT:    v_lshl_add_u32 v0, v0, v1, s2
93; GFX10-NEXT:    ; return to shader part epilog
94  %x = shl i32 %a, %b
95  %result = add i32 %x, %c
96  %bc = bitcast i32 %result to float
97  ret float %bc
98}
99
100define amdgpu_ps float @shl_add_vgpr_const(i32 %a, i32 %b) {
101; VI-LABEL: shl_add_vgpr_const:
102; VI:       ; %bb.0:
103; VI-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
104; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
105; VI-NEXT:    ; return to shader part epilog
106;
107; GFX9-LABEL: shl_add_vgpr_const:
108; GFX9:       ; %bb.0:
109; GFX9-NEXT:    v_lshl_add_u32 v0, v0, 3, v1
110; GFX9-NEXT:    ; return to shader part epilog
111;
112; GFX10-LABEL: shl_add_vgpr_const:
113; GFX10:       ; %bb.0:
114; GFX10-NEXT:    v_lshl_add_u32 v0, v0, 3, v1
115; GFX10-NEXT:    ; return to shader part epilog
116  %x = shl i32 %a, 3
117  %result = add i32 %x, %b
118  %bc = bitcast i32 %result to float
119  ret float %bc
120}
121