1; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,CIVI %s
3; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,CIVI %s
4
5; GCN-LABEL: {{^}}s_shl_v2i16:
6; GFX9: s_load_dword [[LHS:s[0-9]+]]
7; GFX9: s_load_dword [[RHS:s[0-9]+]]
8; GFX9: v_mov_b32_e32 [[VLHS:v[0-9]+]], [[LHS]]
9; GFX9: v_pk_lshlrev_b16 [[RESULT:v[0-9]+]], [[RHS]], [[VLHS]]
10
11; VI: s_load_dword s
12; VI: s_load_dword s
13; VI: s_lshr_b32
14; VI: s_lshr_b32
15; VI: s_and_b32
16; VI: s_and_b32
17; VI: s_lshl_b32
18; VI: s_lshl_b32
19; VI: s_lshl_b32
20; VI: s_and_b32
21; VI: s_or_b32
22
23; CI: s_load_dword s
24; CI: s_load_dword s
25; CI: s_lshr_b32
26; CI: s_and_b32
27; CI: s_lshr_b32
28; CI: s_lshl_b32
29; CI: s_lshl_b32
30; CI: s_lshl_b32
31; CI: s_and_b32
32; CI: s_or_b32
33; CI: _store_dword
34define amdgpu_kernel void @s_shl_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %lhs, <2 x i16> %rhs) #0 {
35  %result = shl <2 x i16> %lhs, %rhs
36  store <2 x i16> %result, <2 x i16> addrspace(1)* %out
37  ret void
38}
39
40; GCN-LABEL: {{^}}v_shl_v2i16:
41; GCN: {{buffer|flat|global}}_load_dword [[LHS:v[0-9]+]]
42; GCN: {{buffer|flat|global}}_load_dword [[RHS:v[0-9]+]]
43; GFX9: v_pk_lshlrev_b16 [[RESULT:v[0-9]+]], [[RHS]], [[LHS]]
44
45; VI: v_lshlrev_b16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
46; VI: v_lshlrev_b16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
47; VI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
48
49; CI: s_mov_b32 [[MASK:s[0-9]+]], 0xffff{{$}}
50; CI: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, [[LHS]]
51; CI: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
52; CI: v_lshlrev_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
53; CI: v_lshlrev_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
54; CI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
55; CI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], v{{[0-9]+}}
56; CI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
57define amdgpu_kernel void @v_shl_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
58  %tid = call i32 @llvm.amdgcn.workitem.id.x()
59  %tid.ext = sext i32 %tid to i64
60  %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
61  %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
62  %b_ptr = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %in.gep, i32 1
63  %a = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
64  %b = load <2 x i16>, <2 x i16> addrspace(1)* %b_ptr
65  %result = shl <2 x i16> %a, %b
66  store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
67  ret void
68}
69
70; GCN-LABEL: {{^}}shl_v_s_v2i16:
71; GFX9: s_load_dword [[RHS:s[0-9]+]]
72; GFX9: {{buffer|flat|global}}_load_dword [[LHS:v[0-9]+]]
73; GFX9: v_pk_lshlrev_b16 [[RESULT:v[0-9]+]], [[RHS]], [[LHS]]
74define amdgpu_kernel void @shl_v_s_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in, <2 x i16> %sgpr) #0 {
75  %tid = call i32 @llvm.amdgcn.workitem.id.x()
76  %tid.ext = sext i32 %tid to i64
77  %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
78  %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
79  %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
80  %result = shl <2 x i16> %vgpr, %sgpr
81  store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
82  ret void
83}
84
85; GCN-LABEL: {{^}}shl_s_v_v2i16:
86; GFX9: s_load_dword [[LHS:s[0-9]+]]
87; GFX9: {{buffer|flat|global}}_load_dword [[RHS:v[0-9]+]]
88; GFX9: v_pk_lshlrev_b16 [[RESULT:v[0-9]+]], [[RHS]], [[LHS]]
89define amdgpu_kernel void @shl_s_v_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in, <2 x i16> %sgpr) #0 {
90  %tid = call i32 @llvm.amdgcn.workitem.id.x()
91  %tid.ext = sext i32 %tid to i64
92  %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
93  %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
94  %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
95  %result = shl <2 x i16> %sgpr, %vgpr
96  store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
97  ret void
98}
99
100; GCN-LABEL: {{^}}shl_imm_v_v2i16:
101; GCN: {{buffer|flat|global}}_load_dword [[RHS:v[0-9]+]]
102; GFX9: v_pk_lshlrev_b16 [[RESULT:v[0-9]+]], [[RHS]], 8
103define amdgpu_kernel void @shl_imm_v_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
104  %tid = call i32 @llvm.amdgcn.workitem.id.x()
105  %tid.ext = sext i32 %tid to i64
106  %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
107  %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
108  %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
109  %result = shl <2 x i16> <i16 8, i16 8>, %vgpr
110  store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
111  ret void
112}
113
114; GCN-LABEL: {{^}}shl_v_imm_v2i16:
115; GCN: {{buffer|flat|global}}_load_dword [[LHS:v[0-9]+]]
116; GFX9: v_pk_lshlrev_b16 [[RESULT:v[0-9]+]], 8, [[LHS]]
117define amdgpu_kernel void @shl_v_imm_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
118  %tid = call i32 @llvm.amdgcn.workitem.id.x()
119  %tid.ext = sext i32 %tid to i64
120  %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
121  %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
122  %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
123  %result = shl <2 x i16> %vgpr, <i16 8, i16 8>
124  store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
125  ret void
126}
127
128; GCN-LABEL: {{^}}v_shl_v4i16:
129; GCN: {{buffer|flat|global}}_load_dwordx2
130; GCN: {{buffer|flat|global}}_load_dwordx2
131; GFX9: v_pk_lshlrev_b16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
132; GFX9: v_pk_lshlrev_b16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
133; GCN: {{buffer|flat|global}}_store_dwordx2
134define amdgpu_kernel void @v_shl_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 {
135  %tid = call i32 @llvm.amdgcn.workitem.id.x()
136  %tid.ext = sext i32 %tid to i64
137  %in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext
138  %out.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %out, i64 %tid.ext
139  %b_ptr = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %in.gep, i32 1
140  %a = load <4 x i16>, <4 x i16> addrspace(1)* %in.gep
141  %b = load <4 x i16>, <4 x i16> addrspace(1)* %b_ptr
142  %result = shl <4 x i16> %a, %b
143  store <4 x i16> %result, <4 x i16> addrspace(1)* %out.gep
144  ret void
145}
146
147; GCN-LABEL: {{^}}shl_v_imm_v4i16:
148; GCN: {{buffer|flat|global}}_load_dwordx2
149; GFX9: v_pk_lshlrev_b16 v{{[0-9]+}}, 8, v{{[0-9]+}}
150; GFX9: v_pk_lshlrev_b16 v{{[0-9]+}}, 8, v{{[0-9]+}}
151; GCN: {{buffer|flat|global}}_store_dwordx2
152define amdgpu_kernel void @shl_v_imm_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 {
153  %tid = call i32 @llvm.amdgcn.workitem.id.x()
154  %tid.ext = sext i32 %tid to i64
155  %in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext
156  %out.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %out, i64 %tid.ext
157  %vgpr = load <4 x i16>, <4 x i16> addrspace(1)* %in.gep
158  %result = shl <4 x i16> %vgpr, <i16 8, i16 8, i16 8, i16 8>
159  store <4 x i16> %result, <4 x i16> addrspace(1)* %out.gep
160  ret void
161}
162
163declare i32 @llvm.amdgcn.workitem.id.x() #1
164
165attributes #0 = { nounwind }
166attributes #1 = { nounwind readnone }
167