1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX9 %s
3; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=VI %s
4; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=CI %s
5; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX10 %s
6
7define amdgpu_kernel void @s_shl_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %lhs, <2 x i16> %rhs) #0 {
8; GFX9-LABEL: s_shl_v2i16:
9; GFX9:       ; %bb.0:
10; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
11; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
12; GFX9-NEXT:    s_mov_b32 s7, 0xf000
13; GFX9-NEXT:    s_mov_b32 s6, -1
14; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
15; GFX9-NEXT:    v_mov_b32_e32 v0, s2
16; GFX9-NEXT:    v_pk_lshlrev_b16 v0, s3, v0
17; GFX9-NEXT:    buffer_store_dword v0, off, s[4:7], 0
18; GFX9-NEXT:    s_endpgm
19;
20; VI-LABEL: s_shl_v2i16:
21; VI:       ; %bb.0:
22; VI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
23; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
24; VI-NEXT:    s_mov_b32 s3, 0xf000
25; VI-NEXT:    s_mov_b32 s2, -1
26; VI-NEXT:    s_waitcnt lgkmcnt(0)
27; VI-NEXT:    s_and_b32 s6, s4, 0xffff
28; VI-NEXT:    s_lshr_b32 s4, s4, 16
29; VI-NEXT:    s_lshr_b32 s7, s5, 16
30; VI-NEXT:    s_lshl_b32 s4, s4, s7
31; VI-NEXT:    s_lshl_b32 s5, s6, s5
32; VI-NEXT:    s_lshl_b32 s4, s4, 16
33; VI-NEXT:    s_and_b32 s5, s5, 0xffff
34; VI-NEXT:    s_or_b32 s4, s5, s4
35; VI-NEXT:    v_mov_b32_e32 v0, s4
36; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
37; VI-NEXT:    s_endpgm
38;
39; CI-LABEL: s_shl_v2i16:
40; CI:       ; %bb.0:
41; CI-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
42; CI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
43; CI-NEXT:    s_mov_b32 s3, 0xf000
44; CI-NEXT:    s_mov_b32 s2, -1
45; CI-NEXT:    s_waitcnt lgkmcnt(0)
46; CI-NEXT:    s_lshr_b32 s6, s4, 16
47; CI-NEXT:    s_lshr_b32 s7, s5, 16
48; CI-NEXT:    s_lshl_b32 s6, s6, s7
49; CI-NEXT:    s_lshl_b32 s4, s4, s5
50; CI-NEXT:    s_lshl_b32 s6, s6, 16
51; CI-NEXT:    s_and_b32 s4, s4, 0xffff
52; CI-NEXT:    s_or_b32 s4, s4, s6
53; CI-NEXT:    v_mov_b32_e32 v0, s4
54; CI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
55; CI-NEXT:    s_endpgm
56;
57; GFX10-LABEL: s_shl_v2i16:
58; GFX10:       ; %bb.0:
59; GFX10-NEXT:    s_clause 0x1
60; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
61; GFX10-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
62; GFX10-NEXT:    s_mov_b32 s7, 0x31016000
63; GFX10-NEXT:    s_mov_b32 s6, -1
64; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
65; GFX10-NEXT:    v_pk_lshlrev_b16 v0, s3, s2
66; GFX10-NEXT:    buffer_store_dword v0, off, s[4:7], 0
67; GFX10-NEXT:    s_endpgm
68  %result = shl <2 x i16> %lhs, %rhs
69  store <2 x i16> %result, <2 x i16> addrspace(1)* %out
70  ret void
71}
72
73define amdgpu_kernel void @v_shl_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
74; GFX9-LABEL: v_shl_v2i16:
75; GFX9:       ; %bb.0:
76; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
77; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
78; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
79; GFX9-NEXT:    global_load_dwordx2 v[0:1], v2, s[2:3]
80; GFX9-NEXT:    s_waitcnt vmcnt(0)
81; GFX9-NEXT:    v_pk_lshlrev_b16 v0, v1, v0
82; GFX9-NEXT:    global_store_dword v2, v0, s[0:1]
83; GFX9-NEXT:    s_endpgm
84;
85; VI-LABEL: v_shl_v2i16:
86; VI:       ; %bb.0:
87; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
88; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
89; VI-NEXT:    s_waitcnt lgkmcnt(0)
90; VI-NEXT:    v_mov_b32_e32 v1, s3
91; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2
92; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
93; VI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
94; VI-NEXT:    v_mov_b32_e32 v3, s1
95; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2
96; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
97; VI-NEXT:    s_waitcnt vmcnt(0)
98; VI-NEXT:    v_lshlrev_b16_e32 v4, v1, v0
99; VI-NEXT:    v_lshlrev_b16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
100; VI-NEXT:    v_or_b32_e32 v0, v4, v0
101; VI-NEXT:    flat_store_dword v[2:3], v0
102; VI-NEXT:    s_endpgm
103;
104; CI-LABEL: v_shl_v2i16:
105; CI:       ; %bb.0:
106; CI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
107; CI-NEXT:    s_mov_b32 s7, 0xf000
108; CI-NEXT:    s_mov_b32 s6, 0
109; CI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
110; CI-NEXT:    v_mov_b32_e32 v1, 0
111; CI-NEXT:    s_waitcnt lgkmcnt(0)
112; CI-NEXT:    s_mov_b64 s[4:5], s[2:3]
113; CI-NEXT:    buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
114; CI-NEXT:    s_mov_b64 s[2:3], s[6:7]
115; CI-NEXT:    s_waitcnt vmcnt(0)
116; CI-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
117; CI-NEXT:    v_lshrrev_b32_e32 v5, 16, v3
118; CI-NEXT:    v_lshlrev_b32_e32 v2, v3, v2
119; CI-NEXT:    v_lshlrev_b32_e32 v3, v5, v4
120; CI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
121; CI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
122; CI-NEXT:    v_or_b32_e32 v2, v2, v3
123; CI-NEXT:    buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
124; CI-NEXT:    s_endpgm
125;
126; GFX10-LABEL: v_shl_v2i16:
127; GFX10:       ; %bb.0:
128; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
129; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
130; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
131; GFX10-NEXT:    global_load_dwordx2 v[0:1], v2, s[2:3]
132; GFX10-NEXT:    s_waitcnt vmcnt(0)
133; GFX10-NEXT:    v_pk_lshlrev_b16 v0, v1, v0
134; GFX10-NEXT:    global_store_dword v2, v0, s[0:1]
135; GFX10-NEXT:    s_endpgm
136  %tid = call i32 @llvm.amdgcn.workitem.id.x()
137  %tid.ext = sext i32 %tid to i64
138  %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
139  %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
140  %b_ptr = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %in.gep, i32 1
141  %a = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
142  %b = load <2 x i16>, <2 x i16> addrspace(1)* %b_ptr
143  %result = shl <2 x i16> %a, %b
144  store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
145  ret void
146}
147
148define amdgpu_kernel void @shl_v_s_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in, <2 x i16> %sgpr) #0 {
149; GFX9-LABEL: shl_v_s_v2i16:
150; GFX9:       ; %bb.0:
151; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
152; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x34
153; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
154; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
155; GFX9-NEXT:    global_load_dword v1, v0, s[6:7]
156; GFX9-NEXT:    s_waitcnt vmcnt(0)
157; GFX9-NEXT:    v_pk_lshlrev_b16 v1, s2, v1
158; GFX9-NEXT:    global_store_dword v0, v1, s[4:5]
159; GFX9-NEXT:    s_endpgm
160;
161; VI-LABEL: shl_v_s_v2i16:
162; VI:       ; %bb.0:
163; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
164; VI-NEXT:    s_load_dword s0, s[0:1], 0x34
165; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
166; VI-NEXT:    s_waitcnt lgkmcnt(0)
167; VI-NEXT:    v_mov_b32_e32 v1, s7
168; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v2
169; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
170; VI-NEXT:    flat_load_dword v3, v[0:1]
171; VI-NEXT:    s_lshr_b32 s1, s0, 16
172; VI-NEXT:    v_add_u32_e32 v0, vcc, s4, v2
173; VI-NEXT:    v_mov_b32_e32 v2, s1
174; VI-NEXT:    v_mov_b32_e32 v1, s5
175; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
176; VI-NEXT:    s_waitcnt vmcnt(0)
177; VI-NEXT:    v_lshlrev_b16_e32 v4, s0, v3
178; VI-NEXT:    v_lshlrev_b16_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
179; VI-NEXT:    v_or_b32_e32 v2, v4, v2
180; VI-NEXT:    flat_store_dword v[0:1], v2
181; VI-NEXT:    s_endpgm
182;
183; CI-LABEL: shl_v_s_v2i16:
184; CI:       ; %bb.0:
185; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
186; CI-NEXT:    s_load_dword s8, s[0:1], 0xd
187; CI-NEXT:    s_mov_b32 s3, 0xf000
188; CI-NEXT:    s_mov_b32 s2, 0
189; CI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
190; CI-NEXT:    s_waitcnt lgkmcnt(0)
191; CI-NEXT:    s_mov_b64 s[0:1], s[6:7]
192; CI-NEXT:    v_mov_b32_e32 v1, 0
193; CI-NEXT:    buffer_load_dword v2, v[0:1], s[0:3], 0 addr64
194; CI-NEXT:    s_lshr_b32 s0, s8, 16
195; CI-NEXT:    s_mov_b64 s[6:7], s[2:3]
196; CI-NEXT:    s_waitcnt vmcnt(0)
197; CI-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
198; CI-NEXT:    v_lshlrev_b32_e32 v2, s8, v2
199; CI-NEXT:    v_lshlrev_b32_e32 v3, s0, v3
200; CI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
201; CI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
202; CI-NEXT:    v_or_b32_e32 v2, v2, v3
203; CI-NEXT:    buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
204; CI-NEXT:    s_endpgm
205;
206; GFX10-LABEL: shl_v_s_v2i16:
207; GFX10:       ; %bb.0:
208; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
209; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
210; GFX10-NEXT:    s_load_dword s0, s[0:1], 0x34
211; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
212; GFX10-NEXT:    global_load_dword v1, v0, s[6:7]
213; GFX10-NEXT:    s_waitcnt vmcnt(0)
214; GFX10-NEXT:    v_pk_lshlrev_b16 v1, s0, v1
215; GFX10-NEXT:    global_store_dword v0, v1, s[4:5]
216; GFX10-NEXT:    s_endpgm
217  %tid = call i32 @llvm.amdgcn.workitem.id.x()
218  %tid.ext = sext i32 %tid to i64
219  %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
220  %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
221  %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
222  %result = shl <2 x i16> %vgpr, %sgpr
223  store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
224  ret void
225}
226
227define amdgpu_kernel void @shl_s_v_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in, <2 x i16> %sgpr) #0 {
228; GFX9-LABEL: shl_s_v_v2i16:
229; GFX9:       ; %bb.0:
230; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
231; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x34
232; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
233; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
234; GFX9-NEXT:    global_load_dword v1, v0, s[6:7]
235; GFX9-NEXT:    s_waitcnt vmcnt(0)
236; GFX9-NEXT:    v_pk_lshlrev_b16 v1, v1, s2
237; GFX9-NEXT:    global_store_dword v0, v1, s[4:5]
238; GFX9-NEXT:    s_endpgm
239;
240; VI-LABEL: shl_s_v_v2i16:
241; VI:       ; %bb.0:
242; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
243; VI-NEXT:    s_load_dword s0, s[0:1], 0x34
244; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
245; VI-NEXT:    s_waitcnt lgkmcnt(0)
246; VI-NEXT:    v_mov_b32_e32 v1, s7
247; VI-NEXT:    v_add_u32_e32 v0, vcc, s6, v2
248; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
249; VI-NEXT:    flat_load_dword v3, v[0:1]
250; VI-NEXT:    s_lshr_b32 s1, s0, 16
251; VI-NEXT:    v_add_u32_e32 v0, vcc, s4, v2
252; VI-NEXT:    v_mov_b32_e32 v2, s1
253; VI-NEXT:    v_mov_b32_e32 v1, s5
254; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
255; VI-NEXT:    s_waitcnt vmcnt(0)
256; VI-NEXT:    v_lshlrev_b16_e64 v4, v3, s0
257; VI-NEXT:    v_lshlrev_b16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
258; VI-NEXT:    v_or_b32_e32 v2, v4, v2
259; VI-NEXT:    flat_store_dword v[0:1], v2
260; VI-NEXT:    s_endpgm
261;
262; CI-LABEL: shl_s_v_v2i16:
263; CI:       ; %bb.0:
264; CI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
265; CI-NEXT:    s_load_dword s8, s[0:1], 0xd
266; CI-NEXT:    s_mov_b32 s3, 0xf000
267; CI-NEXT:    s_mov_b32 s2, 0
268; CI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
269; CI-NEXT:    s_waitcnt lgkmcnt(0)
270; CI-NEXT:    s_mov_b64 s[0:1], s[6:7]
271; CI-NEXT:    v_mov_b32_e32 v1, 0
272; CI-NEXT:    buffer_load_dword v2, v[0:1], s[0:3], 0 addr64
273; CI-NEXT:    s_lshr_b32 s0, s8, 16
274; CI-NEXT:    s_mov_b64 s[6:7], s[2:3]
275; CI-NEXT:    s_waitcnt vmcnt(0)
276; CI-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
277; CI-NEXT:    v_lshl_b32_e32 v2, s8, v2
278; CI-NEXT:    v_lshl_b32_e32 v3, s0, v3
279; CI-NEXT:    v_and_b32_e32 v2, 0xffff, v2
280; CI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
281; CI-NEXT:    v_or_b32_e32 v2, v2, v3
282; CI-NEXT:    buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
283; CI-NEXT:    s_endpgm
284;
285; GFX10-LABEL: shl_s_v_v2i16:
286; GFX10:       ; %bb.0:
287; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
288; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
289; GFX10-NEXT:    s_load_dword s0, s[0:1], 0x34
290; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
291; GFX10-NEXT:    global_load_dword v1, v0, s[6:7]
292; GFX10-NEXT:    s_waitcnt vmcnt(0)
293; GFX10-NEXT:    v_pk_lshlrev_b16 v1, v1, s0
294; GFX10-NEXT:    global_store_dword v0, v1, s[4:5]
295; GFX10-NEXT:    s_endpgm
296  %tid = call i32 @llvm.amdgcn.workitem.id.x()
297  %tid.ext = sext i32 %tid to i64
298  %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
299  %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
300  %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
301  %result = shl <2 x i16> %sgpr, %vgpr
302  store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
303  ret void
304}
305
306define amdgpu_kernel void @shl_imm_v_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
307; GFX9-LABEL: shl_imm_v_v2i16:
308; GFX9:       ; %bb.0:
309; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
310; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
311; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
312; GFX9-NEXT:    global_load_dword v1, v0, s[2:3]
313; GFX9-NEXT:    s_waitcnt vmcnt(0)
314; GFX9-NEXT:    v_pk_lshlrev_b16 v1, v1, 8 op_sel_hi:[1,0]
315; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
316; GFX9-NEXT:    s_endpgm
317;
318; VI-LABEL: shl_imm_v_v2i16:
319; VI:       ; %bb.0:
320; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
321; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
322; VI-NEXT:    v_mov_b32_e32 v4, 8
323; VI-NEXT:    s_waitcnt lgkmcnt(0)
324; VI-NEXT:    v_mov_b32_e32 v1, s3
325; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2
326; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
327; VI-NEXT:    flat_load_dword v3, v[0:1]
328; VI-NEXT:    v_mov_b32_e32 v1, s1
329; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v2
330; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
331; VI-NEXT:    s_waitcnt vmcnt(0)
332; VI-NEXT:    v_lshlrev_b16_e64 v2, v3, 8
333; VI-NEXT:    v_lshlrev_b16_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
334; VI-NEXT:    v_or_b32_e32 v2, v2, v3
335; VI-NEXT:    flat_store_dword v[0:1], v2
336; VI-NEXT:    s_endpgm
337;
338; CI-LABEL: shl_imm_v_v2i16:
339; CI:       ; %bb.0:
340; CI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
341; CI-NEXT:    s_mov_b32 s7, 0xf000
342; CI-NEXT:    s_mov_b32 s6, 0
343; CI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
344; CI-NEXT:    v_mov_b32_e32 v1, 0
345; CI-NEXT:    s_waitcnt lgkmcnt(0)
346; CI-NEXT:    s_mov_b64 s[4:5], s[2:3]
347; CI-NEXT:    buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
348; CI-NEXT:    s_mov_b64 s[2:3], s[6:7]
349; CI-NEXT:    s_waitcnt vmcnt(0)
350; CI-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
351; CI-NEXT:    v_lshl_b32_e32 v2, 8, v2
352; CI-NEXT:    v_lshl_b32_e32 v3, 8, v3
353; CI-NEXT:    v_and_b32_e32 v2, 0xfff8, v2
354; CI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
355; CI-NEXT:    v_or_b32_e32 v2, v2, v3
356; CI-NEXT:    buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
357; CI-NEXT:    s_endpgm
358;
359; GFX10-LABEL: shl_imm_v_v2i16:
360; GFX10:       ; %bb.0:
361; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
362; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
363; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
364; GFX10-NEXT:    global_load_dword v1, v0, s[2:3]
365; GFX10-NEXT:    s_waitcnt vmcnt(0)
366; GFX10-NEXT:    v_pk_lshlrev_b16 v1, v1, 8 op_sel_hi:[1,0]
367; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]
368; GFX10-NEXT:    s_endpgm
369  %tid = call i32 @llvm.amdgcn.workitem.id.x()
370  %tid.ext = sext i32 %tid to i64
371  %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
372  %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
373  %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
374  %result = shl <2 x i16> <i16 8, i16 8>, %vgpr
375  store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
376  ret void
377}
378
379define amdgpu_kernel void @shl_v_imm_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
380; GFX9-LABEL: shl_v_imm_v2i16:
381; GFX9:       ; %bb.0:
382; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
383; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
384; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
385; GFX9-NEXT:    global_load_dword v1, v0, s[2:3]
386; GFX9-NEXT:    s_waitcnt vmcnt(0)
387; GFX9-NEXT:    v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
388; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
389; GFX9-NEXT:    s_endpgm
390;
391; VI-LABEL: shl_v_imm_v2i16:
392; VI:       ; %bb.0:
393; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
394; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
395; VI-NEXT:    s_waitcnt lgkmcnt(0)
396; VI-NEXT:    v_mov_b32_e32 v1, s3
397; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2
398; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
399; VI-NEXT:    flat_load_dword v3, v[0:1]
400; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v2
401; VI-NEXT:    v_mov_b32_e32 v1, s1
402; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
403; VI-NEXT:    s_waitcnt vmcnt(0)
404; VI-NEXT:    v_lshlrev_b32_e32 v2, 8, v3
405; VI-NEXT:    v_and_b32_e32 v2, 0xff000000, v2
406; VI-NEXT:    v_lshlrev_b16_e32 v3, 8, v3
407; VI-NEXT:    v_or_b32_e32 v2, v3, v2
408; VI-NEXT:    flat_store_dword v[0:1], v2
409; VI-NEXT:    s_endpgm
410;
411; CI-LABEL: shl_v_imm_v2i16:
412; CI:       ; %bb.0:
413; CI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
414; CI-NEXT:    s_mov_b32 s7, 0xf000
415; CI-NEXT:    s_mov_b32 s6, 0
416; CI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
417; CI-NEXT:    v_mov_b32_e32 v1, 0
418; CI-NEXT:    s_waitcnt lgkmcnt(0)
419; CI-NEXT:    s_mov_b64 s[4:5], s[2:3]
420; CI-NEXT:    buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
421; CI-NEXT:    s_mov_b64 s[2:3], s[6:7]
422; CI-NEXT:    s_waitcnt vmcnt(0)
423; CI-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
424; CI-NEXT:    v_and_b32_e32 v2, 0xff00ff00, v2
425; CI-NEXT:    buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
426; CI-NEXT:    s_endpgm
427;
428; GFX10-LABEL: shl_v_imm_v2i16:
429; GFX10:       ; %bb.0:
430; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
431; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
432; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
433; GFX10-NEXT:    global_load_dword v1, v0, s[2:3]
434; GFX10-NEXT:    s_waitcnt vmcnt(0)
435; GFX10-NEXT:    v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
436; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]
437; GFX10-NEXT:    s_endpgm
438  %tid = call i32 @llvm.amdgcn.workitem.id.x()
439  %tid.ext = sext i32 %tid to i64
440  %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
441  %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
442  %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
443  %result = shl <2 x i16> %vgpr, <i16 8, i16 8>
444  store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
445  ret void
446}
447
448define amdgpu_kernel void @v_shl_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 {
449; GFX9-LABEL: v_shl_v4i16:
450; GFX9:       ; %bb.0:
451; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
452; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
453; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
454; GFX9-NEXT:    global_load_dwordx4 v[0:3], v4, s[2:3]
455; GFX9-NEXT:    s_waitcnt vmcnt(0)
456; GFX9-NEXT:    v_pk_lshlrev_b16 v1, v3, v1
457; GFX9-NEXT:    v_pk_lshlrev_b16 v0, v2, v0
458; GFX9-NEXT:    global_store_dwordx2 v4, v[0:1], s[0:1]
459; GFX9-NEXT:    s_endpgm
460;
461; VI-LABEL: v_shl_v4i16:
462; VI:       ; %bb.0:
463; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
464; VI-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
465; VI-NEXT:    s_waitcnt lgkmcnt(0)
466; VI-NEXT:    v_mov_b32_e32 v1, s3
467; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v4
468; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
469; VI-NEXT:    flat_load_dwordx4 v[0:3], v[0:1]
470; VI-NEXT:    v_mov_b32_e32 v5, s1
471; VI-NEXT:    v_add_u32_e32 v4, vcc, s0, v4
472; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
473; VI-NEXT:    s_waitcnt vmcnt(0)
474; VI-NEXT:    v_lshlrev_b16_e32 v6, v3, v1
475; VI-NEXT:    v_lshlrev_b16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
476; VI-NEXT:    v_lshlrev_b16_e32 v3, v2, v0
477; VI-NEXT:    v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
478; VI-NEXT:    v_or_b32_e32 v1, v6, v1
479; VI-NEXT:    v_or_b32_e32 v0, v3, v0
480; VI-NEXT:    flat_store_dwordx2 v[4:5], v[0:1]
481; VI-NEXT:    s_endpgm
482;
483; CI-LABEL: v_shl_v4i16:
484; CI:       ; %bb.0:
485; CI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
486; CI-NEXT:    s_mov_b32 s7, 0xf000
487; CI-NEXT:    s_mov_b32 s6, 0
488; CI-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
489; CI-NEXT:    v_mov_b32_e32 v5, 0
490; CI-NEXT:    s_waitcnt lgkmcnt(0)
491; CI-NEXT:    s_mov_b64 s[4:5], s[2:3]
492; CI-NEXT:    buffer_load_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr64
493; CI-NEXT:    s_mov_b64 s[2:3], s[6:7]
494; CI-NEXT:    s_waitcnt vmcnt(0)
495; CI-NEXT:    v_lshrrev_b32_e32 v6, 16, v0
496; CI-NEXT:    v_lshrrev_b32_e32 v7, 16, v1
497; CI-NEXT:    v_lshrrev_b32_e32 v8, 16, v2
498; CI-NEXT:    v_lshrrev_b32_e32 v9, 16, v3
499; CI-NEXT:    v_lshlrev_b32_e32 v1, v3, v1
500; CI-NEXT:    v_lshlrev_b32_e32 v0, v2, v0
501; CI-NEXT:    v_lshlrev_b32_e32 v2, v9, v7
502; CI-NEXT:    v_lshlrev_b32_e32 v3, v8, v6
503; CI-NEXT:    v_and_b32_e32 v1, 0xffff, v1
504; CI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
505; CI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
506; CI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
507; CI-NEXT:    v_or_b32_e32 v1, v1, v2
508; CI-NEXT:    v_or_b32_e32 v0, v0, v3
509; CI-NEXT:    buffer_store_dwordx2 v[0:1], v[4:5], s[0:3], 0 addr64
510; CI-NEXT:    s_endpgm
511;
512; GFX10-LABEL: v_shl_v4i16:
513; GFX10:       ; %bb.0:
514; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
515; GFX10-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
516; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
517; GFX10-NEXT:    global_load_dwordx4 v[0:3], v4, s[2:3]
518; GFX10-NEXT:    s_waitcnt vmcnt(0)
519; GFX10-NEXT:    v_pk_lshlrev_b16 v1, v3, v1
520; GFX10-NEXT:    v_pk_lshlrev_b16 v0, v2, v0
521; GFX10-NEXT:    global_store_dwordx2 v4, v[0:1], s[0:1]
522; GFX10-NEXT:    s_endpgm
523  %tid = call i32 @llvm.amdgcn.workitem.id.x()
524  %tid.ext = sext i32 %tid to i64
525  %in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext
526  %out.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %out, i64 %tid.ext
527  %b_ptr = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %in.gep, i32 1
528  %a = load <4 x i16>, <4 x i16> addrspace(1)* %in.gep
529  %b = load <4 x i16>, <4 x i16> addrspace(1)* %b_ptr
530  %result = shl <4 x i16> %a, %b
531  store <4 x i16> %result, <4 x i16> addrspace(1)* %out.gep
532  ret void
533}
534
535define amdgpu_kernel void @shl_v_imm_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 {
536; GFX9-LABEL: shl_v_imm_v4i16:
537; GFX9:       ; %bb.0:
538; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
539; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
540; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
541; GFX9-NEXT:    global_load_dwordx2 v[0:1], v2, s[2:3]
542; GFX9-NEXT:    s_waitcnt vmcnt(0)
543; GFX9-NEXT:    v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
544; GFX9-NEXT:    v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
545; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
546; GFX9-NEXT:    s_endpgm
547;
548; VI-LABEL: shl_v_imm_v4i16:
549; VI:       ; %bb.0:
550; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
551; VI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
552; VI-NEXT:    s_waitcnt lgkmcnt(0)
553; VI-NEXT:    v_mov_b32_e32 v1, s3
554; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2
555; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
556; VI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
557; VI-NEXT:    v_mov_b32_e32 v3, s1
558; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2
559; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
560; VI-NEXT:    s_waitcnt vmcnt(0)
561; VI-NEXT:    v_lshlrev_b32_e32 v4, 8, v1
562; VI-NEXT:    v_lshlrev_b16_e32 v5, 8, v0
563; VI-NEXT:    v_lshlrev_b32_e32 v0, 8, v0
564; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v1
565; VI-NEXT:    v_and_b32_e32 v4, 0xff000000, v4
566; VI-NEXT:    v_and_b32_e32 v0, 0xff000000, v0
567; VI-NEXT:    v_or_b32_e32 v1, v1, v4
568; VI-NEXT:    v_or_b32_e32 v0, v5, v0
569; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
570; VI-NEXT:    s_endpgm
571;
572; CI-LABEL: shl_v_imm_v4i16:
573; CI:       ; %bb.0:
574; CI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
575; CI-NEXT:    s_mov_b32 s7, 0xf000
576; CI-NEXT:    s_mov_b32 s6, 0
577; CI-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
578; CI-NEXT:    v_mov_b32_e32 v1, 0
579; CI-NEXT:    s_waitcnt lgkmcnt(0)
580; CI-NEXT:    s_mov_b64 s[4:5], s[2:3]
581; CI-NEXT:    buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
582; CI-NEXT:    s_mov_b64 s[2:3], s[6:7]
583; CI-NEXT:    s_waitcnt vmcnt(0)
584; CI-NEXT:    v_lshlrev_b32_e32 v4, 8, v3
585; CI-NEXT:    v_lshrrev_b32_e32 v3, 8, v3
586; CI-NEXT:    v_and_b32_e32 v3, 0xff00, v3
587; CI-NEXT:    v_lshlrev_b32_e32 v2, 8, v2
588; CI-NEXT:    v_and_b32_e32 v4, 0xff00, v4
589; CI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
590; CI-NEXT:    v_or_b32_e32 v3, v4, v3
591; CI-NEXT:    v_and_b32_e32 v2, 0xff00ff00, v2
592; CI-NEXT:    buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
593; CI-NEXT:    s_endpgm
594;
595; GFX10-LABEL: shl_v_imm_v4i16:
596; GFX10:       ; %bb.0:
597; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
598; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
599; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
600; GFX10-NEXT:    global_load_dwordx2 v[0:1], v2, s[2:3]
601; GFX10-NEXT:    s_waitcnt vmcnt(0)
602; GFX10-NEXT:    v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
603; GFX10-NEXT:    v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
604; GFX10-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
605; GFX10-NEXT:    s_endpgm
606  %tid = call i32 @llvm.amdgcn.workitem.id.x()
607  %tid.ext = sext i32 %tid to i64
608  %in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext
609  %out.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %out, i64 %tid.ext
610  %vgpr = load <4 x i16>, <4 x i16> addrspace(1)* %in.gep
611  %result = shl <4 x i16> %vgpr, <i16 8, i16 8, i16 8, i16 8>
612  store <4 x i16> %result, <4 x i16> addrspace(1)* %out.gep
613  ret void
614}
615
616declare i32 @llvm.amdgcn.workitem.id.x() #1
617
618attributes #0 = { nounwind }
619attributes #1 = { nounwind readnone }
620