1; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=GCN -check-prefix=SI %s 2; XUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=GCN -check-prefix=VI %s 3; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s 4 5declare i32 @llvm.r600.read.tidig.x() #0 6 7 8;EG: {{^}}shl_v2i32: 9;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 10;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 11 12;SI: {{^}}shl_v2i32: 13;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 14;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 15 16;VI: {{^}}shl_v2i32: 17;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 18;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 19 20define void @shl_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { 21 %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1 22 %a = load <2 x i32>, <2 x i32> addrspace(1) * %in 23 %b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr 24 %result = shl <2 x i32> %a, %b 25 store <2 x i32> %result, <2 x i32> addrspace(1)* %out 26 ret void 27} 28 29;EG: {{^}}shl_v4i32: 30;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 31;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 32;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 33;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 34 35;SI: {{^}}shl_v4i32: 36;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 37;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 38;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 39;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 40 41;VI: {{^}}shl_v4i32: 42;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 43;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 44;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 45;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 46 47define void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { 48 %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1 49 %a = load <4 x i32>, <4 x i32> addrspace(1) * %in 50 %b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr 51 %result = shl <4 x i32> %a, %b 52 store <4 x i32> %result, <4 x i32> addrspace(1)* %out 53 ret void 54} 55 56;VI: {{^}}shl_i16: 57;VI: v_lshlrev_b16_e32 v{{[0-9]+, [0-9]+, [0-9]+}} 58 59define void @shl_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) { 60 %b_ptr = getelementptr i16, i16 addrspace(1)* %in, i16 1 61 %a = load i16, i16 addrspace(1) * %in 62 %b = load i16, i16 addrspace(1) * %b_ptr 63 %result = shl i16 %a, %b 64 store i16 %result, i16 addrspace(1)* %out 65 ret void 66} 67 68 69;VI: {{^}}shl_v2i16: 70;VI: v_lshlrev_b16_e32 v{{[0-9]+, [0-9]+, [0-9]+}} 71;VI: v_lshlrev_b16_e32 v{{[0-9]+, [0-9]+, [0-9]+}} 72 73define void @shl_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) { 74 %b_ptr = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %in, i16 1 75 %a = load <2 x i16>, <2 x i16> addrspace(1) * %in 76 %b = load <2 x i16>, <2 x i16> addrspace(1) * %b_ptr 77 %result = shl <2 x i16> %a, %b 78 store <2 x i16> %result, <2 x i16> addrspace(1)* %out 79 ret void 80} 81 82 83;VI: {{^}}shl_v4i16: 84;VI: v_lshlrev_b16_e32 v{{[0-9]+, [0-9]+, [0-9]+}} 85;VI: v_lshlrev_b16_e32 v{{[0-9]+, [0-9]+, [0-9]+}} 86;VI: v_lshlrev_b16_e32 v{{[0-9]+, [0-9]+, [0-9]+}} 87;VI: v_lshlrev_b16_e32 v{{[0-9]+, [0-9]+, [0-9]+}} 88 89define void @shl_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) { 90 %b_ptr = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %in, i16 1 91 %a = load <4 x i16>, <4 x i16> addrspace(1) * %in 92 %b = load <4 x i16>, <4 x i16> addrspace(1) * %b_ptr 93 %result = shl <4 x i16> %a, %b 94 store <4 x i16> %result, <4 x i16> addrspace(1)* %out 95 ret void 96} 97 98;EG-LABEL: {{^}}shl_i64: 99;EG: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]] 100;EG: LSHR {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}} 101;EG-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal 102;EG-DAG: LSHR {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1 103;EG-DAG: LSHL {{\*? *}}[[HISMTMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], [[SHIFT]] 104;EG-DAG: OR_INT {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], {{[[HISMTMP]]|PV.[XYZW]|PS}}, {{[[OVERF]]|PV.[XYZW]}} 105;EG-DAG: LSHL {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], [[OPLO]], {{PS|[[SHIFT]]|PV.[XYZW]}} 106;EG-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal 107;EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}} 108;EG-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], .*}}, 0.0 109 110;SI: {{^}}shl_i64: 111;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 112 113;VI: {{^}}shl_i64: 114;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 115 116define void @shl_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { 117 %b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1 118 %a = load i64, i64 addrspace(1) * %in 119 %b = load i64, i64 addrspace(1) * %b_ptr 120 %result = shl i64 %a, %b 121 store i64 %result, i64 addrspace(1)* %out 122 ret void 123} 124 125;EG-LABEL: {{^}}shl_v2i64: 126;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] 127;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] 128;EG-DAG: LSHR {{\*? *}}[[COMPSHA]] 129;EG-DAG: LSHR {{\*? *}}[[COMPSHB]] 130;EG-DAG: LSHR {{.*}}, 1 131;EG-DAG: LSHR {{.*}}, 1 132;EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal 133;EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal 134;EG-DAG: LSHL {{.*}}, [[SHA]] 135;EG-DAG: LSHL {{.*}}, [[SHB]] 136;EG-DAG: LSHL {{.*}}, [[SHA]] 137;EG-DAG: LSHL {{.*}}, [[SHB]] 138;EG-DAG: LSHL 139;EG-DAG: LSHL 140;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal 141;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal 142;EG-DAG: CNDE_INT {{.*}}, 0.0 143;EG-DAG: CNDE_INT {{.*}}, 0.0 144;EG-DAG: CNDE_INT 145;EG-DAG: CNDE_INT 146 147;SI: {{^}}shl_v2i64: 148;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 149;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 150 151;VI: {{^}}shl_v2i64: 152;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 153;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 154 155define void @shl_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) { 156 %b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %in, i64 1 157 %a = load <2 x i64>, <2 x i64> addrspace(1) * %in 158 %b = load <2 x i64>, <2 x i64> addrspace(1) * %b_ptr 159 %result = shl <2 x i64> %a, %b 160 store <2 x i64> %result, <2 x i64> addrspace(1)* %out 161 ret void 162} 163 164;EG: {{^}}shl_v4i64: 165;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] 166;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] 167;EG-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]] 168;EG-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]] 169;EG-DAG: LSHR {{\*? *}}[[COMPSHA]] 170;EG-DAG: LSHR {{\*? *}}[[COMPSHB]] 171;EG-DAG: LSHR {{\*? *}}[[COMPSHC]] 172;EG-DAG: LSHR {{\*? *}}[[COMPSHD]] 173;EG-DAG: LSHR {{.*}}, 1 174;EG-DAG: LSHR {{.*}}, 1 175;EG-DAG: LSHR {{.*}}, 1 176;EG-DAG: LSHR {{.*}}, 1 177;EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal 178;EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal 179;EG-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal 180;EG-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal 181;EG-DAG: LSHL {{.*}}, [[SHA]] 182;EG-DAG: LSHL {{.*}}, [[SHB]] 183;EG-DAG: LSHL {{.*}}, [[SHC]] 184;EG-DAG: LSHL {{.*}}, [[SHD]] 185;EG-DAG: LSHL {{.*}}, [[SHA]] 186;EG-DAG: LSHL {{.*}}, [[SHB]] 187;EG-DAG: LSHL {{.*}}, [[SHC]] 188;EG-DAG: LSHL {{.*}}, [[SHD]] 189;EG-DAG: LSHL 190;EG-DAG: LSHL 191;EG-DAG: LSHL 192;EG-DAG: LSHL 193;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal 194;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal 195;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal 196;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal 197;EG-DAG: CNDE_INT {{.*}}, 0.0 198;EG-DAG: CNDE_INT {{.*}}, 0.0 199;EG-DAG: CNDE_INT {{.*}}, 0.0 200;EG-DAG: CNDE_INT {{.*}}, 0.0 201;EG-DAG: CNDE_INT 202;EG-DAG: CNDE_INT 203;EG-DAG: CNDE_INT 204;EG-DAG: CNDE_INT 205 206;SI: {{^}}shl_v4i64: 207;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 208;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 209;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 210;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 211 212;VI: {{^}}shl_v4i64: 213;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 214;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 215;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 216;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 217 218define void @shl_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) { 219 %b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i64 1 220 %a = load <4 x i64>, <4 x i64> addrspace(1) * %in 221 %b = load <4 x i64>, <4 x i64> addrspace(1) * %b_ptr 222 %result = shl <4 x i64> %a, %b 223 store <4 x i64> %result, <4 x i64> addrspace(1)* %out 224 ret void 225} 226 227; Make sure load width gets reduced to i32 load. 228; GCN-LABEL: {{^}}s_shl_32_i64: 229; GCN-DAG: s_load_dword [[LO_A:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb{{$}} 230; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], 0{{$}} 231; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], [[LO_A]] 232; GCN: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} 233define void @s_shl_32_i64(i64 addrspace(1)* %out, i64 %a) { 234 %result = shl i64 %a, 32 235 store i64 %result, i64 addrspace(1)* %out 236 ret void 237} 238 239; GCN-LABEL: {{^}}v_shl_32_i64: 240; GCN-DAG: buffer_load_dword v[[LO_A:[0-9]+]], 241; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], 0{{$}} 242; GCN: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[LO_A]]{{\]}} 243define void @v_shl_32_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { 244 %tid = call i32 @llvm.r600.read.tidig.x() #0 245 %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid 246 %gep.out = getelementptr i64, i64 addrspace(1)* %out, i32 %tid 247 %a = load i64, i64 addrspace(1)* %gep.in 248 %result = shl i64 %a, 32 249 store i64 %result, i64 addrspace(1)* %gep.out 250 ret void 251} 252 253; FUNC-LABEL: {{^}}s_shl_constant_i64 254; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} 255define void @s_shl_constant_i64(i64 addrspace(1)* %out, i64 %a) { 256 %shl = shl i64 281474976710655, %a 257 store i64 %shl, i64 addrspace(1)* %out, align 8 258 ret void 259} 260 261; FUNC-LABEL: {{^}}v_shl_constant_i64: 262; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]] 263; SI-DAG: s_mov_b32 s[[KLO:[0-9]+]], 0xab19b207 264; SI-DAG: s_movk_i32 s[[KHI:[0-9]+]], 0x11e{{$}} 265; SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\]}}, s{{\[}}[[KLO]]:[[KHI]]{{\]}}, [[VAL]] 266; SI: buffer_store_dwordx2 267define void @v_shl_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 268 %a = load i64, i64 addrspace(1)* %aptr, align 8 269 %shl = shl i64 1231231234567, %a 270 store i64 %shl, i64 addrspace(1)* %out, align 8 271 ret void 272} 273 274; FUNC-LABEL: {{^}}v_shl_i64_32_bit_constant: 275; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]] 276; SI-DAG: s_mov_b32 s[[KLO:[0-9]+]], 0x12d687{{$}} 277; SI-DAG: s_mov_b32 s[[KHI:[0-9]+]], 0{{$}} 278; SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\]}}, s{{\[}}[[KLO]]:[[KHI]]{{\]}}, [[VAL]] 279define void @v_shl_i64_32_bit_constant(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 280 %a = load i64, i64 addrspace(1)* %aptr, align 8 281 %shl = shl i64 1234567, %a 282 store i64 %shl, i64 addrspace(1)* %out, align 8 283 ret void 284} 285 286; FUNC-LABEL: {{^}}v_shl_inline_imm_64_i64: 287; SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\]}}, 64, {{v[0-9]+}} 288define void @v_shl_inline_imm_64_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 289 %a = load i64, i64 addrspace(1)* %aptr, align 8 290 %shl = shl i64 64, %a 291 store i64 %shl, i64 addrspace(1)* %out, align 8 292 ret void 293} 294 295; FUNC-LABEL: {{^}}s_shl_inline_imm_64_i64: 296; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 64, s{{[0-9]+}} 297define void @s_shl_inline_imm_64_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 298 %shl = shl i64 64, %a 299 store i64 %shl, i64 addrspace(1)* %out, align 8 300 ret void 301} 302 303; FUNC-LABEL: {{^}}s_shl_inline_imm_1_i64: 304; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 1, s{{[0-9]+}} 305define void @s_shl_inline_imm_1_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 306 %shl = shl i64 1, %a 307 store i64 %shl, i64 addrspace(1)* %out, align 8 308 ret void 309} 310 311; FUNC-LABEL: {{^}}s_shl_inline_imm_1.0_i64: 312; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 1.0, s{{[0-9]+}} 313define void @s_shl_inline_imm_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 314 %shl = shl i64 4607182418800017408, %a 315 store i64 %shl, i64 addrspace(1)* %out, align 8 316 ret void 317} 318 319; FUNC-LABEL: {{^}}s_shl_inline_imm_neg_1.0_i64: 320; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, -1.0, s{{[0-9]+}} 321define void @s_shl_inline_imm_neg_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 322 %shl = shl i64 13830554455654793216, %a 323 store i64 %shl, i64 addrspace(1)* %out, align 8 324 ret void 325} 326 327; FUNC-LABEL: {{^}}s_shl_inline_imm_0.5_i64: 328; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 0.5, s{{[0-9]+}} 329define void @s_shl_inline_imm_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 330 %shl = shl i64 4602678819172646912, %a 331 store i64 %shl, i64 addrspace(1)* %out, align 8 332 ret void 333} 334 335; FUNC-LABEL: {{^}}s_shl_inline_imm_neg_0.5_i64: 336; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, -0.5, s{{[0-9]+}} 337define void @s_shl_inline_imm_neg_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 338 %shl = shl i64 13826050856027422720, %a 339 store i64 %shl, i64 addrspace(1)* %out, align 8 340 ret void 341} 342 343; FUNC-LABEL: {{^}}s_shl_inline_imm_2.0_i64: 344; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 2.0, s{{[0-9]+}} 345define void @s_shl_inline_imm_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 346 %shl = shl i64 4611686018427387904, %a 347 store i64 %shl, i64 addrspace(1)* %out, align 8 348 ret void 349} 350 351; FUNC-LABEL: {{^}}s_shl_inline_imm_neg_2.0_i64: 352; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, -2.0, s{{[0-9]+}} 353define void @s_shl_inline_imm_neg_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 354 %shl = shl i64 13835058055282163712, %a 355 store i64 %shl, i64 addrspace(1)* %out, align 8 356 ret void 357} 358 359; FUNC-LABEL: {{^}}s_shl_inline_imm_4.0_i64: 360; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 4.0, s{{[0-9]+}} 361define void @s_shl_inline_imm_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 362 %shl = shl i64 4616189618054758400, %a 363 store i64 %shl, i64 addrspace(1)* %out, align 8 364 ret void 365} 366 367; FUNC-LABEL: {{^}}s_shl_inline_imm_neg_4.0_i64: 368; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, -4.0, s{{[0-9]+}} 369define void @s_shl_inline_imm_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 370 %shl = shl i64 13839561654909534208, %a 371 store i64 %shl, i64 addrspace(1)* %out, align 8 372 ret void 373} 374 375 376; Test with the 64-bit integer bitpattern for a 32-bit float in the 377; low 32-bits, which is not a valid 64-bit inline immmediate. 378 379; FUNC-LABEL: {{^}}s_shl_inline_imm_f32_4.0_i64: 380; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 4.0 381; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0{{$}} 382; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}, s{{[0-9]+}} 383define void @s_shl_inline_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 384 %shl = shl i64 1082130432, %a 385 store i64 %shl, i64 addrspace(1)* %out, align 8 386 ret void 387} 388 389; FIXME: Copy of -1 register 390; FUNC-LABEL: {{^}}s_shl_inline_imm_f32_neg_4.0_i64: 391; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], -4.0 392; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], -1{{$}} 393; SI-DAG: s_mov_b32 s[[K_HI_COPY:[0-9]+]], s[[K_HI]] 394; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI_COPY]]{{\]}}, s{{[0-9]+}} 395define void @s_shl_inline_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 396 %shl = shl i64 -1065353216, %a 397 store i64 %shl, i64 addrspace(1)* %out, align 8 398 ret void 399} 400 401; Shift into upper 32-bits 402; FUNC-LABEL: {{^}}s_shl_inline_high_imm_f32_4.0_i64: 403; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 4.0 404; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}} 405; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}, s{{[0-9]+}} 406define void @s_shl_inline_high_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 407 %shl = shl i64 4647714815446351872, %a 408 store i64 %shl, i64 addrspace(1)* %out, align 8 409 ret void 410} 411 412; FUNC-LABEL: {{^}}s_shl_inline_high_imm_f32_neg_4.0_i64: 413; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], -4.0 414; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}} 415; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}, s{{[0-9]+}} 416define void @s_shl_inline_high_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 417 %shl = shl i64 13871086852301127680, %a 418 store i64 %shl, i64 addrspace(1)* %out, align 8 419 ret void 420} 421 422attributes #0 = { nounwind readnone } 423