1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn-- -mcpu=verde -verify-machineinstrs | FileCheck %s -allow-deprecated-dag-overlap --check-prefix=GCN 3; XUN: llc < %s -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,VI 4; RUN: llc < %s -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600-- -mcpu=redwood -verify-machineinstrs | FileCheck %s -allow-deprecated-dag-overlap --check-prefix=EG 5 6declare i32 @llvm.amdgcn.workitem.id.x() #0 7 8declare i32 @llvm.amdgcn.workgroup.id.x() #0 9 10define amdgpu_kernel void @shl_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { 11; GCN-LABEL: shl_v2i32: 12; GCN: ; %bb.0: 13; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 14; GCN-NEXT: s_mov_b32 s3, 0xf000 15; GCN-NEXT: s_mov_b32 s2, -1 16; GCN-NEXT: s_mov_b32 s10, s2 17; GCN-NEXT: s_mov_b32 s11, s3 18; GCN-NEXT: s_waitcnt lgkmcnt(0) 19; GCN-NEXT: s_mov_b32 s8, s6 20; GCN-NEXT: s_mov_b32 s9, s7 21; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 22; GCN-NEXT: s_mov_b32 s0, s4 23; GCN-NEXT: s_mov_b32 s1, s5 24; GCN-NEXT: s_waitcnt vmcnt(0) 25; GCN-NEXT: v_lshl_b32_e32 v1, v1, v3 26; GCN-NEXT: v_lshl_b32_e32 v0, v0, v2 27; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 28; GCN-NEXT: s_endpgm 29; 30; EG-LABEL: shl_v2i32: 31; EG: ; %bb.0: 32; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] 33; EG-NEXT: TEX 1 @6 34; EG-NEXT: ALU 3, @11, KC0[CB0:0-32], KC1[] 35; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 36; EG-NEXT: CF_END 37; EG-NEXT: PAD 38; EG-NEXT: Fetch clause starting at 6: 39; EG-NEXT: VTX_READ_64 T1.XY, T0.X, 8, #1 40; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1 41; EG-NEXT: ALU clause starting at 10: 42; EG-NEXT: MOV * T0.X, KC0[2].Z, 43; EG-NEXT: ALU clause starting at 11: 44; EG-NEXT: LSHL * T0.Y, T0.Y, T1.Y, 45; EG-NEXT: LSHL T0.X, T0.X, T1.X, 46; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 47; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 48 %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1 49 %a = load <2 x i32>, <2 x i32> addrspace(1)* %in 50 %b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr 51 %result = shl <2 x i32> %a, %b 52 store <2 x i32> %result, <2 x i32> addrspace(1)* %out 53 ret void 54} 55 56define amdgpu_kernel void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { 57; GCN-LABEL: shl_v4i32: 58; GCN: ; %bb.0: 59; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 60; GCN-NEXT: s_mov_b32 s3, 0xf000 61; GCN-NEXT: s_mov_b32 s2, -1 62; GCN-NEXT: s_mov_b32 s10, s2 63; GCN-NEXT: s_mov_b32 s11, s3 64; GCN-NEXT: s_waitcnt lgkmcnt(0) 65; GCN-NEXT: s_mov_b32 s8, s6 66; GCN-NEXT: s_mov_b32 s9, s7 67; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 68; GCN-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16 69; GCN-NEXT: s_mov_b32 s0, s4 70; GCN-NEXT: s_mov_b32 s1, s5 71; GCN-NEXT: s_waitcnt vmcnt(0) 72; GCN-NEXT: v_lshl_b32_e32 v3, v3, v7 73; GCN-NEXT: v_lshl_b32_e32 v2, v2, v6 74; GCN-NEXT: v_lshl_b32_e32 v1, v1, v5 75; GCN-NEXT: v_lshl_b32_e32 v0, v0, v4 76; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 77; GCN-NEXT: s_endpgm 78; 79; EG-LABEL: shl_v4i32: 80; EG: ; %bb.0: 81; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] 82; EG-NEXT: TEX 1 @6 83; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[] 84; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1 85; EG-NEXT: CF_END 86; EG-NEXT: PAD 87; EG-NEXT: Fetch clause starting at 6: 88; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1 89; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1 90; EG-NEXT: ALU clause starting at 10: 91; EG-NEXT: MOV * T0.X, KC0[2].Z, 92; EG-NEXT: ALU clause starting at 11: 93; EG-NEXT: LSHL * T0.W, T0.W, T1.W, 94; EG-NEXT: LSHL * T0.Z, T0.Z, T1.Z, 95; EG-NEXT: LSHL * T0.Y, T0.Y, T1.Y, 96; EG-NEXT: LSHL T0.X, T0.X, T1.X, 97; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 98; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 99 %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1 100 %a = load <4 x i32>, <4 x i32> addrspace(1)* %in 101 %b = load <4 x i32>, <4 x i32> addrspace(1)* %b_ptr 102 %result = shl <4 x i32> %a, %b 103 store <4 x i32> %result, <4 x i32> addrspace(1)* %out 104 ret void 105} 106 107define amdgpu_kernel void @shl_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) { 108; GCN-LABEL: shl_i16: 109; GCN: ; %bb.0: 110; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 111; GCN-NEXT: s_mov_b32 s3, 0xf000 112; GCN-NEXT: s_mov_b32 s2, -1 113; GCN-NEXT: s_waitcnt lgkmcnt(0) 114; GCN-NEXT: s_mov_b32 s0, s4 115; GCN-NEXT: s_mov_b32 s1, s5 116; GCN-NEXT: s_mov_b32 s4, s6 117; GCN-NEXT: s_mov_b32 s5, s7 118; GCN-NEXT: s_mov_b32 s6, s2 119; GCN-NEXT: s_mov_b32 s7, s3 120; GCN-NEXT: buffer_load_ushort v0, off, s[4:7], 0 121; GCN-NEXT: buffer_load_ushort v1, off, s[4:7], 0 offset:2 122; GCN-NEXT: s_waitcnt vmcnt(0) 123; GCN-NEXT: v_lshlrev_b32_e32 v0, v1, v0 124; GCN-NEXT: buffer_store_short v0, off, s[0:3], 0 125; GCN-NEXT: s_endpgm 126; 127; EG-LABEL: shl_i16: 128; EG: ; %bb.0: 129; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] 130; EG-NEXT: TEX 1 @6 131; EG-NEXT: ALU 12, @11, KC0[CB0:0-32], KC1[] 132; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X 133; EG-NEXT: CF_END 134; EG-NEXT: PAD 135; EG-NEXT: Fetch clause starting at 6: 136; EG-NEXT: VTX_READ_16 T1.X, T0.X, 2, #1 137; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #1 138; EG-NEXT: ALU clause starting at 10: 139; EG-NEXT: MOV * T0.X, KC0[2].Z, 140; EG-NEXT: ALU clause starting at 11: 141; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x, 142; EG-NEXT: LSHL * T1.W, T0.X, T1.X, 143; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) 144; EG-NEXT: AND_INT T1.W, PS, literal.x, 145; EG-NEXT: LSHL * T0.W, PV.W, literal.y, 146; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45) 147; EG-NEXT: LSHL T0.X, PV.W, PS, 148; EG-NEXT: LSHL * T0.W, literal.x, PS, 149; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) 150; EG-NEXT: MOV T0.Y, 0.0, 151; EG-NEXT: MOV * T0.Z, 0.0, 152; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 153; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 154 %b_ptr = getelementptr i16, i16 addrspace(1)* %in, i16 1 155 %a = load i16, i16 addrspace(1)* %in 156 %b = load i16, i16 addrspace(1)* %b_ptr 157 %result = shl i16 %a, %b 158 store i16 %result, i16 addrspace(1)* %out 159 ret void 160} 161 162define amdgpu_kernel void @shl_i16_v_s(i16 addrspace(1)* %out, i16 addrspace(1)* %in, i16 %b) { 163; GCN-LABEL: shl_i16_v_s: 164; GCN: ; %bb.0: 165; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 166; GCN-NEXT: s_load_dword s8, s[0:1], 0xd 167; GCN-NEXT: s_mov_b32 s3, 0xf000 168; GCN-NEXT: s_mov_b32 s2, -1 169; GCN-NEXT: s_waitcnt lgkmcnt(0) 170; GCN-NEXT: s_mov_b32 s0, s4 171; GCN-NEXT: s_mov_b32 s1, s5 172; GCN-NEXT: s_mov_b32 s4, s6 173; GCN-NEXT: s_mov_b32 s5, s7 174; GCN-NEXT: s_mov_b32 s6, s2 175; GCN-NEXT: s_mov_b32 s7, s3 176; GCN-NEXT: buffer_load_ushort v0, off, s[4:7], 0 177; GCN-NEXT: s_and_b32 s8, s8, 0xffff 178; GCN-NEXT: s_waitcnt vmcnt(0) 179; GCN-NEXT: v_lshlrev_b32_e32 v0, s8, v0 180; GCN-NEXT: buffer_store_short v0, off, s[0:3], 0 181; GCN-NEXT: s_endpgm 182; 183; EG-LABEL: shl_i16_v_s: 184; EG: ; %bb.0: 185; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[] 186; EG-NEXT: TEX 1 @6 187; EG-NEXT: ALU 12, @12, KC0[CB0:0-32], KC1[] 188; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X 189; EG-NEXT: CF_END 190; EG-NEXT: PAD 191; EG-NEXT: Fetch clause starting at 6: 192; EG-NEXT: VTX_READ_16 T1.X, T1.X, 0, #1 193; EG-NEXT: VTX_READ_16 T0.X, T0.X, 44, #3 194; EG-NEXT: ALU clause starting at 10: 195; EG-NEXT: MOV T0.X, 0.0, 196; EG-NEXT: MOV * T1.X, KC0[2].Z, 197; EG-NEXT: ALU clause starting at 12: 198; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x, 199; EG-NEXT: LSHL * T1.W, T1.X, T0.X, 200; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) 201; EG-NEXT: AND_INT T1.W, PS, literal.x, 202; EG-NEXT: LSHL * T0.W, PV.W, literal.y, 203; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45) 204; EG-NEXT: LSHL T0.X, PV.W, PS, 205; EG-NEXT: LSHL * T0.W, literal.x, PS, 206; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) 207; EG-NEXT: MOV T0.Y, 0.0, 208; EG-NEXT: MOV * T0.Z, 0.0, 209; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 210; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 211 %a = load i16, i16 addrspace(1)* %in 212 %result = shl i16 %a, %b 213 store i16 %result, i16 addrspace(1)* %out 214 ret void 215} 216 217define amdgpu_kernel void @shl_i16_v_compute_s(i16 addrspace(1)* %out, i16 addrspace(1)* %in, i16 %b) { 218; GCN-LABEL: shl_i16_v_compute_s: 219; GCN: ; %bb.0: 220; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 221; GCN-NEXT: s_load_dword s8, s[0:1], 0xd 222; GCN-NEXT: s_mov_b32 s3, 0xf000 223; GCN-NEXT: s_mov_b32 s2, -1 224; GCN-NEXT: s_waitcnt lgkmcnt(0) 225; GCN-NEXT: s_mov_b32 s0, s4 226; GCN-NEXT: s_mov_b32 s1, s5 227; GCN-NEXT: s_mov_b32 s4, s6 228; GCN-NEXT: s_mov_b32 s5, s7 229; GCN-NEXT: s_mov_b32 s6, s2 230; GCN-NEXT: s_mov_b32 s7, s3 231; GCN-NEXT: buffer_load_ushort v0, off, s[4:7], 0 232; GCN-NEXT: s_add_i32 s8, s8, 3 233; GCN-NEXT: s_and_b32 s4, s8, 0xffff 234; GCN-NEXT: s_waitcnt vmcnt(0) 235; GCN-NEXT: v_lshlrev_b32_e32 v0, s4, v0 236; GCN-NEXT: buffer_store_short v0, off, s[0:3], 0 237; GCN-NEXT: s_endpgm 238; 239; EG-LABEL: shl_i16_v_compute_s: 240; EG: ; %bb.0: 241; EG-NEXT: ALU 0, @12, KC0[], KC1[] 242; EG-NEXT: TEX 0 @8 243; EG-NEXT: ALU 0, @13, KC0[CB0:0-32], KC1[] 244; EG-NEXT: TEX 0 @10 245; EG-NEXT: ALU 15, @14, KC0[CB0:0-32], KC1[] 246; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X 247; EG-NEXT: CF_END 248; EG-NEXT: PAD 249; EG-NEXT: Fetch clause starting at 8: 250; EG-NEXT: VTX_READ_16 T0.X, T0.X, 44, #3 251; EG-NEXT: Fetch clause starting at 10: 252; EG-NEXT: VTX_READ_16 T1.X, T1.X, 0, #1 253; EG-NEXT: ALU clause starting at 12: 254; EG-NEXT: MOV * T0.X, 0.0, 255; EG-NEXT: ALU clause starting at 13: 256; EG-NEXT: MOV * T1.X, KC0[2].Z, 257; EG-NEXT: ALU clause starting at 14: 258; EG-NEXT: ADD_INT * T0.W, T0.X, literal.x, 259; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) 260; EG-NEXT: AND_INT T0.W, PV.W, literal.x, 261; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y, 262; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45) 263; EG-NEXT: LSHL * T0.W, T1.X, PV.W, 264; EG-NEXT: AND_INT T0.W, PV.W, literal.x, 265; EG-NEXT: LSHL * T1.W, T1.W, literal.y, 266; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45) 267; EG-NEXT: LSHL T0.X, PV.W, PS, 268; EG-NEXT: LSHL * T0.W, literal.x, PS, 269; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) 270; EG-NEXT: MOV T0.Y, 0.0, 271; EG-NEXT: MOV * T0.Z, 0.0, 272; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 273; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 274 %a = load i16, i16 addrspace(1)* %in 275 %b.add = add i16 %b, 3 276 %result = shl i16 %a, %b.add 277 store i16 %result, i16 addrspace(1)* %out 278 ret void 279} 280 281define amdgpu_kernel void @shl_i16_computed_amount(i16 addrspace(1)* %out, i16 addrspace(1)* %in) { 282; GCN-LABEL: shl_i16_computed_amount: 283; GCN: ; %bb.0: 284; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 285; GCN-NEXT: s_mov_b32 s3, 0xf000 286; GCN-NEXT: s_mov_b32 s2, -1 287; GCN-NEXT: s_mov_b32 s10, s2 288; GCN-NEXT: s_mov_b32 s11, s3 289; GCN-NEXT: s_waitcnt lgkmcnt(0) 290; GCN-NEXT: s_mov_b32 s8, s6 291; GCN-NEXT: s_mov_b32 s9, s7 292; GCN-NEXT: v_lshlrev_b32_e32 v0, 1, v0 293; GCN-NEXT: v_mov_b32_e32 v1, 0 294; GCN-NEXT: s_mov_b32 s14, 0 295; GCN-NEXT: s_mov_b32 s15, s3 296; GCN-NEXT: s_mov_b64 s[12:13], s[6:7] 297; GCN-NEXT: buffer_load_ushort v2, off, s[8:11], 0 glc 298; GCN-NEXT: s_waitcnt vmcnt(0) 299; GCN-NEXT: buffer_load_ushort v0, v[0:1], s[12:15], 0 addr64 offset:2 glc 300; GCN-NEXT: s_waitcnt vmcnt(0) 301; GCN-NEXT: s_mov_b32 s0, s4 302; GCN-NEXT: s_mov_b32 s1, s5 303; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 304; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 305; GCN-NEXT: v_lshl_b32_e32 v0, v2, v0 306; GCN-NEXT: buffer_store_short v0, off, s[0:3], 0 307; GCN-NEXT: s_endpgm 308; 309; EG-LABEL: shl_i16_computed_amount: 310; EG: ; %bb.0: 311; EG-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[] 312; EG-NEXT: TEX 0 @8 313; EG-NEXT: ALU 1, @13, KC0[CB0:0-32], KC1[] 314; EG-NEXT: TEX 0 @10 315; EG-NEXT: ALU 15, @15, KC0[CB0:0-32], KC1[] 316; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X 317; EG-NEXT: CF_END 318; EG-NEXT: PAD 319; EG-NEXT: Fetch clause starting at 8: 320; EG-NEXT: VTX_READ_16 T1.X, T1.X, 0, #1 321; EG-NEXT: Fetch clause starting at 10: 322; EG-NEXT: VTX_READ_16 T0.X, T0.X, 2, #1 323; EG-NEXT: ALU clause starting at 12: 324; EG-NEXT: MOV * T1.X, KC0[2].Z, 325; EG-NEXT: ALU clause starting at 13: 326; EG-NEXT: LSHL * T0.W, T0.X, 1, 327; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, 328; EG-NEXT: ALU clause starting at 15: 329; EG-NEXT: ADD_INT * T0.W, T0.X, literal.x, 330; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) 331; EG-NEXT: AND_INT T0.W, PV.W, literal.x, 332; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y, 333; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45) 334; EG-NEXT: LSHL * T0.W, T1.X, PV.W, 335; EG-NEXT: AND_INT T0.W, PV.W, literal.x, 336; EG-NEXT: LSHL * T1.W, T1.W, literal.y, 337; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45) 338; EG-NEXT: LSHL T0.X, PV.W, PS, 339; EG-NEXT: LSHL * T0.W, literal.x, PS, 340; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) 341; EG-NEXT: MOV T0.Y, 0.0, 342; EG-NEXT: MOV * T0.Z, 0.0, 343; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 344; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 345 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 346 %gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i32 %tid 347 %gep.out = getelementptr inbounds i16, i16 addrspace(1)* %out, i32 %tid 348 %b_ptr = getelementptr i16, i16 addrspace(1)* %gep, i16 1 349 %a = load volatile i16, i16 addrspace(1)* %in 350 %b = load volatile i16, i16 addrspace(1)* %b_ptr 351 %b.add = add i16 %b, 3 352 %result = shl i16 %a, %b.add 353 store i16 %result, i16 addrspace(1)* %out 354 ret void 355} 356 357define amdgpu_kernel void @shl_i16_i_s(i16 addrspace(1)* %out, i16 zeroext %a) { 358; GCN-LABEL: shl_i16_i_s: 359; GCN: ; %bb.0: 360; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 361; GCN-NEXT: s_load_dword s0, s[0:1], 0xb 362; GCN-NEXT: s_mov_b32 s7, 0xf000 363; GCN-NEXT: s_mov_b32 s6, -1 364; GCN-NEXT: s_waitcnt lgkmcnt(0) 365; GCN-NEXT: s_lshl_b32 s0, s0, 12 366; GCN-NEXT: v_mov_b32_e32 v0, s0 367; GCN-NEXT: buffer_store_short v0, off, s[4:7], 0 368; GCN-NEXT: s_endpgm 369; 370; EG-LABEL: shl_i16_i_s: 371; EG: ; %bb.0: 372; EG-NEXT: ALU 0, @8, KC0[], KC1[] 373; EG-NEXT: TEX 0 @6 374; EG-NEXT: ALU 14, @9, KC0[CB0:0-32], KC1[] 375; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X 376; EG-NEXT: CF_END 377; EG-NEXT: PAD 378; EG-NEXT: Fetch clause starting at 6: 379; EG-NEXT: VTX_READ_16 T0.X, T0.X, 40, #3 380; EG-NEXT: ALU clause starting at 8: 381; EG-NEXT: MOV * T0.X, 0.0, 382; EG-NEXT: ALU clause starting at 9: 383; EG-NEXT: BFE_INT T0.W, T0.X, 0.0, literal.x, 384; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y, 385; EG-NEXT: 16(2.242078e-44), 3(4.203895e-45) 386; EG-NEXT: LSHL * T0.W, PV.W, literal.x, 387; EG-NEXT: 12(1.681558e-44), 0(0.000000e+00) 388; EG-NEXT: AND_INT T0.W, PV.W, literal.x, 389; EG-NEXT: LSHL * T1.W, T1.W, literal.y, 390; EG-NEXT: 61440(8.609578e-41), 3(4.203895e-45) 391; EG-NEXT: LSHL T0.X, PV.W, PS, 392; EG-NEXT: LSHL * T0.W, literal.x, PS, 393; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) 394; EG-NEXT: MOV T0.Y, 0.0, 395; EG-NEXT: MOV * T0.Z, 0.0, 396; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 397; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 398 %result = shl i16 %a, 12 399 store i16 %result, i16 addrspace(1)* %out 400 ret void 401} 402 403define amdgpu_kernel void @shl_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) { 404; GCN-LABEL: shl_v2i16: 405; GCN: ; %bb.0: 406; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 407; GCN-NEXT: s_mov_b32 s3, 0xf000 408; GCN-NEXT: s_mov_b32 s2, -1 409; GCN-NEXT: s_mov_b32 s10, s2 410; GCN-NEXT: s_mov_b32 s11, s3 411; GCN-NEXT: s_waitcnt lgkmcnt(0) 412; GCN-NEXT: s_mov_b32 s8, s6 413; GCN-NEXT: s_mov_b32 s9, s7 414; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0 415; GCN-NEXT: s_mov_b64 s[12:13], s[6:7] 416; GCN-NEXT: v_mov_b32_e32 v1, 0 417; GCN-NEXT: s_mov_b32 s14, 0 418; GCN-NEXT: s_mov_b32 s15, s3 419; GCN-NEXT: buffer_load_dword v2, off, s[8:11], 0 420; GCN-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64 offset:4 421; GCN-NEXT: s_mov_b32 s6, 0xffff 422; GCN-NEXT: s_mov_b32 s0, s4 423; GCN-NEXT: s_mov_b32 s1, s5 424; GCN-NEXT: s_waitcnt vmcnt(1) 425; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v2 426; GCN-NEXT: s_waitcnt vmcnt(0) 427; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v0 428; GCN-NEXT: v_and_b32_e32 v0, s6, v0 429; GCN-NEXT: v_lshl_b32_e32 v0, v2, v0 430; GCN-NEXT: v_lshl_b32_e32 v1, v1, v3 431; GCN-NEXT: v_and_b32_e32 v0, s6, v0 432; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 433; GCN-NEXT: v_or_b32_e32 v0, v0, v1 434; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 435; GCN-NEXT: s_endpgm 436; 437; EG-LABEL: shl_v2i16: 438; EG: ; %bb.0: 439; EG-NEXT: ALU 2, @12, KC0[CB0:0-32], KC1[] 440; EG-NEXT: TEX 0 @8 441; EG-NEXT: ALU 0, @15, KC0[CB0:0-32], KC1[] 442; EG-NEXT: TEX 0 @10 443; EG-NEXT: ALU 12, @16, KC0[CB0:0-32], KC1[] 444; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T7.X, 1 445; EG-NEXT: CF_END 446; EG-NEXT: PAD 447; EG-NEXT: Fetch clause starting at 8: 448; EG-NEXT: VTX_READ_32 T0.X, T0.X, 4, #1 449; EG-NEXT: Fetch clause starting at 10: 450; EG-NEXT: VTX_READ_32 T7.X, T7.X, 0, #1 451; EG-NEXT: ALU clause starting at 12: 452; EG-NEXT: LSHL * T0.W, T0.X, literal.x, 453; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 454; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, 455; EG-NEXT: ALU clause starting at 15: 456; EG-NEXT: MOV * T7.X, KC0[2].Z, 457; EG-NEXT: ALU clause starting at 16: 458; EG-NEXT: AND_INT T0.Y, T0.X, literal.x, 459; EG-NEXT: AND_INT T0.Z, T7.X, literal.x, BS:VEC_120/SCL_212 460; EG-NEXT: LSHR T0.W, T0.X, literal.y, 461; EG-NEXT: LSHR * T1.W, T7.X, literal.y, 462; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) 463; EG-NEXT: LSHL T0.W, PS, PV.W, 464; EG-NEXT: LSHL * T1.W, PV.Z, PV.Y, 465; EG-NEXT: AND_INT T1.W, PS, literal.x, 466; EG-NEXT: LSHL * T0.W, PV.W, literal.y, 467; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) 468; EG-NEXT: OR_INT T0.X, PV.W, PS, 469; EG-NEXT: LSHR * T7.X, KC0[2].Y, literal.x, 470; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 471 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 472 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i32 %tid 473 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid 474 %b_ptr = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %gep, i16 1 475 %a = load <2 x i16>, <2 x i16> addrspace(1)* %in 476 %b = load <2 x i16>, <2 x i16> addrspace(1)* %b_ptr 477 %result = shl <2 x i16> %a, %b 478 store <2 x i16> %result, <2 x i16> addrspace(1)* %out 479 ret void 480} 481 482define amdgpu_kernel void @shl_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) { 483; GCN-LABEL: shl_v4i16: 484; GCN: ; %bb.0: 485; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 486; GCN-NEXT: s_mov_b32 s3, 0xf000 487; GCN-NEXT: s_mov_b32 s2, 0 488; GCN-NEXT: v_lshlrev_b32_e32 v0, 3, v0 489; GCN-NEXT: v_mov_b32_e32 v1, 0 490; GCN-NEXT: s_waitcnt lgkmcnt(0) 491; GCN-NEXT: s_mov_b64 s[0:1], s[6:7] 492; GCN-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 493; GCN-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[0:3], 0 addr64 offset:8 494; GCN-NEXT: s_mov_b32 s0, 0xffff 495; GCN-NEXT: s_mov_b64 s[6:7], s[2:3] 496; GCN-NEXT: s_waitcnt vmcnt(1) 497; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v2 498; GCN-NEXT: s_waitcnt vmcnt(0) 499; GCN-NEXT: v_and_b32_e32 v8, s0, v4 500; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v4 501; GCN-NEXT: v_and_b32_e32 v9, s0, v5 502; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v3 503; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v5 504; GCN-NEXT: v_lshl_b32_e32 v5, v7, v5 505; GCN-NEXT: v_lshl_b32_e32 v3, v3, v9 506; GCN-NEXT: v_lshl_b32_e32 v4, v6, v4 507; GCN-NEXT: v_lshl_b32_e32 v2, v2, v8 508; GCN-NEXT: v_lshlrev_b32_e32 v5, 16, v5 509; GCN-NEXT: v_and_b32_e32 v3, s0, v3 510; GCN-NEXT: v_lshlrev_b32_e32 v4, 16, v4 511; GCN-NEXT: v_and_b32_e32 v2, s0, v2 512; GCN-NEXT: v_or_b32_e32 v3, v3, v5 513; GCN-NEXT: v_or_b32_e32 v2, v2, v4 514; GCN-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 515; GCN-NEXT: s_endpgm 516; 517; EG-LABEL: shl_v4i16: 518; EG: ; %bb.0: 519; EG-NEXT: ALU 2, @12, KC0[CB0:0-32], KC1[] 520; EG-NEXT: TEX 0 @8 521; EG-NEXT: ALU 3, @15, KC0[], KC1[] 522; EG-NEXT: TEX 0 @10 523; EG-NEXT: ALU 49, @19, KC0[CB0:0-32], KC1[] 524; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T10.XY, T0.X, 1 525; EG-NEXT: CF_END 526; EG-NEXT: PAD 527; EG-NEXT: Fetch clause starting at 8: 528; EG-NEXT: VTX_READ_64 T10.XY, T0.X, 0, #1 529; EG-NEXT: Fetch clause starting at 10: 530; EG-NEXT: VTX_READ_64 T10.XY, T0.X, 8, #1 531; EG-NEXT: ALU clause starting at 12: 532; EG-NEXT: LSHL * T0.W, T0.X, literal.x, 533; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) 534; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, 535; EG-NEXT: ALU clause starting at 15: 536; EG-NEXT: MOV T4.X, T10.X, 537; EG-NEXT: MOV * T5.X, T10.Y, 538; EG-NEXT: MOV T0.Y, PV.X, 539; EG-NEXT: MOV * T0.Z, PS, 540; EG-NEXT: ALU clause starting at 19: 541; EG-NEXT: MOV T2.X, T10.X, 542; EG-NEXT: MOV * T3.X, T10.Y, 543; EG-NEXT: MOV T0.X, T6.X, 544; EG-NEXT: MOV * T1.Y, PV.X, 545; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, 546; EG-NEXT: AND_INT * T2.W, T0.Y, literal.x, 547; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) 548; EG-NEXT: LSHL * T1.W, PS, PV.W, 549; EG-NEXT: AND_INT T1.W, PV.W, literal.x, 550; EG-NEXT: AND_INT * T2.W, T0.X, literal.y, 551; EG-NEXT: 65535(9.183409e-41), -65536(nan) 552; EG-NEXT: OR_INT * T1.W, PS, PV.W, 553; EG-NEXT: MOV T0.X, T3.X, 554; EG-NEXT: MOV * T6.X, PV.W, 555; EG-NEXT: MOV T1.Z, PS, 556; EG-NEXT: LSHR T1.W, T1.Y, literal.x, 557; EG-NEXT: LSHR * T2.W, T0.Y, literal.x, 558; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) 559; EG-NEXT: LSHL T1.W, PS, PV.W, 560; EG-NEXT: AND_INT * T2.W, PV.Z, literal.x, 561; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) 562; EG-NEXT: LSHL * T1.W, PV.W, literal.x, 563; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) 564; EG-NEXT: OR_INT * T1.W, T2.W, PV.W, 565; EG-NEXT: MOV T6.X, PV.W, 566; EG-NEXT: MOV T0.Y, T7.X, 567; EG-NEXT: AND_INT T1.W, T0.X, literal.x, BS:VEC_120/SCL_212 568; EG-NEXT: AND_INT * T2.W, T0.Z, literal.x, 569; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) 570; EG-NEXT: LSHL T1.W, PS, PV.W, 571; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x, 572; EG-NEXT: -65536(nan), 0(0.000000e+00) 573; EG-NEXT: AND_INT * T1.W, PV.W, literal.x, 574; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) 575; EG-NEXT: OR_INT * T1.W, T2.W, PV.W, 576; EG-NEXT: MOV * T7.X, PV.W, 577; EG-NEXT: MOV T0.Y, PV.X, 578; EG-NEXT: LSHR T1.W, T0.X, literal.x, 579; EG-NEXT: LSHR * T2.W, T0.Z, literal.x, 580; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) 581; EG-NEXT: LSHL * T1.W, PS, PV.W, 582; EG-NEXT: AND_INT T0.Z, T0.Y, literal.x, 583; EG-NEXT: LSHL T1.W, PV.W, literal.y, 584; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W, 585; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) 586; EG-NEXT: LSHR T0.X, PS, literal.x, 587; EG-NEXT: OR_INT * T10.Y, PV.Z, PV.W, 588; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 589; EG-NEXT: MOV T7.X, PV.Y, 590; EG-NEXT: MOV * T10.X, T6.X, 591 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 592 %gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i32 %tid 593 %gep.out = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %out, i32 %tid 594 %b_ptr = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %gep, i16 1 595 %a = load <4 x i16>, <4 x i16> addrspace(1)* %gep 596 %b = load <4 x i16>, <4 x i16> addrspace(1)* %b_ptr 597 %result = shl <4 x i16> %a, %b 598 store <4 x i16> %result, <4 x i16> addrspace(1)* %gep.out 599 ret void 600} 601 602define amdgpu_kernel void @shl_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { 603; GCN-LABEL: shl_i64: 604; GCN: ; %bb.0: 605; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 606; GCN-NEXT: s_mov_b32 s3, 0xf000 607; GCN-NEXT: s_mov_b32 s2, -1 608; GCN-NEXT: s_mov_b32 s10, s2 609; GCN-NEXT: s_mov_b32 s11, s3 610; GCN-NEXT: s_waitcnt lgkmcnt(0) 611; GCN-NEXT: s_mov_b32 s8, s6 612; GCN-NEXT: s_mov_b32 s9, s7 613; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 614; GCN-NEXT: s_mov_b32 s0, s4 615; GCN-NEXT: s_mov_b32 s1, s5 616; GCN-NEXT: s_waitcnt vmcnt(0) 617; GCN-NEXT: v_lshl_b64 v[0:1], v[0:1], v2 618; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 619; GCN-NEXT: s_endpgm 620; 621; EG-LABEL: shl_i64: 622; EG: ; %bb.0: 623; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] 624; EG-NEXT: TEX 0 @6 625; EG-NEXT: ALU 15, @9, KC0[CB0:0-32], KC1[] 626; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 627; EG-NEXT: CF_END 628; EG-NEXT: PAD 629; EG-NEXT: Fetch clause starting at 6: 630; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1 631; EG-NEXT: ALU clause starting at 8: 632; EG-NEXT: MOV * T0.X, KC0[2].Z, 633; EG-NEXT: ALU clause starting at 9: 634; EG-NEXT: SUB_INT * T0.W, literal.x, T0.Z, 635; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 636; EG-NEXT: LSHR * T0.W, T0.X, PV.W, 637; EG-NEXT: ADD_INT T1.Z, T0.Z, literal.x, 638; EG-NEXT: LSHR T0.W, PV.W, 1, 639; EG-NEXT: LSHL * T1.W, T0.Y, T0.Z, 640; EG-NEXT: -32(nan), 0(0.000000e+00) 641; EG-NEXT: OR_INT T2.Z, PS, PV.W, 642; EG-NEXT: LSHL T0.W, T0.X, PV.Z, 643; EG-NEXT: SETGT_UINT * T1.W, T0.Z, literal.x, 644; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 645; EG-NEXT: CNDE_INT T0.Y, PS, PV.Z, PV.W, 646; EG-NEXT: LSHL * T0.W, T0.X, T0.Z, 647; EG-NEXT: CNDE_INT T0.X, T1.W, PV.W, 0.0, 648; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 649; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 650 %b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1 651 %a = load i64, i64 addrspace(1)* %in 652 %b = load i64, i64 addrspace(1)* %b_ptr 653 %result = shl i64 %a, %b 654 store i64 %result, i64 addrspace(1)* %out 655 ret void 656} 657 658define amdgpu_kernel void @shl_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) { 659; GCN-LABEL: shl_v2i64: 660; GCN: ; %bb.0: 661; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 662; GCN-NEXT: s_mov_b32 s3, 0xf000 663; GCN-NEXT: s_mov_b32 s2, -1 664; GCN-NEXT: s_mov_b32 s10, s2 665; GCN-NEXT: s_mov_b32 s11, s3 666; GCN-NEXT: s_waitcnt lgkmcnt(0) 667; GCN-NEXT: s_mov_b32 s8, s6 668; GCN-NEXT: s_mov_b32 s9, s7 669; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 670; GCN-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16 671; GCN-NEXT: s_mov_b32 s0, s4 672; GCN-NEXT: s_mov_b32 s1, s5 673; GCN-NEXT: s_waitcnt vmcnt(0) 674; GCN-NEXT: v_lshl_b64 v[2:3], v[2:3], v6 675; GCN-NEXT: v_lshl_b64 v[0:1], v[0:1], v4 676; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 677; GCN-NEXT: s_endpgm 678; 679; EG-LABEL: shl_v2i64: 680; EG: ; %bb.0: 681; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] 682; EG-NEXT: TEX 1 @6 683; EG-NEXT: ALU 28, @11, KC0[CB0:0-32], KC1[] 684; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T0.X, 1 685; EG-NEXT: CF_END 686; EG-NEXT: PAD 687; EG-NEXT: Fetch clause starting at 6: 688; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1 689; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1 690; EG-NEXT: ALU clause starting at 10: 691; EG-NEXT: MOV * T0.X, KC0[2].Z, 692; EG-NEXT: ALU clause starting at 11: 693; EG-NEXT: SUB_INT * T1.W, literal.x, T1.Z, 694; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 695; EG-NEXT: LSHR * T1.W, T0.Z, PV.W, 696; EG-NEXT: SUB_INT T2.Z, literal.x, T1.X, 697; EG-NEXT: LSHR T1.W, PV.W, 1, 698; EG-NEXT: LSHL * T0.W, T0.W, T1.Z, 699; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 700; EG-NEXT: OR_INT T3.Z, PS, PV.W, 701; EG-NEXT: LSHR T0.W, T0.X, PV.Z, 702; EG-NEXT: ADD_INT * T1.W, T1.Z, literal.x, 703; EG-NEXT: -32(nan), 0(0.000000e+00) 704; EG-NEXT: LSHL T2.X, T0.Z, PS, 705; EG-NEXT: SETGT_UINT T1.Y, T1.Z, literal.x, BS:VEC_120/SCL_212 706; EG-NEXT: ADD_INT T2.Z, T1.X, literal.y, 707; EG-NEXT: LSHR T0.W, PV.W, 1, 708; EG-NEXT: LSHL * T1.W, T0.Y, T1.X, 709; EG-NEXT: 31(4.344025e-44), -32(nan) 710; EG-NEXT: OR_INT T0.Y, PS, PV.W, 711; EG-NEXT: LSHL T2.Z, T0.X, PV.Z, 712; EG-NEXT: SETGT_UINT T0.W, T1.X, literal.x, BS:VEC_120/SCL_212 713; EG-NEXT: CNDE_INT * T2.W, PV.Y, T3.Z, PV.X, 714; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 715; EG-NEXT: CNDE_INT T2.Y, PV.W, PV.Y, PV.Z, 716; EG-NEXT: LSHL * T1.W, T0.Z, T1.Z, 717; EG-NEXT: CNDE_INT T2.Z, T1.Y, PV.W, 0.0, 718; EG-NEXT: LSHL * T1.W, T0.X, T1.X, 719; EG-NEXT: CNDE_INT T2.X, T0.W, PV.W, 0.0, 720; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x, 721; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 722 %b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %in, i64 1 723 %a = load <2 x i64>, <2 x i64> addrspace(1)* %in 724 %b = load <2 x i64>, <2 x i64> addrspace(1)* %b_ptr 725 %result = shl <2 x i64> %a, %b 726 store <2 x i64> %result, <2 x i64> addrspace(1)* %out 727 ret void 728} 729 730define amdgpu_kernel void @shl_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) { 731; GCN-LABEL: shl_v4i64: 732; GCN: ; %bb.0: 733; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 734; GCN-NEXT: s_mov_b32 s3, 0xf000 735; GCN-NEXT: s_mov_b32 s2, -1 736; GCN-NEXT: s_mov_b32 s10, s2 737; GCN-NEXT: s_mov_b32 s11, s3 738; GCN-NEXT: s_waitcnt lgkmcnt(0) 739; GCN-NEXT: s_mov_b32 s8, s6 740; GCN-NEXT: s_mov_b32 s9, s7 741; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 742; GCN-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16 743; GCN-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:32 744; GCN-NEXT: buffer_load_dwordx4 v[11:14], off, s[8:11], 0 offset:48 745; GCN-NEXT: s_mov_b32 s0, s4 746; GCN-NEXT: s_mov_b32 s1, s5 747; GCN-NEXT: s_waitcnt vmcnt(1) 748; GCN-NEXT: v_lshl_b64 v[2:3], v[2:3], v10 749; GCN-NEXT: s_waitcnt vmcnt(0) 750; GCN-NEXT: v_lshl_b64 v[6:7], v[6:7], v13 751; GCN-NEXT: v_lshl_b64 v[4:5], v[4:5], v11 752; GCN-NEXT: v_lshl_b64 v[0:1], v[0:1], v8 753; GCN-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16 754; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 755; GCN-NEXT: s_endpgm 756; 757; EG-LABEL: shl_v4i64: 758; EG: ; %bb.0: 759; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[] 760; EG-NEXT: TEX 3 @6 761; EG-NEXT: ALU 58, @15, KC0[CB0:0-32], KC1[] 762; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 0 763; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T4.X, 1 764; EG-NEXT: CF_END 765; EG-NEXT: Fetch clause starting at 6: 766; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 48, #1 767; EG-NEXT: VTX_READ_128 T2.XYZW, T0.X, 0, #1 768; EG-NEXT: VTX_READ_128 T3.XYZW, T0.X, 16, #1 769; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 32, #1 770; EG-NEXT: ALU clause starting at 14: 771; EG-NEXT: MOV * T0.X, KC0[2].Z, 772; EG-NEXT: ALU clause starting at 15: 773; EG-NEXT: SUB_INT * T0.W, literal.x, T1.Z, 774; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 775; EG-NEXT: SUB_INT T4.Z, literal.x, T0.Z, 776; EG-NEXT: SUB_INT T1.W, literal.x, T0.X, 777; EG-NEXT: LSHR * T0.W, T3.Z, PV.W, 778; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 779; EG-NEXT: SUB_INT T0.Y, literal.x, T1.X, 780; EG-NEXT: LSHR T5.Z, PS, 1, 781; EG-NEXT: LSHR T0.W, T2.X, PV.W, 782; EG-NEXT: LSHR * T1.W, T2.Z, PV.Z, 783; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 784; EG-NEXT: LSHL T4.X, T3.W, T1.Z, 785; EG-NEXT: LSHR T1.Y, PS, 1, 786; EG-NEXT: LSHL T4.Z, T2.W, T0.Z, BS:VEC_120/SCL_212 787; EG-NEXT: LSHR T0.W, PV.W, 1, 788; EG-NEXT: LSHL * T1.W, T2.Y, T0.X, 789; EG-NEXT: OR_INT T5.X, PS, PV.W, 790; EG-NEXT: OR_INT T1.Y, PV.Z, PV.Y, 791; EG-NEXT: OR_INT T4.Z, PV.X, T5.Z, 792; EG-NEXT: LSHR T0.W, T3.X, T0.Y, 793; EG-NEXT: ADD_INT * T1.W, T1.Z, literal.x, 794; EG-NEXT: -32(nan), 0(0.000000e+00) 795; EG-NEXT: LSHL T4.X, T3.Z, PS, 796; EG-NEXT: SETGT_UINT T0.Y, T1.Z, literal.x, BS:VEC_120/SCL_212 797; EG-NEXT: ADD_INT T5.Z, T1.X, literal.y, 798; EG-NEXT: LSHR T0.W, PV.W, 1, 799; EG-NEXT: LSHL * T1.W, T3.Y, T1.X, 800; EG-NEXT: 31(4.344025e-44), -32(nan) 801; EG-NEXT: OR_INT T6.X, PS, PV.W, 802; EG-NEXT: LSHL T2.Y, T3.X, PV.Z, 803; EG-NEXT: SETGT_UINT T5.Z, T1.X, literal.x, BS:VEC_120/SCL_212 804; EG-NEXT: ADD_INT T0.W, T0.Z, literal.y, 805; EG-NEXT: CNDE_INT * T3.W, PV.Y, T4.Z, PV.X, 806; EG-NEXT: 31(4.344025e-44), -32(nan) 807; EG-NEXT: LSHL T4.X, T2.Z, PV.W, 808; EG-NEXT: CNDE_INT T3.Y, PV.Z, PV.X, PV.Y, 809; EG-NEXT: SETGT_UINT * T4.Z, T0.Z, literal.x, BS:VEC_120/SCL_212 810; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 811; EG-NEXT: LSHL T0.W, T3.Z, T1.Z, 812; EG-NEXT: ADD_INT * T1.W, T0.X, literal.x, 813; EG-NEXT: -32(nan), 0(0.000000e+00) 814; EG-NEXT: LSHL T6.X, T2.X, PS, 815; EG-NEXT: SETGT_UINT T2.Y, T0.X, literal.x, BS:VEC_120/SCL_212 816; EG-NEXT: CNDE_INT * T3.Z, T0.Y, PV.W, 0.0, 817; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 818; EG-NEXT: LSHL T0.W, T3.X, T1.X, BS:VEC_120/SCL_212 819; EG-NEXT: CNDE_INT * T1.W, T4.Z, T1.Y, T4.X, 820; EG-NEXT: CNDE_INT T3.X, T5.Z, PV.W, 0.0, 821; EG-NEXT: CNDE_INT T1.Y, T2.Y, T5.X, T6.X, 822; EG-NEXT: LSHL T0.W, T2.Z, T0.Z, BS:VEC_120/SCL_212 823; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x, 824; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) 825; EG-NEXT: LSHR T4.X, PS, literal.x, 826; EG-NEXT: CNDE_INT T1.Z, T4.Z, PV.W, 0.0, 827; EG-NEXT: LSHL * T0.W, T2.X, T0.X, 828; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 829; EG-NEXT: CNDE_INT T1.X, T2.Y, PV.W, 0.0, 830; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x, 831; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 832 %b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i64 1 833 %a = load <4 x i64>, <4 x i64> addrspace(1)* %in 834 %b = load <4 x i64>, <4 x i64> addrspace(1)* %b_ptr 835 %result = shl <4 x i64> %a, %b 836 store <4 x i64> %result, <4 x i64> addrspace(1)* %out 837 ret void 838} 839 840; Make sure load width gets reduced to i32 load. 841define amdgpu_kernel void @s_shl_32_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) { 842; GCN-LABEL: s_shl_32_i64: 843; GCN: ; %bb.0: 844; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 845; GCN-NEXT: s_load_dword s0, s[0:1], 0x13 846; GCN-NEXT: s_mov_b32 s7, 0xf000 847; GCN-NEXT: s_mov_b32 s6, -1 848; GCN-NEXT: v_mov_b32_e32 v0, 0 849; GCN-NEXT: s_waitcnt lgkmcnt(0) 850; GCN-NEXT: v_mov_b32_e32 v1, s0 851; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 852; GCN-NEXT: s_endpgm 853; 854; EG-LABEL: s_shl_32_i64: 855; EG: ; %bb.0: 856; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[] 857; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 858; EG-NEXT: CF_END 859; EG-NEXT: PAD 860; EG-NEXT: ALU clause starting at 4: 861; EG-NEXT: MOV * T0.Y, KC0[4].W, 862; EG-NEXT: MOV T0.X, 0.0, 863; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 864; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 865 %result = shl i64 %a, 32 866 store i64 %result, i64 addrspace(1)* %out 867 ret void 868} 869 870define amdgpu_kernel void @v_shl_32_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { 871; GCN-LABEL: v_shl_32_i64: 872; GCN: ; %bb.0: 873; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 874; GCN-NEXT: s_ashr_i32 s3, s2, 31 875; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 3 876; GCN-NEXT: v_mov_b32_e32 v0, s0 877; GCN-NEXT: s_mov_b32 s7, 0xf000 878; GCN-NEXT: s_mov_b32 s6, 0 879; GCN-NEXT: s_waitcnt lgkmcnt(0) 880; GCN-NEXT: s_mov_b64 s[4:5], s[10:11] 881; GCN-NEXT: v_mov_b32_e32 v1, s1 882; GCN-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 883; GCN-NEXT: s_mov_b64 s[10:11], s[6:7] 884; GCN-NEXT: v_mov_b32_e32 v2, 0 885; GCN-NEXT: s_waitcnt vmcnt(0) 886; GCN-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[8:11], 0 addr64 887; GCN-NEXT: s_endpgm 888; 889; EG-LABEL: v_shl_32_i64: 890; EG: ; %bb.0: 891; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] 892; EG-NEXT: TEX 0 @6 893; EG-NEXT: ALU 4, @11, KC0[CB0:0-32], KC1[] 894; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XY, T2.X, 1 895; EG-NEXT: CF_END 896; EG-NEXT: PAD 897; EG-NEXT: Fetch clause starting at 6: 898; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 899; EG-NEXT: ALU clause starting at 8: 900; EG-NEXT: LSHL * T0.W, T1.X, literal.x, 901; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) 902; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, 903; EG-NEXT: ALU clause starting at 11: 904; EG-NEXT: MOV T1.X, 0.0, 905; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W, 906; EG-NEXT: LSHR T2.X, PV.W, literal.x, 907; EG-NEXT: MOV * T1.Y, T0.X, 908; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 909 %tid = call i32 @llvm.amdgcn.workgroup.id.x() #0 910 %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid 911 %gep.out = getelementptr i64, i64 addrspace(1)* %out, i32 %tid 912 %a = load i64, i64 addrspace(1)* %gep.in 913 %result = shl i64 %a, 32 914 store i64 %result, i64 addrspace(1)* %gep.out 915 ret void 916} 917 918define amdgpu_kernel void @s_shl_constant_i64(i64 addrspace(1)* %out, i64 %a) { 919; GCN-LABEL: s_shl_constant_i64: 920; GCN: ; %bb.0: 921; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 922; GCN-NEXT: s_mov_b32 s2, -1 923; GCN-NEXT: s_mov_b32 s9, 0xffff 924; GCN-NEXT: s_mov_b32 s8, s2 925; GCN-NEXT: s_mov_b32 s3, 0xf000 926; GCN-NEXT: s_waitcnt lgkmcnt(0) 927; GCN-NEXT: s_mov_b32 s0, s4 928; GCN-NEXT: s_mov_b32 s1, s5 929; GCN-NEXT: s_lshl_b64 s[4:5], s[8:9], s6 930; GCN-NEXT: v_mov_b32_e32 v0, s4 931; GCN-NEXT: v_mov_b32_e32 v1, s5 932; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 933; GCN-NEXT: s_endpgm 934; 935; EG-LABEL: s_shl_constant_i64: 936; EG: ; %bb.0: 937; EG-NEXT: ALU 17, @4, KC0[CB0:0-32], KC1[] 938; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 939; EG-NEXT: CF_END 940; EG-NEXT: PAD 941; EG-NEXT: ALU clause starting at 4: 942; EG-NEXT: SUB_INT * T0.W, literal.x, KC0[2].W, 943; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 944; EG-NEXT: LSHR * T0.W, literal.x, PV.W, 945; EG-NEXT: -1(nan), 0(0.000000e+00) 946; EG-NEXT: ADD_INT T0.Z, KC0[2].W, literal.x, 947; EG-NEXT: LSHR T0.W, PV.W, 1, 948; EG-NEXT: LSHL * T1.W, literal.y, KC0[2].W, 949; EG-NEXT: -32(nan), 65535(9.183409e-41) 950; EG-NEXT: OR_INT T1.Z, PS, PV.W, 951; EG-NEXT: LSHL T0.W, literal.x, PV.Z, 952; EG-NEXT: SETGT_UINT * T1.W, KC0[2].W, literal.y, 953; EG-NEXT: -1(nan), 31(4.344025e-44) 954; EG-NEXT: CNDE_INT T0.Y, PS, PV.Z, PV.W, 955; EG-NEXT: LSHL * T0.W, literal.x, KC0[2].W, 956; EG-NEXT: -1(nan), 0(0.000000e+00) 957; EG-NEXT: CNDE_INT T0.X, T1.W, PV.W, 0.0, 958; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 959; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 960 %shl = shl i64 281474976710655, %a 961 store i64 %shl, i64 addrspace(1)* %out, align 8 962 ret void 963} 964 965define amdgpu_kernel void @v_shl_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 966; GCN-LABEL: v_shl_constant_i64: 967; GCN: ; %bb.0: 968; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 969; GCN-NEXT: s_mov_b32 s3, 0xf000 970; GCN-NEXT: s_mov_b32 s2, -1 971; GCN-NEXT: s_mov_b32 s10, s2 972; GCN-NEXT: s_mov_b32 s11, s3 973; GCN-NEXT: s_waitcnt lgkmcnt(0) 974; GCN-NEXT: s_mov_b32 s8, s6 975; GCN-NEXT: s_mov_b32 s9, s7 976; GCN-NEXT: buffer_load_dword v0, off, s[8:11], 0 977; GCN-NEXT: s_movk_i32 s7, 0x11e 978; GCN-NEXT: s_mov_b32 s6, 0xab19b207 979; GCN-NEXT: s_mov_b32 s0, s4 980; GCN-NEXT: s_mov_b32 s1, s5 981; GCN-NEXT: s_waitcnt vmcnt(0) 982; GCN-NEXT: v_lshl_b64 v[0:1], s[6:7], v0 983; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 984; GCN-NEXT: s_endpgm 985; 986; EG-LABEL: v_shl_constant_i64: 987; EG: ; %bb.0: 988; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] 989; EG-NEXT: TEX 0 @6 990; EG-NEXT: ALU 17, @9, KC0[CB0:0-32], KC1[] 991; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 992; EG-NEXT: CF_END 993; EG-NEXT: PAD 994; EG-NEXT: Fetch clause starting at 6: 995; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 996; EG-NEXT: ALU clause starting at 8: 997; EG-NEXT: MOV * T0.X, KC0[2].Z, 998; EG-NEXT: ALU clause starting at 9: 999; EG-NEXT: SUB_INT * T0.W, literal.x, T0.X, 1000; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 1001; EG-NEXT: LSHR * T0.W, literal.x, PV.W, 1002; EG-NEXT: -1424379385(-5.460358e-13), 0(0.000000e+00) 1003; EG-NEXT: ADD_INT T0.Z, T0.X, literal.x, 1004; EG-NEXT: LSHR T0.W, PV.W, 1, 1005; EG-NEXT: LSHL * T1.W, literal.y, T0.X, 1006; EG-NEXT: -32(nan), 286(4.007714e-43) 1007; EG-NEXT: OR_INT T1.Z, PS, PV.W, 1008; EG-NEXT: SETGT_UINT T0.W, T0.X, literal.x, 1009; EG-NEXT: LSHL * T1.W, literal.y, PV.Z, 1010; EG-NEXT: 31(4.344025e-44), -1424379385(-5.460358e-13) 1011; EG-NEXT: CNDE_INT T0.Y, PV.W, PV.Z, PS, 1012; EG-NEXT: LSHL * T1.W, literal.x, T0.X, 1013; EG-NEXT: -1424379385(-5.460358e-13), 0(0.000000e+00) 1014; EG-NEXT: CNDE_INT T0.X, T0.W, PV.W, 0.0, 1015; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1016; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1017 %a = load i64, i64 addrspace(1)* %aptr, align 8 1018 %shl = shl i64 1231231234567, %a 1019 store i64 %shl, i64 addrspace(1)* %out, align 8 1020 ret void 1021} 1022 1023define amdgpu_kernel void @v_shl_i64_32_bit_constant(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 1024; GCN-LABEL: v_shl_i64_32_bit_constant: 1025; GCN: ; %bb.0: 1026; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 1027; GCN-NEXT: s_mov_b32 s3, 0xf000 1028; GCN-NEXT: s_mov_b32 s2, -1 1029; GCN-NEXT: s_mov_b32 s10, s2 1030; GCN-NEXT: s_mov_b32 s11, s3 1031; GCN-NEXT: s_waitcnt lgkmcnt(0) 1032; GCN-NEXT: s_mov_b32 s8, s6 1033; GCN-NEXT: s_mov_b32 s9, s7 1034; GCN-NEXT: buffer_load_dword v0, off, s[8:11], 0 1035; GCN-NEXT: s_mov_b32 s7, 0 1036; GCN-NEXT: s_mov_b32 s6, 0x12d687 1037; GCN-NEXT: s_mov_b32 s0, s4 1038; GCN-NEXT: s_mov_b32 s1, s5 1039; GCN-NEXT: s_waitcnt vmcnt(0) 1040; GCN-NEXT: v_lshl_b64 v[0:1], s[6:7], v0 1041; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 1042; GCN-NEXT: s_endpgm 1043; 1044; EG-LABEL: v_shl_i64_32_bit_constant: 1045; EG: ; %bb.0: 1046; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] 1047; EG-NEXT: TEX 0 @6 1048; EG-NEXT: ALU 14, @9, KC0[CB0:0-32], KC1[] 1049; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1050; EG-NEXT: CF_END 1051; EG-NEXT: PAD 1052; EG-NEXT: Fetch clause starting at 6: 1053; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 1054; EG-NEXT: ALU clause starting at 8: 1055; EG-NEXT: MOV * T0.X, KC0[2].Z, 1056; EG-NEXT: ALU clause starting at 9: 1057; EG-NEXT: SUB_INT T0.W, literal.x, T0.X, 1058; EG-NEXT: ADD_INT * T1.W, T0.X, literal.y, 1059; EG-NEXT: 31(4.344025e-44), -32(nan) 1060; EG-NEXT: LSHR * T0.W, literal.x, PV.W, 1061; EG-NEXT: 1234567(1.729997e-39), 0(0.000000e+00) 1062; EG-NEXT: LSHR T0.Z, PV.W, 1, 1063; EG-NEXT: LSHL T0.W, literal.x, T1.W, 1064; EG-NEXT: SETGT_UINT * T1.W, T0.X, literal.y, 1065; EG-NEXT: 1234567(1.729997e-39), 31(4.344025e-44) 1066; EG-NEXT: CNDE_INT T0.Y, PS, PV.Z, PV.W, 1067; EG-NEXT: LSHL * T0.W, literal.x, T0.X, 1068; EG-NEXT: 1234567(1.729997e-39), 0(0.000000e+00) 1069; EG-NEXT: CNDE_INT T0.X, T1.W, PV.W, 0.0, 1070; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1071; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1072 %a = load i64, i64 addrspace(1)* %aptr, align 8 1073 %shl = shl i64 1234567, %a 1074 store i64 %shl, i64 addrspace(1)* %out, align 8 1075 ret void 1076} 1077 1078define amdgpu_kernel void @v_shl_inline_imm_64_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 1079; GCN-LABEL: v_shl_inline_imm_64_i64: 1080; GCN: ; %bb.0: 1081; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 1082; GCN-NEXT: s_mov_b32 s3, 0xf000 1083; GCN-NEXT: s_mov_b32 s2, -1 1084; GCN-NEXT: s_mov_b32 s10, s2 1085; GCN-NEXT: s_mov_b32 s11, s3 1086; GCN-NEXT: s_waitcnt lgkmcnt(0) 1087; GCN-NEXT: s_mov_b32 s8, s6 1088; GCN-NEXT: s_mov_b32 s9, s7 1089; GCN-NEXT: buffer_load_dword v0, off, s[8:11], 0 1090; GCN-NEXT: s_mov_b32 s0, s4 1091; GCN-NEXT: s_mov_b32 s1, s5 1092; GCN-NEXT: s_waitcnt vmcnt(0) 1093; GCN-NEXT: v_lshl_b64 v[0:1], 64, v0 1094; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 1095; GCN-NEXT: s_endpgm 1096; 1097; EG-LABEL: v_shl_inline_imm_64_i64: 1098; EG: ; %bb.0: 1099; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] 1100; EG-NEXT: TEX 0 @6 1101; EG-NEXT: ALU 14, @9, KC0[CB0:0-32], KC1[] 1102; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1103; EG-NEXT: CF_END 1104; EG-NEXT: PAD 1105; EG-NEXT: Fetch clause starting at 6: 1106; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 1107; EG-NEXT: ALU clause starting at 8: 1108; EG-NEXT: MOV * T0.X, KC0[2].Z, 1109; EG-NEXT: ALU clause starting at 9: 1110; EG-NEXT: SUB_INT T0.W, literal.x, T0.X, 1111; EG-NEXT: ADD_INT * T1.W, T0.X, literal.y, 1112; EG-NEXT: 31(4.344025e-44), -32(nan) 1113; EG-NEXT: LSHR * T0.W, literal.x, PV.W, 1114; EG-NEXT: 64(8.968310e-44), 0(0.000000e+00) 1115; EG-NEXT: LSHR T0.Z, PV.W, 1, 1116; EG-NEXT: LSHL T0.W, literal.x, T1.W, 1117; EG-NEXT: SETGT_UINT * T1.W, T0.X, literal.y, 1118; EG-NEXT: 64(8.968310e-44), 31(4.344025e-44) 1119; EG-NEXT: CNDE_INT T0.Y, PS, PV.Z, PV.W, 1120; EG-NEXT: LSHL * T0.W, literal.x, T0.X, 1121; EG-NEXT: 64(8.968310e-44), 0(0.000000e+00) 1122; EG-NEXT: CNDE_INT T0.X, T1.W, PV.W, 0.0, 1123; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1124; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1125 %a = load i64, i64 addrspace(1)* %aptr, align 8 1126 %shl = shl i64 64, %a 1127 store i64 %shl, i64 addrspace(1)* %out, align 8 1128 ret void 1129} 1130 1131define amdgpu_kernel void @s_shl_inline_imm_64_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1132; GCN-LABEL: s_shl_inline_imm_64_i64: 1133; GCN: ; %bb.0: 1134; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1135; GCN-NEXT: s_load_dword s0, s[0:1], 0xd 1136; GCN-NEXT: s_mov_b32 s7, 0xf000 1137; GCN-NEXT: s_mov_b32 s6, -1 1138; GCN-NEXT: s_waitcnt lgkmcnt(0) 1139; GCN-NEXT: s_lshl_b64 s[0:1], 64, s0 1140; GCN-NEXT: v_mov_b32_e32 v0, s0 1141; GCN-NEXT: v_mov_b32_e32 v1, s1 1142; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1143; GCN-NEXT: s_endpgm 1144; 1145; EG-LABEL: s_shl_inline_imm_64_i64: 1146; EG: ; %bb.0: 1147; EG-NEXT: ALU 14, @4, KC0[CB0:0-32], KC1[] 1148; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1149; EG-NEXT: CF_END 1150; EG-NEXT: PAD 1151; EG-NEXT: ALU clause starting at 4: 1152; EG-NEXT: SUB_INT * T0.W, literal.x, KC0[2].W, 1153; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 1154; EG-NEXT: LSHR T0.W, literal.x, PV.W, 1155; EG-NEXT: ADD_INT * T1.W, KC0[2].W, literal.y, 1156; EG-NEXT: 64(8.968310e-44), -32(nan) 1157; EG-NEXT: LSHL T0.Z, literal.x, PS, 1158; EG-NEXT: LSHR T0.W, PV.W, 1, 1159; EG-NEXT: SETGT_UINT * T1.W, KC0[2].W, literal.y, 1160; EG-NEXT: 64(8.968310e-44), 31(4.344025e-44) 1161; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, PV.Z, 1162; EG-NEXT: LSHL * T0.W, literal.x, KC0[2].W, 1163; EG-NEXT: 64(8.968310e-44), 0(0.000000e+00) 1164; EG-NEXT: CNDE_INT T0.X, T1.W, PV.W, 0.0, 1165; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1166; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1167 %shl = shl i64 64, %a 1168 store i64 %shl, i64 addrspace(1)* %out, align 8 1169 ret void 1170} 1171 1172define amdgpu_kernel void @s_shl_inline_imm_1_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1173; GCN-LABEL: s_shl_inline_imm_1_i64: 1174; GCN: ; %bb.0: 1175; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1176; GCN-NEXT: s_load_dword s0, s[0:1], 0xd 1177; GCN-NEXT: s_mov_b32 s7, 0xf000 1178; GCN-NEXT: s_mov_b32 s6, -1 1179; GCN-NEXT: s_waitcnt lgkmcnt(0) 1180; GCN-NEXT: s_lshl_b64 s[0:1], 1, s0 1181; GCN-NEXT: v_mov_b32_e32 v0, s0 1182; GCN-NEXT: v_mov_b32_e32 v1, s1 1183; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1184; GCN-NEXT: s_endpgm 1185; 1186; EG-LABEL: s_shl_inline_imm_1_i64: 1187; EG: ; %bb.0: 1188; EG-NEXT: ALU 8, @4, KC0[CB0:0-32], KC1[] 1189; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1190; EG-NEXT: CF_END 1191; EG-NEXT: PAD 1192; EG-NEXT: ALU clause starting at 4: 1193; EG-NEXT: ADD_INT T0.Z, KC0[2].W, literal.x, 1194; EG-NEXT: SETGT_UINT T0.W, KC0[2].W, literal.y, 1195; EG-NEXT: LSHL * T1.W, 1, KC0[2].W, 1196; EG-NEXT: -32(nan), 31(4.344025e-44) 1197; EG-NEXT: CNDE_INT T0.X, PV.W, PS, 0.0, 1198; EG-NEXT: LSHL T1.W, 1, PV.Z, 1199; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1200; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1201; EG-NEXT: CNDE_INT * T0.Y, T0.W, 0.0, PV.W, 1202 %shl = shl i64 1, %a 1203 store i64 %shl, i64 addrspace(1)* %out, align 8 1204 ret void 1205} 1206 1207define amdgpu_kernel void @s_shl_inline_imm_1_0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1208; GCN-LABEL: s_shl_inline_imm_1_0_i64: 1209; GCN: ; %bb.0: 1210; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1211; GCN-NEXT: s_load_dword s0, s[0:1], 0xd 1212; GCN-NEXT: s_mov_b32 s7, 0xf000 1213; GCN-NEXT: s_mov_b32 s6, -1 1214; GCN-NEXT: s_waitcnt lgkmcnt(0) 1215; GCN-NEXT: s_lshl_b64 s[0:1], 1.0, s0 1216; GCN-NEXT: v_mov_b32_e32 v0, s0 1217; GCN-NEXT: v_mov_b32_e32 v1, s1 1218; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1219; GCN-NEXT: s_endpgm 1220; 1221; EG-LABEL: s_shl_inline_imm_1_0_i64: 1222; EG: ; %bb.0: 1223; EG-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[] 1224; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1225; EG-NEXT: CF_END 1226; EG-NEXT: PAD 1227; EG-NEXT: ALU clause starting at 4: 1228; EG-NEXT: SETGT_UINT T0.W, KC0[2].W, literal.x, 1229; EG-NEXT: LSHL * T1.W, literal.y, KC0[2].W, 1230; EG-NEXT: 31(4.344025e-44), 1072693248(1.875000e+00) 1231; EG-NEXT: CNDE_INT * T0.Y, PV.W, PS, 0.0, 1232; EG-NEXT: MOV T0.X, 0.0, 1233; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1234; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1235 %shl = shl i64 4607182418800017408, %a 1236 store i64 %shl, i64 addrspace(1)* %out, align 8 1237 ret void 1238} 1239 1240define amdgpu_kernel void @s_shl_inline_imm_neg_1_0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1241; GCN-LABEL: s_shl_inline_imm_neg_1_0_i64: 1242; GCN: ; %bb.0: 1243; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1244; GCN-NEXT: s_load_dword s0, s[0:1], 0xd 1245; GCN-NEXT: s_mov_b32 s7, 0xf000 1246; GCN-NEXT: s_mov_b32 s6, -1 1247; GCN-NEXT: s_waitcnt lgkmcnt(0) 1248; GCN-NEXT: s_lshl_b64 s[0:1], -1.0, s0 1249; GCN-NEXT: v_mov_b32_e32 v0, s0 1250; GCN-NEXT: v_mov_b32_e32 v1, s1 1251; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1252; GCN-NEXT: s_endpgm 1253; 1254; EG-LABEL: s_shl_inline_imm_neg_1_0_i64: 1255; EG: ; %bb.0: 1256; EG-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[] 1257; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1258; EG-NEXT: CF_END 1259; EG-NEXT: PAD 1260; EG-NEXT: ALU clause starting at 4: 1261; EG-NEXT: SETGT_UINT T0.W, KC0[2].W, literal.x, 1262; EG-NEXT: LSHL * T1.W, literal.y, KC0[2].W, 1263; EG-NEXT: 31(4.344025e-44), -1074790400(-1.875000e+00) 1264; EG-NEXT: CNDE_INT * T0.Y, PV.W, PS, 0.0, 1265; EG-NEXT: MOV T0.X, 0.0, 1266; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1267; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1268 %shl = shl i64 13830554455654793216, %a 1269 store i64 %shl, i64 addrspace(1)* %out, align 8 1270 ret void 1271} 1272 1273define amdgpu_kernel void @s_shl_inline_imm_0_5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1274; GCN-LABEL: s_shl_inline_imm_0_5_i64: 1275; GCN: ; %bb.0: 1276; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1277; GCN-NEXT: s_load_dword s0, s[0:1], 0xd 1278; GCN-NEXT: s_mov_b32 s7, 0xf000 1279; GCN-NEXT: s_mov_b32 s6, -1 1280; GCN-NEXT: s_waitcnt lgkmcnt(0) 1281; GCN-NEXT: s_lshl_b64 s[0:1], 0.5, s0 1282; GCN-NEXT: v_mov_b32_e32 v0, s0 1283; GCN-NEXT: v_mov_b32_e32 v1, s1 1284; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1285; GCN-NEXT: s_endpgm 1286; 1287; EG-LABEL: s_shl_inline_imm_0_5_i64: 1288; EG: ; %bb.0: 1289; EG-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[] 1290; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1291; EG-NEXT: CF_END 1292; EG-NEXT: PAD 1293; EG-NEXT: ALU clause starting at 4: 1294; EG-NEXT: SETGT_UINT T0.W, KC0[2].W, literal.x, 1295; EG-NEXT: LSHL * T1.W, literal.y, KC0[2].W, 1296; EG-NEXT: 31(4.344025e-44), 1071644672(1.750000e+00) 1297; EG-NEXT: CNDE_INT * T0.Y, PV.W, PS, 0.0, 1298; EG-NEXT: MOV T0.X, 0.0, 1299; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1300; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1301 %shl = shl i64 4602678819172646912, %a 1302 store i64 %shl, i64 addrspace(1)* %out, align 8 1303 ret void 1304} 1305 1306define amdgpu_kernel void @s_shl_inline_imm_neg_0_5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1307; GCN-LABEL: s_shl_inline_imm_neg_0_5_i64: 1308; GCN: ; %bb.0: 1309; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1310; GCN-NEXT: s_load_dword s0, s[0:1], 0xd 1311; GCN-NEXT: s_mov_b32 s7, 0xf000 1312; GCN-NEXT: s_mov_b32 s6, -1 1313; GCN-NEXT: s_waitcnt lgkmcnt(0) 1314; GCN-NEXT: s_lshl_b64 s[0:1], -0.5, s0 1315; GCN-NEXT: v_mov_b32_e32 v0, s0 1316; GCN-NEXT: v_mov_b32_e32 v1, s1 1317; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1318; GCN-NEXT: s_endpgm 1319; 1320; EG-LABEL: s_shl_inline_imm_neg_0_5_i64: 1321; EG: ; %bb.0: 1322; EG-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[] 1323; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1324; EG-NEXT: CF_END 1325; EG-NEXT: PAD 1326; EG-NEXT: ALU clause starting at 4: 1327; EG-NEXT: SETGT_UINT T0.W, KC0[2].W, literal.x, 1328; EG-NEXT: LSHL * T1.W, literal.y, KC0[2].W, 1329; EG-NEXT: 31(4.344025e-44), -1075838976(-1.750000e+00) 1330; EG-NEXT: CNDE_INT * T0.Y, PV.W, PS, 0.0, 1331; EG-NEXT: MOV T0.X, 0.0, 1332; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1333; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1334 %shl = shl i64 13826050856027422720, %a 1335 store i64 %shl, i64 addrspace(1)* %out, align 8 1336 ret void 1337} 1338 1339define amdgpu_kernel void @s_shl_inline_imm_2_0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1340; GCN-LABEL: s_shl_inline_imm_2_0_i64: 1341; GCN: ; %bb.0: 1342; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1343; GCN-NEXT: s_load_dword s0, s[0:1], 0xd 1344; GCN-NEXT: s_mov_b32 s7, 0xf000 1345; GCN-NEXT: s_mov_b32 s6, -1 1346; GCN-NEXT: s_waitcnt lgkmcnt(0) 1347; GCN-NEXT: s_lshl_b64 s[0:1], 2.0, s0 1348; GCN-NEXT: v_mov_b32_e32 v0, s0 1349; GCN-NEXT: v_mov_b32_e32 v1, s1 1350; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1351; GCN-NEXT: s_endpgm 1352; 1353; EG-LABEL: s_shl_inline_imm_2_0_i64: 1354; EG: ; %bb.0: 1355; EG-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[] 1356; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1357; EG-NEXT: CF_END 1358; EG-NEXT: PAD 1359; EG-NEXT: ALU clause starting at 4: 1360; EG-NEXT: SETGT_UINT T0.W, KC0[2].W, literal.x, 1361; EG-NEXT: LSHL * T1.W, literal.y, KC0[2].W, 1362; EG-NEXT: 31(4.344025e-44), 1073741824(2.000000e+00) 1363; EG-NEXT: CNDE_INT * T0.Y, PV.W, PS, 0.0, 1364; EG-NEXT: MOV T0.X, 0.0, 1365; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1366; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1367 %shl = shl i64 4611686018427387904, %a 1368 store i64 %shl, i64 addrspace(1)* %out, align 8 1369 ret void 1370} 1371 1372define amdgpu_kernel void @s_shl_inline_imm_neg_2_0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1373; GCN-LABEL: s_shl_inline_imm_neg_2_0_i64: 1374; GCN: ; %bb.0: 1375; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1376; GCN-NEXT: s_load_dword s0, s[0:1], 0xd 1377; GCN-NEXT: s_mov_b32 s7, 0xf000 1378; GCN-NEXT: s_mov_b32 s6, -1 1379; GCN-NEXT: s_waitcnt lgkmcnt(0) 1380; GCN-NEXT: s_lshl_b64 s[0:1], -2.0, s0 1381; GCN-NEXT: v_mov_b32_e32 v0, s0 1382; GCN-NEXT: v_mov_b32_e32 v1, s1 1383; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1384; GCN-NEXT: s_endpgm 1385; 1386; EG-LABEL: s_shl_inline_imm_neg_2_0_i64: 1387; EG: ; %bb.0: 1388; EG-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[] 1389; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1390; EG-NEXT: CF_END 1391; EG-NEXT: PAD 1392; EG-NEXT: ALU clause starting at 4: 1393; EG-NEXT: SETGT_UINT T0.W, KC0[2].W, literal.x, 1394; EG-NEXT: LSHL * T1.W, literal.y, KC0[2].W, 1395; EG-NEXT: 31(4.344025e-44), -1073741824(-2.000000e+00) 1396; EG-NEXT: CNDE_INT * T0.Y, PV.W, PS, 0.0, 1397; EG-NEXT: MOV T0.X, 0.0, 1398; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1399; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1400 %shl = shl i64 13835058055282163712, %a 1401 store i64 %shl, i64 addrspace(1)* %out, align 8 1402 ret void 1403} 1404 1405define amdgpu_kernel void @s_shl_inline_imm_4_0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1406; GCN-LABEL: s_shl_inline_imm_4_0_i64: 1407; GCN: ; %bb.0: 1408; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1409; GCN-NEXT: s_load_dword s0, s[0:1], 0xd 1410; GCN-NEXT: s_mov_b32 s7, 0xf000 1411; GCN-NEXT: s_mov_b32 s6, -1 1412; GCN-NEXT: s_waitcnt lgkmcnt(0) 1413; GCN-NEXT: s_lshl_b64 s[0:1], 4.0, s0 1414; GCN-NEXT: v_mov_b32_e32 v0, s0 1415; GCN-NEXT: v_mov_b32_e32 v1, s1 1416; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1417; GCN-NEXT: s_endpgm 1418; 1419; EG-LABEL: s_shl_inline_imm_4_0_i64: 1420; EG: ; %bb.0: 1421; EG-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[] 1422; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1423; EG-NEXT: CF_END 1424; EG-NEXT: PAD 1425; EG-NEXT: ALU clause starting at 4: 1426; EG-NEXT: SETGT_UINT T0.W, KC0[2].W, literal.x, 1427; EG-NEXT: LSHL * T1.W, literal.y, KC0[2].W, 1428; EG-NEXT: 31(4.344025e-44), 1074790400(2.250000e+00) 1429; EG-NEXT: CNDE_INT * T0.Y, PV.W, PS, 0.0, 1430; EG-NEXT: MOV T0.X, 0.0, 1431; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1432; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1433 %shl = shl i64 4616189618054758400, %a 1434 store i64 %shl, i64 addrspace(1)* %out, align 8 1435 ret void 1436} 1437 1438define amdgpu_kernel void @s_shl_inline_imm_neg_4_0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1439; GCN-LABEL: s_shl_inline_imm_neg_4_0_i64: 1440; GCN: ; %bb.0: 1441; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1442; GCN-NEXT: s_load_dword s0, s[0:1], 0xd 1443; GCN-NEXT: s_mov_b32 s7, 0xf000 1444; GCN-NEXT: s_mov_b32 s6, -1 1445; GCN-NEXT: s_waitcnt lgkmcnt(0) 1446; GCN-NEXT: s_lshl_b64 s[0:1], -4.0, s0 1447; GCN-NEXT: v_mov_b32_e32 v0, s0 1448; GCN-NEXT: v_mov_b32_e32 v1, s1 1449; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1450; GCN-NEXT: s_endpgm 1451; 1452; EG-LABEL: s_shl_inline_imm_neg_4_0_i64: 1453; EG: ; %bb.0: 1454; EG-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[] 1455; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1456; EG-NEXT: CF_END 1457; EG-NEXT: PAD 1458; EG-NEXT: ALU clause starting at 4: 1459; EG-NEXT: SETGT_UINT T0.W, KC0[2].W, literal.x, 1460; EG-NEXT: LSHL * T1.W, literal.y, KC0[2].W, 1461; EG-NEXT: 31(4.344025e-44), -1072693248(-2.250000e+00) 1462; EG-NEXT: CNDE_INT * T0.Y, PV.W, PS, 0.0, 1463; EG-NEXT: MOV T0.X, 0.0, 1464; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1465; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1466 %shl = shl i64 13839561654909534208, %a 1467 store i64 %shl, i64 addrspace(1)* %out, align 8 1468 ret void 1469} 1470 1471 1472; Test with the 64-bit integer bitpattern for a 32-bit float in the 1473; low 32-bits, which is not a valid 64-bit inline immmediate. 1474define amdgpu_kernel void @s_shl_inline_imm_f32_4_0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1475; GCN-LABEL: s_shl_inline_imm_f32_4_0_i64: 1476; GCN: ; %bb.0: 1477; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1478; GCN-NEXT: s_load_dword s2, s[0:1], 0xd 1479; GCN-NEXT: s_mov_b32 s1, 0 1480; GCN-NEXT: s_mov_b32 s0, 4.0 1481; GCN-NEXT: s_mov_b32 s7, 0xf000 1482; GCN-NEXT: s_mov_b32 s6, -1 1483; GCN-NEXT: s_waitcnt lgkmcnt(0) 1484; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], s2 1485; GCN-NEXT: v_mov_b32_e32 v0, s0 1486; GCN-NEXT: v_mov_b32_e32 v1, s1 1487; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1488; GCN-NEXT: s_endpgm 1489; 1490; EG-LABEL: s_shl_inline_imm_f32_4_0_i64: 1491; EG: ; %bb.0: 1492; EG-NEXT: ALU 14, @4, KC0[CB0:0-32], KC1[] 1493; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1494; EG-NEXT: CF_END 1495; EG-NEXT: PAD 1496; EG-NEXT: ALU clause starting at 4: 1497; EG-NEXT: SUB_INT * T0.W, literal.x, KC0[2].W, 1498; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 1499; EG-NEXT: LSHR T0.W, literal.x, PV.W, 1500; EG-NEXT: ADD_INT * T1.W, KC0[2].W, literal.y, 1501; EG-NEXT: 1082130432(4.000000e+00), -32(nan) 1502; EG-NEXT: LSHL T0.Z, literal.x, PS, 1503; EG-NEXT: LSHR T0.W, PV.W, 1, 1504; EG-NEXT: SETGT_UINT * T1.W, KC0[2].W, literal.y, 1505; EG-NEXT: 1082130432(4.000000e+00), 31(4.344025e-44) 1506; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, PV.Z, 1507; EG-NEXT: LSHL * T0.W, literal.x, KC0[2].W, 1508; EG-NEXT: 1082130432(4.000000e+00), 0(0.000000e+00) 1509; EG-NEXT: CNDE_INT T0.X, T1.W, PV.W, 0.0, 1510; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1511; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1512 %shl = shl i64 1082130432, %a 1513 store i64 %shl, i64 addrspace(1)* %out, align 8 1514 ret void 1515} 1516 1517; FIXME: Copy of -1 register 1518define amdgpu_kernel void @s_shl_inline_imm_f32_neg_4_0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1519; GCN-LABEL: s_shl_inline_imm_f32_neg_4_0_i64: 1520; GCN: ; %bb.0: 1521; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1522; GCN-NEXT: s_load_dword s2, s[0:1], 0xd 1523; GCN-NEXT: s_mov_b32 s6, -1 1524; GCN-NEXT: s_mov_b32 s0, -4.0 1525; GCN-NEXT: s_mov_b32 s1, s6 1526; GCN-NEXT: s_mov_b32 s7, 0xf000 1527; GCN-NEXT: s_waitcnt lgkmcnt(0) 1528; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], s2 1529; GCN-NEXT: v_mov_b32_e32 v0, s0 1530; GCN-NEXT: v_mov_b32_e32 v1, s1 1531; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1532; GCN-NEXT: s_endpgm 1533; 1534; EG-LABEL: s_shl_inline_imm_f32_neg_4_0_i64: 1535; EG: ; %bb.0: 1536; EG-NEXT: ALU 17, @4, KC0[CB0:0-32], KC1[] 1537; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1538; EG-NEXT: CF_END 1539; EG-NEXT: PAD 1540; EG-NEXT: ALU clause starting at 4: 1541; EG-NEXT: SUB_INT * T0.W, literal.x, KC0[2].W, 1542; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 1543; EG-NEXT: LSHR * T0.W, literal.x, PV.W, 1544; EG-NEXT: -1065353216(-4.000000e+00), 0(0.000000e+00) 1545; EG-NEXT: ADD_INT T0.Z, KC0[2].W, literal.x, 1546; EG-NEXT: LSHR T0.W, PV.W, 1, 1547; EG-NEXT: LSHL * T1.W, literal.y, KC0[2].W, 1548; EG-NEXT: -32(nan), -1(nan) 1549; EG-NEXT: OR_INT T1.Z, PS, PV.W, 1550; EG-NEXT: LSHL T0.W, literal.x, PV.Z, 1551; EG-NEXT: SETGT_UINT * T1.W, KC0[2].W, literal.y, 1552; EG-NEXT: -1065353216(-4.000000e+00), 31(4.344025e-44) 1553; EG-NEXT: CNDE_INT T0.Y, PS, PV.Z, PV.W, 1554; EG-NEXT: LSHL * T0.W, literal.x, KC0[2].W, 1555; EG-NEXT: -1065353216(-4.000000e+00), 0(0.000000e+00) 1556; EG-NEXT: CNDE_INT T0.X, T1.W, PV.W, 0.0, 1557; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1558; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1559 %shl = shl i64 -1065353216, %a 1560 store i64 %shl, i64 addrspace(1)* %out, align 8 1561 ret void 1562} 1563 1564define amdgpu_kernel void @s_shl_inline_high_imm_f32_4_0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1565; GCN-LABEL: s_shl_inline_high_imm_f32_4_0_i64: 1566; GCN: ; %bb.0: 1567; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1568; GCN-NEXT: s_load_dword s2, s[0:1], 0xd 1569; GCN-NEXT: s_mov_b32 s1, 4.0 1570; GCN-NEXT: s_mov_b32 s0, 0 1571; GCN-NEXT: s_mov_b32 s7, 0xf000 1572; GCN-NEXT: s_mov_b32 s6, -1 1573; GCN-NEXT: s_waitcnt lgkmcnt(0) 1574; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], s2 1575; GCN-NEXT: v_mov_b32_e32 v0, s0 1576; GCN-NEXT: v_mov_b32_e32 v1, s1 1577; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1578; GCN-NEXT: s_endpgm 1579; 1580; EG-LABEL: s_shl_inline_high_imm_f32_4_0_i64: 1581; EG: ; %bb.0: 1582; EG-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[] 1583; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1584; EG-NEXT: CF_END 1585; EG-NEXT: PAD 1586; EG-NEXT: ALU clause starting at 4: 1587; EG-NEXT: SETGT_UINT T0.W, KC0[2].W, literal.x, 1588; EG-NEXT: LSHL * T1.W, literal.y, KC0[2].W, 1589; EG-NEXT: 31(4.344025e-44), 1082130432(4.000000e+00) 1590; EG-NEXT: CNDE_INT * T0.Y, PV.W, PS, 0.0, 1591; EG-NEXT: MOV T0.X, 0.0, 1592; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1593; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1594 %shl = shl i64 4647714815446351872, %a 1595 store i64 %shl, i64 addrspace(1)* %out, align 8 1596 ret void 1597} 1598 1599define amdgpu_kernel void @s_shl_inline_high_imm_f32_neg_4_0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1600; GCN-LABEL: s_shl_inline_high_imm_f32_neg_4_0_i64: 1601; GCN: ; %bb.0: 1602; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1603; GCN-NEXT: s_load_dword s2, s[0:1], 0xd 1604; GCN-NEXT: s_mov_b32 s1, -4.0 1605; GCN-NEXT: s_mov_b32 s0, 0 1606; GCN-NEXT: s_mov_b32 s7, 0xf000 1607; GCN-NEXT: s_mov_b32 s6, -1 1608; GCN-NEXT: s_waitcnt lgkmcnt(0) 1609; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], s2 1610; GCN-NEXT: v_mov_b32_e32 v0, s0 1611; GCN-NEXT: v_mov_b32_e32 v1, s1 1612; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1613; GCN-NEXT: s_endpgm 1614; 1615; EG-LABEL: s_shl_inline_high_imm_f32_neg_4_0_i64: 1616; EG: ; %bb.0: 1617; EG-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[] 1618; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1619; EG-NEXT: CF_END 1620; EG-NEXT: PAD 1621; EG-NEXT: ALU clause starting at 4: 1622; EG-NEXT: SETGT_UINT T0.W, KC0[2].W, literal.x, 1623; EG-NEXT: LSHL * T1.W, literal.y, KC0[2].W, 1624; EG-NEXT: 31(4.344025e-44), -1065353216(-4.000000e+00) 1625; EG-NEXT: CNDE_INT * T0.Y, PV.W, PS, 0.0, 1626; EG-NEXT: MOV T0.X, 0.0, 1627; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1628; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1629 %shl = shl i64 13871086852301127680, %a 1630 store i64 %shl, i64 addrspace(1)* %out, align 8 1631 ret void 1632} 1633 1634define amdgpu_kernel void @test_mul2(i32 %p) { 1635; GCN-LABEL: test_mul2: 1636; GCN: ; %bb.0: 1637; GCN-NEXT: s_load_dword s0, s[0:1], 0x9 1638; GCN-NEXT: s_mov_b32 s3, 0xf000 1639; GCN-NEXT: s_mov_b32 s2, -1 1640; GCN-NEXT: s_waitcnt lgkmcnt(0) 1641; GCN-NEXT: s_lshl_b32 s0, s0, 1 1642; GCN-NEXT: v_mov_b32_e32 v0, s0 1643; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 1644; GCN-NEXT: s_waitcnt vmcnt(0) 1645; GCN-NEXT: s_endpgm 1646; 1647; EG-LABEL: test_mul2: 1648; EG: ; %bb.0: 1649; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] 1650; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1 1651; EG-NEXT: CF_END 1652; EG-NEXT: PAD 1653; EG-NEXT: ALU clause starting at 4: 1654; EG-NEXT: MOV T0.X, literal.x, 1655; EG-NEXT: LSHL * T1.X, KC0[2].Y, 1, 1656; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00) 1657 %i = mul i32 %p, 2 1658 store volatile i32 %i, i32 addrspace(1)* undef 1659 ret void 1660} 1661 1662define void @shl_or_k(i32 addrspace(1)* %out, i32 %in) { 1663; GCN-LABEL: shl_or_k: 1664; GCN: ; %bb.0: 1665; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1666; GCN-NEXT: s_mov_b32 s6, 0 1667; GCN-NEXT: v_lshlrev_b32_e32 v2, 2, v2 1668; GCN-NEXT: s_mov_b32 s7, 0xf000 1669; GCN-NEXT: s_mov_b32 s4, s6 1670; GCN-NEXT: s_mov_b32 s5, s6 1671; GCN-NEXT: v_or_b32_e32 v2, 4, v2 1672; GCN-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 1673; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) 1674; GCN-NEXT: s_setpc_b64 s[30:31] 1675; 1676; EG-LABEL: shl_or_k: 1677; EG: ; %bb.0: 1678; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[] 1679; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 1680; EG-NEXT: CF_END 1681; EG-NEXT: PAD 1682; EG-NEXT: ALU clause starting at 4: 1683; EG-NEXT: LSHL * T0.W, KC0[2].Z, literal.x, 1684; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1685; EG-NEXT: OR_INT T0.X, PV.W, literal.x, 1686; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, 1687; EG-NEXT: 4(5.605194e-45), 2(2.802597e-45) 1688 %tmp0 = or i32 %in, 1 1689 %tmp2 = shl i32 %tmp0, 2 1690 store i32 %tmp2, i32 addrspace(1)* %out 1691 ret void 1692} 1693 1694define void @shl_or_k_two_uses(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 %in) { 1695; GCN-LABEL: shl_or_k_two_uses: 1696; GCN: ; %bb.0: 1697; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1698; GCN-NEXT: s_mov_b32 s6, 0 1699; GCN-NEXT: v_or_b32_e32 v4, 1, v4 1700; GCN-NEXT: s_mov_b32 s7, 0xf000 1701; GCN-NEXT: s_mov_b32 s4, s6 1702; GCN-NEXT: s_mov_b32 s5, s6 1703; GCN-NEXT: v_lshlrev_b32_e32 v5, 2, v4 1704; GCN-NEXT: buffer_store_dword v5, v[0:1], s[4:7], 0 addr64 1705; GCN-NEXT: buffer_store_dword v4, v[2:3], s[4:7], 0 addr64 1706; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) 1707; GCN-NEXT: s_setpc_b64 s[30:31] 1708; 1709; EG-LABEL: shl_or_k_two_uses: 1710; EG: ; %bb.0: 1711; EG-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[] 1712; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T3.X, 0 1713; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1 1714; EG-NEXT: CF_END 1715; EG-NEXT: ALU clause starting at 4: 1716; EG-NEXT: LSHR T0.X, KC0[2].Z, literal.x, 1717; EG-NEXT: OR_INT * T1.X, KC0[2].W, 1, 1718; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1719; EG-NEXT: LSHL T2.X, PS, literal.x, 1720; EG-NEXT: LSHR * T3.X, KC0[2].Y, literal.x, 1721; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1722 %tmp0 = or i32 %in, 1 1723 %tmp2 = shl i32 %tmp0, 2 1724 store i32 %tmp2, i32 addrspace(1)* %out0 1725 store i32 %tmp0, i32 addrspace(1)* %out1 1726 ret void 1727} 1728 1729attributes #0 = { nounwind readnone } 1730