1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -amdgpu-scalarize-global-loads=false -march=amdgcn -mtriple=amdgcn-- -mcpu=verde -verify-machineinstrs | FileCheck %s --check-prefixes=SI 3; RUN: llc < %s -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s -check-prefixes=VI 4; RUN: llc < %s -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600-- -mcpu=redwood -verify-machineinstrs | FileCheck %s --check-prefixes=EG 5 6declare i32 @llvm.amdgcn.workitem.id.x() #0 7 8declare i32 @llvm.amdgcn.workgroup.id.x() #0 9 10define amdgpu_kernel void @shl_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { 11; SI-LABEL: shl_v2i32: 12; SI: ; %bb.0: 13; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 14; SI-NEXT: s_mov_b32 s3, 0xf000 15; SI-NEXT: s_mov_b32 s2, -1 16; SI-NEXT: s_mov_b32 s10, s2 17; SI-NEXT: s_mov_b32 s11, s3 18; SI-NEXT: s_waitcnt lgkmcnt(0) 19; SI-NEXT: s_mov_b32 s8, s6 20; SI-NEXT: s_mov_b32 s9, s7 21; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 22; SI-NEXT: s_mov_b32 s0, s4 23; SI-NEXT: s_mov_b32 s1, s5 24; SI-NEXT: s_waitcnt vmcnt(0) 25; SI-NEXT: v_lshl_b32_e32 v1, v1, v3 26; SI-NEXT: v_lshl_b32_e32 v0, v0, v2 27; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 28; SI-NEXT: s_endpgm 29; 30; VI-LABEL: shl_v2i32: 31; VI: ; %bb.0: 32; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 33; VI-NEXT: s_mov_b32 s3, 0xf000 34; VI-NEXT: s_mov_b32 s2, -1 35; VI-NEXT: s_waitcnt lgkmcnt(0) 36; VI-NEXT: s_load_dwordx2 s[8:9], s[6:7], 0x0 37; VI-NEXT: s_load_dwordx2 s[6:7], s[6:7], 0x8 38; VI-NEXT: s_mov_b32 s0, s4 39; VI-NEXT: s_mov_b32 s1, s5 40; VI-NEXT: s_waitcnt lgkmcnt(0) 41; VI-NEXT: s_lshl_b32 s4, s9, s7 42; VI-NEXT: s_lshl_b32 s5, s8, s6 43; VI-NEXT: v_mov_b32_e32 v0, s5 44; VI-NEXT: v_mov_b32_e32 v1, s4 45; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 46; VI-NEXT: s_endpgm 47; 48; EG-LABEL: shl_v2i32: 49; EG: ; %bb.0: 50; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] 51; EG-NEXT: TEX 1 @6 52; EG-NEXT: ALU 3, @11, KC0[CB0:0-32], KC1[] 53; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 54; EG-NEXT: CF_END 55; EG-NEXT: PAD 56; EG-NEXT: Fetch clause starting at 6: 57; EG-NEXT: VTX_READ_64 T1.XY, T0.X, 8, #1 58; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1 59; EG-NEXT: ALU clause starting at 10: 60; EG-NEXT: MOV * T0.X, KC0[2].Z, 61; EG-NEXT: ALU clause starting at 11: 62; EG-NEXT: LSHL * T0.Y, T0.Y, T1.Y, 63; EG-NEXT: LSHL T0.X, T0.X, T1.X, 64; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 65; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 66 %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1 67 %a = load <2 x i32>, <2 x i32> addrspace(1)* %in 68 %b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr 69 %result = shl <2 x i32> %a, %b 70 store <2 x i32> %result, <2 x i32> addrspace(1)* %out 71 ret void 72} 73 74define amdgpu_kernel void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { 75; SI-LABEL: shl_v4i32: 76; SI: ; %bb.0: 77; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 78; SI-NEXT: s_mov_b32 s3, 0xf000 79; SI-NEXT: s_mov_b32 s2, -1 80; SI-NEXT: s_mov_b32 s10, s2 81; SI-NEXT: s_mov_b32 s11, s3 82; SI-NEXT: s_waitcnt lgkmcnt(0) 83; SI-NEXT: s_mov_b32 s8, s6 84; SI-NEXT: s_mov_b32 s9, s7 85; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 86; SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16 87; SI-NEXT: s_mov_b32 s0, s4 88; SI-NEXT: s_mov_b32 s1, s5 89; SI-NEXT: s_waitcnt vmcnt(0) 90; SI-NEXT: v_lshl_b32_e32 v3, v3, v7 91; SI-NEXT: v_lshl_b32_e32 v2, v2, v6 92; SI-NEXT: v_lshl_b32_e32 v1, v1, v5 93; SI-NEXT: v_lshl_b32_e32 v0, v0, v4 94; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 95; SI-NEXT: s_endpgm 96; 97; VI-LABEL: shl_v4i32: 98; VI: ; %bb.0: 99; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 100; VI-NEXT: s_mov_b32 s3, 0xf000 101; VI-NEXT: s_mov_b32 s2, -1 102; VI-NEXT: s_waitcnt lgkmcnt(0) 103; VI-NEXT: s_mov_b32 s0, s4 104; VI-NEXT: s_mov_b32 s1, s5 105; VI-NEXT: s_load_dwordx4 s[8:11], s[6:7], 0x0 106; VI-NEXT: s_load_dwordx4 s[4:7], s[6:7], 0x10 107; VI-NEXT: s_waitcnt lgkmcnt(0) 108; VI-NEXT: s_lshl_b32 s7, s11, s7 109; VI-NEXT: s_lshl_b32 s6, s10, s6 110; VI-NEXT: s_lshl_b32 s5, s9, s5 111; VI-NEXT: s_lshl_b32 s4, s8, s4 112; VI-NEXT: v_mov_b32_e32 v0, s4 113; VI-NEXT: v_mov_b32_e32 v1, s5 114; VI-NEXT: v_mov_b32_e32 v2, s6 115; VI-NEXT: v_mov_b32_e32 v3, s7 116; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 117; VI-NEXT: s_endpgm 118; 119; EG-LABEL: shl_v4i32: 120; EG: ; %bb.0: 121; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] 122; EG-NEXT: TEX 1 @6 123; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[] 124; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1 125; EG-NEXT: CF_END 126; EG-NEXT: PAD 127; EG-NEXT: Fetch clause starting at 6: 128; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1 129; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1 130; EG-NEXT: ALU clause starting at 10: 131; EG-NEXT: MOV * T0.X, KC0[2].Z, 132; EG-NEXT: ALU clause starting at 11: 133; EG-NEXT: LSHL * T0.W, T0.W, T1.W, 134; EG-NEXT: LSHL * T0.Z, T0.Z, T1.Z, 135; EG-NEXT: LSHL * T0.Y, T0.Y, T1.Y, 136; EG-NEXT: LSHL T0.X, T0.X, T1.X, 137; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 138; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 139 %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1 140 %a = load <4 x i32>, <4 x i32> addrspace(1)* %in 141 %b = load <4 x i32>, <4 x i32> addrspace(1)* %b_ptr 142 %result = shl <4 x i32> %a, %b 143 store <4 x i32> %result, <4 x i32> addrspace(1)* %out 144 ret void 145} 146 147define amdgpu_kernel void @shl_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) { 148; SI-LABEL: shl_i16: 149; SI: ; %bb.0: 150; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 151; SI-NEXT: s_mov_b32 s3, 0xf000 152; SI-NEXT: s_mov_b32 s2, -1 153; SI-NEXT: s_waitcnt lgkmcnt(0) 154; SI-NEXT: s_mov_b32 s0, s4 155; SI-NEXT: s_mov_b32 s1, s5 156; SI-NEXT: s_mov_b32 s4, s6 157; SI-NEXT: s_mov_b32 s5, s7 158; SI-NEXT: s_mov_b32 s6, s2 159; SI-NEXT: s_mov_b32 s7, s3 160; SI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 161; SI-NEXT: buffer_load_ushort v1, off, s[4:7], 0 offset:2 162; SI-NEXT: s_waitcnt vmcnt(0) 163; SI-NEXT: v_lshlrev_b32_e32 v0, v1, v0 164; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 165; SI-NEXT: s_endpgm 166; 167; VI-LABEL: shl_i16: 168; VI: ; %bb.0: 169; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 170; VI-NEXT: s_mov_b32 s3, 0xf000 171; VI-NEXT: s_mov_b32 s2, -1 172; VI-NEXT: s_waitcnt lgkmcnt(0) 173; VI-NEXT: s_mov_b32 s0, s4 174; VI-NEXT: s_mov_b32 s1, s5 175; VI-NEXT: s_mov_b32 s4, s6 176; VI-NEXT: s_mov_b32 s5, s7 177; VI-NEXT: s_mov_b32 s6, s2 178; VI-NEXT: s_mov_b32 s7, s3 179; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 180; VI-NEXT: buffer_load_ushort v1, off, s[4:7], 0 offset:2 181; VI-NEXT: s_waitcnt vmcnt(0) 182; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v0 183; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 184; VI-NEXT: s_endpgm 185; 186; EG-LABEL: shl_i16: 187; EG: ; %bb.0: 188; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] 189; EG-NEXT: TEX 1 @6 190; EG-NEXT: ALU 12, @11, KC0[CB0:0-32], KC1[] 191; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X 192; EG-NEXT: CF_END 193; EG-NEXT: PAD 194; EG-NEXT: Fetch clause starting at 6: 195; EG-NEXT: VTX_READ_16 T1.X, T0.X, 2, #1 196; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #1 197; EG-NEXT: ALU clause starting at 10: 198; EG-NEXT: MOV * T0.X, KC0[2].Z, 199; EG-NEXT: ALU clause starting at 11: 200; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x, 201; EG-NEXT: LSHL * T1.W, T0.X, T1.X, 202; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) 203; EG-NEXT: AND_INT T1.W, PS, literal.x, 204; EG-NEXT: LSHL * T0.W, PV.W, literal.y, 205; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45) 206; EG-NEXT: LSHL T0.X, PV.W, PS, 207; EG-NEXT: LSHL * T0.W, literal.x, PS, 208; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) 209; EG-NEXT: MOV T0.Y, 0.0, 210; EG-NEXT: MOV * T0.Z, 0.0, 211; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 212; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 213 %b_ptr = getelementptr i16, i16 addrspace(1)* %in, i16 1 214 %a = load i16, i16 addrspace(1)* %in 215 %b = load i16, i16 addrspace(1)* %b_ptr 216 %result = shl i16 %a, %b 217 store i16 %result, i16 addrspace(1)* %out 218 ret void 219} 220 221define amdgpu_kernel void @shl_i16_v_s(i16 addrspace(1)* %out, i16 addrspace(1)* %in, i16 %b) { 222; SI-LABEL: shl_i16_v_s: 223; SI: ; %bb.0: 224; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 225; SI-NEXT: s_load_dword s8, s[0:1], 0xd 226; SI-NEXT: s_mov_b32 s3, 0xf000 227; SI-NEXT: s_mov_b32 s2, -1 228; SI-NEXT: s_waitcnt lgkmcnt(0) 229; SI-NEXT: s_mov_b32 s0, s4 230; SI-NEXT: s_mov_b32 s1, s5 231; SI-NEXT: s_mov_b32 s4, s6 232; SI-NEXT: s_mov_b32 s5, s7 233; SI-NEXT: s_mov_b32 s6, s2 234; SI-NEXT: s_mov_b32 s7, s3 235; SI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 236; SI-NEXT: s_waitcnt vmcnt(0) 237; SI-NEXT: v_lshlrev_b32_e32 v0, s8, v0 238; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 239; SI-NEXT: s_endpgm 240; 241; VI-LABEL: shl_i16_v_s: 242; VI: ; %bb.0: 243; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 244; VI-NEXT: s_load_dword s8, s[0:1], 0x34 245; VI-NEXT: s_mov_b32 s3, 0xf000 246; VI-NEXT: s_mov_b32 s2, -1 247; VI-NEXT: s_waitcnt lgkmcnt(0) 248; VI-NEXT: s_mov_b32 s0, s4 249; VI-NEXT: s_mov_b32 s1, s5 250; VI-NEXT: s_mov_b32 s4, s6 251; VI-NEXT: s_mov_b32 s5, s7 252; VI-NEXT: s_mov_b32 s6, s2 253; VI-NEXT: s_mov_b32 s7, s3 254; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 255; VI-NEXT: s_waitcnt vmcnt(0) 256; VI-NEXT: v_lshlrev_b32_e32 v0, s8, v0 257; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 258; VI-NEXT: s_endpgm 259; 260; EG-LABEL: shl_i16_v_s: 261; EG: ; %bb.0: 262; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[] 263; EG-NEXT: TEX 1 @6 264; EG-NEXT: ALU 12, @12, KC0[CB0:0-32], KC1[] 265; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X 266; EG-NEXT: CF_END 267; EG-NEXT: PAD 268; EG-NEXT: Fetch clause starting at 6: 269; EG-NEXT: VTX_READ_16 T1.X, T1.X, 0, #1 270; EG-NEXT: VTX_READ_16 T0.X, T0.X, 44, #3 271; EG-NEXT: ALU clause starting at 10: 272; EG-NEXT: MOV T0.X, 0.0, 273; EG-NEXT: MOV * T1.X, KC0[2].Z, 274; EG-NEXT: ALU clause starting at 12: 275; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x, 276; EG-NEXT: LSHL * T1.W, T1.X, T0.X, 277; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) 278; EG-NEXT: AND_INT T1.W, PS, literal.x, 279; EG-NEXT: LSHL * T0.W, PV.W, literal.y, 280; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45) 281; EG-NEXT: LSHL T0.X, PV.W, PS, 282; EG-NEXT: LSHL * T0.W, literal.x, PS, 283; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) 284; EG-NEXT: MOV T0.Y, 0.0, 285; EG-NEXT: MOV * T0.Z, 0.0, 286; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 287; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 288 %a = load i16, i16 addrspace(1)* %in 289 %result = shl i16 %a, %b 290 store i16 %result, i16 addrspace(1)* %out 291 ret void 292} 293 294define amdgpu_kernel void @shl_i16_v_compute_s(i16 addrspace(1)* %out, i16 addrspace(1)* %in, i16 %b) { 295; SI-LABEL: shl_i16_v_compute_s: 296; SI: ; %bb.0: 297; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 298; SI-NEXT: s_load_dword s8, s[0:1], 0xd 299; SI-NEXT: s_mov_b32 s3, 0xf000 300; SI-NEXT: s_mov_b32 s2, -1 301; SI-NEXT: s_waitcnt lgkmcnt(0) 302; SI-NEXT: s_mov_b32 s0, s4 303; SI-NEXT: s_mov_b32 s1, s5 304; SI-NEXT: s_mov_b32 s4, s6 305; SI-NEXT: s_mov_b32 s5, s7 306; SI-NEXT: s_mov_b32 s6, s2 307; SI-NEXT: s_mov_b32 s7, s3 308; SI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 309; SI-NEXT: s_add_i32 s8, s8, 3 310; SI-NEXT: s_waitcnt vmcnt(0) 311; SI-NEXT: v_lshlrev_b32_e32 v0, s8, v0 312; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 313; SI-NEXT: s_endpgm 314; 315; VI-LABEL: shl_i16_v_compute_s: 316; VI: ; %bb.0: 317; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 318; VI-NEXT: s_load_dword s8, s[0:1], 0x34 319; VI-NEXT: s_mov_b32 s3, 0xf000 320; VI-NEXT: s_mov_b32 s2, -1 321; VI-NEXT: s_waitcnt lgkmcnt(0) 322; VI-NEXT: s_mov_b32 s0, s4 323; VI-NEXT: s_mov_b32 s1, s5 324; VI-NEXT: s_mov_b32 s4, s6 325; VI-NEXT: s_mov_b32 s5, s7 326; VI-NEXT: s_mov_b32 s6, s2 327; VI-NEXT: s_mov_b32 s7, s3 328; VI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 329; VI-NEXT: s_add_i32 s8, s8, 3 330; VI-NEXT: s_waitcnt vmcnt(0) 331; VI-NEXT: v_lshlrev_b32_e32 v0, s8, v0 332; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 333; VI-NEXT: s_endpgm 334; 335; EG-LABEL: shl_i16_v_compute_s: 336; EG: ; %bb.0: 337; EG-NEXT: ALU 0, @12, KC0[], KC1[] 338; EG-NEXT: TEX 0 @8 339; EG-NEXT: ALU 0, @13, KC0[CB0:0-32], KC1[] 340; EG-NEXT: TEX 0 @10 341; EG-NEXT: ALU 15, @14, KC0[CB0:0-32], KC1[] 342; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X 343; EG-NEXT: CF_END 344; EG-NEXT: PAD 345; EG-NEXT: Fetch clause starting at 8: 346; EG-NEXT: VTX_READ_16 T0.X, T0.X, 44, #3 347; EG-NEXT: Fetch clause starting at 10: 348; EG-NEXT: VTX_READ_16 T1.X, T1.X, 0, #1 349; EG-NEXT: ALU clause starting at 12: 350; EG-NEXT: MOV * T0.X, 0.0, 351; EG-NEXT: ALU clause starting at 13: 352; EG-NEXT: MOV * T1.X, KC0[2].Z, 353; EG-NEXT: ALU clause starting at 14: 354; EG-NEXT: ADD_INT * T0.W, T0.X, literal.x, 355; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) 356; EG-NEXT: AND_INT T0.W, PV.W, literal.x, 357; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y, 358; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45) 359; EG-NEXT: LSHL * T0.W, T1.X, PV.W, 360; EG-NEXT: AND_INT T0.W, PV.W, literal.x, 361; EG-NEXT: LSHL * T1.W, T1.W, literal.y, 362; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45) 363; EG-NEXT: LSHL T0.X, PV.W, PS, 364; EG-NEXT: LSHL * T0.W, literal.x, PS, 365; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) 366; EG-NEXT: MOV T0.Y, 0.0, 367; EG-NEXT: MOV * T0.Z, 0.0, 368; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 369; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 370 %a = load i16, i16 addrspace(1)* %in 371 %b.add = add i16 %b, 3 372 %result = shl i16 %a, %b.add 373 store i16 %result, i16 addrspace(1)* %out 374 ret void 375} 376 377define amdgpu_kernel void @shl_i16_computed_amount(i16 addrspace(1)* %out, i16 addrspace(1)* %in) { 378; SI-LABEL: shl_i16_computed_amount: 379; SI: ; %bb.0: 380; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 381; SI-NEXT: s_mov_b32 s3, 0xf000 382; SI-NEXT: s_mov_b32 s2, -1 383; SI-NEXT: s_mov_b32 s10, s2 384; SI-NEXT: s_mov_b32 s11, s3 385; SI-NEXT: s_waitcnt lgkmcnt(0) 386; SI-NEXT: s_mov_b32 s8, s6 387; SI-NEXT: s_mov_b32 s9, s7 388; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0 389; SI-NEXT: v_mov_b32_e32 v1, 0 390; SI-NEXT: s_mov_b32 s14, 0 391; SI-NEXT: s_mov_b32 s15, s3 392; SI-NEXT: s_mov_b64 s[12:13], s[6:7] 393; SI-NEXT: buffer_load_ushort v2, off, s[8:11], 0 glc 394; SI-NEXT: s_waitcnt vmcnt(0) 395; SI-NEXT: buffer_load_ushort v0, v[0:1], s[12:15], 0 addr64 offset:2 glc 396; SI-NEXT: s_waitcnt vmcnt(0) 397; SI-NEXT: s_mov_b32 s0, s4 398; SI-NEXT: s_mov_b32 s1, s5 399; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0 400; SI-NEXT: v_lshlrev_b32_e32 v0, v0, v2 401; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 402; SI-NEXT: s_endpgm 403; 404; VI-LABEL: shl_i16_computed_amount: 405; VI: ; %bb.0: 406; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 407; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v0 408; VI-NEXT: s_mov_b32 s3, 0xf000 409; VI-NEXT: s_mov_b32 s2, -1 410; VI-NEXT: s_mov_b32 s10, s2 411; VI-NEXT: s_waitcnt lgkmcnt(0) 412; VI-NEXT: v_mov_b32_e32 v1, s7 413; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v0 414; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 415; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0 416; VI-NEXT: s_mov_b32 s8, s6 417; VI-NEXT: s_mov_b32 s9, s7 418; VI-NEXT: s_mov_b32 s11, s3 419; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 420; VI-NEXT: buffer_load_ushort v2, off, s[8:11], 0 glc 421; VI-NEXT: s_waitcnt vmcnt(0) 422; VI-NEXT: flat_load_ushort v0, v[0:1] glc 423; VI-NEXT: s_waitcnt vmcnt(0) 424; VI-NEXT: s_mov_b32 s0, s4 425; VI-NEXT: s_mov_b32 s1, s5 426; VI-NEXT: v_add_u16_e32 v0, 3, v0 427; VI-NEXT: v_lshlrev_b16_e32 v0, v0, v2 428; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 429; VI-NEXT: s_endpgm 430; 431; EG-LABEL: shl_i16_computed_amount: 432; EG: ; %bb.0: 433; EG-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[] 434; EG-NEXT: TEX 0 @8 435; EG-NEXT: ALU 1, @13, KC0[CB0:0-32], KC1[] 436; EG-NEXT: TEX 0 @10 437; EG-NEXT: ALU 15, @15, KC0[CB0:0-32], KC1[] 438; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X 439; EG-NEXT: CF_END 440; EG-NEXT: PAD 441; EG-NEXT: Fetch clause starting at 8: 442; EG-NEXT: VTX_READ_16 T1.X, T1.X, 0, #1 443; EG-NEXT: Fetch clause starting at 10: 444; EG-NEXT: VTX_READ_16 T0.X, T0.X, 2, #1 445; EG-NEXT: ALU clause starting at 12: 446; EG-NEXT: MOV * T1.X, KC0[2].Z, 447; EG-NEXT: ALU clause starting at 13: 448; EG-NEXT: LSHL * T0.W, T0.X, 1, 449; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, 450; EG-NEXT: ALU clause starting at 15: 451; EG-NEXT: ADD_INT * T0.W, T0.X, literal.x, 452; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) 453; EG-NEXT: AND_INT T0.W, PV.W, literal.x, 454; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y, 455; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45) 456; EG-NEXT: LSHL * T0.W, T1.X, PV.W, 457; EG-NEXT: AND_INT T0.W, PV.W, literal.x, 458; EG-NEXT: LSHL * T1.W, T1.W, literal.y, 459; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45) 460; EG-NEXT: LSHL T0.X, PV.W, PS, 461; EG-NEXT: LSHL * T0.W, literal.x, PS, 462; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) 463; EG-NEXT: MOV T0.Y, 0.0, 464; EG-NEXT: MOV * T0.Z, 0.0, 465; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 466; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 467 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 468 %gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i32 %tid 469 %gep.out = getelementptr inbounds i16, i16 addrspace(1)* %out, i32 %tid 470 %b_ptr = getelementptr i16, i16 addrspace(1)* %gep, i16 1 471 %a = load volatile i16, i16 addrspace(1)* %in 472 %b = load volatile i16, i16 addrspace(1)* %b_ptr 473 %b.add = add i16 %b, 3 474 %result = shl i16 %a, %b.add 475 store i16 %result, i16 addrspace(1)* %out 476 ret void 477} 478 479define amdgpu_kernel void @shl_i16_i_s(i16 addrspace(1)* %out, i16 zeroext %a) { 480; SI-LABEL: shl_i16_i_s: 481; SI: ; %bb.0: 482; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 483; SI-NEXT: s_load_dword s0, s[0:1], 0xb 484; SI-NEXT: s_mov_b32 s7, 0xf000 485; SI-NEXT: s_mov_b32 s6, -1 486; SI-NEXT: s_waitcnt lgkmcnt(0) 487; SI-NEXT: s_lshl_b32 s0, s0, 12 488; SI-NEXT: v_mov_b32_e32 v0, s0 489; SI-NEXT: buffer_store_short v0, off, s[4:7], 0 490; SI-NEXT: s_endpgm 491; 492; VI-LABEL: shl_i16_i_s: 493; VI: ; %bb.0: 494; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 495; VI-NEXT: s_load_dword s0, s[0:1], 0x2c 496; VI-NEXT: s_mov_b32 s7, 0xf000 497; VI-NEXT: s_mov_b32 s6, -1 498; VI-NEXT: s_waitcnt lgkmcnt(0) 499; VI-NEXT: s_lshl_b32 s0, s0, 12 500; VI-NEXT: v_mov_b32_e32 v0, s0 501; VI-NEXT: buffer_store_short v0, off, s[4:7], 0 502; VI-NEXT: s_endpgm 503; 504; EG-LABEL: shl_i16_i_s: 505; EG: ; %bb.0: 506; EG-NEXT: ALU 0, @8, KC0[], KC1[] 507; EG-NEXT: TEX 0 @6 508; EG-NEXT: ALU 14, @9, KC0[CB0:0-32], KC1[] 509; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X 510; EG-NEXT: CF_END 511; EG-NEXT: PAD 512; EG-NEXT: Fetch clause starting at 6: 513; EG-NEXT: VTX_READ_16 T0.X, T0.X, 40, #3 514; EG-NEXT: ALU clause starting at 8: 515; EG-NEXT: MOV * T0.X, 0.0, 516; EG-NEXT: ALU clause starting at 9: 517; EG-NEXT: BFE_INT T0.W, T0.X, 0.0, literal.x, 518; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y, 519; EG-NEXT: 16(2.242078e-44), 3(4.203895e-45) 520; EG-NEXT: LSHL * T0.W, PV.W, literal.x, 521; EG-NEXT: 12(1.681558e-44), 0(0.000000e+00) 522; EG-NEXT: AND_INT T0.W, PV.W, literal.x, 523; EG-NEXT: LSHL * T1.W, T1.W, literal.y, 524; EG-NEXT: 61440(8.609578e-41), 3(4.203895e-45) 525; EG-NEXT: LSHL T0.X, PV.W, PS, 526; EG-NEXT: LSHL * T0.W, literal.x, PS, 527; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) 528; EG-NEXT: MOV T0.Y, 0.0, 529; EG-NEXT: MOV * T0.Z, 0.0, 530; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 531; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 532 %result = shl i16 %a, 12 533 store i16 %result, i16 addrspace(1)* %out 534 ret void 535} 536 537define amdgpu_kernel void @shl_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) { 538; SI-LABEL: shl_v2i16: 539; SI: ; %bb.0: 540; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 541; SI-NEXT: s_mov_b32 s3, 0xf000 542; SI-NEXT: s_mov_b32 s2, -1 543; SI-NEXT: s_mov_b32 s10, s2 544; SI-NEXT: s_mov_b32 s11, s3 545; SI-NEXT: s_waitcnt lgkmcnt(0) 546; SI-NEXT: s_mov_b32 s8, s6 547; SI-NEXT: s_mov_b32 s9, s7 548; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 549; SI-NEXT: v_mov_b32_e32 v1, 0 550; SI-NEXT: s_mov_b32 s14, 0 551; SI-NEXT: s_mov_b32 s15, s3 552; SI-NEXT: s_mov_b64 s[12:13], s[6:7] 553; SI-NEXT: buffer_load_dword v2, off, s[8:11], 0 554; SI-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64 offset:4 555; SI-NEXT: s_mov_b32 s0, s4 556; SI-NEXT: s_mov_b32 s1, s5 557; SI-NEXT: s_waitcnt vmcnt(1) 558; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v2 559; SI-NEXT: s_waitcnt vmcnt(0) 560; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v0 561; SI-NEXT: v_lshlrev_b32_e32 v0, v0, v2 562; SI-NEXT: v_lshlrev_b32_e32 v1, v3, v1 563; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0 564; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 565; SI-NEXT: v_or_b32_e32 v0, v0, v1 566; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 567; SI-NEXT: s_endpgm 568; 569; VI-LABEL: shl_v2i16: 570; VI: ; %bb.0: 571; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 572; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 573; VI-NEXT: s_waitcnt lgkmcnt(0) 574; VI-NEXT: s_load_dword s4, s[2:3], 0x0 575; VI-NEXT: v_mov_b32_e32 v1, s3 576; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0 577; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 578; VI-NEXT: v_add_u32_e32 v0, vcc, 4, v0 579; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 580; VI-NEXT: flat_load_dword v0, v[0:1] 581; VI-NEXT: s_waitcnt lgkmcnt(0) 582; VI-NEXT: s_lshr_b32 s5, s4, 16 583; VI-NEXT: v_mov_b32_e32 v1, s5 584; VI-NEXT: s_mov_b32 s3, 0xf000 585; VI-NEXT: s_mov_b32 s2, -1 586; VI-NEXT: s_waitcnt vmcnt(0) 587; VI-NEXT: v_lshlrev_b16_e64 v2, v0, s4 588; VI-NEXT: v_lshlrev_b16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 589; VI-NEXT: v_or_b32_e32 v0, v2, v0 590; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 591; VI-NEXT: s_endpgm 592; 593; EG-LABEL: shl_v2i16: 594; EG: ; %bb.0: 595; EG-NEXT: ALU 2, @12, KC0[CB0:0-32], KC1[] 596; EG-NEXT: TEX 0 @8 597; EG-NEXT: ALU 0, @15, KC0[CB0:0-32], KC1[] 598; EG-NEXT: TEX 0 @10 599; EG-NEXT: ALU 12, @16, KC0[CB0:0-32], KC1[] 600; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T7.X, 1 601; EG-NEXT: CF_END 602; EG-NEXT: PAD 603; EG-NEXT: Fetch clause starting at 8: 604; EG-NEXT: VTX_READ_32 T0.X, T0.X, 4, #1 605; EG-NEXT: Fetch clause starting at 10: 606; EG-NEXT: VTX_READ_32 T7.X, T7.X, 0, #1 607; EG-NEXT: ALU clause starting at 12: 608; EG-NEXT: LSHL * T0.W, T0.X, literal.x, 609; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 610; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, 611; EG-NEXT: ALU clause starting at 15: 612; EG-NEXT: MOV * T7.X, KC0[2].Z, 613; EG-NEXT: ALU clause starting at 16: 614; EG-NEXT: AND_INT T0.Y, T0.X, literal.x, 615; EG-NEXT: AND_INT T0.Z, T7.X, literal.x, BS:VEC_120/SCL_212 616; EG-NEXT: LSHR T0.W, T0.X, literal.y, 617; EG-NEXT: LSHR * T1.W, T7.X, literal.y, 618; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) 619; EG-NEXT: LSHL T0.W, PS, PV.W, 620; EG-NEXT: LSHL * T1.W, PV.Z, PV.Y, 621; EG-NEXT: AND_INT T1.W, PS, literal.x, 622; EG-NEXT: LSHL * T0.W, PV.W, literal.y, 623; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) 624; EG-NEXT: OR_INT T0.X, PV.W, PS, 625; EG-NEXT: LSHR * T7.X, KC0[2].Y, literal.x, 626; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 627 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 628 %gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i32 %tid 629 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid 630 %b_ptr = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %gep, i16 1 631 %a = load <2 x i16>, <2 x i16> addrspace(1)* %in 632 %b = load <2 x i16>, <2 x i16> addrspace(1)* %b_ptr 633 %result = shl <2 x i16> %a, %b 634 store <2 x i16> %result, <2 x i16> addrspace(1)* %out 635 ret void 636} 637 638define amdgpu_kernel void @shl_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) { 639; SI-LABEL: shl_v4i16: 640; SI: ; %bb.0: 641; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 642; SI-NEXT: s_mov_b32 s3, 0xf000 643; SI-NEXT: s_mov_b32 s2, 0 644; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 645; SI-NEXT: v_mov_b32_e32 v1, 0 646; SI-NEXT: s_waitcnt lgkmcnt(0) 647; SI-NEXT: s_mov_b64 s[0:1], s[6:7] 648; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 649; SI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[0:3], 0 addr64 offset:8 650; SI-NEXT: s_mov_b32 s0, 0xffff 651; SI-NEXT: s_mov_b64 s[6:7], s[2:3] 652; SI-NEXT: s_waitcnt vmcnt(1) 653; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v2 654; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v3 655; SI-NEXT: s_waitcnt vmcnt(0) 656; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v4 657; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v5 658; SI-NEXT: v_lshlrev_b32_e32 v3, v5, v3 659; SI-NEXT: v_lshlrev_b32_e32 v2, v4, v2 660; SI-NEXT: v_lshlrev_b32_e32 v4, v9, v7 661; SI-NEXT: v_lshlrev_b32_e32 v5, v8, v6 662; SI-NEXT: v_and_b32_e32 v3, s0, v3 663; SI-NEXT: v_and_b32_e32 v2, s0, v2 664; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 665; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 666; SI-NEXT: v_or_b32_e32 v3, v3, v4 667; SI-NEXT: v_or_b32_e32 v2, v2, v5 668; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 669; SI-NEXT: s_endpgm 670; 671; VI-LABEL: shl_v4i16: 672; VI: ; %bb.0: 673; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 674; VI-NEXT: v_lshlrev_b32_e32 v4, 3, v0 675; VI-NEXT: s_waitcnt lgkmcnt(0) 676; VI-NEXT: v_mov_b32_e32 v1, s3 677; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4 678; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 679; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0 680; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc 681; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] 682; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3] 683; VI-NEXT: v_mov_b32_e32 v5, s1 684; VI-NEXT: v_add_u32_e32 v4, vcc, s0, v4 685; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc 686; VI-NEXT: s_waitcnt vmcnt(0) 687; VI-NEXT: v_lshlrev_b16_e32 v6, v3, v1 688; VI-NEXT: v_lshlrev_b16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 689; VI-NEXT: v_lshlrev_b16_e32 v3, v2, v0 690; VI-NEXT: v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 691; VI-NEXT: v_or_b32_e32 v1, v6, v1 692; VI-NEXT: v_or_b32_e32 v0, v3, v0 693; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1] 694; VI-NEXT: s_endpgm 695; 696; EG-LABEL: shl_v4i16: 697; EG: ; %bb.0: 698; EG-NEXT: ALU 2, @12, KC0[CB0:0-32], KC1[] 699; EG-NEXT: TEX 0 @8 700; EG-NEXT: ALU 3, @15, KC0[], KC1[] 701; EG-NEXT: TEX 0 @10 702; EG-NEXT: ALU 49, @19, KC0[CB0:0-32], KC1[] 703; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T10.XY, T0.X, 1 704; EG-NEXT: CF_END 705; EG-NEXT: PAD 706; EG-NEXT: Fetch clause starting at 8: 707; EG-NEXT: VTX_READ_64 T10.XY, T0.X, 0, #1 708; EG-NEXT: Fetch clause starting at 10: 709; EG-NEXT: VTX_READ_64 T10.XY, T0.X, 8, #1 710; EG-NEXT: ALU clause starting at 12: 711; EG-NEXT: LSHL * T0.W, T0.X, literal.x, 712; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) 713; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, 714; EG-NEXT: ALU clause starting at 15: 715; EG-NEXT: MOV T4.X, T10.X, 716; EG-NEXT: MOV * T5.X, T10.Y, 717; EG-NEXT: MOV T0.Y, PV.X, 718; EG-NEXT: MOV * T0.Z, PS, 719; EG-NEXT: ALU clause starting at 19: 720; EG-NEXT: MOV T2.X, T10.X, 721; EG-NEXT: MOV * T3.X, T10.Y, 722; EG-NEXT: MOV T0.X, T6.X, 723; EG-NEXT: MOV * T1.Y, PV.X, 724; EG-NEXT: AND_INT T1.W, PV.Y, literal.x, 725; EG-NEXT: AND_INT * T2.W, T0.Y, literal.x, 726; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) 727; EG-NEXT: LSHL * T1.W, PS, PV.W, 728; EG-NEXT: AND_INT T1.W, PV.W, literal.x, 729; EG-NEXT: AND_INT * T2.W, T0.X, literal.y, 730; EG-NEXT: 65535(9.183409e-41), -65536(nan) 731; EG-NEXT: OR_INT * T1.W, PS, PV.W, 732; EG-NEXT: MOV T0.X, T3.X, 733; EG-NEXT: MOV * T6.X, PV.W, 734; EG-NEXT: MOV T1.Z, PS, 735; EG-NEXT: LSHR T1.W, T1.Y, literal.x, 736; EG-NEXT: LSHR * T2.W, T0.Y, literal.x, 737; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) 738; EG-NEXT: LSHL T1.W, PS, PV.W, 739; EG-NEXT: AND_INT * T2.W, PV.Z, literal.x, 740; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) 741; EG-NEXT: LSHL * T1.W, PV.W, literal.x, 742; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) 743; EG-NEXT: OR_INT * T1.W, T2.W, PV.W, 744; EG-NEXT: MOV T6.X, PV.W, 745; EG-NEXT: MOV T0.Y, T7.X, 746; EG-NEXT: AND_INT T1.W, T0.X, literal.x, BS:VEC_120/SCL_212 747; EG-NEXT: AND_INT * T2.W, T0.Z, literal.x, 748; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) 749; EG-NEXT: LSHL T1.W, PS, PV.W, 750; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x, 751; EG-NEXT: -65536(nan), 0(0.000000e+00) 752; EG-NEXT: AND_INT * T1.W, PV.W, literal.x, 753; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) 754; EG-NEXT: OR_INT * T1.W, T2.W, PV.W, 755; EG-NEXT: MOV * T7.X, PV.W, 756; EG-NEXT: MOV T0.Y, PV.X, 757; EG-NEXT: LSHR T1.W, T0.X, literal.x, 758; EG-NEXT: LSHR * T2.W, T0.Z, literal.x, 759; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) 760; EG-NEXT: LSHL * T1.W, PS, PV.W, 761; EG-NEXT: AND_INT T0.Z, T0.Y, literal.x, 762; EG-NEXT: LSHL T1.W, PV.W, literal.y, 763; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W, 764; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44) 765; EG-NEXT: LSHR T0.X, PS, literal.x, 766; EG-NEXT: OR_INT * T10.Y, PV.Z, PV.W, 767; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 768; EG-NEXT: MOV T7.X, PV.Y, 769; EG-NEXT: MOV * T10.X, T6.X, 770 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 771 %gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i32 %tid 772 %gep.out = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %out, i32 %tid 773 %b_ptr = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %gep, i16 1 774 %a = load <4 x i16>, <4 x i16> addrspace(1)* %gep 775 %b = load <4 x i16>, <4 x i16> addrspace(1)* %b_ptr 776 %result = shl <4 x i16> %a, %b 777 store <4 x i16> %result, <4 x i16> addrspace(1)* %gep.out 778 ret void 779} 780 781define amdgpu_kernel void @shl_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { 782; SI-LABEL: shl_i64: 783; SI: ; %bb.0: 784; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 785; SI-NEXT: s_mov_b32 s3, 0xf000 786; SI-NEXT: s_mov_b32 s2, -1 787; SI-NEXT: s_mov_b32 s10, s2 788; SI-NEXT: s_mov_b32 s11, s3 789; SI-NEXT: s_waitcnt lgkmcnt(0) 790; SI-NEXT: s_mov_b32 s8, s6 791; SI-NEXT: s_mov_b32 s9, s7 792; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 793; SI-NEXT: s_mov_b32 s0, s4 794; SI-NEXT: s_mov_b32 s1, s5 795; SI-NEXT: s_waitcnt vmcnt(0) 796; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], v2 797; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 798; SI-NEXT: s_endpgm 799; 800; VI-LABEL: shl_i64: 801; VI: ; %bb.0: 802; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 803; VI-NEXT: s_mov_b32 s7, 0xf000 804; VI-NEXT: s_mov_b32 s6, -1 805; VI-NEXT: s_waitcnt lgkmcnt(0) 806; VI-NEXT: s_mov_b32 s4, s0 807; VI-NEXT: s_mov_b32 s5, s1 808; VI-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0 809; VI-NEXT: s_waitcnt lgkmcnt(0) 810; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s2 811; VI-NEXT: v_mov_b32_e32 v0, s0 812; VI-NEXT: v_mov_b32_e32 v1, s1 813; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 814; VI-NEXT: s_endpgm 815; 816; EG-LABEL: shl_i64: 817; EG: ; %bb.0: 818; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] 819; EG-NEXT: TEX 0 @6 820; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[] 821; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 822; EG-NEXT: CF_END 823; EG-NEXT: PAD 824; EG-NEXT: Fetch clause starting at 6: 825; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1 826; EG-NEXT: ALU clause starting at 8: 827; EG-NEXT: MOV * T0.X, KC0[2].Z, 828; EG-NEXT: ALU clause starting at 9: 829; EG-NEXT: AND_INT T1.Y, T0.Z, literal.x, 830; EG-NEXT: LSHR T1.Z, T0.Y, 1, 831; EG-NEXT: BIT_ALIGN_INT T0.W, T0.Y, T0.X, 1, 832; EG-NEXT: NOT_INT * T1.W, T0.Z, 833; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 834; EG-NEXT: BIT_ALIGN_INT T1.Z, PV.Z, PV.W, PS, 835; EG-NEXT: LSHL T0.W, T0.X, PV.Y, 836; EG-NEXT: AND_INT * T1.W, T0.Z, literal.x, 837; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 838; EG-NEXT: CNDE_INT * T0.Y, PS, PV.Z, PV.W, 839; EG-NEXT: CNDE_INT T0.X, T1.W, T0.W, 0.0, 840; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 841; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 842 %b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1 843 %a = load i64, i64 addrspace(1)* %in 844 %b = load i64, i64 addrspace(1)* %b_ptr 845 %result = shl i64 %a, %b 846 store i64 %result, i64 addrspace(1)* %out 847 ret void 848} 849 850define amdgpu_kernel void @shl_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) { 851; SI-LABEL: shl_v2i64: 852; SI: ; %bb.0: 853; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 854; SI-NEXT: s_mov_b32 s3, 0xf000 855; SI-NEXT: s_mov_b32 s2, -1 856; SI-NEXT: s_mov_b32 s10, s2 857; SI-NEXT: s_mov_b32 s11, s3 858; SI-NEXT: s_waitcnt lgkmcnt(0) 859; SI-NEXT: s_mov_b32 s8, s6 860; SI-NEXT: s_mov_b32 s9, s7 861; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 862; SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16 863; SI-NEXT: s_mov_b32 s0, s4 864; SI-NEXT: s_mov_b32 s1, s5 865; SI-NEXT: s_waitcnt vmcnt(0) 866; SI-NEXT: v_lshl_b64 v[2:3], v[2:3], v6 867; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], v4 868; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 869; SI-NEXT: s_endpgm 870; 871; VI-LABEL: shl_v2i64: 872; VI: ; %bb.0: 873; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 874; VI-NEXT: s_mov_b32 s3, 0xf000 875; VI-NEXT: s_mov_b32 s2, -1 876; VI-NEXT: s_waitcnt lgkmcnt(0) 877; VI-NEXT: s_mov_b32 s0, s4 878; VI-NEXT: s_mov_b32 s1, s5 879; VI-NEXT: s_load_dwordx4 s[8:11], s[6:7], 0x0 880; VI-NEXT: s_load_dwordx4 s[4:7], s[6:7], 0x10 881; VI-NEXT: s_waitcnt lgkmcnt(0) 882; VI-NEXT: s_lshl_b64 s[6:7], s[10:11], s6 883; VI-NEXT: s_lshl_b64 s[4:5], s[8:9], s4 884; VI-NEXT: v_mov_b32_e32 v0, s4 885; VI-NEXT: v_mov_b32_e32 v1, s5 886; VI-NEXT: v_mov_b32_e32 v2, s6 887; VI-NEXT: v_mov_b32_e32 v3, s7 888; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 889; VI-NEXT: s_endpgm 890; 891; EG-LABEL: shl_v2i64: 892; EG: ; %bb.0: 893; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[] 894; EG-NEXT: TEX 1 @6 895; EG-NEXT: ALU 22, @11, KC0[CB0:0-32], KC1[] 896; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T0.X, 1 897; EG-NEXT: CF_END 898; EG-NEXT: PAD 899; EG-NEXT: Fetch clause starting at 6: 900; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1 901; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1 902; EG-NEXT: ALU clause starting at 10: 903; EG-NEXT: MOV * T0.X, KC0[2].Z, 904; EG-NEXT: ALU clause starting at 11: 905; EG-NEXT: AND_INT T1.Y, T1.Z, literal.x, 906; EG-NEXT: LSHR T2.Z, T0.W, 1, 907; EG-NEXT: BIT_ALIGN_INT T0.W, T0.W, T0.Z, 1, 908; EG-NEXT: NOT_INT * T1.W, T1.Z, 909; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 910; EG-NEXT: BIT_ALIGN_INT T0.W, PV.Z, PV.W, PS, 911; EG-NEXT: LSHL * T1.W, T0.Z, PV.Y, 912; EG-NEXT: AND_INT T2.X, T1.Z, literal.x, 913; EG-NEXT: AND_INT T1.Y, T1.X, literal.y, 914; EG-NEXT: LSHR T0.Z, T0.Y, 1, 915; EG-NEXT: BIT_ALIGN_INT T2.W, T0.Y, T0.X, 1, 916; EG-NEXT: NOT_INT * T3.W, T1.X, 917; EG-NEXT: 32(4.484155e-44), 31(4.344025e-44) 918; EG-NEXT: BIT_ALIGN_INT T0.Y, PV.Z, PV.W, PS, 919; EG-NEXT: LSHL T0.Z, T0.X, PV.Y, 920; EG-NEXT: AND_INT T2.W, T1.X, literal.x, BS:VEC_120/SCL_212 921; EG-NEXT: CNDE_INT * T3.W, PV.X, T0.W, T1.W, 922; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 923; EG-NEXT: CNDE_INT T3.Y, PV.W, PV.Y, PV.Z, 924; EG-NEXT: CNDE_INT * T3.Z, T2.X, T1.W, 0.0, 925; EG-NEXT: CNDE_INT T3.X, T2.W, T0.Z, 0.0, 926; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x, 927; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 928 %b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %in, i64 1 929 %a = load <2 x i64>, <2 x i64> addrspace(1)* %in 930 %b = load <2 x i64>, <2 x i64> addrspace(1)* %b_ptr 931 %result = shl <2 x i64> %a, %b 932 store <2 x i64> %result, <2 x i64> addrspace(1)* %out 933 ret void 934} 935 936define amdgpu_kernel void @shl_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) { 937; SI-LABEL: shl_v4i64: 938; SI: ; %bb.0: 939; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 940; SI-NEXT: s_mov_b32 s3, 0xf000 941; SI-NEXT: s_mov_b32 s2, -1 942; SI-NEXT: s_mov_b32 s10, s2 943; SI-NEXT: s_mov_b32 s11, s3 944; SI-NEXT: s_waitcnt lgkmcnt(0) 945; SI-NEXT: s_mov_b32 s8, s6 946; SI-NEXT: s_mov_b32 s9, s7 947; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 948; SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16 949; SI-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:32 950; SI-NEXT: buffer_load_dwordx4 v[11:14], off, s[8:11], 0 offset:48 951; SI-NEXT: s_mov_b32 s0, s4 952; SI-NEXT: s_mov_b32 s1, s5 953; SI-NEXT: s_waitcnt vmcnt(1) 954; SI-NEXT: v_lshl_b64 v[2:3], v[2:3], v10 955; SI-NEXT: s_waitcnt vmcnt(0) 956; SI-NEXT: v_lshl_b64 v[6:7], v[6:7], v13 957; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], v11 958; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], v8 959; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16 960; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 961; SI-NEXT: s_endpgm 962; 963; VI-LABEL: shl_v4i64: 964; VI: ; %bb.0: 965; VI-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x24 966; VI-NEXT: s_mov_b32 s3, 0xf000 967; VI-NEXT: s_mov_b32 s2, -1 968; VI-NEXT: s_waitcnt lgkmcnt(0) 969; VI-NEXT: s_mov_b32 s0, s12 970; VI-NEXT: s_mov_b32 s1, s13 971; VI-NEXT: s_load_dwordx8 s[4:11], s[14:15], 0x0 972; VI-NEXT: s_load_dwordx8 s[12:19], s[14:15], 0x20 973; VI-NEXT: s_waitcnt lgkmcnt(0) 974; VI-NEXT: s_lshl_b64 s[10:11], s[10:11], s18 975; VI-NEXT: s_lshl_b64 s[8:9], s[8:9], s16 976; VI-NEXT: s_lshl_b64 s[6:7], s[6:7], s14 977; VI-NEXT: s_lshl_b64 s[4:5], s[4:5], s12 978; VI-NEXT: v_mov_b32_e32 v0, s8 979; VI-NEXT: v_mov_b32_e32 v1, s9 980; VI-NEXT: v_mov_b32_e32 v2, s10 981; VI-NEXT: v_mov_b32_e32 v3, s11 982; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16 983; VI-NEXT: s_nop 0 984; VI-NEXT: v_mov_b32_e32 v0, s4 985; VI-NEXT: v_mov_b32_e32 v1, s5 986; VI-NEXT: v_mov_b32_e32 v2, s6 987; VI-NEXT: v_mov_b32_e32 v3, s7 988; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 989; VI-NEXT: s_endpgm 990; 991; EG-LABEL: shl_v4i64: 992; EG: ; %bb.0: 993; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[] 994; EG-NEXT: TEX 3 @6 995; EG-NEXT: ALU 47, @15, KC0[CB0:0-32], KC1[] 996; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 0 997; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 1 998; EG-NEXT: CF_END 999; EG-NEXT: Fetch clause starting at 6: 1000; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 48, #1 1001; EG-NEXT: VTX_READ_128 T2.XYZW, T0.X, 0, #1 1002; EG-NEXT: VTX_READ_128 T3.XYZW, T0.X, 32, #1 1003; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 16, #1 1004; EG-NEXT: ALU clause starting at 14: 1005; EG-NEXT: MOV * T0.X, KC0[2].Z, 1006; EG-NEXT: ALU clause starting at 15: 1007; EG-NEXT: AND_INT T4.Z, T1.Z, literal.x, 1008; EG-NEXT: LSHR T1.W, T0.W, 1, 1009; EG-NEXT: NOT_INT * T3.W, T1.Z, 1010; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 1011; EG-NEXT: BIT_ALIGN_INT T4.X, T0.W, T0.Z, 1, 1012; EG-NEXT: AND_INT T1.Y, T3.Z, literal.x, BS:VEC_201 1013; EG-NEXT: LSHR T5.Z, T2.W, 1, BS:VEC_120/SCL_212 1014; EG-NEXT: BIT_ALIGN_INT T0.W, T2.W, T2.Z, 1, BS:VEC_102/SCL_221 1015; EG-NEXT: NOT_INT * T2.W, T3.Z, 1016; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 1017; EG-NEXT: BIT_ALIGN_INT T3.Y, PV.Z, PV.W, PS, 1018; EG-NEXT: LSHL T2.Z, T2.Z, PV.Y, 1019; EG-NEXT: BIT_ALIGN_INT T0.W, T1.W, PV.X, T3.W, 1020; EG-NEXT: LSHL * T1.W, T0.Z, T4.Z, 1021; EG-NEXT: AND_INT T4.X, T1.Z, literal.x, 1022; EG-NEXT: AND_INT T1.Y, T1.X, literal.y, 1023; EG-NEXT: LSHR T0.Z, T0.Y, 1, 1024; EG-NEXT: BIT_ALIGN_INT T2.W, T0.Y, T0.X, 1, 1025; EG-NEXT: NOT_INT * T3.W, T1.X, 1026; EG-NEXT: 32(4.484155e-44), 31(4.344025e-44) 1027; EG-NEXT: AND_INT T5.X, T3.Z, literal.x, 1028; EG-NEXT: BIT_ALIGN_INT T0.Y, PV.Z, PV.W, PS, 1029; EG-NEXT: LSHL T0.Z, T0.X, PV.Y, 1030; EG-NEXT: AND_INT T2.W, T1.X, literal.x, BS:VEC_120/SCL_212 1031; EG-NEXT: CNDE_INT * T4.W, PV.X, T0.W, T1.W, 1032; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 1033; EG-NEXT: AND_INT T0.X, T3.X, literal.x, 1034; EG-NEXT: CNDE_INT T4.Y, PV.W, PV.Y, PV.Z, 1035; EG-NEXT: LSHR T1.Z, T2.Y, 1, 1036; EG-NEXT: BIT_ALIGN_INT T0.W, T2.Y, T2.X, 1, 1037; EG-NEXT: NOT_INT * T3.W, T3.X, 1038; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 1039; EG-NEXT: BIT_ALIGN_INT T1.X, PV.Z, PV.W, PS, 1040; EG-NEXT: LSHL T0.Y, T2.X, PV.X, 1041; EG-NEXT: CNDE_INT T4.Z, T4.X, T1.W, 0.0, BS:VEC_120/SCL_212 1042; EG-NEXT: AND_INT * T0.W, T3.X, literal.x, BS:VEC_201 1043; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 1044; EG-NEXT: CNDE_INT * T1.W, T5.X, T3.Y, T2.Z, 1045; EG-NEXT: CNDE_INT T4.X, T2.W, T0.Z, 0.0, 1046; EG-NEXT: CNDE_INT T1.Y, T0.W, T1.X, T0.Y, BS:VEC_120/SCL_212 1047; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x, 1048; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) 1049; EG-NEXT: LSHR T0.X, PV.W, literal.x, 1050; EG-NEXT: CNDE_INT T1.Z, T5.X, T2.Z, 0.0, 1051; EG-NEXT: CNDE_INT * T1.X, T0.W, T0.Y, 0.0, 1052; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1053; EG-NEXT: LSHR * T2.X, KC0[2].Y, literal.x, 1054; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1055 %b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i64 1 1056 %a = load <4 x i64>, <4 x i64> addrspace(1)* %in 1057 %b = load <4 x i64>, <4 x i64> addrspace(1)* %b_ptr 1058 %result = shl <4 x i64> %a, %b 1059 store <4 x i64> %result, <4 x i64> addrspace(1)* %out 1060 ret void 1061} 1062 1063; Make sure load width gets reduced to i32 load. 1064define amdgpu_kernel void @s_shl_32_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) { 1065; SI-LABEL: s_shl_32_i64: 1066; SI: ; %bb.0: 1067; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1068; SI-NEXT: s_load_dword s0, s[0:1], 0x13 1069; SI-NEXT: s_mov_b32 s7, 0xf000 1070; SI-NEXT: s_mov_b32 s6, -1 1071; SI-NEXT: v_mov_b32_e32 v0, 0 1072; SI-NEXT: s_waitcnt lgkmcnt(0) 1073; SI-NEXT: v_mov_b32_e32 v1, s0 1074; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1075; SI-NEXT: s_endpgm 1076; 1077; VI-LABEL: s_shl_32_i64: 1078; VI: ; %bb.0: 1079; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 1080; VI-NEXT: s_load_dword s0, s[0:1], 0x4c 1081; VI-NEXT: s_mov_b32 s7, 0xf000 1082; VI-NEXT: s_mov_b32 s6, -1 1083; VI-NEXT: v_mov_b32_e32 v0, 0 1084; VI-NEXT: s_waitcnt lgkmcnt(0) 1085; VI-NEXT: v_mov_b32_e32 v1, s0 1086; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1087; VI-NEXT: s_endpgm 1088; 1089; EG-LABEL: s_shl_32_i64: 1090; EG: ; %bb.0: 1091; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[] 1092; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1093; EG-NEXT: CF_END 1094; EG-NEXT: PAD 1095; EG-NEXT: ALU clause starting at 4: 1096; EG-NEXT: MOV * T0.Y, KC0[4].W, 1097; EG-NEXT: MOV T0.X, 0.0, 1098; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1099; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1100 %result = shl i64 %a, 32 1101 store i64 %result, i64 addrspace(1)* %out 1102 ret void 1103} 1104 1105define amdgpu_kernel void @v_shl_32_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { 1106; SI-LABEL: v_shl_32_i64: 1107; SI: ; %bb.0: 1108; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 1109; SI-NEXT: s_ashr_i32 s3, s2, 31 1110; SI-NEXT: s_lshl_b64 s[0:1], s[2:3], 3 1111; SI-NEXT: v_mov_b32_e32 v0, s0 1112; SI-NEXT: s_mov_b32 s7, 0xf000 1113; SI-NEXT: s_mov_b32 s6, 0 1114; SI-NEXT: s_waitcnt lgkmcnt(0) 1115; SI-NEXT: s_mov_b64 s[4:5], s[10:11] 1116; SI-NEXT: v_mov_b32_e32 v1, s1 1117; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 1118; SI-NEXT: s_mov_b64 s[10:11], s[6:7] 1119; SI-NEXT: v_mov_b32_e32 v2, 0 1120; SI-NEXT: s_waitcnt vmcnt(0) 1121; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[8:11], 0 addr64 1122; SI-NEXT: s_endpgm 1123; 1124; VI-LABEL: v_shl_32_i64: 1125; VI: ; %bb.0: 1126; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 1127; VI-NEXT: s_ashr_i32 s3, s2, 31 1128; VI-NEXT: s_lshl_b64 s[0:1], s[2:3], 3 1129; VI-NEXT: v_mov_b32_e32 v0, 0 1130; VI-NEXT: s_waitcnt lgkmcnt(0) 1131; VI-NEXT: s_add_u32 s2, s6, s0 1132; VI-NEXT: s_addc_u32 s3, s7, s1 1133; VI-NEXT: s_load_dword s2, s[2:3], 0x0 1134; VI-NEXT: s_add_u32 s0, s4, s0 1135; VI-NEXT: s_addc_u32 s1, s5, s1 1136; VI-NEXT: v_mov_b32_e32 v3, s1 1137; VI-NEXT: v_mov_b32_e32 v2, s0 1138; VI-NEXT: s_waitcnt lgkmcnt(0) 1139; VI-NEXT: v_mov_b32_e32 v1, s2 1140; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] 1141; VI-NEXT: s_endpgm 1142; 1143; EG-LABEL: v_shl_32_i64: 1144; EG: ; %bb.0: 1145; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] 1146; EG-NEXT: TEX 0 @6 1147; EG-NEXT: ALU 4, @11, KC0[CB0:0-32], KC1[] 1148; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XY, T2.X, 1 1149; EG-NEXT: CF_END 1150; EG-NEXT: PAD 1151; EG-NEXT: Fetch clause starting at 6: 1152; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 1153; EG-NEXT: ALU clause starting at 8: 1154; EG-NEXT: LSHL * T0.W, T1.X, literal.x, 1155; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) 1156; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, 1157; EG-NEXT: ALU clause starting at 11: 1158; EG-NEXT: MOV T1.X, 0.0, 1159; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W, 1160; EG-NEXT: LSHR T2.X, PV.W, literal.x, 1161; EG-NEXT: MOV * T1.Y, T0.X, 1162; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1163 %tid = call i32 @llvm.amdgcn.workgroup.id.x() #0 1164 %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid 1165 %gep.out = getelementptr i64, i64 addrspace(1)* %out, i32 %tid 1166 %a = load i64, i64 addrspace(1)* %gep.in 1167 %result = shl i64 %a, 32 1168 store i64 %result, i64 addrspace(1)* %gep.out 1169 ret void 1170} 1171 1172define amdgpu_kernel void @s_shl_constant_i64(i64 addrspace(1)* %out, i64 %a) { 1173; SI-LABEL: s_shl_constant_i64: 1174; SI: ; %bb.0: 1175; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 1176; SI-NEXT: s_mov_b32 s2, -1 1177; SI-NEXT: s_mov_b32 s9, 0xffff 1178; SI-NEXT: s_mov_b32 s8, s2 1179; SI-NEXT: s_mov_b32 s3, 0xf000 1180; SI-NEXT: s_waitcnt lgkmcnt(0) 1181; SI-NEXT: s_mov_b32 s0, s4 1182; SI-NEXT: s_mov_b32 s1, s5 1183; SI-NEXT: s_lshl_b64 s[4:5], s[8:9], s6 1184; SI-NEXT: v_mov_b32_e32 v0, s4 1185; SI-NEXT: v_mov_b32_e32 v1, s5 1186; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 1187; SI-NEXT: s_endpgm 1188; 1189; VI-LABEL: s_shl_constant_i64: 1190; VI: ; %bb.0: 1191; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 1192; VI-NEXT: s_mov_b32 s2, -1 1193; VI-NEXT: s_mov_b32 s9, 0xffff 1194; VI-NEXT: s_mov_b32 s8, s2 1195; VI-NEXT: s_mov_b32 s3, 0xf000 1196; VI-NEXT: s_waitcnt lgkmcnt(0) 1197; VI-NEXT: s_mov_b32 s0, s4 1198; VI-NEXT: s_mov_b32 s1, s5 1199; VI-NEXT: s_lshl_b64 s[4:5], s[8:9], s6 1200; VI-NEXT: v_mov_b32_e32 v0, s4 1201; VI-NEXT: v_mov_b32_e32 v1, s5 1202; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 1203; VI-NEXT: s_endpgm 1204; 1205; EG-LABEL: s_shl_constant_i64: 1206; EG: ; %bb.0: 1207; EG-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[] 1208; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1209; EG-NEXT: CF_END 1210; EG-NEXT: PAD 1211; EG-NEXT: ALU clause starting at 4: 1212; EG-NEXT: AND_INT T0.Z, KC0[2].W, literal.x, 1213; EG-NEXT: MOV T0.W, literal.y, 1214; EG-NEXT: NOT_INT * T1.W, KC0[2].W, 1215; EG-NEXT: 31(4.344025e-44), -1(nan) 1216; EG-NEXT: BIT_ALIGN_INT T1.Z, literal.x, PV.W, PS, 1217; EG-NEXT: LSHL T0.W, literal.y, PV.Z, 1218; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.z, 1219; EG-NEXT: 32767(4.591635e-41), -1(nan) 1220; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 1221; EG-NEXT: CNDE_INT * T0.Y, PS, PV.Z, PV.W, 1222; EG-NEXT: CNDE_INT T0.X, T1.W, T0.W, 0.0, 1223; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1224; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1225 %shl = shl i64 281474976710655, %a 1226 store i64 %shl, i64 addrspace(1)* %out, align 8 1227 ret void 1228} 1229 1230define amdgpu_kernel void @v_shl_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 1231; SI-LABEL: v_shl_constant_i64: 1232; SI: ; %bb.0: 1233; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 1234; SI-NEXT: s_mov_b32 s3, 0xf000 1235; SI-NEXT: s_mov_b32 s2, -1 1236; SI-NEXT: s_mov_b32 s10, s2 1237; SI-NEXT: s_mov_b32 s11, s3 1238; SI-NEXT: s_waitcnt lgkmcnt(0) 1239; SI-NEXT: s_mov_b32 s8, s6 1240; SI-NEXT: s_mov_b32 s9, s7 1241; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0 1242; SI-NEXT: s_mov_b32 s6, 0xab19b207 1243; SI-NEXT: s_movk_i32 s7, 0x11e 1244; SI-NEXT: s_mov_b32 s0, s4 1245; SI-NEXT: s_mov_b32 s1, s5 1246; SI-NEXT: s_waitcnt vmcnt(0) 1247; SI-NEXT: v_lshl_b64 v[0:1], s[6:7], v0 1248; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 1249; SI-NEXT: s_endpgm 1250; 1251; VI-LABEL: v_shl_constant_i64: 1252; VI: ; %bb.0: 1253; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1254; VI-NEXT: s_mov_b32 s7, 0xf000 1255; VI-NEXT: s_mov_b32 s6, -1 1256; VI-NEXT: s_waitcnt lgkmcnt(0) 1257; VI-NEXT: s_load_dword s2, s[2:3], 0x0 1258; VI-NEXT: s_mov_b32 s4, s0 1259; VI-NEXT: s_mov_b32 s5, s1 1260; VI-NEXT: s_mov_b32 s0, 0xab19b207 1261; VI-NEXT: s_movk_i32 s1, 0x11e 1262; VI-NEXT: s_waitcnt lgkmcnt(0) 1263; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s2 1264; VI-NEXT: v_mov_b32_e32 v0, s0 1265; VI-NEXT: v_mov_b32_e32 v1, s1 1266; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1267; VI-NEXT: s_endpgm 1268; 1269; EG-LABEL: v_shl_constant_i64: 1270; EG: ; %bb.0: 1271; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] 1272; EG-NEXT: TEX 0 @6 1273; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[] 1274; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1275; EG-NEXT: CF_END 1276; EG-NEXT: PAD 1277; EG-NEXT: Fetch clause starting at 6: 1278; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 1279; EG-NEXT: ALU clause starting at 8: 1280; EG-NEXT: MOV * T0.X, KC0[2].Z, 1281; EG-NEXT: ALU clause starting at 9: 1282; EG-NEXT: NOT_INT T0.Z, T0.X, 1283; EG-NEXT: MOV T0.W, literal.x, 1284; EG-NEXT: AND_INT * T1.W, T0.X, literal.y, 1285; EG-NEXT: 1435293955(1.935796e+13), 31(4.344025e-44) 1286; EG-NEXT: LSHL T1.Z, literal.x, PS, 1287; EG-NEXT: BIT_ALIGN_INT T0.W, literal.y, PV.W, PV.Z, 1288; EG-NEXT: AND_INT * T1.W, T0.X, literal.z, 1289; EG-NEXT: -1424379385(-5.460358e-13), 143(2.003857e-43) 1290; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 1291; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, PV.Z, 1292; EG-NEXT: CNDE_INT T0.X, T1.W, T1.Z, 0.0, 1293; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1294; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1295 %a = load i64, i64 addrspace(1)* %aptr, align 8 1296 %shl = shl i64 1231231234567, %a 1297 store i64 %shl, i64 addrspace(1)* %out, align 8 1298 ret void 1299} 1300 1301define amdgpu_kernel void @v_shl_i64_32_bit_constant(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 1302; SI-LABEL: v_shl_i64_32_bit_constant: 1303; SI: ; %bb.0: 1304; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 1305; SI-NEXT: s_mov_b32 s3, 0xf000 1306; SI-NEXT: s_mov_b32 s2, -1 1307; SI-NEXT: s_mov_b32 s10, s2 1308; SI-NEXT: s_mov_b32 s11, s3 1309; SI-NEXT: s_waitcnt lgkmcnt(0) 1310; SI-NEXT: s_mov_b32 s8, s6 1311; SI-NEXT: s_mov_b32 s9, s7 1312; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0 1313; SI-NEXT: s_mov_b64 s[6:7], 0x12d687 1314; SI-NEXT: s_mov_b32 s0, s4 1315; SI-NEXT: s_mov_b32 s1, s5 1316; SI-NEXT: s_waitcnt vmcnt(0) 1317; SI-NEXT: v_lshl_b64 v[0:1], s[6:7], v0 1318; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 1319; SI-NEXT: s_endpgm 1320; 1321; VI-LABEL: v_shl_i64_32_bit_constant: 1322; VI: ; %bb.0: 1323; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1324; VI-NEXT: s_mov_b32 s7, 0xf000 1325; VI-NEXT: s_mov_b32 s6, -1 1326; VI-NEXT: s_waitcnt lgkmcnt(0) 1327; VI-NEXT: s_load_dword s2, s[2:3], 0x0 1328; VI-NEXT: s_mov_b32 s4, s0 1329; VI-NEXT: s_mov_b32 s5, s1 1330; VI-NEXT: s_mov_b64 s[0:1], 0x12d687 1331; VI-NEXT: s_waitcnt lgkmcnt(0) 1332; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s2 1333; VI-NEXT: v_mov_b32_e32 v0, s0 1334; VI-NEXT: v_mov_b32_e32 v1, s1 1335; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1336; VI-NEXT: s_endpgm 1337; 1338; EG-LABEL: v_shl_i64_32_bit_constant: 1339; EG: ; %bb.0: 1340; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] 1341; EG-NEXT: TEX 0 @6 1342; EG-NEXT: ALU 11, @9, KC0[CB0:0-32], KC1[] 1343; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1344; EG-NEXT: CF_END 1345; EG-NEXT: PAD 1346; EG-NEXT: Fetch clause starting at 6: 1347; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 1348; EG-NEXT: ALU clause starting at 8: 1349; EG-NEXT: MOV * T0.X, KC0[2].Z, 1350; EG-NEXT: ALU clause starting at 9: 1351; EG-NEXT: AND_INT T0.W, T0.X, literal.x, 1352; EG-NEXT: NOT_INT * T1.W, T0.X, 1353; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 1354; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, literal.x, PS, 1355; EG-NEXT: LSHL T0.W, literal.y, PV.W, 1356; EG-NEXT: AND_INT * T1.W, T0.X, literal.z, 1357; EG-NEXT: 617283(8.649977e-40), 1234567(1.729997e-39) 1358; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 1359; EG-NEXT: CNDE_INT * T0.Y, PS, PV.Z, PV.W, 1360; EG-NEXT: CNDE_INT T0.X, T1.W, T0.W, 0.0, 1361; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1362; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1363 %a = load i64, i64 addrspace(1)* %aptr, align 8 1364 %shl = shl i64 1234567, %a 1365 store i64 %shl, i64 addrspace(1)* %out, align 8 1366 ret void 1367} 1368 1369define amdgpu_kernel void @v_shl_inline_imm_64_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 1370; SI-LABEL: v_shl_inline_imm_64_i64: 1371; SI: ; %bb.0: 1372; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 1373; SI-NEXT: s_mov_b32 s3, 0xf000 1374; SI-NEXT: s_mov_b32 s2, -1 1375; SI-NEXT: s_mov_b32 s10, s2 1376; SI-NEXT: s_mov_b32 s11, s3 1377; SI-NEXT: s_waitcnt lgkmcnt(0) 1378; SI-NEXT: s_mov_b32 s8, s6 1379; SI-NEXT: s_mov_b32 s9, s7 1380; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0 1381; SI-NEXT: s_mov_b32 s0, s4 1382; SI-NEXT: s_mov_b32 s1, s5 1383; SI-NEXT: s_waitcnt vmcnt(0) 1384; SI-NEXT: v_lshl_b64 v[0:1], 64, v0 1385; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 1386; SI-NEXT: s_endpgm 1387; 1388; VI-LABEL: v_shl_inline_imm_64_i64: 1389; VI: ; %bb.0: 1390; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 1391; VI-NEXT: s_mov_b32 s7, 0xf000 1392; VI-NEXT: s_mov_b32 s6, -1 1393; VI-NEXT: s_waitcnt lgkmcnt(0) 1394; VI-NEXT: s_mov_b32 s4, s0 1395; VI-NEXT: s_load_dword s0, s[2:3], 0x0 1396; VI-NEXT: s_mov_b32 s5, s1 1397; VI-NEXT: s_waitcnt lgkmcnt(0) 1398; VI-NEXT: s_lshl_b64 s[0:1], 64, s0 1399; VI-NEXT: v_mov_b32_e32 v0, s0 1400; VI-NEXT: v_mov_b32_e32 v1, s1 1401; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1402; VI-NEXT: s_endpgm 1403; 1404; EG-LABEL: v_shl_inline_imm_64_i64: 1405; EG: ; %bb.0: 1406; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] 1407; EG-NEXT: TEX 0 @6 1408; EG-NEXT: ALU 10, @9, KC0[CB0:0-32], KC1[] 1409; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1410; EG-NEXT: CF_END 1411; EG-NEXT: PAD 1412; EG-NEXT: Fetch clause starting at 6: 1413; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 1414; EG-NEXT: ALU clause starting at 8: 1415; EG-NEXT: MOV * T0.X, KC0[2].Z, 1416; EG-NEXT: ALU clause starting at 9: 1417; EG-NEXT: AND_INT T0.W, T0.X, literal.x, 1418; EG-NEXT: NOT_INT * T1.W, T0.X, 1419; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 1420; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, literal.x, PS, 1421; EG-NEXT: LSHL T0.W, literal.y, PV.W, 1422; EG-NEXT: AND_INT * T1.W, T0.X, literal.x, 1423; EG-NEXT: 32(4.484155e-44), 64(8.968310e-44) 1424; EG-NEXT: CNDE_INT * T0.Y, PS, PV.Z, PV.W, 1425; EG-NEXT: CNDE_INT T0.X, T1.W, T0.W, 0.0, 1426; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1427; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1428 %a = load i64, i64 addrspace(1)* %aptr, align 8 1429 %shl = shl i64 64, %a 1430 store i64 %shl, i64 addrspace(1)* %out, align 8 1431 ret void 1432} 1433 1434define amdgpu_kernel void @s_shl_inline_imm_64_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1435; SI-LABEL: s_shl_inline_imm_64_i64: 1436; SI: ; %bb.0: 1437; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1438; SI-NEXT: s_load_dword s0, s[0:1], 0xd 1439; SI-NEXT: s_mov_b32 s7, 0xf000 1440; SI-NEXT: s_mov_b32 s6, -1 1441; SI-NEXT: s_waitcnt lgkmcnt(0) 1442; SI-NEXT: s_lshl_b64 s[0:1], 64, s0 1443; SI-NEXT: v_mov_b32_e32 v0, s0 1444; SI-NEXT: v_mov_b32_e32 v1, s1 1445; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1446; SI-NEXT: s_endpgm 1447; 1448; VI-LABEL: s_shl_inline_imm_64_i64: 1449; VI: ; %bb.0: 1450; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 1451; VI-NEXT: s_load_dword s0, s[0:1], 0x34 1452; VI-NEXT: s_mov_b32 s7, 0xf000 1453; VI-NEXT: s_mov_b32 s6, -1 1454; VI-NEXT: s_waitcnt lgkmcnt(0) 1455; VI-NEXT: s_lshl_b64 s[0:1], 64, s0 1456; VI-NEXT: v_mov_b32_e32 v0, s0 1457; VI-NEXT: v_mov_b32_e32 v1, s1 1458; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1459; VI-NEXT: s_endpgm 1460; 1461; EG-LABEL: s_shl_inline_imm_64_i64: 1462; EG: ; %bb.0: 1463; EG-NEXT: ALU 10, @4, KC0[CB0:0-32], KC1[] 1464; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1465; EG-NEXT: CF_END 1466; EG-NEXT: PAD 1467; EG-NEXT: ALU clause starting at 4: 1468; EG-NEXT: NOT_INT T0.W, KC0[2].W, 1469; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.x, 1470; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 1471; EG-NEXT: LSHL T0.Z, literal.x, PS, 1472; EG-NEXT: BIT_ALIGN_INT T0.W, 0.0, literal.y, PV.W, 1473; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y, 1474; EG-NEXT: 64(8.968310e-44), 32(4.484155e-44) 1475; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, PV.Z, 1476; EG-NEXT: CNDE_INT T0.X, T1.W, T0.Z, 0.0, 1477; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1478; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1479 %shl = shl i64 64, %a 1480 store i64 %shl, i64 addrspace(1)* %out, align 8 1481 ret void 1482} 1483 1484define amdgpu_kernel void @s_shl_inline_imm_1_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1485; SI-LABEL: s_shl_inline_imm_1_i64: 1486; SI: ; %bb.0: 1487; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1488; SI-NEXT: s_load_dword s0, s[0:1], 0xd 1489; SI-NEXT: s_mov_b32 s7, 0xf000 1490; SI-NEXT: s_mov_b32 s6, -1 1491; SI-NEXT: s_waitcnt lgkmcnt(0) 1492; SI-NEXT: s_lshl_b64 s[0:1], 1, s0 1493; SI-NEXT: v_mov_b32_e32 v0, s0 1494; SI-NEXT: v_mov_b32_e32 v1, s1 1495; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1496; SI-NEXT: s_endpgm 1497; 1498; VI-LABEL: s_shl_inline_imm_1_i64: 1499; VI: ; %bb.0: 1500; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 1501; VI-NEXT: s_load_dword s0, s[0:1], 0x34 1502; VI-NEXT: s_mov_b32 s7, 0xf000 1503; VI-NEXT: s_mov_b32 s6, -1 1504; VI-NEXT: s_waitcnt lgkmcnt(0) 1505; VI-NEXT: s_lshl_b64 s[0:1], 1, s0 1506; VI-NEXT: v_mov_b32_e32 v0, s0 1507; VI-NEXT: v_mov_b32_e32 v1, s1 1508; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1509; VI-NEXT: s_endpgm 1510; 1511; EG-LABEL: s_shl_inline_imm_1_i64: 1512; EG: ; %bb.0: 1513; EG-NEXT: ALU 11, @4, KC0[CB0:0-32], KC1[] 1514; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1515; EG-NEXT: CF_END 1516; EG-NEXT: PAD 1517; EG-NEXT: ALU clause starting at 4: 1518; EG-NEXT: AND_INT T0.W, KC0[2].W, literal.x, 1519; EG-NEXT: LSHL * T1.W, KC0[2].W, literal.y, 1520; EG-NEXT: 31(4.344025e-44), 26(3.643376e-44) 1521; EG-NEXT: ASHR T1.W, PS, literal.x, 1522; EG-NEXT: LSHL * T0.W, 1, PV.W, 1523; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 1524; EG-NEXT: AND_INT T0.Y, PV.W, PS, 1525; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.x, 1526; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 1527; EG-NEXT: CNDE_INT T0.X, PV.W, T0.W, 0.0, 1528; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1529; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1530 %shl = shl i64 1, %a 1531 store i64 %shl, i64 addrspace(1)* %out, align 8 1532 ret void 1533} 1534 1535define amdgpu_kernel void @s_shl_inline_imm_1_0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1536; SI-LABEL: s_shl_inline_imm_1_0_i64: 1537; SI: ; %bb.0: 1538; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1539; SI-NEXT: s_load_dword s0, s[0:1], 0xd 1540; SI-NEXT: s_mov_b32 s7, 0xf000 1541; SI-NEXT: s_mov_b32 s6, -1 1542; SI-NEXT: s_waitcnt lgkmcnt(0) 1543; SI-NEXT: s_lshl_b64 s[0:1], 1.0, s0 1544; SI-NEXT: v_mov_b32_e32 v0, s0 1545; SI-NEXT: v_mov_b32_e32 v1, s1 1546; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1547; SI-NEXT: s_endpgm 1548; 1549; VI-LABEL: s_shl_inline_imm_1_0_i64: 1550; VI: ; %bb.0: 1551; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 1552; VI-NEXT: s_load_dword s0, s[0:1], 0x34 1553; VI-NEXT: s_mov_b32 s7, 0xf000 1554; VI-NEXT: s_mov_b32 s6, -1 1555; VI-NEXT: s_waitcnt lgkmcnt(0) 1556; VI-NEXT: s_lshl_b64 s[0:1], 1.0, s0 1557; VI-NEXT: v_mov_b32_e32 v0, s0 1558; VI-NEXT: v_mov_b32_e32 v1, s1 1559; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1560; VI-NEXT: s_endpgm 1561; 1562; EG-LABEL: s_shl_inline_imm_1_0_i64: 1563; EG: ; %bb.0: 1564; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[] 1565; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1566; EG-NEXT: CF_END 1567; EG-NEXT: PAD 1568; EG-NEXT: ALU clause starting at 4: 1569; EG-NEXT: NOT_INT * T0.W, KC0[2].W, 1570; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W, 1571; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y, 1572; EG-NEXT: 536346624(1.050321e-19), 32(4.484155e-44) 1573; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0, 1574; EG-NEXT: MOV T0.X, 0.0, 1575; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1576; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1577 %shl = shl i64 4607182418800017408, %a 1578 store i64 %shl, i64 addrspace(1)* %out, align 8 1579 ret void 1580} 1581 1582define amdgpu_kernel void @s_shl_inline_imm_neg_1_0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1583; SI-LABEL: s_shl_inline_imm_neg_1_0_i64: 1584; SI: ; %bb.0: 1585; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1586; SI-NEXT: s_load_dword s0, s[0:1], 0xd 1587; SI-NEXT: s_mov_b32 s7, 0xf000 1588; SI-NEXT: s_mov_b32 s6, -1 1589; SI-NEXT: s_waitcnt lgkmcnt(0) 1590; SI-NEXT: s_lshl_b64 s[0:1], -1.0, s0 1591; SI-NEXT: v_mov_b32_e32 v0, s0 1592; SI-NEXT: v_mov_b32_e32 v1, s1 1593; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1594; SI-NEXT: s_endpgm 1595; 1596; VI-LABEL: s_shl_inline_imm_neg_1_0_i64: 1597; VI: ; %bb.0: 1598; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 1599; VI-NEXT: s_load_dword s0, s[0:1], 0x34 1600; VI-NEXT: s_mov_b32 s7, 0xf000 1601; VI-NEXT: s_mov_b32 s6, -1 1602; VI-NEXT: s_waitcnt lgkmcnt(0) 1603; VI-NEXT: s_lshl_b64 s[0:1], -1.0, s0 1604; VI-NEXT: v_mov_b32_e32 v0, s0 1605; VI-NEXT: v_mov_b32_e32 v1, s1 1606; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1607; VI-NEXT: s_endpgm 1608; 1609; EG-LABEL: s_shl_inline_imm_neg_1_0_i64: 1610; EG: ; %bb.0: 1611; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[] 1612; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1613; EG-NEXT: CF_END 1614; EG-NEXT: PAD 1615; EG-NEXT: ALU clause starting at 4: 1616; EG-NEXT: NOT_INT * T0.W, KC0[2].W, 1617; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W, 1618; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y, 1619; EG-NEXT: 1610088448(3.574057e+19), 32(4.484155e-44) 1620; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0, 1621; EG-NEXT: MOV T0.X, 0.0, 1622; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1623; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1624 %shl = shl i64 13830554455654793216, %a 1625 store i64 %shl, i64 addrspace(1)* %out, align 8 1626 ret void 1627} 1628 1629define amdgpu_kernel void @s_shl_inline_imm_0_5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1630; SI-LABEL: s_shl_inline_imm_0_5_i64: 1631; SI: ; %bb.0: 1632; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1633; SI-NEXT: s_load_dword s0, s[0:1], 0xd 1634; SI-NEXT: s_mov_b32 s7, 0xf000 1635; SI-NEXT: s_mov_b32 s6, -1 1636; SI-NEXT: s_waitcnt lgkmcnt(0) 1637; SI-NEXT: s_lshl_b64 s[0:1], 0.5, s0 1638; SI-NEXT: v_mov_b32_e32 v0, s0 1639; SI-NEXT: v_mov_b32_e32 v1, s1 1640; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1641; SI-NEXT: s_endpgm 1642; 1643; VI-LABEL: s_shl_inline_imm_0_5_i64: 1644; VI: ; %bb.0: 1645; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 1646; VI-NEXT: s_load_dword s0, s[0:1], 0x34 1647; VI-NEXT: s_mov_b32 s7, 0xf000 1648; VI-NEXT: s_mov_b32 s6, -1 1649; VI-NEXT: s_waitcnt lgkmcnt(0) 1650; VI-NEXT: s_lshl_b64 s[0:1], 0.5, s0 1651; VI-NEXT: v_mov_b32_e32 v0, s0 1652; VI-NEXT: v_mov_b32_e32 v1, s1 1653; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1654; VI-NEXT: s_endpgm 1655; 1656; EG-LABEL: s_shl_inline_imm_0_5_i64: 1657; EG: ; %bb.0: 1658; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[] 1659; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1660; EG-NEXT: CF_END 1661; EG-NEXT: PAD 1662; EG-NEXT: ALU clause starting at 4: 1663; EG-NEXT: NOT_INT * T0.W, KC0[2].W, 1664; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W, 1665; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y, 1666; EG-NEXT: 535822336(1.016440e-19), 32(4.484155e-44) 1667; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0, 1668; EG-NEXT: MOV T0.X, 0.0, 1669; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1670; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1671 %shl = shl i64 4602678819172646912, %a 1672 store i64 %shl, i64 addrspace(1)* %out, align 8 1673 ret void 1674} 1675 1676define amdgpu_kernel void @s_shl_inline_imm_neg_0_5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1677; SI-LABEL: s_shl_inline_imm_neg_0_5_i64: 1678; SI: ; %bb.0: 1679; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1680; SI-NEXT: s_load_dword s0, s[0:1], 0xd 1681; SI-NEXT: s_mov_b32 s7, 0xf000 1682; SI-NEXT: s_mov_b32 s6, -1 1683; SI-NEXT: s_waitcnt lgkmcnt(0) 1684; SI-NEXT: s_lshl_b64 s[0:1], -0.5, s0 1685; SI-NEXT: v_mov_b32_e32 v0, s0 1686; SI-NEXT: v_mov_b32_e32 v1, s1 1687; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1688; SI-NEXT: s_endpgm 1689; 1690; VI-LABEL: s_shl_inline_imm_neg_0_5_i64: 1691; VI: ; %bb.0: 1692; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 1693; VI-NEXT: s_load_dword s0, s[0:1], 0x34 1694; VI-NEXT: s_mov_b32 s7, 0xf000 1695; VI-NEXT: s_mov_b32 s6, -1 1696; VI-NEXT: s_waitcnt lgkmcnt(0) 1697; VI-NEXT: s_lshl_b64 s[0:1], -0.5, s0 1698; VI-NEXT: v_mov_b32_e32 v0, s0 1699; VI-NEXT: v_mov_b32_e32 v1, s1 1700; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1701; VI-NEXT: s_endpgm 1702; 1703; EG-LABEL: s_shl_inline_imm_neg_0_5_i64: 1704; EG: ; %bb.0: 1705; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[] 1706; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1707; EG-NEXT: CF_END 1708; EG-NEXT: PAD 1709; EG-NEXT: ALU clause starting at 4: 1710; EG-NEXT: NOT_INT * T0.W, KC0[2].W, 1711; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W, 1712; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y, 1713; EG-NEXT: 1609564160(3.458765e+19), 32(4.484155e-44) 1714; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0, 1715; EG-NEXT: MOV T0.X, 0.0, 1716; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1717; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1718 %shl = shl i64 13826050856027422720, %a 1719 store i64 %shl, i64 addrspace(1)* %out, align 8 1720 ret void 1721} 1722 1723define amdgpu_kernel void @s_shl_inline_imm_2_0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1724; SI-LABEL: s_shl_inline_imm_2_0_i64: 1725; SI: ; %bb.0: 1726; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1727; SI-NEXT: s_load_dword s0, s[0:1], 0xd 1728; SI-NEXT: s_mov_b32 s7, 0xf000 1729; SI-NEXT: s_mov_b32 s6, -1 1730; SI-NEXT: s_waitcnt lgkmcnt(0) 1731; SI-NEXT: s_lshl_b64 s[0:1], 2.0, s0 1732; SI-NEXT: v_mov_b32_e32 v0, s0 1733; SI-NEXT: v_mov_b32_e32 v1, s1 1734; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1735; SI-NEXT: s_endpgm 1736; 1737; VI-LABEL: s_shl_inline_imm_2_0_i64: 1738; VI: ; %bb.0: 1739; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 1740; VI-NEXT: s_load_dword s0, s[0:1], 0x34 1741; VI-NEXT: s_mov_b32 s7, 0xf000 1742; VI-NEXT: s_mov_b32 s6, -1 1743; VI-NEXT: s_waitcnt lgkmcnt(0) 1744; VI-NEXT: s_lshl_b64 s[0:1], 2.0, s0 1745; VI-NEXT: v_mov_b32_e32 v0, s0 1746; VI-NEXT: v_mov_b32_e32 v1, s1 1747; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1748; VI-NEXT: s_endpgm 1749; 1750; EG-LABEL: s_shl_inline_imm_2_0_i64: 1751; EG: ; %bb.0: 1752; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[] 1753; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1754; EG-NEXT: CF_END 1755; EG-NEXT: PAD 1756; EG-NEXT: ALU clause starting at 4: 1757; EG-NEXT: NOT_INT * T0.W, KC0[2].W, 1758; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W, 1759; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y, 1760; EG-NEXT: 536870912(1.084202e-19), 32(4.484155e-44) 1761; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0, 1762; EG-NEXT: MOV T0.X, 0.0, 1763; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1764; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1765 %shl = shl i64 4611686018427387904, %a 1766 store i64 %shl, i64 addrspace(1)* %out, align 8 1767 ret void 1768} 1769 1770define amdgpu_kernel void @s_shl_inline_imm_neg_2_0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1771; SI-LABEL: s_shl_inline_imm_neg_2_0_i64: 1772; SI: ; %bb.0: 1773; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1774; SI-NEXT: s_load_dword s0, s[0:1], 0xd 1775; SI-NEXT: s_mov_b32 s7, 0xf000 1776; SI-NEXT: s_mov_b32 s6, -1 1777; SI-NEXT: s_waitcnt lgkmcnt(0) 1778; SI-NEXT: s_lshl_b64 s[0:1], -2.0, s0 1779; SI-NEXT: v_mov_b32_e32 v0, s0 1780; SI-NEXT: v_mov_b32_e32 v1, s1 1781; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1782; SI-NEXT: s_endpgm 1783; 1784; VI-LABEL: s_shl_inline_imm_neg_2_0_i64: 1785; VI: ; %bb.0: 1786; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 1787; VI-NEXT: s_load_dword s0, s[0:1], 0x34 1788; VI-NEXT: s_mov_b32 s7, 0xf000 1789; VI-NEXT: s_mov_b32 s6, -1 1790; VI-NEXT: s_waitcnt lgkmcnt(0) 1791; VI-NEXT: s_lshl_b64 s[0:1], -2.0, s0 1792; VI-NEXT: v_mov_b32_e32 v0, s0 1793; VI-NEXT: v_mov_b32_e32 v1, s1 1794; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1795; VI-NEXT: s_endpgm 1796; 1797; EG-LABEL: s_shl_inline_imm_neg_2_0_i64: 1798; EG: ; %bb.0: 1799; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[] 1800; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1801; EG-NEXT: CF_END 1802; EG-NEXT: PAD 1803; EG-NEXT: ALU clause starting at 4: 1804; EG-NEXT: NOT_INT * T0.W, KC0[2].W, 1805; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W, 1806; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y, 1807; EG-NEXT: 1610612736(3.689349e+19), 32(4.484155e-44) 1808; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0, 1809; EG-NEXT: MOV T0.X, 0.0, 1810; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1811; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1812 %shl = shl i64 13835058055282163712, %a 1813 store i64 %shl, i64 addrspace(1)* %out, align 8 1814 ret void 1815} 1816 1817define amdgpu_kernel void @s_shl_inline_imm_4_0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1818; SI-LABEL: s_shl_inline_imm_4_0_i64: 1819; SI: ; %bb.0: 1820; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1821; SI-NEXT: s_load_dword s0, s[0:1], 0xd 1822; SI-NEXT: s_mov_b32 s7, 0xf000 1823; SI-NEXT: s_mov_b32 s6, -1 1824; SI-NEXT: s_waitcnt lgkmcnt(0) 1825; SI-NEXT: s_lshl_b64 s[0:1], 4.0, s0 1826; SI-NEXT: v_mov_b32_e32 v0, s0 1827; SI-NEXT: v_mov_b32_e32 v1, s1 1828; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1829; SI-NEXT: s_endpgm 1830; 1831; VI-LABEL: s_shl_inline_imm_4_0_i64: 1832; VI: ; %bb.0: 1833; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 1834; VI-NEXT: s_load_dword s0, s[0:1], 0x34 1835; VI-NEXT: s_mov_b32 s7, 0xf000 1836; VI-NEXT: s_mov_b32 s6, -1 1837; VI-NEXT: s_waitcnt lgkmcnt(0) 1838; VI-NEXT: s_lshl_b64 s[0:1], 4.0, s0 1839; VI-NEXT: v_mov_b32_e32 v0, s0 1840; VI-NEXT: v_mov_b32_e32 v1, s1 1841; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1842; VI-NEXT: s_endpgm 1843; 1844; EG-LABEL: s_shl_inline_imm_4_0_i64: 1845; EG: ; %bb.0: 1846; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[] 1847; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1848; EG-NEXT: CF_END 1849; EG-NEXT: PAD 1850; EG-NEXT: ALU clause starting at 4: 1851; EG-NEXT: NOT_INT * T0.W, KC0[2].W, 1852; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W, 1853; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y, 1854; EG-NEXT: 537395200(1.151965e-19), 32(4.484155e-44) 1855; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0, 1856; EG-NEXT: MOV T0.X, 0.0, 1857; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1858; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1859 %shl = shl i64 4616189618054758400, %a 1860 store i64 %shl, i64 addrspace(1)* %out, align 8 1861 ret void 1862} 1863 1864define amdgpu_kernel void @s_shl_inline_imm_neg_4_0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1865; SI-LABEL: s_shl_inline_imm_neg_4_0_i64: 1866; SI: ; %bb.0: 1867; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1868; SI-NEXT: s_load_dword s0, s[0:1], 0xd 1869; SI-NEXT: s_mov_b32 s7, 0xf000 1870; SI-NEXT: s_mov_b32 s6, -1 1871; SI-NEXT: s_waitcnt lgkmcnt(0) 1872; SI-NEXT: s_lshl_b64 s[0:1], -4.0, s0 1873; SI-NEXT: v_mov_b32_e32 v0, s0 1874; SI-NEXT: v_mov_b32_e32 v1, s1 1875; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1876; SI-NEXT: s_endpgm 1877; 1878; VI-LABEL: s_shl_inline_imm_neg_4_0_i64: 1879; VI: ; %bb.0: 1880; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 1881; VI-NEXT: s_load_dword s0, s[0:1], 0x34 1882; VI-NEXT: s_mov_b32 s7, 0xf000 1883; VI-NEXT: s_mov_b32 s6, -1 1884; VI-NEXT: s_waitcnt lgkmcnt(0) 1885; VI-NEXT: s_lshl_b64 s[0:1], -4.0, s0 1886; VI-NEXT: v_mov_b32_e32 v0, s0 1887; VI-NEXT: v_mov_b32_e32 v1, s1 1888; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1889; VI-NEXT: s_endpgm 1890; 1891; EG-LABEL: s_shl_inline_imm_neg_4_0_i64: 1892; EG: ; %bb.0: 1893; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[] 1894; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1895; EG-NEXT: CF_END 1896; EG-NEXT: PAD 1897; EG-NEXT: ALU clause starting at 4: 1898; EG-NEXT: NOT_INT * T0.W, KC0[2].W, 1899; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W, 1900; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y, 1901; EG-NEXT: 1611137024(3.919933e+19), 32(4.484155e-44) 1902; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0, 1903; EG-NEXT: MOV T0.X, 0.0, 1904; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1905; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1906 %shl = shl i64 13839561654909534208, %a 1907 store i64 %shl, i64 addrspace(1)* %out, align 8 1908 ret void 1909} 1910 1911 1912; Test with the 64-bit integer bitpattern for a 32-bit float in the 1913; low 32-bits, which is not a valid 64-bit inline immmediate. 1914define amdgpu_kernel void @s_shl_inline_imm_f32_4_0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1915; SI-LABEL: s_shl_inline_imm_f32_4_0_i64: 1916; SI: ; %bb.0: 1917; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1918; SI-NEXT: s_load_dword s2, s[0:1], 0xd 1919; SI-NEXT: s_mov_b64 s[0:1], 0x40800000 1920; SI-NEXT: s_mov_b32 s7, 0xf000 1921; SI-NEXT: s_mov_b32 s6, -1 1922; SI-NEXT: s_waitcnt lgkmcnt(0) 1923; SI-NEXT: s_lshl_b64 s[0:1], s[0:1], s2 1924; SI-NEXT: v_mov_b32_e32 v0, s0 1925; SI-NEXT: v_mov_b32_e32 v1, s1 1926; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1927; SI-NEXT: s_endpgm 1928; 1929; VI-LABEL: s_shl_inline_imm_f32_4_0_i64: 1930; VI: ; %bb.0: 1931; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 1932; VI-NEXT: s_load_dword s2, s[0:1], 0x34 1933; VI-NEXT: s_mov_b64 s[0:1], 0x40800000 1934; VI-NEXT: s_mov_b32 s7, 0xf000 1935; VI-NEXT: s_mov_b32 s6, -1 1936; VI-NEXT: s_waitcnt lgkmcnt(0) 1937; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s2 1938; VI-NEXT: v_mov_b32_e32 v0, s0 1939; VI-NEXT: v_mov_b32_e32 v1, s1 1940; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1941; VI-NEXT: s_endpgm 1942; 1943; EG-LABEL: s_shl_inline_imm_f32_4_0_i64: 1944; EG: ; %bb.0: 1945; EG-NEXT: ALU 11, @4, KC0[CB0:0-32], KC1[] 1946; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 1947; EG-NEXT: CF_END 1948; EG-NEXT: PAD 1949; EG-NEXT: ALU clause starting at 4: 1950; EG-NEXT: NOT_INT T0.W, KC0[2].W, 1951; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.x, 1952; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00) 1953; EG-NEXT: LSHL T0.Z, literal.x, PS, 1954; EG-NEXT: BIT_ALIGN_INT T0.W, 0.0, literal.y, PV.W, 1955; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.z, 1956; EG-NEXT: 1082130432(4.000000e+00), 541065216(1.626303e-19) 1957; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 1958; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, PV.Z, 1959; EG-NEXT: CNDE_INT T0.X, T1.W, T0.Z, 0.0, 1960; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 1961; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 1962 %shl = shl i64 1082130432, %a 1963 store i64 %shl, i64 addrspace(1)* %out, align 8 1964 ret void 1965} 1966 1967; FIXME: Copy of -1 register 1968define amdgpu_kernel void @s_shl_inline_imm_f32_neg_4_0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 1969; SI-LABEL: s_shl_inline_imm_f32_neg_4_0_i64: 1970; SI: ; %bb.0: 1971; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 1972; SI-NEXT: s_load_dword s2, s[0:1], 0xd 1973; SI-NEXT: s_mov_b32 s6, -1 1974; SI-NEXT: s_mov_b32 s0, -4.0 1975; SI-NEXT: s_mov_b32 s1, s6 1976; SI-NEXT: s_mov_b32 s7, 0xf000 1977; SI-NEXT: s_waitcnt lgkmcnt(0) 1978; SI-NEXT: s_lshl_b64 s[0:1], s[0:1], s2 1979; SI-NEXT: v_mov_b32_e32 v0, s0 1980; SI-NEXT: v_mov_b32_e32 v1, s1 1981; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1982; SI-NEXT: s_endpgm 1983; 1984; VI-LABEL: s_shl_inline_imm_f32_neg_4_0_i64: 1985; VI: ; %bb.0: 1986; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 1987; VI-NEXT: s_load_dword s2, s[0:1], 0x34 1988; VI-NEXT: s_mov_b32 s6, -1 1989; VI-NEXT: s_mov_b32 s0, -4.0 1990; VI-NEXT: s_mov_b32 s1, s6 1991; VI-NEXT: s_mov_b32 s7, 0xf000 1992; VI-NEXT: s_waitcnt lgkmcnt(0) 1993; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s2 1994; VI-NEXT: v_mov_b32_e32 v0, s0 1995; VI-NEXT: v_mov_b32_e32 v1, s1 1996; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1997; VI-NEXT: s_endpgm 1998; 1999; EG-LABEL: s_shl_inline_imm_f32_neg_4_0_i64: 2000; EG: ; %bb.0: 2001; EG-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[] 2002; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 2003; EG-NEXT: CF_END 2004; EG-NEXT: PAD 2005; EG-NEXT: ALU clause starting at 4: 2006; EG-NEXT: AND_INT T0.Z, KC0[2].W, literal.x, 2007; EG-NEXT: MOV T0.W, literal.y, 2008; EG-NEXT: NOT_INT * T1.W, KC0[2].W, 2009; EG-NEXT: 31(4.344025e-44), -532676608(-5.534023e+19) 2010; EG-NEXT: BIT_ALIGN_INT T1.Z, literal.x, PV.W, PS, 2011; EG-NEXT: LSHL T0.W, literal.y, PV.Z, 2012; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.z, 2013; EG-NEXT: 2147483647(nan), -1065353216(-4.000000e+00) 2014; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) 2015; EG-NEXT: CNDE_INT * T0.Y, PS, PV.Z, PV.W, 2016; EG-NEXT: CNDE_INT T0.X, T1.W, T0.W, 0.0, 2017; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 2018; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 2019 %shl = shl i64 -1065353216, %a 2020 store i64 %shl, i64 addrspace(1)* %out, align 8 2021 ret void 2022} 2023 2024define amdgpu_kernel void @s_shl_inline_high_imm_f32_4_0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 2025; SI-LABEL: s_shl_inline_high_imm_f32_4_0_i64: 2026; SI: ; %bb.0: 2027; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 2028; SI-NEXT: s_load_dword s2, s[0:1], 0xd 2029; SI-NEXT: s_mov_b32 s0, 0 2030; SI-NEXT: s_mov_b32 s1, 4.0 2031; SI-NEXT: s_mov_b32 s7, 0xf000 2032; SI-NEXT: s_mov_b32 s6, -1 2033; SI-NEXT: s_waitcnt lgkmcnt(0) 2034; SI-NEXT: s_lshl_b64 s[0:1], s[0:1], s2 2035; SI-NEXT: v_mov_b32_e32 v0, s0 2036; SI-NEXT: v_mov_b32_e32 v1, s1 2037; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 2038; SI-NEXT: s_endpgm 2039; 2040; VI-LABEL: s_shl_inline_high_imm_f32_4_0_i64: 2041; VI: ; %bb.0: 2042; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 2043; VI-NEXT: s_load_dword s2, s[0:1], 0x34 2044; VI-NEXT: s_mov_b32 s0, 0 2045; VI-NEXT: s_mov_b32 s1, 4.0 2046; VI-NEXT: s_mov_b32 s7, 0xf000 2047; VI-NEXT: s_mov_b32 s6, -1 2048; VI-NEXT: s_waitcnt lgkmcnt(0) 2049; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s2 2050; VI-NEXT: v_mov_b32_e32 v0, s0 2051; VI-NEXT: v_mov_b32_e32 v1, s1 2052; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 2053; VI-NEXT: s_endpgm 2054; 2055; EG-LABEL: s_shl_inline_high_imm_f32_4_0_i64: 2056; EG: ; %bb.0: 2057; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[] 2058; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 2059; EG-NEXT: CF_END 2060; EG-NEXT: PAD 2061; EG-NEXT: ALU clause starting at 4: 2062; EG-NEXT: NOT_INT * T0.W, KC0[2].W, 2063; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W, 2064; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y, 2065; EG-NEXT: 541065216(1.626303e-19), 32(4.484155e-44) 2066; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0, 2067; EG-NEXT: MOV T0.X, 0.0, 2068; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 2069; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 2070 %shl = shl i64 4647714815446351872, %a 2071 store i64 %shl, i64 addrspace(1)* %out, align 8 2072 ret void 2073} 2074 2075define amdgpu_kernel void @s_shl_inline_high_imm_f32_neg_4_0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 2076; SI-LABEL: s_shl_inline_high_imm_f32_neg_4_0_i64: 2077; SI: ; %bb.0: 2078; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 2079; SI-NEXT: s_load_dword s2, s[0:1], 0xd 2080; SI-NEXT: s_mov_b32 s0, 0 2081; SI-NEXT: s_mov_b32 s1, -4.0 2082; SI-NEXT: s_mov_b32 s7, 0xf000 2083; SI-NEXT: s_mov_b32 s6, -1 2084; SI-NEXT: s_waitcnt lgkmcnt(0) 2085; SI-NEXT: s_lshl_b64 s[0:1], s[0:1], s2 2086; SI-NEXT: v_mov_b32_e32 v0, s0 2087; SI-NEXT: v_mov_b32_e32 v1, s1 2088; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 2089; SI-NEXT: s_endpgm 2090; 2091; VI-LABEL: s_shl_inline_high_imm_f32_neg_4_0_i64: 2092; VI: ; %bb.0: 2093; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 2094; VI-NEXT: s_load_dword s2, s[0:1], 0x34 2095; VI-NEXT: s_mov_b32 s0, 0 2096; VI-NEXT: s_mov_b32 s1, -4.0 2097; VI-NEXT: s_mov_b32 s7, 0xf000 2098; VI-NEXT: s_mov_b32 s6, -1 2099; VI-NEXT: s_waitcnt lgkmcnt(0) 2100; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s2 2101; VI-NEXT: v_mov_b32_e32 v0, s0 2102; VI-NEXT: v_mov_b32_e32 v1, s1 2103; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 2104; VI-NEXT: s_endpgm 2105; 2106; EG-LABEL: s_shl_inline_high_imm_f32_neg_4_0_i64: 2107; EG: ; %bb.0: 2108; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[] 2109; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 2110; EG-NEXT: CF_END 2111; EG-NEXT: PAD 2112; EG-NEXT: ALU clause starting at 4: 2113; EG-NEXT: NOT_INT * T0.W, KC0[2].W, 2114; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W, 2115; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y, 2116; EG-NEXT: 1614807040(5.534023e+19), 32(4.484155e-44) 2117; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0, 2118; EG-NEXT: MOV T0.X, 0.0, 2119; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 2120; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 2121 %shl = shl i64 13871086852301127680, %a 2122 store i64 %shl, i64 addrspace(1)* %out, align 8 2123 ret void 2124} 2125 2126define amdgpu_kernel void @test_mul2(i32 %p) { 2127; SI-LABEL: test_mul2: 2128; SI: ; %bb.0: 2129; SI-NEXT: s_load_dword s0, s[0:1], 0x9 2130; SI-NEXT: s_mov_b32 s3, 0xf000 2131; SI-NEXT: s_mov_b32 s2, -1 2132; SI-NEXT: s_waitcnt lgkmcnt(0) 2133; SI-NEXT: s_lshl_b32 s0, s0, 1 2134; SI-NEXT: v_mov_b32_e32 v0, s0 2135; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 2136; SI-NEXT: s_waitcnt vmcnt(0) 2137; SI-NEXT: s_endpgm 2138; 2139; VI-LABEL: test_mul2: 2140; VI: ; %bb.0: 2141; VI-NEXT: s_load_dword s0, s[0:1], 0x24 2142; VI-NEXT: s_mov_b32 s3, 0xf000 2143; VI-NEXT: s_mov_b32 s2, -1 2144; VI-NEXT: s_waitcnt lgkmcnt(0) 2145; VI-NEXT: s_lshl_b32 s0, s0, 1 2146; VI-NEXT: v_mov_b32_e32 v0, s0 2147; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 2148; VI-NEXT: s_waitcnt vmcnt(0) 2149; VI-NEXT: s_endpgm 2150; 2151; EG-LABEL: test_mul2: 2152; EG: ; %bb.0: 2153; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] 2154; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1 2155; EG-NEXT: CF_END 2156; EG-NEXT: PAD 2157; EG-NEXT: ALU clause starting at 4: 2158; EG-NEXT: MOV T0.X, literal.x, 2159; EG-NEXT: LSHL * T1.X, KC0[2].Y, 1, 2160; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00) 2161 %i = mul i32 %p, 2 2162 store volatile i32 %i, i32 addrspace(1)* undef 2163 ret void 2164} 2165 2166define void @shl_or_k(i32 addrspace(1)* %out, i32 %in) { 2167; SI-LABEL: shl_or_k: 2168; SI: ; %bb.0: 2169; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2170; SI-NEXT: s_mov_b32 s6, 0 2171; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v2 2172; SI-NEXT: s_mov_b32 s7, 0xf000 2173; SI-NEXT: s_mov_b32 s4, s6 2174; SI-NEXT: s_mov_b32 s5, s6 2175; SI-NEXT: v_or_b32_e32 v2, 4, v2 2176; SI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 2177; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) 2178; SI-NEXT: s_setpc_b64 s[30:31] 2179; 2180; VI-LABEL: shl_or_k: 2181; VI: ; %bb.0: 2182; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2183; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v2 2184; VI-NEXT: v_or_b32_e32 v2, 4, v2 2185; VI-NEXT: flat_store_dword v[0:1], v2 2186; VI-NEXT: s_waitcnt vmcnt(0) 2187; VI-NEXT: s_setpc_b64 s[30:31] 2188; 2189; EG-LABEL: shl_or_k: 2190; EG: ; %bb.0: 2191; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[] 2192; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 2193; EG-NEXT: CF_END 2194; EG-NEXT: PAD 2195; EG-NEXT: ALU clause starting at 4: 2196; EG-NEXT: LSHL * T0.W, KC0[2].Z, literal.x, 2197; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 2198; EG-NEXT: OR_INT T0.X, PV.W, literal.x, 2199; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, 2200; EG-NEXT: 4(5.605194e-45), 2(2.802597e-45) 2201 %tmp0 = or i32 %in, 1 2202 %tmp2 = shl i32 %tmp0, 2 2203 store i32 %tmp2, i32 addrspace(1)* %out 2204 ret void 2205} 2206 2207define void @shl_or_k_two_uses(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 %in) { 2208; SI-LABEL: shl_or_k_two_uses: 2209; SI: ; %bb.0: 2210; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2211; SI-NEXT: s_mov_b32 s6, 0 2212; SI-NEXT: v_or_b32_e32 v4, 1, v4 2213; SI-NEXT: s_mov_b32 s7, 0xf000 2214; SI-NEXT: s_mov_b32 s4, s6 2215; SI-NEXT: s_mov_b32 s5, s6 2216; SI-NEXT: v_lshlrev_b32_e32 v5, 2, v4 2217; SI-NEXT: buffer_store_dword v5, v[0:1], s[4:7], 0 addr64 2218; SI-NEXT: buffer_store_dword v4, v[2:3], s[4:7], 0 addr64 2219; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) 2220; SI-NEXT: s_setpc_b64 s[30:31] 2221; 2222; VI-LABEL: shl_or_k_two_uses: 2223; VI: ; %bb.0: 2224; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 2225; VI-NEXT: v_or_b32_e32 v4, 1, v4 2226; VI-NEXT: v_lshlrev_b32_e32 v5, 2, v4 2227; VI-NEXT: flat_store_dword v[0:1], v5 2228; VI-NEXT: flat_store_dword v[2:3], v4 2229; VI-NEXT: s_waitcnt vmcnt(0) 2230; VI-NEXT: s_setpc_b64 s[30:31] 2231; 2232; EG-LABEL: shl_or_k_two_uses: 2233; EG: ; %bb.0: 2234; EG-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[] 2235; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T3.X, 0 2236; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1 2237; EG-NEXT: CF_END 2238; EG-NEXT: ALU clause starting at 4: 2239; EG-NEXT: LSHR T0.X, KC0[2].Z, literal.x, 2240; EG-NEXT: OR_INT * T1.X, KC0[2].W, 1, 2241; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 2242; EG-NEXT: LSHL T2.X, PS, literal.x, 2243; EG-NEXT: LSHR * T3.X, KC0[2].Y, literal.x, 2244; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) 2245 %tmp0 = or i32 %in, 1 2246 %tmp2 = shl i32 %tmp0, 2 2247 store i32 %tmp2, i32 addrspace(1)* %out0 2248 store i32 %tmp0, i32 addrspace(1)* %out1 2249 ret void 2250} 2251 2252attributes #0 = { nounwind readnone } 2253