1; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s 2; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=GCN -check-prefix=SI %s 3; XUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=GCN -check-prefix=VI %s 4 5declare i32 @llvm.r600.read.tidig.x() #0 6 7 8;EG: {{^}}shl_v2i32: 9;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 10;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 11 12;SI: {{^}}shl_v2i32: 13;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 14;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 15 16;VI: {{^}}shl_v2i32: 17;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 18;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 19 20define void @shl_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { 21 %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1 22 %a = load <2 x i32>, <2 x i32> addrspace(1) * %in 23 %b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr 24 %result = shl <2 x i32> %a, %b 25 store <2 x i32> %result, <2 x i32> addrspace(1)* %out 26 ret void 27} 28 29;EG: {{^}}shl_v4i32: 30;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 31;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 32;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 33;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 34 35;SI: {{^}}shl_v4i32: 36;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 37;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 38;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 39;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 40 41;VI: {{^}}shl_v4i32: 42;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 43;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 44;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 45;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 46 47define void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { 48 %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1 49 %a = load <4 x i32>, <4 x i32> addrspace(1) * %in 50 %b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr 51 %result = shl <4 x i32> %a, %b 52 store <4 x i32> %result, <4 x i32> addrspace(1)* %out 53 ret void 54} 55 56;EG-LABEL: {{^}}shl_i64: 57;EG: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]] 58;EG: LSHR {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}} 59;EG-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal 60;EG-DAG: LSHR {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1 61;EG-DAG: LSHL {{\*? *}}[[HISMTMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], [[SHIFT]] 62;EG-DAG: OR_INT {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], {{[[HISMTMP]]|PV.[XYZW]|PS}}, {{[[OVERF]]|PV.[XYZW]}} 63;EG-DAG: LSHL {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], [[OPLO]], {{PS|[[SHIFT]]|PV.[XYZW]}} 64;EG-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal 65;EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}} 66;EG-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], .*}}, 0.0 67 68;SI: {{^}}shl_i64: 69;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 70 71;VI: {{^}}shl_i64: 72;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 73 74define void @shl_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { 75 %b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1 76 %a = load i64, i64 addrspace(1) * %in 77 %b = load i64, i64 addrspace(1) * %b_ptr 78 %result = shl i64 %a, %b 79 store i64 %result, i64 addrspace(1)* %out 80 ret void 81} 82 83;EG-LABEL: {{^}}shl_v2i64: 84;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] 85;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] 86;EG-DAG: LSHR {{\*? *}}[[COMPSHA]] 87;EG-DAG: LSHR {{\*? *}}[[COMPSHB]] 88;EG-DAG: LSHR {{.*}}, 1 89;EG-DAG: LSHR {{.*}}, 1 90;EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal 91;EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal 92;EG-DAG: LSHL {{.*}}, [[SHA]] 93;EG-DAG: LSHL {{.*}}, [[SHB]] 94;EG-DAG: LSHL {{.*}}, [[SHA]] 95;EG-DAG: LSHL {{.*}}, [[SHB]] 96;EG-DAG: LSHL 97;EG-DAG: LSHL 98;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal 99;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal 100;EG-DAG: CNDE_INT {{.*}}, 0.0 101;EG-DAG: CNDE_INT {{.*}}, 0.0 102;EG-DAG: CNDE_INT 103;EG-DAG: CNDE_INT 104 105;SI: {{^}}shl_v2i64: 106;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 107;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 108 109;VI: {{^}}shl_v2i64: 110;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 111;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 112 113define void @shl_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) { 114 %b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %in, i64 1 115 %a = load <2 x i64>, <2 x i64> addrspace(1) * %in 116 %b = load <2 x i64>, <2 x i64> addrspace(1) * %b_ptr 117 %result = shl <2 x i64> %a, %b 118 store <2 x i64> %result, <2 x i64> addrspace(1)* %out 119 ret void 120} 121 122;EG: {{^}}shl_v4i64: 123;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] 124;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] 125;EG-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]] 126;EG-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]] 127;EG-DAG: LSHR {{\*? *}}[[COMPSHA]] 128;EG-DAG: LSHR {{\*? *}}[[COMPSHB]] 129;EG-DAG: LSHR {{\*? *}}[[COMPSHC]] 130;EG-DAG: LSHR {{\*? *}}[[COMPSHD]] 131;EG-DAG: LSHR {{.*}}, 1 132;EG-DAG: LSHR {{.*}}, 1 133;EG-DAG: LSHR {{.*}}, 1 134;EG-DAG: LSHR {{.*}}, 1 135;EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal 136;EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal 137;EG-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal 138;EG-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal 139;EG-DAG: LSHL {{.*}}, [[SHA]] 140;EG-DAG: LSHL {{.*}}, [[SHB]] 141;EG-DAG: LSHL {{.*}}, [[SHC]] 142;EG-DAG: LSHL {{.*}}, [[SHD]] 143;EG-DAG: LSHL {{.*}}, [[SHA]] 144;EG-DAG: LSHL {{.*}}, [[SHB]] 145;EG-DAG: LSHL {{.*}}, [[SHC]] 146;EG-DAG: LSHL {{.*}}, [[SHD]] 147;EG-DAG: LSHL 148;EG-DAG: LSHL 149;EG-DAG: LSHL 150;EG-DAG: LSHL 151;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal 152;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal 153;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal 154;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal 155;EG-DAG: CNDE_INT {{.*}}, 0.0 156;EG-DAG: CNDE_INT {{.*}}, 0.0 157;EG-DAG: CNDE_INT {{.*}}, 0.0 158;EG-DAG: CNDE_INT {{.*}}, 0.0 159;EG-DAG: CNDE_INT 160;EG-DAG: CNDE_INT 161;EG-DAG: CNDE_INT 162;EG-DAG: CNDE_INT 163 164;SI: {{^}}shl_v4i64: 165;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 166;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 167;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 168;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} 169 170;VI: {{^}}shl_v4i64: 171;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 172;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 173;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 174;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} 175 176define void @shl_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) { 177 %b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i64 1 178 %a = load <4 x i64>, <4 x i64> addrspace(1) * %in 179 %b = load <4 x i64>, <4 x i64> addrspace(1) * %b_ptr 180 %result = shl <4 x i64> %a, %b 181 store <4 x i64> %result, <4 x i64> addrspace(1)* %out 182 ret void 183} 184 185; Make sure load width gets reduced to i32 load. 186; GCN-LABEL: {{^}}s_shl_32_i64: 187; GCN-DAG: s_load_dword [[LO_A:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb{{$}} 188; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], 0{{$}} 189; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], [[LO_A]] 190; GCN: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} 191define void @s_shl_32_i64(i64 addrspace(1)* %out, i64 %a) { 192 %result = shl i64 %a, 32 193 store i64 %result, i64 addrspace(1)* %out 194 ret void 195} 196 197; GCN-LABEL: {{^}}v_shl_32_i64: 198; GCN-DAG: buffer_load_dword v[[LO_A:[0-9]+]], 199; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], 0{{$}} 200; GCN: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[LO_A]]{{\]}} 201define void @v_shl_32_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { 202 %tid = call i32 @llvm.r600.read.tidig.x() #0 203 %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid 204 %gep.out = getelementptr i64, i64 addrspace(1)* %out, i32 %tid 205 %a = load i64, i64 addrspace(1)* %gep.in 206 %result = shl i64 %a, 32 207 store i64 %result, i64 addrspace(1)* %gep.out 208 ret void 209} 210 211attributes #0 = { nounwind readnone } 212